ML145053CP [LANSDALE]
10-Bit A/D Converter With Serial Interface CMOS; 10位A / D转换器，串行接口CMOS
| 型号： | ML145053CP |
| 厂家： | 
LANSDALE SEMICONDUCTOR INC. |
| 描述： | 10-Bit A/D Converter With Serial Interface CMOS |
| 文件： | 总15页 (文件大小：804K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ML145053
10-Bit A/D Converter With
Serial Interface
CMOS
Legacy Device: Motorola MC145053
This ratiometric 10-bit ADC has a serial interface port to provide commu-
nication with MCUs and MPUs. Either a 10- or 16-bit format can be used.
The16-bit format can be one continuous 16-bit stream or two intermittent 8-
bit streams. The converter operates from a single power supply with no exter-
nal trimming required. Reference voltages down to 4.0 V are accommodated.
The ML145053 has an internal clock oscillator to operate the dynamic A/D
conversion sequence and an end-of-conversion (EOC) output.
P DIP 14 = CP
PLASTIC
CASE 646
SOG 14 = -5P
SOG
CASE 751A
• 5 Analog Input Channels with Internal Sample-and-Hold
• Operating Temperature Range: T – 40 to 125°C
A
• Successive Approximation Conversion Time: 44 µs Maximum
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
• Maximum Sample Rate: 20.4 ks/s
P DIP 14
MC145053P
ML145053CP
SOG 14
MC145053D
ML145053-5P
• Analog Input Range with 5-Volt Supply: 0 to 5 V
• Monotonic with No Missing Codes
• Direct Interface to Motorola SPI and National MICROWIRE™
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
Serial DataPorts
• Digital Inputs/Outputs are TTL, NMOS, and CMOS Compatible
• Low Power Consumption: 14 mW
PIN ASSIGNMENT
• Chip Complexity: 1630 Elements (FETs, Capacitors, etc.)
• See Application Note AN1062 for Operation with QSPI
EOC
AN0
AN1
AN2
AN3
AN4
1
2
3
4
5
6
7
14
V
DD
13 SCLK
12
11
D
D
BLOCK DIAGRAM
in
out
V
V
ref
9
AG
8
10 CS
9
8
V
V
MUX OUT
10–BIT RC DAC
ref
WITH SAMPLE AND HOLD
V
SS
AG
PIN 14 = V
PIN 7 = V
DD
SUCCESSIVE APPROXIMATION
REGISTER
2
3
4
5
6
SS
AN0
AN1
AN2
AN3
ANALOG
MUX
MUX ADDRESS
REGISTER
AN4
AN5
AN6
AN7
INTERNAL
TEST
VOLTAGES
12
11
D
out
in
D
DATA REGISTER
AUTO–ZEROED
COMPARATOR
10
13
CS
SCLK
DIGITAL CONTROL
LOGIC
1
EOC
MICROWIRE is a trademark of National Semiconductor Corp.
Page 1 of 15
www.lansdale.com
Issue A
ML145053
LANSDALE Semiconductor, Inc.
MAXIMUM RATINGS*
Symbol
Parameter
DC Supply Voltage (Referenced to V
DC Reference Voltage
Value
Unit
V
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications
of any voltage higher than maximum rated
voltages to this high-impedance circuit. For
V
DD
)
SS
– 0.5 to + 6.0
V
ref
V
to V
DD
– 0.1 to V
ref
+ 0.1
V
AG
V
AG
Analog Ground
V
V
SS
V
V
V
in
DC Input Voltage, Any Analog or Digital
Input
– 0.5 to
+ 0.5
V
proper operation, V and V
in out
should be
SS in out
SS
constrainedto the range V
≤(V or V ) ≤
DD
V
.
DD
V
out
DC Output Voltage
V
V
– 0.5 to
DD
V
SS
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either
or V ). Unused outputs must be left
+ 0.5
V
I
in
DC Input Current, per Pin
DC Output Current, per Pin
20
mA
mA
mA
C
SS
open.
DD
I
25
out
I
, I
DC Supply Current, V
Storage Temperature
and V
Pins
SS
50
DD SS
DD
T
stg
– 65 to 150
260
T
L
Lead Temperature, 1 mm from Case for
10 Seconds
C
* MaximumRatingsarethosevaluesbeyondwhichdamagetothedevicemayoccur. Func-
tional operation should be restricted to the Operation Ranges below..
OPERATION RANGES (Applicable to Guaranteed Limits)
Symbol
Parameter
Value
Unit
V
V
DD
DC Supply Voltage, Referenced to V
DC Reference Voltage
4.5 to 5.5
SS
V
ref
V
+ 4.0 to V
AG DD
+ 0.1
V
V
AG
Analog Ground
V – 0.1 to V – 4.0
SS ref
V
V
Analog Input Voltage (See Note)
Digital Input Voltage, Output Voltage
Ambient Operating Temperature
V
to V
V
AI
V , V
AG
ref
V
SS
to V
V
in out
T
DD
– 40 to 125
convert to zero. See V
C
A
NOTE: Analog input voltages greater than V
convert to full scale. Input voltages less than V
AG
and V
pin
ref
ref
AG
descriptions.
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V , Full Temperature and Voltage Ranges per Operation Ranges Table, unless otherwise indicated)
SS
Guaranteed
Limit
Symbol
Parameter
Test Condition
Unit
V
IH
Minimum High-Level Input Voltage
(D , SCLK, CS)
in
2.0
V
V
Maximum Low-Level Input Voltage
0.8
2.4
V
V
IL
(D , SCLK, CS)
in
V
OH
Minimum High-Level Output Voltage
(D , EOC)
out
I
I
= – 1.6 mA
= – 20 µA
out
out
V
– 0.1
DD
V
OL
Minimum Low-Level Output Voltage
(D , EOC)
out
I
I
= + 1.6 mA
= + 20 µA
0.4
0.1
V
out
out
I
in
Maximum Input Leakage Current
(D , SCLK, CS)
in
V
in
= V
or V
DD
2.5
µA
SS
I
Maximum Three-State Leakage Current (D
Maximum Power Supply Current
)
V
= V
or V
DD
10
2.5
100
1
µA
mA
µA
µA
OZ
out
out
= V
SS
or V , All Outputs Open
I
V
in
DD
SS
DD
= V
I
Maximum Static Analog Reference Current (V
)
V
= V , V
ref
ref
ref
= V
DD AG
to V
SS
I
Maximum Analog Mux Input Leakage Current between all
deselected inputs and any selected input (AN0–AN4)
V
Al
Al
SS
DD
Page 2 of 15
www.lansdale.com
Issue A
ML145053
LANSDALE Semiconductor, Inc.
A/D CONVERTER ELECTRICAL CHARACTERISTICS
(Full Temperature and Voltage Ranges per Operation Ranges Table)
Guaranteed
Limit
10
1
Characteristic
Resolution
Definition and Test Conditions
Unit
Bits
Number of bits resolved by the A/D converter
Maximum Nonlinearity
Maximum Zero Error
Maximum difference between an ideal and an actual ADC transfer function
LSB
LSB
Difference between the maximum input voltage of an ideal and an actual
ADC for zero output code
1
Maximum Full-Scale Error
Difference between the minimum input voltage of an ideal and an actual
ADC for full-scale output code
1
LSB
Maximum Total Unadjusted Error
Maximum Quantization Error
Absolute Accuracy
Maximum sum of nonlinearity, zero error, and full-scale error
Uncertainty due to converter resolution
1
LSB
LSB
LSB
1/2
Difference between the actual input voltage and the full-scale weighted
equivalent of the binary output code, all error sources included
1-1/2
Maximum Conversion Time
Data Transfer Time
Total time to perform a single analog-to-digital conversion
44
µs
Total time to transfer digital serial data into and out of the device
10 to 16
SCLK
cycles
Sample Acquisition Time
Minimum Total Cycle Time
Maximum Sample Rate
Analog input acquisition time window
6
SCLK
cycles
Total time to transfer serial data, sample the analog input, and perform the
conversion; SCLK = 2.1 MHz
49
µs
Rate at which analog inputs may be sampled; SCLK = 2.1 MHz
20.4
ks/s
Page 3 of 15
www.lansdale.com
Issue A
ML145053
LANSDALE Semiconductor, Inc.
AC ELECTRICAL CHARACTERISTICS
(Full Temperature and Voltage Ranges per Operation Ranges Table)
Guaranteed
Limit
Figure
Symbol
Parameter
Unit
1
f
Clock Frequency, SCLK
(10-bit xfer) Min
(11- to 16-bit xfer) Min
(10- to 16-bit xfer) Max)
0
MHz
Note 1
2.1
Note: Refer to t , t
wH wL
below
1
1
t
Minimum Clock High Time, SCLK
Minimum Clock Low Time, SCLK
Maximum Propagation Delay, SCLK to D
190
190
125
10
ns
ns
ns
ns
ns
µs
ns
ns
ns
µs
wH
t
wL
, t
1, 7
1, 7
2, 7
2, 7
3
t
PLH PHL
out
t
h
Minimum Hold Time, SCLK to D
out
t
, t
PLZ PHZ
, t
PZL PZH
Maximum Propagation Delay, CS to D
High-Z
150
2.3
out
out
t
Maximum Propagation Delay, CS to D
Driven
t
Minimum Setup Time, D to SCLK
in
Minimum Hold Time, SCLK to D
in
100
0
su
3
t
h
t
d
4, 7, 8
5
Maximum Delay Time, EOC to D
out
(MSB)
100
2.425
Note 2
t
Minimum Setup Time, CS to SCLK
su
–
t
Minimum Time Required Between 10th SCLK Falling Edge ( 0.8 V) and
CS to Allow a Conversion
CSd
–
t
Maximum Delay Between 10th SCLK Falling Edge ( 2 V) and CS to
Abort a Conversion
9
µs
CAs
5
6, 8
1
t
Minimum Hold Time, Last SCLK to CS
0
ns
h
t
Maximum Propagation Delay, 10th SCLK to EOC
2.35
µs
PHL
t , t
Maximum Input Rise and Fall Times
SCLK
D , CS
in
1
10
ms
µs
r f
1, 4, 6 – 8
–
t
, t
Maximum Output Transition Time, Any Output
Maximum Input Capacitance
300
ns
TLH THL
C
AN0 – AN4
55
15
pF
in
SCLK, CS, D
in
–
C
Maximum Three-State Output Capacitance
D
15
pF
out
out
NOTES:
1. After the 10th SCLK falling edge (≥2 V), at least 1 SCLK rising edge (≥ 2 V) must occur within 18.5 µs.
2. A CS edge may be received immediately after an active transition on the EOC pin.
Page 4 of 15
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Issue A
ML145053
LANSDALE Semiconductor, Inc.
SWITCHING WAVEFORMS
t
t
WH
WL
t
t
r
f
2.0 V
SCLK
2.0 V
0.8 V
CS
1/f
0.8 V
t
, t
PLH PHL
t
, t
PZH PZL
t
, t
PHZ PLZ
2.4 V
D
out
90%
10%
2.4 V
0.4 V
0.4 V
t
D
out
, t
TLH THL
Figure 1.
Figure 2.
t
TLH
2.4 V
EOC
VALID
0.4 V
2.0 V
0.8 V
t
D
d
in
2.4 V
0.4 V
VALID MSB
t
h
t
su
D
out
2.0 V
0.8 V
SCLK
NOTE: D
is driven only when CS is active (low).
out
Figure 3.
Figure 4.
2.0 V
10TH
SCLK
EOC
CS
CLOCK
0.8 V
0.8 V
t
PHL
t
t
h
su
2.4 V
FIRST
LAST
0.4 V
SCLK
0.8 V
0.8 V
CLOCK
CLOCK
t
THL
Figure 5.
Figure 6.
V
V
DD
DD
TEST
POINT
TEST
POINT
EOC
D
out
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
12 k
100 pF
12 k
50 pF
Figure 7. Test Circuit
Figure 8. Test Circuit
Page 5 of 15
www.lansdale.com
Issue A
ML145053
LANSDALE Semiconductor, Inc.
PIN DESCRIPTIONS
D
out
Serial Data Output of the A/D Conversion Result (Pin 11)
DIGITAL INPUTS AND OUTPUT
This output is in the high-impedance state when CS is in-
active high. When the chip recognizes a valid active low on
The various serial bit-stream formats for the ML145053 are
illustrated in the timing diagrams of Figures 9 through 14.
Table 1 assists in selection of the appropriate diagram. Note
that the ADC accepts 16 clocks which makes it SPI (Serial
Peripheral Interface) compatible.
CS, D
is taken out of the high-impedance state and is driv-
out
en with the MSB of the previous conversion result. (For the
first transfer after power-up, data on D is undefined for the
entire transfer.) The value on D
significant result bit upon the first falling edge of SCLK.The
remaining result bits are shifted out in order, with the LSB
out
changes to the second most
out
Table 1. Timing Diagram Selection
appearing on D
upon the ninth falling edge of SCLK. Note
out
that the order of the transfer is MSB to LSB. Upon the10th
falling edge of SCLK, D is immediately driven low (if
No. of Clocks in Using
Serial Transfer
Interval
Figure
No.
out
Serial Transfer
CS
allowed by CS) so that transfers of more than 10 SCLKs read
zeroes as the unused LSBs.
10
10
Yes
No
Don't Care
9
Don't Care
10
11
12
13
14
When CS is held active low between transfers, D
is driv-
out
11 to 16
16
Yes
No
Shorter than Conversion
Shorter than Conversion
Longer than Conversion
Longer than Conversion
en from a low level to the MSB of the conversion result for
three cases: Case 1 – upon the 16th SCLK falling edge if the
transfer is longer than the conversion time (Figure 14); Case 2
– upon completion of a conversion for a 16-bit transfer interval
shorter than the conversion (Figure 12); Case 3 – upon com-
pletion of a conversion for a 10-bit transfer (Figure 10).
11 to 16
16
Yes
No
CS
Active-Low Chip Select Input (Pin 10)
Chip select initializes the chip to perform conversions and
D
in
provides 3-state control of the data output pin (D ). While
Serial Data Input (Pin 12)
out
inactive high, CS forces D
to the high-impedance state and
out
The four-bit serial input stream begins with the MSB of the
analog mux address (or the user test mode) that is to be con-
verted next. The address is shifted in on the first four rising
edges of SCLK. After the four mux address bits have been
received, the data on Din is ignored for the remainder of the
present serial transfer. See Table 2 in Applications Information.
disables the data input (Din) and serial clock (SCLK) pins. A
high-to-low transition on CS resets the serial dataport and syn-
chronizes it to the MPU data stream. CS can remain active
during the conversion cycle and can stay in the active low state
for multiple serial transfers or CS can be inactive high after
each transfer. If CS is kept active low between transfers, the
length of each transfer is limited to either 10 or 16 SCLK
cycles. If CS is in the inactive high state between transfers,
each transfer can be anywhere from 10 to16 SCLK cycles
long. See the SCLK pin description for a more detailed discus-
sion of these requirements.
SCLK
Serial Data Clock (Pin 13)
This clock input drives the internal I/O state machine to per-
form three major functions: (1) drives the data shift registers to
simultaneously shift in the next mux address from the D pin
in
pin, (2)
Spurious chip selects caused by system noise are minimized
by the internal circuitry. Any transitions on the CS pin are rec-
ognized as valid only if the level is maintained for about 2 µs
after the transition.
and shift out the previous conversion result on the D
out
begins sampling the analog voltage onto the RCDAC as soon as
the new mux address is available, and (3) transfers control to
the A/D conversion state machine after the last bit of the previ-
ous conversion result has been shifted out on the D
pin.
out
NOTE
The serial data shift registers are completely static, allowing
SCLK rates down to the DC. There are some cases, however,
that require a minimum SCLK frequency as discussed later in
this section. At least ten SCLK cycles are required for each
simultaneous data transfer. If the 16-bit format is used, SCLK
can be one continuous 16-bit stream or two intermittent 8-bit
streams. After the serial port has been initiated to perform a
serial transfer*, the new mux address is shifted in
If CS is inactive high after the 10th SCLK cycle and
then goes active low before the A/D conversion is com-
plete, the conversion is aborted and the chip enters the
initial state, ready for another serial transfer/conversion
sequence. At this point, the output data register contains
the result from the conversion before the aborted con-
version. Note that the last step of the A/D conversion
sequence is to update the output data register with the
result. Therefore, if CS goes active low in an attempt to
abort the conversion too close to the end of the conver-
sion sequence, the result register may be corrupted and
the chip could be thrown out of sync with the processor
until CS is toggled again (refer to the AC Electrical
Characteristics in the spec tables).
*The serial port can be initiated in three ways: (1) a recognized CS
falling edge, (2) the end of an A/D conversion if the port is per-
forming either a 10-bit or a 16-bit “shorter-than-conversion” trans-
fer with CS active low between transfers, and (3) the 16th falling
edge of SCLK if the port is performing 16-bit “longer-than-conver-
sion” transfers with CS active low between transfers.
Page 6 of 15
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Issue A
ML145053
LANSDALE Semiconductor, Inc.
on the first four rising edges of SCLK, and the previous 10-bit from unselected channels to a selected channel and leakage
conversion result is shifted out on the first nine falling edges
of SCLK. After the fourth rising edge of SCLK, the new mux
address is available; therefore, on the next edge of SCLK (the
fourth falling edge), the analog input voltage on the selected
currents through the ESD protection diodes on the selected
channel occur. These leakage currents cause an offset voltage
to appear across any series source resistance on the selected
channel. Therefore, any source resistance greater than 1 kΩ
mux input begins charging the RC DAC and continues to do so (Lansdale test condition) may induce errors in excess of guar-
until the tenth falling edge of SCLK. After this tenth SCLK
edge, the analog input voltage is disabled from the RC DAC
anteed specifications.There are three tests available that verify
the functionality of all the control logic as well as the succes-
and the RC DAC begins the “hold” portion of the A/D conver- sive approximation comparator. These tests are performed by
sion sequence. Also upon this tenth SCLK edge, control of the addressing $B, $C, or $D and they convert a voltage of (V
+
ref
internal circuitry is transferred to the internal clock oscillator
which drives the successive approximation logic to complete
the conversion. If 16 SCLK cycles are used during each trans-
fer, then there is a constraint on the minimum SCLK frequen-
cy. Specifically, there must be at least one rising edge on
SCLK before the A/D conversion is complete. If the SCLK
frequency is too low and a rising edge does not occur during
the conversion, the chip is thrown out of sync with the proces-
sor and CS needs to be toggled in order to restore proper oper-
V
AG
)/2, V , or V , respectively. The voltages are obtained
AG ref
internally by sampling V or V
ments of the RC DAC during the sample phase. Addressing
$B, $C, or $D produces an output of $200 (half scale), $000,
onto the appropriate ele-
AG
ref
or $3FF (full scale), respectively, if the converter is functioning
properly. However, deviation from these values occurs in the
presence of sufficient system noise (external to the chip)
onV , V , V , or V
.
DD SS ref AG
ation. If 10 SCLKs are used per transfer, then there is no lower POWER AND REFERENCE PINS
frequency limit on SCLK. Also note that if the ADC is operat-
ed such that CS is inactive high between transfers, then the
number of SCLK cycles per transfer can be anything between
10 and 16 cycles, but the “rising edge” constraint is still in
effect if more than 10 SCLKs are used. (If CS stays active low
for multiple transfers, the number of SCLK cycles must be
either 10 or 16.)
V
and V
DD
SS
Device Supply Pins (Pins 7 and 14)
V
is normally connected to digital ground; V
is con-
DD
SS
nected to a positive digital supply voltage. Low frequency
(V – V ) variations over the range of 4.5 to 5.5 volts do
DD
SS
not affect the A/D accuracy. (See the Operations Ranges Table
for restrictions on V and V relative to V and V .)
ref AG DD SS
EOC
Excessive inductance in the V or V lines, as on automat-
ic test equipment, may cause A/D offsets > 1 LSB. Use of a
DD
SS
End-of-Conversion Output (Pin 1)
EOC goes low on the tenth falling edge of SCLK. A low-to-
high transition on EOC occurs when the A/D conversion is
complete and the data is ready for transfer.
0.1 µF bypass capacitor across these pins is recommended.
V
and V
ref
AG
Analog Reference Voltage Pins (Pins 8 and 9)
ANALOG INPUTS AND TEST MODES
Analog reference voltage pins which determine the lower
and upper boundary of the A/D conversion. Analog input volt-
AN0 through AN4
Analog Multiplexer Inputs (Pins 2 – 6)
ages ≥ V produce a full scale output and input voltages ≤
ref
V
AG
produce an output of zero. CAUTION: The analog input
The input AN0 is addressed by loading $0 into the mux
address register. AN1 is addressed by $1, AN2 by $2, AN3 by
$3, and AN4 by $4. Table 2 shows the input format for a 16-bit free as possible to avoid degradation of the A/D conversion.
stream. The mux features a break-before-make switching struc- Ideally, V and V should be single-point connected to the
ture to minimize noise injection into the analog inputs. The
source resistance driving these inputs must be ≤ 1 kΩ. During
normal operation, leakage currents through the analog mux
voltage must be ≥ V and ≤ V . The A/D conversion result
SS DD
is ratiometric to V – V . V and V must be as noise-
ref AG ref AG
ref
AG
voltage supply driving the system's transducers. Use of a 0.22
µF bypass capacitor across these pins is strongly urged.
Page 7 of 15
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Issue A
ML145053
LANSDALE Semiconductor, Inc.
CS
HIGH IMPEDANCE
D9
D
D9–MSB
D8
D7
D6
D5
D4
D3
D2
D1
D0
out
1
2
3
4
5
6
7
8
9
10
1
SCLK
D
in
A3
MSB
EOC
A/D CONVERSION
INITERVAL
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
RE-INITIALIZE
INITIALIZE
Figure 9. Timing for 10-Clock Transfer Using CS
MUST BE HIGH ON POWER UP
CS
D
D9–MSB
D8
A2
D7
A1
D6
A0
D5
D4
D3
D2
D1
D0
D9
out
LOW LEVEL
1
2
3
4
5
6
7
8
9
10
1
SCLK
D
in
A3
A3
MSB
EOC
A/D CONVERSION
INITERVAL
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
INITIALIZE
Figure 10. Timing for 10-Clock Transfer Not Using CS
NOTES:
1. D9, D8, D7, D6, D5, …, D0 = the result of the previous A/D conversion.
2. A3, A2, A1, A0 = the mux address for the next A/D conversion.
Page 8 of 15
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Issue A
ML145053
LANSDALE Semiconductor, Inc.
Page 9 of 15
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Issue A
ML145053
LANSDALE Semiconductor, Inc.
Page 10 of 15
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Issue A
ML145053
LANSDALE Semiconductor, Inc.
Legacy Applications Information
DESCRIPTION
A reference circuit voltage of 5 volts is used for the applica-
tion shown in Figure 15. However, the reference circuitry may
This example application of the ML145053 ADC interfaces
four analog signals to a microprocessor.
be simplified by tying VAG to system ground and V to the
system's positive supply. (See Figure 16.)
ref
Figure 15 illustrates how the ML145053 is used as a cost
effective means to simplify this type of circuit design. Utilizing
one ADC, four analog inputs are interfaced to a CMOS or
NMOS microprocessor with a serial peripheral interface (SPI)
port. Processors with National Semiconductor's MICROWIRE
serial port may also be used. Full duplex operation optimizes
throughput for this system.
A bypass capacitor of approximately 0.22 µF across theV
ref
and V
pins is recommended. These pins are adjacent on the
AG
ADC package which facilitates mounting the capacitor very
close to the ADC.
SOFTWARE CONSIDERATIONS
The software flow for acquisition is straight forward. The
four analog inputs, AN0 through AN3, are scanned by reading
the analog value of the previously addressed channel into the
MCU and sending the address of the next channel to be read to
the ADC, simultaneously.
The designer utilizing the ML145053 has the end-of-con-
version signal (at pin 1) to define the conversion interval. EOC
may be used to generate an interrupt, which is serviced by
reading the serial data from the ADC. The software flow
should then process and format the data.
When this ADC is used with a 16-bit (2-byte) transfer, there
are two types of offsets involved. In the first type of offset, the
channel information sent to the ADCs is offset by 12 bits. That
is, in the 16-bit stream, only the first 4 bits (4 MSBs) contain
the channel information. The balance of the bits are don't
cares. This results in 3 don't-care nibbles, as shown in Table 2.
The second type of offset is in the conversion result returned
from the ADC; this is offset by 6 bits. In the 16-bitstream, the
first 10 bits (10 MSBs) contain the conversion result. The last
6 bits are zeroes. The hexadecimal result is shown in the first
column of Table 3. The second column shows the result after
the offset is removed by a micro-processor routine. If the 16-
bit format is used, the ADC can transfer one continuous 16-bit
stream or two intermittent 8-bitstreams.
DIGITAL DESIGN CONSIDERATIONS
Motorola's MC68HC05C4 CMOS MCU may be chosen to
reduce power supply size and cost. The NMOS MCUs may be
used if power consumption is not critical. A V
µF bypass capacitor should be closely mounted to the ADC.
The ML145053 has the end-of-conversion (EOC) signal at
output pin 1 to define when data is ready.
or V 0.1
DD
SS
ANALOG DESIGN CONSIDERATIONS
Analog signal sources with output impedances of less than
1 kΩ may be directly interfaced to the ADC, eliminating the
need for buffer amplifiers. Separate lines connect the V and
ref
V
pins on the ADC with the controllers to provide isolation
AG
from system noise.
Although not indicated in Figure 15, the V and sensor out-
ref
put lines may need to be shielded, depending on their length
and electrical environment. This should be verified during pro-
totyping with an oscilloscope. If shielding is required, a twist-
ed pair or foil-shielded wire (not coax) is appropriate for this
low frequency application. One wire of the pair or the shield
must be V
.
AG
Page 11 of 15
www.lansdale.com
Issue A
ML145053
LANSDALE Semiconductor, Inc.
Legacy Applications Information
Table 2. Programmer's Guide for 16-Bit Transfers:
Input Code
Table 3. Programmer's Guide for 16-Bit Transfers:
Output Code
Input
Address
in Hex
Conversion
Result Without
Offset Removed
Conversion
Result With
Offset Removed
Channel to be
Converted Next
Comment
Value
$0XXX
$1XXX
$2XXX
$3XXX
$4XXX
$5XXX
$6XXX
$7XXX
$8XXX
$9XXX
$AXXX
$BXXX
$CXXX
$DXXX
$EXXX
$FXXX
AN0
AN1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
$0000
$0040
$0080
$00C0
$0100
$0140
$0180
$01C0
$0200
$0240
$0280
$02C0
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
Zero
Zero + 1 LSB
Zero + 2 LSBs
Zero + 3 LSBs
Zero + 4 LSBs
Zero + 5 LSBs
Zero + 6 LSBs
Zero + 7 LSBs
Zero + 8 LSBs
Zero + 9 LSBs
Zero + 10 LSBs
Zero + 11 LSBs
AN2
AN3
AN4
None
None
None
None
None
None
AN5
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Half Scale Test: Output = $8000
Zero Test: Output = $0000
Full Scale Test: Output = $FFC0
Not Allowed
AN6
AN7
$FF40
$FF80
$FFC0
$03FD
$03FE
$03FF
Full Scale – 2 LSBs
Full Scale – 1 LSB
Full Scale
None
None
Not Allowed
+ 5 V
0.1 µF
V
V
ref
DD
0.22µF
CS
µP
SPI PORT
D
in
SCLK
AN0
AN1
ANALOG
SENSORS,
ETC.
D
out
ML145053
ADC
AN2
AN3
EOC
AN4
5 VOLT
REFERENCE
CIRCUIT
V
V
AG
SS
Figure 15. Example Application
Page 12 of 15
www.lansdale.com
Issue A
ML145053
LANSDALE Semiconductor, Inc.
Legacy Applications Information
DIGIGAL + V
ANALOG + V
DO NOT CONNECT
AT IC
V
V
DD
ref
TO
SENSORS,
ETC.
ML145053
5 V
0.22 µF
0.1 µF
SUPPLY
V
V
SS
ANALOG GND
DIGITAL GND
AG
DO NOT CONNECT
AT IC
Figure 16. Alternate Configuration Using the Digital Supply for the Reference Voltage
Compatible Motorola MCUs/MPUs
This is not a complete listing of Motorola's MCUs/MPUs.
Contact your Motorola representative if you need
additional information.
Memory (Bytes)
Instruction
Set
SPI
SCI
Motorla Part
Number
ROM
EEPROM
M6805
2096
2096
4160
4160
8K
–
–
MC68HC05C2
MC68HC05C3
MC68HC05C4
MC68HSC05C4
MC68HSC05C8
MC68HCL05C4
MC68HCL05C8
MC68HC05C8
MC68HC805C4
–
Ye s
Ye s
Ye s
Ye s
Ye s
Ye s
Ye s
–
–
–
–
–
4160
8K
–
–
7700
–
4160
M68000
–
–
–
MC68HC000
1
2
3
4
SPI = Serial Peripheral Interface.
SCI = Serial Communication Interface.
High Speed.
Low Powe.r
Page 13 of 15
www.lansdale.com
Issue A
ML145053
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
PLASTIC DIP
(ML145053CP)
CASE 646-06
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION
AT SEATING PLANE AT MAXIMUM MATERIAL
CONDITION
2. DIMENSION L TO CENTER OF LEADS WHEN FORMED
PARALLEL
14
1
8
B
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
4. ROUNDED CORNERS OPTIONAL
7
INCHES
MIN MAX
0.715 0.770 18.16 19.56
MILLIMETERS
MIN MAX
A
F
DIM
A
B
C
D
F
G
H
J
K
0.240 0.260
0.145 0.185
0.015 0.021
0.040 0.070
0.100 BSC
0.052 0.095
0.008 0.015
0.115 0.135
0.300 BSC
6.10
3.69
0.38
1.02
6.60
4.69
0.53
1.78
L
C
2.54 BSC
1.32
0.20
2.92
2.41
0.38
3.43
J
N
L
M
N
7.62 BSC
K
0°
10°
0°
10°
0.015 0.039
0.39
1.01
H
G
D PSLEAATNIENG
M
Page 14 of 15
www.lansdale.com
Issue A
ML145053
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
SOG PACKAGE
(ML145053-5P)
CASE 751A-03
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982
2. CONTROLLING DIMENSION: MILLIMETER
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION
-A-
14
1
8
7
4. MAXIMUM HOLD PROTRUSION 0.15 (0.006) PER
SIDE
-B-
P 7 PL
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION
M
M
0.25 (0.010)
B
INCHES
MILLIMETERS
MIN MAX
G
F
R X 45°
DIM
A
B
C
D
F
G
J
K
M
P
MIN
MAX
8.75
4.00
1.75
0.49
1.25
C
8.55
3.80
1.35
0.35
0.40
0.337 0.334
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
J
M
SEAT-
ING
K
B
1.27 BSC
0.19
0.10
0°
0.25
0.25
7°
0.008 0.009
0.004 0.009
PLANE
M
S
S
0.25 (0.010)
A
T
0°
7°
5.80
0.25
6.20
0.50
0.228 0.244
0.010 0.019
R
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabil-
ity, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the cus-
tomer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
Page 15 of 15
www.lansdale.com
Issue A
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