ML145051RP [LANSDALE]
10-Bit A/D Converter with Serial Interface - CMOS; 10位A / D转换器，串行接口 - CMOS
| 型号： | ML145051RP |
| 厂家： | 
LANSDALE SEMICONDUCTOR INC. |
| 描述： | 10-Bit A/D Converter with Serial Interface - CMOS |
| 文件： | 总15页 (文件大小：555K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ML145050
ML145051
10-Bit A/D Converter
with Serial Interface - CMOS
Legacy Device: Motorola MC145050, MC145051
These ratio metric 10-bit ADCs have serial interface ports to provide
communication with MCUs and MPUs. Either a 10- or 16-bit format
can be used. The 16-bit format can be one continuous 16-bit stream or
two intermittent 8-bit streams. The converters operate from a single
power supply with no external trimming required. Reference voltages
down to 4.0 V are accommodated.
The ML145050 has the same pin out as the 8-bit ML145040 which
allows an external clock (ADCLK) to operate the dynamic A/D con-
version sequence. The ML145051 has the same pin out as the 8-bit
ML145041 which has an internal clock oscillator and an end-of-con-
version (EOC) output.
P DIP 20 = RP
PLASTIC
CASE 738
SO 20W = -6P
SOG
CASE 751D
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
P DIP 20
SOG 20W
P DIP 20
SOG 20W
MC145050P
MC145050DW
MC145051P
ML145050RP
ML145050-6P
ML145051RP
ML145051-6P
MC145051DW
• 11 Analog Input Channels with Internal Sample-and-Hold
• Operating Temperature Range: – 40 to 125°C
• Successive Approximation Conversion Time:
ML145050 – 21 µs (with 2.1 MHz ADCLK)
ML145051 – 44 µs Maximum
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
• Maximum Sample Rate:
PIN ASSIGNMENT
ML145050 – 38 ks/s
*ADCLK (ML145050); EOC (ML145051)
ML145051 – 20.4 ks/s
• Analog Input Range with 5-Volt Supply: 0 to 5 V
• Monotonic with No Missing Codes
• Direct Interface to Motorola SPI and National MICROWIRE
Serial Data Ports
• Digital Inputs/Outputs are TTL, NMOS, and CMOS Compatible
• Low Power Consumption: 14 mW
AN0
AN1
AN2
AN3
AN4
1
2
3
4
5
20
19
18
17
16
V
DD
*
SCLK
D
in
D
out
AN5
AN6
6
7
15
14
CS
V
ref
• Chip Complexity: 1630 Elements (FETs, Capacitors, etc.)
• See Application Note AN1062 for Operation with QSPI
AN7
AN8
8
9
13
12
V
AG
AN10
V
10
11
AN9
SS
MICROWARE is A Trademark Of National Semiconductor Corp.
Page 1 of 15
www.lansdale.com
Issue B
ML145050, ML145051
LANSDALE Semiconductor, Inc.
BLOCK DIAGRAM
1
2
V
V
ref
14
10-BIT RC DAC
WITH SAMPLE AND HOLD
AG
AN0
AN1
13
3
4
MUX OUT
AN2
AN3
5
AN4
AN5
AN6
6
ANALOG
MUX
SUCCESSIVE APPROXIMATION
REGISTER
7
8
PIN 20 = V
PIN 10 = V
DD
SS
AN7
AN8
9
MUX ADDRESS
REGISTER
11
12
AN9
AN10
INTERNAL
TEST
VOLTAGES
AN11
AN12
AN13
17
16
D
in
DATA REGISTER
D
out
AUTO-ZEROED
COMPARATOR
15
18
19
CS
DIGITAL CONTROL
LOGIC
SCLK
ADCLK (ML145050 ONLY)
EOC (ML145051 ONLY)
19
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
DC Supply Voltage (Referenced to V
DC Reference Voltage
Value
– 0.5 to + 6.0
to V + 0.1
Unit
V
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications
of any voltage higher than maximum rated
voltages to this high-impedance circuit. For
V
DD
)
SS
V
ref
V
V
AG
DD
– 0.1 to V
ref
V
AG
Analog Ground
V
V
SS
V
in
DC Input Voltage, Any Analog or Digital
Input
V
V
– 0.5 to
+ 0.5
V
proper operation, V and V
should be
SS
DD
in out
constrained to the range V
≤(V or V ) ≤
SS
in out
V
.
DD
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either
or V ). Unused outputs must be left
V
out
DC Output Voltage
V
V
– 0.5 to
V
SS
+ 0.5
20
DD
V
SS
open.
I
in
DC Input Current, per Pin
DC Output Current, per Pin
mA
mA
mA
C
DD
I
25
out
I
, I
DC Supply Current, V
Storage Temperature
and V
Pins
SS
50
DD SS
DD
T
stg
– 65 to 150
260
T
L
Lead Temperature, 1 mm from Case for
10 Seconds
C
* MaximumRatingsarethosevaluesbeyondwhichdamagetothedevicemayoccur.Func-
tional operation should be restricted to the Operation Ranges below..
OPERATION RANGES (Applicable to Guaranteed Limits)
Symbol
Parameter
Value
Unit
V
V
DD
DC Supply Voltage, Referenced to V
DC Reference Voltage
4.5 to 5.5
SS
V
ref
V
+ 4.0 to V
AG DD
+ 0.1
V
V
AG
Analog Ground
V – 0.1 to V – 4.0
SS ref
V
V
Analog Input Voltage (See Note)
Digital Input Voltage, Output Voltage
Ambient Operating Temperature
V
to V
V
AI
AG
ref
V , V
in out
V
SS
to V
V
DD
T
– 40 to 125
convert to zero. See V
ref
C
A
NOTE: Analog input voltages greater than V
descriptions.
convert to full scale. Input voltages less than V
and V pin
AG
ref
AG
Page 2 of 15
www.lansdale.com
Issue B
ML145050, ML145051
LANSDALE Semiconductor, Inc.
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V , Full Temperature and Voltage Ranges per Operation Ranges Table, unless otherwise indicated)
SS
Guaranteed
Limit
Symbol
Parameter
Test Condition
Unit
V
IH
Minimum High-Level Input Voltage
(D , SCLK, CS, ADCLK)
in
2.0
V
V
Maximum Low-Level Input Voltage
(D , SCLK, CS, ADCLK)
in
0.8
2.4
V
V
IL
V
OH
Minimum High-Level Output Voltage
(D , EOC)
out
I
I
= – 1.6 mA
= – 20 µA
out
out
V
– 0.1
DD
V
OL
Minimum Low-Level Output Voltage
(D , EOC)
out
I
I
= + 1.6 mA
= 20 µA
0.4
0.1
V
out
out
I
in
Maximum Input Leakage Current
(D , SCLK, CS, ADCLK)
in
V
in
= V
or V
+ 2.5
µA
SS
DD
I
Maximum Three-State Leakage Current (D
Maximum Power Supply Current
)
V
= V
or V
+ 10
2.5
µA
mA
µA
µA
OZ
out
out
SS
DD
I
V
in
= V
or V , All Outputs Open
SS
DD
DD
= V
SS
I
Maximum Static Analog Reference Current (V
)
V
ref
= V , V
100
+ 1
ref
ref
DD AG
to V
DD
I
Maximum Analog Mux Input Leakage Current between all
deselected inputs and any selected input (AN0 AN10)
V
Al
= V
Al
SS
A/D CONVERTER ELECTRICAL CHARACTERISTICS
(Full Temperature and Voltage Ranges per Operation Ranges Table; ML145050: 500 kHz ≤ ADCLK ≤ 2.1 MHz, unless otherwise noted)
Guaranteed
Limit
10
1
Characteristic
Resolution
Definition and Test Conditions
Number of bits resolved by the A/D converter
Unit
Bits
LSB
LSB
Maximum Nonlinearity
Maximum Zero Error
Maximum difference between an ideal and an actual ADC transfer function
Difference between the maximum input voltage of an ideal and an actual
ADC for zero output code
1
Maximum Full-Scale Error
Difference between the minimum input voltage of an ideal and an actual
ADC for full-scale output code
1
LSB
Maximum Total Unadjusted Error
Maximum Quantization Error
Absolute Accuracy
Maximum sum of nonlinearity, zero error, and full-scale error
Uncertainty due to converter resolution
1
LSB
LSB
LSB
1/2
Difference between the actual input voltage and the full-scale weighted
equivalent of the binary output code, all error sources included
1-1/2
Maximum Conversion Time
Total time to perform a single analog-to-digital conversion
ML145050
ML145051
44
ADCLK
cycles
µs
44
Data Transfer Time
Total time to transfer digital serial data into and out of the device
Analog input acquisition time window
10 to 16
SCLK
cycles
Sample Acquisition Time
Minimum Total Cycle Time
6
SCLK
cycles
Total time to transfer serial data, sample the analog input, and perform the
conversion
µs
26
49
ML145050: ADCLK = 2.1 MHz, SCLK = 2.1 MHz
ML145051: SCLK = 2.1 MHz
Maximum Sample Rate
Rate at which analog inputs may be sampled
ML145050: ADCLK = 2.1 MHz, SCLK = 2.1 MHz
ML145051: SCLK = 2.1 MHz
ks/s
38
20.4
Page 3 of 15
www.lansdale.com
Issue B
ML145050, ML145051
LANSDALE Semiconductor, Inc.
AC ELECTRICAL CHARACTERISTICS
(Full Temperature and Voltage Ranges per Operation Ranges Table)
Guaranteed
Limit
Figure
Symbol
Parameter
Unit
1
f
Clock Frequency, SCLK
(10-bit xfer) Min
(11- to 16-bit xfer) Min
(10- to 16-bit xfer) Max)
0
MHz
Note 1
2.1
Note: Refer to t
, t below
wH wL
1
1
1
f
Clock Frequency, ADCLK
Note: Refer to t , t below
Minimum
Maximum
500
2.1
kHz
MHz
wH wL
t
Minimum Clock High Time
ADCLK
SCLK
190
190
ns
ns
wH
t
Minimum Clock Low Time
ADCLK
SCLK
190
190
wL
1, 7
1, 7
2, 7
2, 7
t
, t
Maximum Propagation Delay, SCLK to D
125
10
ns
ns
ns
PLH PHL
out
t
h
Minimum Hold Time, SCLK to D
out
t
, t
PLZ PHZ
Maximum Propagation Delay, CS to D
Maximum Propagation Delay, CS to D
High-Z
150
out
out
t
, t
PZL PZH
Driven
ML145050
ML145051
2 ADCLK cycles + 300
2.3
ns
µs
3
t
Minimum Setup Time, D to SCLK
in
100
0
ns
ns
ns
su
3
4, 7, 8
5
t
t
Minimum Hold Time, SCLK to D
h
d
in
Maximum Delay Time, EOC to D
out
Minimum Setup Time, CS to SCLK
(MSB)
ML145051
100
t
su
ML145050
ML145051
2 ADCLK cycles + 425
2.425
ns
µs
–
–
t
Minimum Time Required Between 10th SCLK Falling
Edge ( 0.8 V) and CS to Allow a Conversion
ML145050
ML145051
44
Note 2
ADCLK
cycles
CSd
t
Maximum Delay Between 10th SCLK Falling Edge
ML145050
ML145051
36
ADCLK
cycles
µs
CAs
(
2 V) and CS to Abort a Conversion
9
0
5
6, 8
1
t
h
Minimum Hold Time, Last SCLK to CS
Maximum Propagation Delay, 10th SCLK to EOC
Maximum Input Rise and Fall Times
ns
t
ML145051
2.35
µs
PHL
t , t
SCLK
ADCLK
D , CS
in
1
250
10
ms
ns
µs
r f
1, 4, 6 – 8
–
t
, t
Maximum Output Transition Time, Any Output
Maximum Input Capacitance
300
ns
TLH THL
C
AN0 – AN10
55
15
pF
in
ADCLK, SCLK, CS, D
in
–
C
Maximum Three-State Output Capacitance
D
15
pF
out
out
NOTES:
1. After the 10th SCLK falling edge (≤ 2 V), at least 1 SCLK rising edge (≥ 2 V) must occur within 38 ADCLKs (ML145050) or 18.5 µs
(ML145051).
2. On the ML145051, a CS edge may be received immediately after an active transition on the EOC pin.
Page 4 of 15
www.lansdale.com
Issue B
ML145050, ML145051
LANSDALE Semiconductor, Inc.
SWITCHING WAVEFORMS
t
t
wH
wL
t
t
r
f
2.0 V
SCLK
0.8 V
2.0 V
CS
1/f
0.8 V
t
, t
PLH PHL
t
, t
PZH PZL
t
h
t
90%
10%
, t
PHZ PLZ
2.4 V
0.4 V
D
out
2.4 V
0.4 V
D
out
t
, t
TLH THL
Figure 1.
Figure 2.
t
TLH
2.4 V
EOC
VALID
0.4 V
2.0 V
0.8 V
D
in
t
d
2.4 V
0.4 V
t
h
t
su
D
out
VALID MSB
2.0 V
0.8 V
SCLK
NOTE: D
is driven only when CS is active (low).
out
Figure 3.
Figure 4.
10TH
CLOCK
2.0 V
SCLK
EOC
CS
0.8 V
0.8 V
t
PHL
t
t
h
su
2.4 V
FIRST
LAST
CLOCK
0.4 V
SCLK
0.8 V
0.8 V
CLOCK
t
THL
Figure 5.
Figure 6.
V
V
DD
DD
TEST
POINT
TEST
POINT
2.18 k
2.18 k
D
out
EOC
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
12 k
100 pF
12 k
50 pF
Figure 7. Test Circuit
Figure 8. Test Circuit
Page 5 of 15
www.lansdale.com
Issue B
ML145050, ML145051
LANSDALE Semiconductor, Inc.
PIN DESCRIPTIONS
D
out
Serial Data Output of the A/D Conversion Result(Pin 16)
DIGITAL INPUTS AND OUTPUT
This output is in the high-impedance state when CS is in
active high. When the chip recognizes a valid active low on
The various serial bit-stream formats for the ML145050/51
are illustrated in the timing diagrams of Figures 9 through 14.
Table 1 assists in selection of the appropriate diagram. Note
that the ADCs accept 16 clocks which makes them SPI (Serial
Peripheral Interface) compatible.
CS, D
is taken out of the high-impedance state and is driv-
out
en with the MSB of the previous conversion result. (For the-
first transfer after power-up, data on D is undefined for the
out
changes to the second most
entire transfer.) The value on D
out
significant result bit upon the first falling edge of SCLK. The
remaining result bits are shifted out in order, with the LSB
Table 1. Timing Diagram Selection
appearing on D
upon the ninth falling edge of SCLK. Note
out
that the order of the transfer is MSB to LSB. Upon the 10th
falling edge of SCLK, D is immediately driven low (if
No. of Clocks in Using
Serial Transfer
Interval
Figure
No.
Serial Transfer
CS
out
10
10
Yes
No
Don't Care
Don't Care
Shorter than Conversion
Shorter than Conversion
Longer than Conversion
Longer than Conversion
9
allowed by CS) so that transfers of more than 10 SCLKs read
zeroes as the unused LSBs.
When CS is held active low between transfers, D
en from a low level to the MSB of the conversion result for
three cases: Case 1 – upon the 16th SCLK falling edge if the
transfer is longer than the conversion time (Figure 14); Case 2
– upon completion of a conversion for a 16-bit transfer interval
shorter than the conversion (Figure 12); Case 3– upon comple-
tion of a conversion for a 10-bit transfer (Figure 10).
10
11
12
13
14
11 to 16
16
Yes
No
is driv-
out
11 to 16
16
Yes
No
CS
Active-Low Chip Select Input (Pin 15)
Chip select initializes the chip to perform conversions and
provides 3-state control of the data output pin (D ). While
out
Din
inactive high, CS forces D
to the high-impedance state and
out
Serial Data Input (Pin 17)
disables the data input (D ) and serial clock (SCLK) pins. A
in
The four-bit serial input stream begins with the MSB of the
analog mux address (or the user test mode) that is to be con-
verted next. The address is shifted in on the first four rising
edges of SCLK. After the four mux address bits have been
received, the data on D is ignored for the remainder of the
present serial transfer. See Table 2 in Applications Information.
high-to-low transition on CS resets the serial dataport and syn-
chronizes it to the MPU data stream. CS can remain active
during the conversion cycle and can stay in the active low state
for multiple serial transfers or CS can be in active high after
each transfer. If CS is kept active low between transfers, the
length of each transfer is limited to either 10 or 16 SCLK
cycles. If CS is in the inactive high state between transfers,
each transfer can be anywhere from 10 to16 SCLK cycles
long. See the SCLK pin description for a more detailed discus-
sion of these requirements.
in
SCLK
Serial Data Clock (Pin 18)
This clock input drives the internal I/O state machine to per-
On the ML145050/51 spurious chip selects caused by system form three major functions: (1) drives the data shift registers to
noise are minimized by the internal circuitry.
simultaneously shift in the next mux address from the D pin
in
Any transitions on the ML145050 CS pin are recognized as
valid only if the level is maintained for a setup time plus two
falling edges of ADCLK after the transition.
and shift out the previous conversion result on the D
pin,
out
(2) begins sampling the analog voltage onto the RCDAC as
soon as the new mux address is available, and (3) transfers
control to the A/D conversion state machine (driven by
Transitions on the ML145051 CS pin are recognized as valid
only if the level is maintained for about 2 ms after the transition. ADCLK) after the last bit of the previous conversion result has
been shifted out on the D pin.
out
NOTE
The serial data shift registers are completely static, allowing
SCLK rates down to the DC. There are some cases, however,
that require a minimum SCLK frequency as discussed later in
this section. SCLK need not be synchronous to ADCLK. At
least ten SCLK cycles are required for each simultaneous data
transfer. If the 16-bit format is used, SCLK can be one contin-
uous 16-bit stream or two intermittent 8-bit streams. After the
serial port has been initiated to perform a serial transfer*, the
new mux address is shifted in on the first
If CS is inactive high after the 10th SCLK cycle-
and then goes active low before the A/D conversion
is complete, the conversion is aborted and the chip
enters the initial state, ready for another serial trans-
fer/conversion sequence. At this point, the output
data register contains the result from the conversion
before the aborted conversion. Note that the last
step of the A/D conversion sequence is to update the
output data register with the result. Therefore, if CS
goes active low in an attempt to abort the conver-
sion too close to the end of the conversion
*The serial port can be initiated in three ways: (1) a recog-
nized CS falling edge, (2) the end of an A/D conversion if the
port is perform-ing either a 10-bit or a 16-bit “shorter-than-
conversion” transfer with CS active low between transfers,
and (3) the 16th falling edge of SCLK if the port is perform-
ing 16-bit “longer-than-conversion” transfers with CS active
low between transfers.
sequence, the result register may be corrupted and
the chip could be thrown out of sync with the
processor until CS is toggled again (refer to the AC
Electrical Characteristics in the spec tables).
Page 6 of 15
www.lansdale.com
Issue B
ML145050, ML145051
LANSDALE Semiconductor, Inc.
dress register. AN1 is addressed by $1, AN2 by $2, 0, AN10 by
$A. Table 2 shows the input format for a 16-bit stream. The
mux features a break-before-make switching structure to mini-
mize noise injection into the analog inputs. The source resist-
ance driving these inputs must be ≤1 kΩ.
four rising edges of SCLK, and the previous 10-bit conversion
result is shifted out on the first nine falling edges of SCLK.
After the fourth rising edge of SCLK, the new mux address is
available; therefore, on the next edge of SCLK (the fourth
falling edge), the analog input voltage on the selected mux
input begins charging the RC DAC and continues to do so until
the tenth falling edge of SCLK. After this tenth SCLK edge,
the analog input voltage is disabled from the RC DAC and the
RC DAC begins the “hold” portion of the A/D conversion
sequence. Also upon this tenth SCLK edge, control of the
internal circuitry is transferred to ADCLK which drives the
successive approximation logic to complete the conversion. If
16 SCLK cycles are used during each transfer, then there is a
constraint on the minimum SCLK frequency. Specifically,
During normal operation, leakage currents through the ana-
log mux from unselected channels to a selected channel and
leakage currents through the ESD protection diodes on the
selected channel occur. These leakage currents cause an offset
voltage to appear across any series source resistance on the
selected channel. Therefore, any source resistance greater than
1 kΩ (Lansdale test condition) may induce errors in excess of
guaranteed specifications.
There are three tests available that verify the functionality of
there must be at least one rising edge on SCLK before the A/D all the control logic as well as the successive approximation
conversion is complete. If the SCLK frequency is too low and
a rising edge does not occur during the conversion, the chip is
thrown out of sync with the processor and CS needs to be tog-
comparator. These tests are performed by addressing $B, $C,
or $D and they convert a voltage of (V + V )/2,V , or
ref AG AG
V
, respectively. The voltages are obtained internally by sam-
ref
gled in order to restore proper operation. If 10 SCLKs are used pling V or V
onto the appropriate elements of the RC
ref AG
per transfer, then there is no lower frequency limit on SCLK.
Also note that if the ADC is operated such that CS is inactive
high between transfers, then the number of SCLK cycles per
transfer can be anything between 10 and 16 cycles, but the
“rising edge” constraint is still in effect if more than 10
SCLKs are used. (If CS stays active low for multiple transfers,
the number of SCLK cycles must be either 10 or 16.)
DAC during the sample phase. Addressing $B, $C, or $D pro-
duces an output of $200 (half scale), $000, or $3FF (full
scale), respectively, if the converter is functioning properly.
However, deviation from these values occurs in the presence of
sufficient system noise (external to the chip) on V , V
,
DD SS
V
, or V .
ref AG
POWER AND REFERENCE PINS
V and V
ADCLK
A/D Conversion Clock Input (Pin 19, ML145050 Only)
SS
DD
Device Supply Pins (Pins 10 and 20)
This pin clocks the dynamic A/D conversion sequence, and
may be asynchronous to SCLK. Control of the chip passes to
ADCLK after the tenth falling edge of SCLK. Control of the
chip is passed back to SCLK after the successive approxima-
tion conversion sequence is complete (44 ADCLK cycles), or
after a valid chip select is recognized. ADCLK also drives the
V
is normally connected to digital ground; V
is con-
DD
SS
nected to a positive digital supply voltage. Low frequency
(V – V ) variations over the range of 4.5 to 5.5 volts do
DD
SS
not affect the A/D accuracy. (See the Operations Ranges Table
for restrictions on V and V relative to V and V .)
ref AG SS
DD
CS recognition logic. The chip ignores transitions on CS unless Excessive inductance in the V
or V lines, as on automat-
DD
SS
the state remains for a setup time plus two falling edges of
ADCLK. The source driving ADCLK must be free running.
ic test equipment, may cause A/D offsets > 1 LSB. Use of a
0.1
µF bypass capacitor across these pins is recommended.
EOC
V
and V
ref
AG
End-of-Conversion Output (Pin 19, ML145051 Only)
Analog Reference Voltage Pins (Pins 13 and 14)
EOC goes low on the tenth falling edge of SCLK. A low-to-
high transition on EOC occurs when the A/D conversion is
complete and the data is ready for transfer.
Analog reference voltage pins which determine the lower
and upper boundary of the A/D conversion. Analog input volt-
ages ≤ V produce a full scale output and input voltages ≤
ref
V
AG
produce an output of zero. CAUTION: The analog input
ANALOG INPUTS AND TEST MODE
voltage must be ≥ V and ≤ V . The A/D conversion result
SS
DD
is ratio metric to V – V . V and V
ref AG ref AG
must be as noise-
AN0 through AN10
Analog Multiplexer Inputs (Pins 1 – 9, 11, 12)
free as possible to avoid degradation of the A/D conversion.
Ideally, V and V should be single-point connected to the
ref
AG
voltage supply driving the system's transducers. Use of a 0.22
The input AN0 is addressed by loading $0 into the mux ad-
µF bypass capacitor across these pins is strongly urged.
Page 7 of 15
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Issue B
ML145050, ML145051
LANSDALE Semiconductor, Inc.
CS
HIGH IMPEDANCE
D9
D
D9 – MSB
1
D8
A2
D7
A1
D6
D5
D4
D3
D2
D1
D0
out
2
3
4
5
6
7
8
9
10
1
SCLK
SAMPLE ANALOG INPUT
D
in
A3
A0
A3
MSB
EOC
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
A/D CONVERSION
INTERVAL
INITIALIZE
RE-INITIALIZE
Figure 9. Timing for 10-Clock Transfer Using CS*
MUST BE HIGH ON POWER UP
CS
D
D9 – MSB
D8
A2
D7
A1
D6
D5
D4
D3
D2
D1
D0
D9
out
LOW LEVEL
SCLK
1
2
3
4
5
6
7
8
9
10
1
SAMPLE ANALOG INPUT
A3
A0
A3
D
in
MSB
EOC
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
A/D CONVERSION
INTERVAL
INITIALIZE
Figure 10. Timing for 10-Clock Transfer Not Using CS*
NOTES:
1. D9, D8, D7, 0 , D0 = the result of the previous A/D conversion.
2. A3, A2, A1, A0 = the mux address for the next A/D conversion.
* This figure illustrates the behavior of the ML145051. The ML145050 behaves identically except there is no EOC signal and the conversion time
is 44 ADCLK cycles (user-controlled time).
Page 8 of 15
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Issue B
ML145050, ML145051
LANSDALE Semiconductor, Inc.
Page 9 of 15
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Issue B
ML145050, ML145051
LANSDALE Semiconductor, Inc.
Page 10 of 15
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Issue B
ML145050, ML145051
LANSDALE Semiconductor, Inc.
Legacy Applications Information
DESCRIPTION
and electrical environment. This should be verified during pro-
totyping with an oscilloscope. If shielding is required, a twist-
ed pair or foil-shielded wire (not coax) is appropriate for this
low frequency application. One wire of the pair or the shield
This example application of the ML145050/ML145051
ADCs interfaces three controllers to a microprocessor and
processes data in real-time for a video game. The standard joy-
stick X-axis (left/right) and Y-axis (up/down) controls as well
as engine thrust controls are accommodated.
Figure 15 illustrates how the ML145050/ML145051 is used
as a cost-effective means to simplify this type of circuit design.
Utilizing one ADC, three controllers are interfaced to a CMOS
or NMOS microprocessor with a serial peripheral interface
(SPI) port. Processors with National Semiconductor's
MICROWIRE serial port may also be used. Full duplex opera-
tion optimizes throughput for this system.
must be V
.
AG
A reference circuit voltage of 5 volts is used for this applica-
tion. The reference circuitry may be as simple as tying V to
AG
system ground and V to the system's positive supply. (See
ref
Figure 16.) However, the system power supply noise may
require that a separate supply be used for the voltage reference.
This supply must provide source current forV as well as
ref
current for the controller potentiometers.
A bypass capacitor of approximately 0.22 µF across the V
ref
and V
pins is recommended. These pins are adjacent on the
AG
ADC package which facilitates mounting the capacitor very
close to the ADC.
DIGITAL DESIGN CONSIDERATIONS
Motorola's MC68HC05C4 CMOS MCU may be chosen to
reduce power supply size and cost. The NMOS MCUs maybe
SOFTWARE CONSIDERATIONS
used if power consumption is not critical. A V
or V 0.1
The software flow for acquisition is straight forward. The
DD
SS
µF bypass capacitor should be closely mounted to the ADC.
Both the ML145050 and ML145051 accommodate all the
analog system inputs. The ML145050, when used with a 2
MHz MCU, takes 27 µs to sample the analog input, perform
the conversion, and transfer the serial data at 2 MHz. Forty-
four ADCLK cycles (2 MHz at input pin 19) must be provided
and counted by the MCU before reading the ADC results. The
ML145051 has the end-of-conversion (EOC) signal (at output
pin 19) to define when data is ready, but has a slower 49 µs
cycle time. However, the 49 µs is constant for serial data rates
of 2 MHz independent of the MCU clock frequency. Therefore,
the ML145051 may be used with the CMOS MCU operating at
reduced clock rates to minimize power consumption without
severely sacrificing ADC cycle times, with EOC being used to
generate an interrupt. (The ML145051 may also be used with
MCUs which do not provide a system clock.)
nine analog inputs, AN0 through AN8, are scanned by reading
the analog value of the previously addressed channel into the
MCU and sending the address of the next channel to be read to
the ADC, simultaneously.
If the design is realized using the ML145050, 44 ADCLK
cycles (at pin 19) must be counted by the MCU to allow time
for A/D conversion. The designer utilizing the MC145051 has
the end-of-conversion signal (at pin 19) to define the conver-
sion interval. EOC may be used to generate an interrupt, which
is serviced by reading the serial data from the ADC. The soft-
ware flow should then process and format the data, and transfer
the information to the video circuitry for updating the display.
When these ADCs are used with a 16-bit (2-byte) transfer,
there are two types of offsets involved. In the first type of off-
set, the channel information sent to the ADCs is offset by 12
bits. That is, in the 16-bit stream, only the first 4 bits (4 MSBs)
contain the channel information. The balance of the bits are
don't cares. This results in 3 don't-care nibbles, as shown in
Table 2. The second type of offset is in the conversion result
returned from the ADCs; this is offset by 6 bits. In the 16-bit
stream, the first 10 bits (10 MSBs) contain the conversion
results. The last 6 bits are zeroes. The hexadecimal result is
shown in the first column of Table 3. The second column shows
the result after the offset is removed by a microprocessor rou-
tine. If the 16-bit format is used, these ADCs can transfer one
continuous 16-bit stream or two intermittent 8-bitstreams.
ANALOG DESIGN CONSIDERATIONS
Controllers with output impedances of less than 1 kΩ maybe
directly interfaced to these ADCs, eliminating the need for
buffer amplifiers. Separate lines connect the V and V
ref
AG
pins on the ADC with the controllers to provide isolation from
system noise.
Although not indicated in Figure 15, the V and controller
ref
output lines may need to be shielded, depending on their length
Page 11 of 15
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Issue B
ML145050, ML145051
LANSDALE Semiconductor, Inc.
Legacy Applications Information
Table 2. Programmer's Guide for 16-Bit Transfers:
Input Code
Table 3. Programmer's Guide for 16-Bit Transfers:
Output Code
Input
Address
in Hex
Conversion
Result Without
Offset Removed
Conversion
Result With
Offset Removed
Channel to be
Converted Next
Comment
Value
$0XXX
$1XXX
$2XXX
$3XXX
$4XXX
$5XXX
$6XXX
$7XXX
$8XXX
$9XXX
$AXXX
$BXXX
$CXXX
$DXXX
$EXXX
$FXXX
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
Pin 9
Pin 11
Pin 12
$0000
$0040
$0080
$00C0
$0100
$0140
$0180
$01C0
$0200
$0240
$0280
$02C0
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
Zero
Zero + 1 LSB
Zero + 2 LSBs
Zero + 3 LSBs
Zero + 4 LSBs
Zero + 5 LSBs
Zero + 6 LSBs
Zero + 7 LSBs
Zero + 8 LSBs
Zero + 9 LSBs
Zero + 10 LSBs
Zero + 11 LSBs
AN9
AN10
AN11
AN12
AN13
None
None
Half Scale Test: Output = $8000
Zero Test: Output = $0000
Full Scale Test: Output = $FFC0
Not Allowed
$FF40
$FF80
$FFC0
$03FD
$03FE
$03FF
Full Scale – 2 LSBs
Full Scale – 1 LSB
Full Scale
Not Allowed
+ 5 V
0.1 µF
0.22 µF
V
V
DD
ref
LEFT/RIGHT
CS
AN0
AN1
AN2
µ
P
UP/DOWN
D
in
CONTROLLER
#1
ENGINE THRUST
SCLK
SPI PORT
D
out
ADCLK
ADC
ML145050
LEFT/RIGHT
UP/DOWN
AN3
AN4
AN5
CONTROLLER
#2
(ML145050)
ENGINE THRUST
EOC
ML145051
(ML145051)
LEFT/RIGHT
UP/DOWN
5 VOLT
REFERENCE
CIRCUIT
AN6
AN7
AN8
CONTROLLER
#3
AN9
VIDEO
CIRCUITRY
ENGINE THRUST
AN10
V
V
AG
SS
VIDEO
MONITOR
Figure 15. Joystick Interface
Page 12 of 15
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Issue B
ML145050, ML145051
LANSDALE Semiconductor, Inc.
Legacy Applications Information
DIGITAL + V
ANALOG + V
DO NOT CONNECT
AT I C
V
V
DD
ref
TO
5 V
SUPPLY
ML145050
ML145051
0.22
µF
0.1 µF
JOYSTICKS
V
V
SS
ANALOG GND
DIGITAL GND
AG
DO NOT CONNECT
AT I C
Figure 16. Alternate Configuration Using the Digital Supply for the Reference Voltage
Compatible Motorola MCUs/MPUs
This is not a complete listing of Motorola's MCUs/MPUs.
Contact your Motorola representative if you need
additional information.
Memory (Bytes)
Instruction
Set
SPI
SCI
Device
Number
ROM
EEPROM
M6805
2096
2096
4160
4160
8K
4160
8K
7700
–
–
–
–
–
–
–
–
–
4160
–
MC68HC05C2
MC68HC05C3
MC68HC05C4
MC68HSC05C5
MC68HSC05C8
MC68HCL05C4
MC68HCL05C8
MC68HC05C8
MC68HC805C5
Yes
Yes
Yes
Yes
Yes
Yes
Yes
–
M68000
–
–
–
MC68HC000
SPI = Serial Peripheral Interface.
SCI = Serial Communication Interface.
High Speed.
✟
✟
Low Power.
Page 13 of 15
www.lansdale.com
Issue B
ML145050, ML145051
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
P DIP 20 = RP
(ML145050RP, ML145051RP)
CASE 738-03
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
20
1
11
0
B
1
C
L
INCHES
MIN MAX
1.070 25.66
MILLIMETERS
DIM
A
B
C
D
E
MIN
MAX
27.17
6.60
4.57
0.55
1.010
0.240
0.150
0.015
0.260
0.180
0.022
6.10
3.81
0.39
-T-
SEATING
PLANE
K
M
0.050 BSC
1.27 BSC
1.27
0.050
0.070
1.77
F
E
N
G
J
K
L
M
N
0.100 BSC
2.54 BSC
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
G
F
J 20 PL
0.300 BSC
7.62 BSC
0°
D 20 PL
M
M
0.25 (0.010)
T
B
0°
15°
15°
0.020
0.040
0.51
1.01
M
M
0.25 (0.010)
T
A
Page 14 of 15
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Issue B
ML145050, ML145051
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
SOG 20W = -6P
(ML145050-6P, ML145051-6P)
CASE 751D-04
-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
20
11
-B-
P 10 PL
M
M
0.010 (0.25)
B
1
1
0
D 20 PL
J
MILLIMETERS
INCHES
M
S
S
0.010 (0.25)
T
B
A
DIM
A
B
C
D
F
G
J
MIN
12.65
7.40
MAX
12.95
7.60
MIN
MAX
0.499
0.292
0.093
0.014
0.020
0.510
0.299
0.104
0.019
0.035
F
2.35
0.35
0.50
2.65
0.49
0.90
R X 45°
1.27 BSC
0.050 BSC
0.25
0.10
0°
0.32
0.25
7°
0.010
0.004
0°
0.012
0.009
7°
K
M
P
C
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
-T-
R
M
SEATING
PLANE
G 18 PL
K
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabili-
ty, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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Issue B
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