ML145145VP [LANSDALE]
4-Bit Data Bus Input PLL Frequency Synthesizer; 4位数据总线输入锁相环频率合成器
| 型号： | ML145145VP |
| 厂家： | 
LANSDALE SEMICONDUCTOR INC. |
| 描述： | 4-Bit Data Bus Input PLL Frequency Synthesizer |
| 文件： | 总12页 (文件大小：1804K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ML145145
4–Bit Data Bus Input PLL
Frequency Synthesizer
INTERFACES WITH SINGLE–MODULUS PRESCALERS
Legacy Device: Motorola MC145145-2
The ML145145 is programmed by a 4–bit input, with
strobe and address lines. The device features consist of a
reference oscillator, 12–bit programmable reference
divider, digital phase detector, 14–bit programmable
divide–by–N counter, and the necessary latch circuitry for
accepting the 4–bit input data.
P DIP 18 = VP
PLASTIC DIP
CASE 707
18
1
SOG 20 = -6P
SOG PACKAGE
20
CASE 751D
• Operating Temperature Range: T – 40 to 85°C
A
1
• Low Power Consumption Through the Use of CMOS
Technology
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
• 3.0 to 9.0 V Supply Range
P DIP 18
SOG 20
MC145145P1
ML145145VP
MC145145DW2 ML145145-6P
• Single Modulus 4–Bit Data Bus Programming
• ÷N Range = 3 to 16,383, ÷R Range = 3 to 4,095
• “Linearized” Digital Phase Detector Enhances
Transfer Function Linearity
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
• Two Error Signal Options:
Single–Ended (Three–State)
Double–Ended
PIN ASSIGNMENTS
PLASTIC DIP
D1
D0
1
2
3
4
5
6
18
17
16
15
14
13
D2
D3
f
REF
in
out
BLOCK DIAGRAM
V
V
φ
φ
SS
R
REF
out
DD
V
OSC
LD
PD
ST
A2
in
OSC
7
8
9
12
11
10
out
A0
out
OSC
in
12–BIT R COUNTER
A1
OSC
out
LOCK
DETECT
LATCH 4 LATCH 5 LATCH 6
LD
PD
SOG PACKAGE
D1
D0
1
2
20
19
D2
D3
D0
D1
D2
f
PHASE
DETECTOR
A
NC
3
4
18
17
REF
R
out
out
D3
A0
A1
f
φ
f
in
R
V
LATCH
CONTROL
CIRCUITRY
V
V
5
6
16
15
φ
V
SS
LATCHES
LD
PD
ST
A2
NC
DD
A2
ST
OSC
in
7
14
13
12
11
out
φ
V
PHASE
DETECTOR
B
LATCH 0
LATCH 1 LATCH 2 L3
OSC
8
out
A0
φ
R
9
f
in
14–BIT N COUNTER
A1
10
NC = NO CONNECTION
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PIN DESCRIPTIONS
latch, the falling edge of strobe latches data into the latch. This
pin should normally be held low to avoid loading latches with
invalid data.
INPUT PINS
D0 – D3
OUTPUT PINS
Data Inputs (PDIP – Pins 2, 1, 18, 17; SOG – Pins 2, 1, 20, 19)
PDout
Information at these inputs is transferred to the internal
latches when the ST input is in the high state. D3 is most sig-
nigicant bit.
Single–Ended Phase Detector output (PDIP – Pin 12, SOG
– Pin 14)
Three–state output of phase detector for use as loop–error
signal.
f
in
Frequency Input (PDIP – Pin 3, SOG – Pin 4)
Frequency f > f or f Leading: Negative Pulses
V
V
R
R
R
V
V
Input to ÷N portion of synthesizer. f is typically derived
in
Frequency f < f or f Lagging: Positive Pulses
from the loop VCO and is ac couples. For larger amplitude sig-
nals (standard CMOS – logic levels) dc coupling may be used.
Frequency f = f and Phase Coincidence: High–Impedance
V
State
OSCin/OSCout
Reference Oscillator Input/Output (PDIP – Pins 6, 7; SOG
– Pins 7, 8)
LD
Lock Detector Signal (PDIP – Pin 13, SOG – Pin 15)
High level when loop is locked (f , f of same phase and
R V
frequency). Pulses low when loop is out of lock.
φV, φR
These pins form an on–chip reference oscillator when con-
nected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be con-
nected from OSC to ground and OSC
may also serve as input for an externally–generated reference
signal. This signal is typically AC coupled to OSC but for
larger amplitude signals (standard CMOS–logic levels) DC
coupling may also be used. In the external refrence mode, no
Phase Detect or Outputs (PDIP – Pin 12, SOG – Pin 14)
These phase detector outputs can be combined externally for
a loop–error signal. A single–ended output is also available for
to ground. OSC
in
out
in
this purpose (see PD ).
out
in
If frequency f is greater than f or if the phase of f is
V
R
V
leading, then error information is provided by φV pulsing low.
φR remains essentially high.
connection is required to OSC
.
out
If the frequency of f – f and both are in phase, then both
V
R
A0 – A2
φV and φR remain high except for a small minimum time peri-
Address Inputs (PDIP – Pins 8, 9, 10; SOG – Pins 9, 10, 12)
od when both pulse low in phase.
A0, A1 and A2 are used to define which latch receives the
information on the data input lines. The addresses refer to the
following latches:
REF
out
Buffered Reference Output (DIP – Pin 16, SOG – Pin 18)
Buffered output of on–chip reference oscillator or externally
provided reference–input signal.
POWER SUPPLY PINS
V
SS
Ground (PDIP – Pin 4, SOG – Pin 5)
Circuit Ground
V
DD
Positive Power Supply (PDIP – Pin 5, SOG – Pin 6)
ST
The positive supply voltage may range from 3.0 to 9.0 V
Strobe Transfer (PDIP – Pin 11, SOG – Pin 13)
with respect to V
.
SS
The rising edge of strobe transfers data into the addressed
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CRYSTAL OSCILLATOR CONSIDERATIONS
portion of all of C1 variable. The crystal and associated com-
ponents must be located as close as possible to the OSC and
in
The following options may be considered to provide a refer-
ence frequency to Motorola’s CMOS frequency sytnthesizers.
OSC
pins to minimize distortion, stray capacitance, stray
out
inductance and startup stablilization time. In some cases, stray
capacitance should be added to the value for C and C
.
out
Use of a Hybrid Crystal Oscillator
in
Power is dissipated in the effective series resistance of the
Commercially available temperature–compensated crystal
oscillators (TCXOs) or crystal–controlled data clock oscilla-
tors provide very stable reference frequencies. An oscillator
capable of sinking and sourcing 50 µA at CMOS logic levels
crystal R , in Figure 9. The drive level specified by the crystal
e
manufacturer is the maximum stress that a crystal can with-
stand without damage or excessive shift in frequency. R1 in
Figure 7 limits the drive level. The use of R1 may not be nec-
essary in some cases (i.e., R1 = 0 Ω)
may be direct or DC coupled to OSC . In general, the highest
in
frequency capability is obtained utilizing a direct–coupled
To verify that the maximum dc supply voltage does not over-
drive the crystal, monitor the output frequency as a function of
square wave having a rail–to–rail (V
swing. If the oscillator does not have CMOS logic levels on the
outputs, capacitive or AC coupling to OSC may be used.
to V ) voltage
DD
SS
voltage at OSC . (Care should be taken to minimize load-
out
in
ing.) The frequency should increase very slightly as the dc sup-
ply voltage is increased. An overdriven crystal will decrease in
frequency or become unstable with an increase in supply volt-
age. The operating supply voltage must be reduced or R1 must
be increased in value if the overdriven condition exists. The
user should note that the oscillator start–up time is proportion-
al to the value of R1.
OSC , and unbuffered output, should be left floating.
out
For additional information about TCXOs and data clock
oscillators, please consult the latest version of the eem
Electronic Engineers Master Catalog, the Gold Book, or simi-
lar publications.
Design an Off–Chip Reference
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufactureres have developed
expertise in CMOS oscillator design with crystals. Discussions
with such manufacturers can prove very helpful (see Table 1).
The user may design an off–chip crystal oscillator using ICs
specifically developed for crystal oscillator applications, such
as the ML12061 MECL device. The reference signal from the
MECL device is ac coupled to OSC . For large amplitude sig-
in
nals (standard CMOS logic levels), DC coupling is used.
OSC , an unbuffered output, should be left floating. In gen-
out
eral, the highest freqency capability is obtained with a
direct–coupled square wave having rail–to–rail voltage swing.
Use of the On–Chip Oscillator Circuitry
The on–chip amplifier (a digital inverter) along with an appro-
priate crystal may be used to provide a reference source fre-
quency. A fundamental mode crystal, parallel resonant at the
desired operating frequency, should be connected as shown in
Figure 7.
For V
= 5.0 V, the crystal should be specified for a load-
DD
ing capactitanc. C , which does not exceed 32 pf for frequen-
L
cies to approximately 8.0 to 15 MHz and 10 pF for higher fre-
quencies. These are guidelines that provide a reasonable com-
promise between IC capacitance, drive capability, swamping
c–variations in stray and IC input/output capacitance, and real-
istic C values. The shunt load capacitance. C , presented
L
L
across the crystal can be estimated to be:
where
Cin = 5.0 pf (see Figure 8)
Cout = 6.0 pf (see Figure 8)
Ca = 1.0 pf (see Figure 8)
CO = the crystal’s holder capacitance (see Figure 9)
C1 and C2 = external capacitors (see Figure 7)
The oscillator can be “trimmed” on–frequency by making a
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RECOMMENDED READING
processor–controlled system this strobe input is accessed when
the PLL is addressed. The remaining data and address inputs
will directly interface to the microprocessor’s data and address
buses.
The ÷ R programability is used to advantage in Figure 10.
Here, the nominal ÷ R value is 3667, but by programming
small changes in this value, fine tuning is accomplised. Better
tuning resolution is achievable with this method than by chang-
ing the ÷ N due to the use of the large fixed prescaling value
of ÷ 256 provided by the ML12079.
The two–loop synthesizer, in Figure 11, takes advantage of
these features to control the phase–locked loop with a minu-
mum of dedicated lines while preserving optimal loop per-
formance. Both 25 Hz and 100 Hz steps are provided while the
relatively large reference frequencies of 10 Khz or 10.1 kHz
are maintained.
Technical Note TN–24, Stated Corp.
Technical Note TN–\7, Stated Corp.
E. Hafner, “The Piezoelectric Crystal Unit – Definitions and
Method of Measurement”, Proc IEEE, Vol. 57, No. 2 Feb.,
1969
D. Kemper, L. Rosine, “Quartz Crystals for Frequency
Control”, Electro–Technology, June, 1969.
P.J. Ottowitz, “A Guide to Crystal Selection”, Electronic
Design, May, 1966.
LEGACY APPLICATIONS
The features of the ML145145 permit bus operation with a
dedicated wire needed only for the strobe input. In a micro-
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OUTLINE DIMENSIONS
P DIP 18 = VP
(ML145145VP)
CASE 707–02
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
18
10
9
B
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
1
MILLIMETERS
INCHES
DIM
A
B
C
D
F
MIN
22.22
6.10
3.56
0.36
1.27
MAX
23.24
6.60
4.57
0.56
1.78
MIN
MAX
A
0.875
0.240
0.140
0.014
0.050
0.915
0.260
0.180
0.022
0.070
L
C
G
H
J
K
L
M
N
2.54 BSC
1.02
0.20
2.92
1.52
0.30
3.43
K
N
J
F
D
M
SEATING
PLANE
7.62 BSC
H
G
0°
15°
0.51
1.02
SOG 20W = -6P
(ML145145-6P)
CASE 751D–04
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOW ABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
10X P
–B–
M
M
0.010 (0.25)
B
1
10
MILLIMETERS
INCHES
20X D
DIM
A
B
C
D
MIN
12.65
7.40
2.35
0.35
0.50
MAX
12.95
7.60
2.65
0.49
0.90
MIN
MAX
0.510
0.299
0.104
0.019
0.035
J
0.499
0.292
0.093
0.014
0.020
M
S
S
0.010 (0.25)
T
A
B
F
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.25
0.10
0°
0.32
0.25
7°
0.010
0.004
0°
0.012
0.009
7°
R X 45°
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
C
SEATING
PLANE
–T–
M
18X G
K
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliabil-
ity, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the cus-
tomer’s technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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