概述
数据手册ML610406 概述
8-bit Microcontroller with a Built-in LCD driver
ML610406 数据手册
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PDF下载FEDL610406-05
Issue Date: May. 23, 2014
ML610404/ML610405/ML610406
8-bit Microcontroller with a Built-in LCD driver
GENERAL DESCRIPTION
ML610404/ML610405/ML610406 is a high-performance 8-bit CMOS microcontroller into which peripheral circuits, such as
synchronous serial port, UART, melody driver, RC oscillation type A/D converter, and LCD driver, are incorporated around
LAPIS Semiconductor-original 8-bit CPU nX-U8/100. ML610404/ML610405/ML610406 operates in both high/low-speed
mode and power-saving mode, it is most suitable for battery operated products.
The short TAT are entertained by offering MTP version ML610Q407/ML610Q408/ML610Q409.
ML610404P/ ML610405P/ML610406P support industrial temperature -40°C to +85°C, are added to the product lineup.
FEATURES
• CPU
− 8-bit RISC CPU (CPU name: nX-U8/100)
− Instruction system: 16-bit instructions
− Instruction set:
Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic
shift, and so on
− Minimum instruction execution time
30.5 µs (@32.768 kHz system clock)
2µs (@500kHz system clock)
0.5µs(@2MHz system clock)
• Internal memory
−
ML610404/5/6 :
Internal 8KByte Mask ROM (4K×16 bits) (including unusable 128 Byte TEST area)
Internal 256Byte Data RAM (256×8 bits)
• Interrupt controller
− 1 non-maskable interrupt sources
Internal source: 1 (Watch dog timer)
− 27 maskable interrupt sources
Internal sources: 14 (Synchronous serial port 0, Synchronous serial port 1, Timer0, Timer1, Timer2, Timer3, UART0,
Melody0, RC Oscillation type A/D converter, PWM0, TBC128Hz, TBC32Hz, TBC16Hz, TBC2Hz)
External sources: 13 (P00, P01, P02, P03, P04, P50, P51, P52, P53, P54, P55, P56, P57)
(One interrupt request is generated from P50 to P57 interrupt sources.)
• Time base counter
− Low-speed time base counter ×1 channel
Frequency compensation (Compensation range: Approx. −488ppm to +488ppm. Compensation accuracy: Approx.
0.48ppm)
− High-speed time base counter ×1 channel
•
Watchdog timer
− Non-maskable interrupt and reset
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, 8s)
• Timers
− 8 bits × 4 channels [also available is 16-bit configuration (using Timers 0 and 1, or Timers 2 and 3) x 2 channels]
− Clock frequency measurement function mode (16-bit configuration using Timers 2 and 3 x 1 channel only)
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FEDL610406-05
ML610404/ML610405/ML610406
• Capture
− Time base capture × 2 channels (4096 Hz to 32 Hz)
• PWM
− Resolution 16 bits × 1 channel
• Synchronous serial port
− Master/slave selectable × 2 channel
− LSB first/MSB first selectable
− 8-bit length/16-bit length selectable
• UART
− TXD/RXD × 1 channel
− Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
− Positive logic/negative logic selectable
− Built-in baud rate generator
• Melody driver
− Scale: 29 types (Melody sound frequency: 508 Hz to 32.768 kHz)
− Tone length: 63 types
− Tempo: 15 types
− Buzzer output mode (4 output modes, 8 frequencies, 16 duty levels)
• RC oscillation type A/D converter
− 16-bit counter
− Time division × 2 channels
• General-purpose ports
− Input-only port × 5 channels (including secondary functions)
− Output-only port
ML610404: × 12 channels (including secondary functions)
ML610405: × 8 channels (including secondary functions)
ML610406: × 4 channels (including secondary functions)
− Input/output port × 22 channels (including secondary functions)
• LCD driver
Number of segments
ML610404: Up to 105 dots (select among 21 segments x 5 commons, 22 segments x 4 commons, 23 segments
x 3 commons, and 24segments x 2 commons)
ML610405: Up to 125 dots (select among 25 segments x 5 commons, 26 segments x 4 commons, 27 segments
x 3 commons, and 28 segments x 2 commons)
ML610406: Up to 145 dots (select among 29 segments x 5 commons, 30 segments x 4 commons, 31 segments
x 3 commons, and 32 segments x 2 commons)
− 1/1 to 1/5 duty
− 1/2, 1/3 bias (built-in bias generation circuit)
− Frame frequency selecable: approx. 64Hz, 73Hz, 85Hz, and 102Hz
− Bias voltage multiplying clock selectable (8 types)
− LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable
− Programmable display allocation function
• Reset
− Reset through the RESET_N pin
− Power-on reset generation when powered on
− Reset when oscillation stop of the low-speed clock is detected (Cancellation by a mask option is possible)
− Reset by the watchdog timer (WDT) overflow
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FEDL610406-05
ML610404/ML610405/ML610406
• Clock
− Low-speed clock (Operation of this LSI is not guaranteed under a condition with no supply of low-speed crystal oscillation
clock)
Crystal oscillation (32.768 kHz)
− High-speed clock: Built-in RC oscillation (500 kHz, 2MHz)
• Power management
− HALT mode: Suspends the instruction execution by CPU (peripheral circuits are in operating states)
− STOP mode: Stops the low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are
stopped.)
− High-speed clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the
oscillation clock)
− Block control function: Completely stops the operation of any function block circuit that is not used (resets registers and
stops clock)
• Guaranteed operating range
− Operating temperature: -20°C to +70°C (P version: -40°C to +85°C)
− Operating voltage: VDD = 1.25V to 3.6V
3/30
FEDL610406-05
ML610404/ML610405/ML610406
• Product name – Supported Function
- Chip (Die) -
Low-speed
oscillation
stop detect reset
LCD bias
Operating
temperature
Product availability
1/2
1/3
Cancellation by a
mask option is
possible
Cancellation by a
mask option is
possible
ML610404-ｘｘｘWA
Yes
Yes
Yes
-20°C to +70°C
-20°C to +70°C
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ML610405-ｘｘｘWA
Cancellation by a
mask option is
possible
ML610406-ｘｘｘWA
ML610404P-ｘｘｘWA
ML610405P-ｘｘｘWA
ML610406P-ｘｘｘWA
Yes
Yes
Yes
Yes
-20°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Yes
Yes
Yes
Yes
Cancellation by a
mask option is
possible
Cancellation by a
mask option is
possible
Cancellation by a
mask option is
possible
Low-speed
oscillation
stop detect reset
LCD bias
-80-pin plastic
TQFP -
Operating
temperature
Product availability
1/2
1/3
Cancellation by a
mask option is
possible
Cancellation by a
mask option is
possible
ML610404-ｘｘｘTB
ML610405-ｘｘｘTB
Yes
Yes
-20°C to +70°C
-20°C to +70°C
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Cancellation by a
mask option is
possible
ML610406-ｘｘｘTB
ML610404P-ｘｘｘTB
ML610405P-ｘｘｘTB
ML610406P-ｘｘｘTB
-20°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-
-
Cancellation by a
mask option is
possible
Cancellation by a
mask option is
possible
Cancellation by a
mask option is
possible
-
xxx: ROM code number (xxx of the blank product is NNN)
Q: MTP version
P: Wide range temperature version (P version)
WA: Chip (Die)
TB: TQFP
4/30
FEDL610406-05
ML610404/ML610405/ML610406
BLOCK DIAGRAM
Block Diagram of ML610404/ML610405/ML610406
CPU (nX-U8/100)
EPSW1～3
ELR1～3
LR
ECSR1～3
DSR/CSR
PC
GREG
0～15
PSW
EA
Timing
Controller
ALU
SP
Program
Memory
(ROM)
BUS
Controller
Instruction
Decoder
Instruction
Register
8Kbyte
Data-bus
INT
2
VDD
VSS
SCK0*
SIN0*
RAM
256byte
SSIO
×2
SOUT0*
RESET_N
TEST0
RESET &
TEST
SCK1*
SIN1*
SOUT1*
Interrupt
Controller
XT0**
XT1**
INT
1
INT
1
OSC
WDT
TBC
LSCLK*
OUTCLK*
RXD0*
TXD0*
UART
INT
4
INT
1
Power
VDDL
PWM
PWM0*
MD0*
INT
1
INT
1
IN0*
CS0*
RS0*
RT0*
RCT0*
RCM*
IN1*
CS1*
RS1*
RT1*
Melody
Capture
×2
INT
6
RC-ADC
×2
INT
４
P00 to P04
P20 to P23, P24
P30 to P35
P40 to P47
P50 to P57
8bit Timer
×4
GPIO
P60 to P67 (ML610404)
P60 to P63 (ML610405)
Display
Allocation
RAM
COM0 to COM4 (*1)(*2)(*3)
LCD
Driver
SEG0 to SEG23 (ML610404) (*1)
SEG0 to SEG27 (ML610405) (*2)
SEG0 to SEG31 (ML610406) (*3)
VL1, VL2, VL3
Display
register
320bit
LCD
BIAS
C1, C2
* Secondary function or Tertiary function
“*1”: Select among 21 segments x 5 commons, 22 segments x 4 commons, 23 segments x 3 commons, and 24 segments x 2
commons with the register
“*2”: Select among 25 segments x 5 commons, 26 segments x 4 commons, 27 segments x 3 commons, and 28 segments x 2
commons with the register
“*3”: Select among 29 segments x 5 commons, 30 segments x 4 commons, 31 segments x 3 commons, and 32 segments x 2
commons with the register
Figure 1 Block Diagram of ML610404/ML610405/ML610406
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PIN CONFIGURATION
Pin Layout of ML610404 Chip
SEG15
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
P24 60
P00 61
P01 62
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
P02
P03 64
P04 65
63
P30
P31
P34
P32
P33
P35
P57
P56
P55
P54
P53
P52
P51
66
67
68
69
70
71
72
73
74
75
76
77
78
SEG8
SEG7
2.1 mm
SEG6
SEG5
SEG4
SEG3
COM4/SEG2
COM3/SEG1
COM2/SEG0
COM1
COM0
C2
C1
Y
2.1 mm
X
Note:
The assignment of the pads P30 to P35 are not in order.
Chip size: 2.1 mm × 2.1 mm
PAD count: 78 pins
Minimum PAD pitch: 80µm
PAD aperture: 70µm×70µm
Chip thickness: 350µm
Voltage of the rear side of chip: VSS leve
Figure 2 Dimensions of ML610404 Chip
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FEDL610406-05
ML610404/ML610405/ML610406
Pin Layout of ML610405 Chip
SEG15
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
P24 60
P00 61
P01 62
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
P02
P03 64
P04 65
63
P30
P31
P34
P32
P33
P35
P57
P56
P55
P54
P53
P52
P51
66
67
68
69
70
71
72
73
74
75
76
77
78
SEG8
SEG7
2.1 mm
SEG6
SEG5
SEG4
SEG3
COM4/SEG2
COM3/SEG1
COM2/SEG0
COM1
COM0
C2
C1
Y
2.1 mm
X
Note:
The assignment of the pads P30 to P35 are not in order.
Chip size: 2.1 mm × 2.1 mm
PAD count: 78 pins
Minimum PAD pitch: 80µm
PAD aperture: 70µm×70µm
Chip thickness: 350µm
Voltage of the rear side of chip: VSS level.
Figure 3 Dimensions of ML610405 Chip
7/30
FEDL610406-05
ML610404/ML610405/ML610406
Pin Layout of ML610406 Chip
SEG15
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
P24 60
P00 61
P01 62
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
P02
P03 64
P04 65
63
P30
P31
P34
P32
P33
P35
P57
P56
P55
P54
P53
P52
P51
66
67
68
69
70
71
72
73
74
75
76
77
78
SEG8
SEG7
2.1 mm
SEG6
SEG5
SEG4
SEG3
COM4/SEG2
COM3/SEG1
COM2/SEG0
COM1
COM0
C2
C1
Y
2.1 mm
X
Note:
The assignment of the pads P30 to P35 are not in order.
Chip size: 2.1 mm × 2.1 mm
PAD count: 78pins
Minimum PAD pitch: 80 µm
PAD aperture: 70 µm×70 µm
Chip thickness: 350 µm
Voltage of the rear side of chip: VSS level.
Figure 4 Dimensions of ML610406 Chip
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ML610404/ML610405/ML610406
Pad Coordinates of ML610404/ML610405/M610406 Chip
Table 1 Pad Coordinates of ML610404/ML610405/ML610406
Chip Center: X=0,Y=0
ML610404/5/6
ML610404/5/6
PAD
No.
Pad
Name
PAD
No.
Pad
Name
X (µm)
Y (µm)
X (µm)
Y (µm)
1
P50
P40
-773
-693
-613
-533
-453
-373
-293
-213
-133
-53
-944
-944
-944
-944
-944
-944
-944
-944
-944
-944
-944
-944
-944
-944
-944
-944
-944
-944
-944
-810
-730
-650
-570
-490
-410
-330
-250
-170
-90
-10
70
150
230
310
390
470
550
630
710
944
944
944
944
44
45
46
47
450
370
290
210
944
944
944
944
SEG20
SEG21
SEG22
SEG23
P67 (*1)
SEG24 (*2)(*3)
P66 (*1)
SEG25 (*2)(*3)
P65 (*1)
SEG26 (*2)(*3)
P64 (*1)
SEG27 (*2)(*3)
P63 (*1)(*2)
SEG28 (*3)
P62 (*1)(*2)
SEG29 (*3)
P61 (*1)(*2)
SEG30 (*3)
P60 (*1)(*2)
SEG31 (*3)
VSS
2
3
P41
4
P42
5
P43
48
49
50
51
52
53
54
6
P44
115
35
944
944
944
944
944
944
944
7
P45
8
P46
9
P47
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
VDD
-45
VSS
27
VDDL
107
187
347
427
507
587
667
747
944
944
944
944
944
944
944
944
944
944
944
944
944
944
944
944
944
944
944
944
770
690
610
530
-125
-205
-285
-365
XT0
XT1
RESET_N
TEST0
VL1
VL2
VL3
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
C1
-445
-525
-605
-685
-765
-944
-944
-944
-944
-944
-944
-944
-944
-944
-944
-944
-944
-944
-944
-944
-944
-944
-944
-944
944
944
944
944
944
717
617
537
457
377
297
217
137
57
C2
COM0
COM1
COM2/SEG0
COM3/SEG1
COM4/SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
P20
P21
P22
P24
P00
P01
P02
P03
P04
P30
P31
P34
-23
P32
-103
-183
-263
-343
-423
-503
-583
-663
-743
P33
P35
P57
P56
P55
P54
P53
P52
P51
(*1) Pad for ML610404 . (*2) Pad for ML610405. (*3) Pad for ML610406
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FEDL610406-05
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List of Pins
Primary function
Function
Secondary function or Tertiary function
PIN PAD
Secondary/
No.
No.
Pin name
I/O
Pin name
I/O
Function
Tertiary
11,57 11,56
Vss
VDD
Negative power supply pin
Positive power supply pin
Power supply pin for internal logic
(internally generated)
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
10
12
10
12
VDDL
⎯
⎯
⎯
⎯
⎯
Power supply pin for LCD bias
(internally generated or connected
to positive power supply pin)(*1)
Power supply pin for LCD bias
(internally generated or connected
to positive power supply pin)(*1)
Power supply pin for LCD bias
(internally generated or connected
to positive power supply pin)(*1)
Capacitor connection pin for LCD
bias generation
18
19
17
18
VL1
⎯
⎯
⎯
⎯
⎯
VL2
⎯
⎯
⎯
⎯
⎯
⎯
20
21
19
20
VL3
C1
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Capacitor connection pin for LCD
bias generation
22
17
21
16
C2
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
TEST0
I/O Test input pin
16
14
15
15
13
14
RESET_N
XT0
I
I
O
Reset input pin
Low-speed clock oscillation pin
Low-speed clock oscillation pin
Input port,
External interrupt,
Capture 0 input
Input port,
External interrupt,
Capture 1 input
Input port,
External interrupt,
UART0 received data
Input port,
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
XT1
P00/EXI0/
CAP0
62
63
61
62
I
I
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
P01/EXI1/
CAP1
P02/EXI2/
RXD0
64
65
63
64
I
I
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
P03/EXI3
External interrupt
Input port,
P04/EXI4/
T02P0CK
Timer 0/Timer 2/PWM0 external
clock input
66
65
I
⎯
⎯
⎯
⎯
External interrupt
58
59
60
61
57
58
59
60
P20/LED0
P21/LED1
P22/LED2
P24/LED4
O
O
O
O
Output port
Output port
Output port
Output port
Secondary
Secondary
Secondary
Secondary
LSCLK
OUTCLK
MD0
O
O
O
O
Low-speed clock output
High-speed clock output
Melody 0 output
PWM0
PWM0 output
RC type ADC0 oscillation
input pin
RC type ADC0 reference
capacitor connection pin
RC type ADC0
67
68
66
67
P30
P31
I/O Input/output port
I/O Input/output port
Secondary
Secondary
IN0
I
CS0
O
69
70
71
72
68
69
70
71
P34
P32
P33
P35
I/O Input/output port
I/O Input/output port
I/O Input/output port
I/O Input/output port
Secondary
Secondary
Secondary
Secondary
RCT0
RS0
O
O
O
O
resistor/capacitor sensor
connection pin
RC type ADC0 reference
resistor connection pin
RC type ADC0 measurement
resistor sensor connection
pin
RT0
RC type ADC oscillation
monitor
RCM
10/30
FEDL610406-05
ML610404/ML610405/ML610406
Primary function
Function
Secondary function or Tertiary function
PIN PAD
Secondary
/Tertiary
No.
No.
Pin name
P40
I/O
Pin name I/O
Function
Secondary
⎯
SIN0
⎯
⎯
I
⎯
⎯
2
2
I/O Input/output port
I/O Input/output port
Tertiary
SSIO0 data input
Secondary
⎯
SSIO0 synchronous clock
input/output
3
3
P41
Tertiary
SCK0
I/O
Secondary
Tertiary
Secondary
Tertiary
RXD0
SOUT0
TXD0
I
UART data input
SSIO0 data output
UART data output
PWM0 output
4
5
4
5
P42
P43
I/O Input/output port
I/O Input/output port
O
O
O
PWM0
Input/output port,
I/O Timer 0/Timer 2/PWM0 external
clock input
RC type ADC1 oscillation input
pin
SSIO0 data input
RC type ADC1 reference
capacitor connection pin
SSIO0 synchronous clock
input/output
RC type ADC1 reference
resistor connection pin
SSIO0 data output
P44/
T02P0CK
Secondary
Tertiary
IN1
SIN0
CS1
I
I
6
7
8
6
7
8
Input/output port,
Secondary
O
P45/T13CK I/O Timer 1/Timer
input
3 external clock
Tertiary
SCK0
I/O
Secondary
Tertiary
RS1
SOUT0
RT1
O
O
O
P46
I/O Input/output port
I/O Input/output port
RC type ADC1 measurement
resistor sensor connection pin
Melody 0 output
9
1
9
1
P47
Secondary
Input/output port,
I/O
Secondary
Tertiary
Secondary
MD0
SIN1
⎯
O
I
⎯
P50/EXI8
External interrupt
SSIO1 data input
⎯
SSIO1 synchronous clock
input/output
Input/output port,
External interrupt
79
78
P51/EXI8
I/O
Tertiary
SCK1
I/O
Input/output port,
External interrupt
Input/output port,
External interrupt
Input/output port,
External interrupt
Secondary
Tertiary
⎯
SOUT1
⎯
O
⎯
78
77
76
77
76
75
P52/EXI8
P53/EXI8
P54/EXI8
I/O
I/O
I/O
SSIO1 data output
⎯
⎯
⎯
⎯
Secondary
Tertiary
Secondary
⎯
SIN1
⎯
⎯
I
⎯
⎯
SSIO1 data input
⎯
SSIO1 synchronous clock
input/output
Input/output port,
External interrupt
75
74
P55/EXI8
I/O
Tertiary
SCK1
I/O
Secondary
Tertiary
Input/output port,
External interrupt
Input/output port,
External interrupt
⎯
SOUT1
⎯
O
⎯
74
73
73
72
P56/EXI8
P57/EXI8
I/O
I/O
SSIO1 data output
⎯
⎯
⎯
⎯
11/30
FEDL610406-05
ML610404/ML610405/ML610406
Primary function
Function
Secondary function or Tertiary function
PIN PAD
Secondary/
Tertiary
Pin
name
No.
No.
Pin name
I/O
I/O
Function
23
24
22
23
COM0
COM1
COM2/
SEG0
COM3/
SEG1
O
O
LCD common pin
LCD common pin
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
25
26
27
24
25
26
O
O
O
LCD common/segment pin
LCD common/segment pin
LCD common/segment pin
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
COM4/
SEG2
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
Output port
LCD segment pin
Output port
LCD segment pin
Output port
LCD segment pin
Output port
LCD segment pin
Output port
LCD segment pin
Output port
LCD segment pin
Output port
LCD segment pin
Output port
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
P67(*2)
49
50
51
52
53
54
55
56
48
49
50
51
52
53
54
55
SEG24(*3)
P66(*2)
SEG25(*3)
P65(*2)
SEG26(*3)
P64(*2)
SEG27(*3)
P63(*4)
SEG28(*5)
P62(*4)
SEG29*5)
P61(*4)
SEG30(*5)
P60(*4)
SEG31(*5)
(*1) Internally generated, or connect to either positive power supply pin (VDD) or power supply pin for internal logic (VDDL). For
details, see user’s manual.
(*2) Pin for ML610404
(*3) Pin for ML610405/ML610406
(*4) Pin for ML610404/ML610405
(*5) Pin for ML610406
12/30
FEDL610406-05
ML610404/ML610405/ML610406
PIN DESCRIPTION
Primary/
Secondary/
Tertiary
Pin name
I/O
I
Description
Logic
System
Reset input pin. When this pin is set to a “L” level, system reset mode is
set and the internal section is initialized. When this pin is set to a “H” level
subsequently, program execution starts. A pull-up resistor is internally
connected.
RESET_N
—
Negative
XT0
XT1
I
—
—
—
—
—
Crystal connection pin for low-speed clock.
O
A 32.768 kHz crystal resonator is connected to this pin. Capacitors CDL
and CGL are connected across this pin and VSS. (see measuring circuit 1) .
Low-speed clock output. Assigned to the secondary function of the P20
pin.
High-speed clock output pin. This pin is used as the secondary function of
the P21 pin.
LSCLK
O
O
Secondary
OUTCLK
Secondary
—
General-purpose input port
General-purpose input port.
General-purpose output port
P00 to P04
I
Primary
Primary
Positive
Positive
P20 to P22,
P24
O
General-purpose output port.
This cannot be used as the general output port when used as the
secondary function.
General-purpose input/output port
P30 to P35 I/O
P40 to P47 I/O
P50 to P57 I/O
Primary
Primary
Primary
Positive
Positive
Positive
General-purpose input/output port.
This cannot be used as the general input/output port when used as the
secondary function.
General-purpose input/output port.
This cannot be used as the general input/output port when used as the
secondary or tertiary function.
General-purpose input/output port.
This cannot be used as the general input/output port when used as the
secondary function.
P60 to P63
P64 to P67
O
O
Primary
Primary
Positive
Positive
General-purpose output port.
Incorporated only into ML610404/ML610405, and not into ML610406.
General-purpose output port.
Incorporated only into ML610404, and not into ML610405/ ML610406.
13/30
FEDL610406-05
ML610404/ML610405/ML610406
Primary/
Secondary/
Tertiary
Pin name
UART
I/O
Description
Logic
UART data output pin. This pin is used as the secondary function of the
P43 pin.
UART data input pin. This pin is used as the secondary function of the
P42 or the primary function of the P02 pin.
TXD0
O
I
Secondary Positive
RXD0
Primary/
Positive
Secondary
Synchronous serial (SSIO)
Synchronous serial clock input/output pin. This pin is used as the tertiary
function of the P41 or P45 pin.
Synchronous serial data input pin. This pin is used as the tertiary function
of the P40 or P44 pin.
Synchronous serial data output pin. This pin is used as the tertiary
function of the P42 or P46 pin.
Synchronous serial clock input/output pin. Assigned to the tertiary
function of the P51 pin and P55 pin.
Synchronous serial data input pin. Assigned to the tertiary function of the
P50 pin and P54 pin.
Synchronous serial data output pin. Assigned to the tertiary function of the
P52 pin and P56 pin.
SCK0
SIN0
I/O
I
Tertiary
Tertiary
Tertiary
Tertiary
Tertiary
Tertiary
—
Positive
Positive
—
SOUT0
SCK1
SIN1
O
I/O
I
Positive
Positive
SOUT1
O
PWM
PWM0 output pin. This pin is used as the secondary function of the P24
and tertiary function of the P43 pin.
PWM0
O
O
Positive
—
Secondary
Tertiary
PWM0 external clock input pin. This pin is used as the primary function of
the P04 pin and P44 pin.
T02P0CK
Primary
External interrupt
External maskable interrupt input pins. Interrupt enable and edge
selection can be performed for each bit by software. These pins are used
as the primary functions of the P00 to P04 pins.
External maskable interrupt input pins. Interrupt enable and edge
selection can be performed for each bit by software. Assigned to the
primary function of the P50 to P57 pins.
Positive/
negative
EXI0-4
I
Primary
Primary
Positive/
negative
EXI8
I
Capture
Capture trigger input pins. The value of the time base counter is captured
in the register synchronously with the interrupt edge selected by software.
These pins are used as the primary functions of the P00 pin(CAP0) and
P01 pin(CAP1).
Positive/
negative
Positive/
negative
CAP0
I
I
Primary
Primary
CAP1
Timer
External clock input pin used for both Timer 0 and Timer 2. This pin is
used as the primary function of the P04 pin and P44 pin.
External clock input pin used for both Timer 1 and Timer 3. This pin is
used as the primary function of the P45 pin.
T02P0CK
I
I
Primary
Primary
—
—
T13CK
Melody
MD0
Melody/buzzer signal output pin. This pin is used as the secondary
function of the P22 and P50 pins.
Positive/
negative
O
O
Secondary
Primary
LED drive
LED0 to
LED2, LED4
N-channel open drain output pins to drive LED. This pin is used as the
primary function of the P20 to P22 and P24 pins.
Positive/
negative
14/30
FEDL610406-05
ML610404/ML610405/ML610406
Primary/
Secondary/
Tertiary
Pin name
I/O
Description
Logic
RC oscillation type A/D converter
Channel 0 oscillation input pin. This pin is used as the secondary function
of the P30 pin.
Channel 0 reference capacitor connection pin. This pin is used as the
secondary function of the P31 pin.
This pin is used as the secondary function of the P32 pin which is the
reference resistor connection pin of Channel 0.
Resistor/capacitor sensor connection pin of Channel 0 for measurement.
This pin is used as the secondary function of the P34 pin.
Resistor sensor connection pin of Channel 0 for measurement. This pin is
used as the secondary function of the P33 pin.
RC oscillation monitor pin. This pin is used as the secondary function of
the P35 pin.
Oscillation input pin of Channel 1. This pin is used as the secondary
function of the P44 pin.
Reference capacitor connection pin of Channel 1. This pin is used as the
secondary function of the P45 pin.
Reference resistor connection pin of Channel 1. This pin is used as the
secondary function of the P46 pin.
IN0
CS0
RS0
RCT0
RT0
RCM
IN1
I
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
—
—
—
—
—
—
—
—
—
—
O
O
O
O
O
I
CS1
RS1
RT1
O
O
O
Resistor sensor connection pin for measurement of Channel 1. This pin is
used as the secondary function of the P47 pin.
LCD drive signal
Common output pins. COM2, COM3, and COM4 can be switched to
SEG0, SEG1, and SEG2, respectively, through the register setting. To
change the setting, switch between COM4 and SEG2 for one pin and
switch between COM3, COM4 and SEG1, SEG2 for two pins.
Segment output pin. The SEG0, SEG1, and SEG2 pins are for switching
the register setting with the COM2, COM3, and COM4.
COM0 to
COM4
O
—
—
SEG0 to
SEG23
O
O
O
—
—
—
—
—
—
Segment output pin. Incorporated into ML610405/ML610406, not into
ML610404.
SEG24 to
SEG27
Segment output pin. Incorporated into ML610406, not into
ML610404/ML610405.
SEG28 to
SEG31
LCD driver power supply
Power supply pin for LCD bias (internally generated) or power supply
connection pin. Depending on LCD Bias setting and VDD voltage level, VDD
or VDDL or capacitor is connected.
VL1
VL2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VL3
Power supply pins for LCD bias (internally generated). Capacitor C12 (see
measuring circuit 1) is connected between C1 and C2.
C1
C2
For testing
TEST0
Power supply
VSS
Pin for testing. A pull-down resistor is internally connected.
I/O
—
Positive
Negative power supply pin.
Positive power supply pin.
—
—
—
—
—
—
—
—
—
VDD
Positive power supply pin (internally generated) for internal logic.
VDDL
Capacitor CL (see measuring circuit 1) is connected between this pin and
VSS
.
15/30
FEDL610406-05
ML610404/ML610405/ML610406
TERMINATION OF UNUSED PINS
Table 3 shows methods of terminating the unused pins.
Table 3 Termination of Unused Pins
Recommended pin handling
Pin
VL1
VL2
Open
Open
VL3
Open
C1, C2
RESET_N
TEST0
P00 to P04
P20 to P22, P24
P30 to P35
Open
Open
Open
VDD or VSS
Open
Open
P40 to P47
Open
P50 to P57
Open
P60 to P67
Open
COM0 to COM4
SEG0 to SEG31
Open
Open
Note:
It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors
or the output mode since the supply current may become excessively large if the pins are left open in the high impedance
input setting.
16/30
FEDL610406-05
ML610404/ML610405/ML610406
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
(VSS = 0V)
Parameter
Power supply voltage 1
Power supply voltage 2
Power supply voltage 3
Power supply voltage 4
Power supply voltage 5
Input voltage
Symbol
Condition
Ta = 25°C
Rating
−0.3 to +4.6
−0.3 to +3.6
−0.3 to +2.0
−0.3 to +4.0
−0.3 to +6.0
−0.3 to VDD+0.3
−0.3 to VDD+0.3
−12 to +11
−12 to +20
0.9
Unit
V
VDD
VDDL
VL1
Ta = 25°C
V
Ta = 25°C
V
VL2
Ta = 25°C
V
VL3
Ta = 25°C
V
VIN
Ta = 25°C
V
Output voltage
VOUT
IOUT1
IOUT2
PD
Ta = 25°C
V
Output current 1
Port 3 to 6, Ta = 25°C
Port 2, Ta = 25°C
Ta = 25°C
mA
mA
W
°C
Output current 2
Power dissipation
Storage temperature
TSTG
⎯
−55 to +150
RECOMMENDED OPERATING CONDITIONS
(VSS = 0V)
Unit
Parameter
Symbol
TOP
Condition
Range
without P version
P version
-20 to +70
-40 to +85
1.25 to 3.6
Operating temperature
°C
V
fOP = 30k to 625kHz
Operating voltage
VDD
fOP
fOP = 30k to 2.5MHz
VDD = 1.25 to 3.6V
1.8 to 3.6
30k to 625k
Operating frequency (CPU)
Hz
V
DD = 1.8 to 3.6V
30k to 2.5M
CV
CL
―
1.0±30% to 2.2±30%*1
0.47±30% to 2.2±30%*2
µF
VDD pin external capacitance
VDDL pin external capacitance
⎯
µF
VL1, 2, or 3 pin external capacitance
Ca, b, c
C12
⎯
⎯
0.1±30%
µF
µF
Pin-to-pin (C1 to C2) external
capacitance
0.47±30%
*1: Please select as CV is larger than CL or same as CL.
*2: When the load of VDD is small and the power rise time is too short, it may happen that the power-on reset is not
generated. In this case please select CL with larger capacitance
CLOCK GENERATION CIRCUIT OPERATING CONDITIONS
(VSS = 0V)
Rating
Typ.
Parameter
Symbol
fXTL
Condition
Unit
Hz
Ω
Min.
Max.
Low-speed crystal oscillation
frequency
Recommended equivalent series
resistance value of low-speed
crystal oscillation
⎯
⎯
⎯
32.768k
⎯
RL
⎯
⎯
40k
CL=6pF of crystal
oscillation
⎯
⎯
⎯
12
18
24
⎯
⎯
⎯
Low-speed crystal oscillation
external capacitor
CL=9pF of crystal
oscillation
CDL/CGL
pF
CL=12pF of
crystal oscillation
17/30
FEDL610406-05
ML610404/ML610405/ML610406
DC CHARACTERISTICS (1/5)
(VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Rating
Typ.
Measuring
circuit
Parameter
Symbol
Condition
Unit
Min.
Typ.
−10%
Typ.
−25%
Typ.
−10%
Typ.
Max.
Typ.
+10%
Typ.
+25%
Typ.
+10%
Typ.
Ta = 25°C
500
500
2.0
VDD = 1.25
kHz
to 3.6V
3
*
500kHz/2MHz RC oscillation
frequency
fRC
Ta = 25°C
VDD = 1.80
to 3.6V
MHz
3
*
2.0
0.6
⎯
−25%
+25%
Low-speed crystal oscillation
start time*2
500kHz/2MHz RC oscillation
start time
Low-speed oscillation stop
detect time*1
TXTL
TRC
⎯
⎯
⎯
⎯
2
3
s
1
µs
ms
TSTOP
PRST
⎯
⎯
⎯
12
200
⎯
16.4
⎯
41
⎯
Reset pulse width
µs
Reset noise elimination
pulse width
PNRST
⎯
0.3
Power-on reset generated
power rise time
TPOR
⎯
⎯
⎯
10
ms
*1: When low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is
reset to shift to system reset mode.
*2 : 32.768KHz Crystal resonator DT-26 (Load Capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (CGL=CDL=6pF)
*3 : Recommended operating temperature (Ta=-20 to 70°C, Ta=-40 to 85°C for P version)
VIL1
VIL1
RESET_N
PRST
Reset pulse width (PRST
)
0.9xVDD
VDD
0.1xVDD
TPOR
Power-on reset activation power rise time (TPOR
)
18/30
FEDL610406-05
ML610404/ML610405/ML610406
DC CHARACTERISTICS (2/5)
(VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Rating
Typ.
1.2
Measuring
circuit
Parameter
Symbol
VDDL
Condition
Unit
V
Min.
1.1
Max.
1.3
fOP = 30k to 625kHz
fOP = 30k to 2.5MHz
VDDL voltage
1.35
1.5
1.65
VDDL temperature
deviation *1
1
∆VDDL
∆VDDL
VDD = 3.0V
⎯
-1
⎯
mV/°C
VDDL voltage
⎯
⎯
5
20
mV/V
dependency *1
*1: The maximum VDDL voltage becomes the VDD voltage level when the VDDL voltage determined by the temperature and voltage deviations
mathematically exceeds the VDD voltage.
19/30
FEDL610406-05
ML610404/ML610405/ML610406
DC CHARACTERISTICS (3/5)
(VDD=3.0V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Rating
Typ.
Measuring
circuit
Parameter
Symbol
Condition
Unit
Min.
Max.
0.8
Ta= 25°C
⎯
0.4
CPU: In STOP state.
Supply current 1
Low-speed/high-speed oscillation:
stopped.
IDD1
µA
5
*
⎯
⎯
6.5
CPU: In HALT state (LTBC and WDT
are Operating.).*3*4
Ta= 25°C
⎯
⎯
⎯
⎯
0.9
⎯
1.8
7.5
1
Supply current 2
Supply current 3
High-speed 500kHz/2MHz
oscillation: Stopped.
IDD2
µA
5
*
LCD and BIAS circuits: Operating. *6
CPU: In 32.768kHz operating
state.*1*3
Ta= 25°C
4.0
⎯
7.5
High-speed 500kHz/2MHz
oscillation: Stopped.
IDD3
µA
µA
µA
5
*
11.0
LCD and BIAS circuits: Operating. *2
Ta= 25°C
⎯
⎯
60
80
90
Supply current
4-1
CPU: In 500kHz RC operating state.
LCD/BIAS circuits: Operating. *2
IDD4-1
IDD4-2
5
*
⎯
1
Ta= 25°C
⎯
⎯
240
300
320
Supply current
4-2
CPU: In 2MHz RC operating state.
LCD/BIAS circuits: Operating. *2
5
*
⎯
*1: When the CPU operating rate is 100% (No HALT state).
*2: All SEGs: off waveform, No LCD panel load, 1/3 bias, 1/3 duty, Frame frequency: Approx. 64 Hz, Bias voltage multiplying
clock: 1/128 LSCLK (256Hz)
*3 : 32.768KHz Crystal resonator DT-26 (Load capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (CGL=CDL=6pF).
*4 : Significant bits of BLKCON0 to BLKCON4 registers are all “1” except DLCD bit on BLKCON4.
*5 : Recommended operating temperature (Ta=-20 to 70°C, Ta=-40 to 85°C for P version)
*6 : LCD stop mode, 1/3 bias, Bias voltage multiplying clock: 1/128 LSCLK (256Hz)
20/30
FEDL610406-05
ML610404/ML610405/ML610406
DC CHARACTERISTICS (4/5)
(VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Rating
Typ.
Measuring
circuit
Parameter
Symbol
Condition
Unit
Min.
Max.
Output voltage 1
(P20 to P22,P24
(N-channel open
drain output
mode is not
selected))
VDD
−0.5
VDD
−0.3
⎯
IOH1 = −0.5mA, VDD = 1.8 to 3.6V
⎯
⎯
VOH1
IOH1 = -0.03mA, VDD = 1.25 to 3.6V
IOL1 = +0.5mA, VDD = 1.8 to 3.6V
⎯
⎯
⎯
0.5
(P30 to P35)
(P40 to P47)
(P50 to P57)
VOL1
VOL2
IOL1 = +0.1mA, VDD = 1.25 to 3.6V
IOL2 = +5mA, VDD = 1.8 to 3.6V
⎯
⎯
⎯
⎯
0.3
(P60 to P63) *2
(P60 to P67) *1
Output voltage 2
(P20 to P22,P24
(N-channel open
drain output mode
is not selected))
0.5
V
2
VL3
−0.2
VOH3
VOML3
VOML3S
VOLM3
IOH3 = −0.05mA, VL1=1.2V
IOML3 = +0.05mA, VL1=1.2V
IOML3S = −0.05mA, VL1=1.2V
IOLM3 = +0.05mA, VL1=1.2V
⎯
⎯
⎯
⎯
⎯
VL2
+0.2
Output voltage 3
(COM0 to 4)
⎯
(SEG0 to 23)*1
(SEG0 to 27)*2
(SEG0 to 31)*3
VL2
−0.2
⎯
VL1
+0.2
⎯
VL1
−0.2
VOLM3S
VOL3
IOLM3S = −0.05mA, VL1=1.2V
⎯
⎯
⎯
IOL3 = +0.05mA, VL1=1.2V
⎯
0.2
Output leakage
(P20 to P22,P24)
(P30 to P35)
IOOH
VOH = VDD (in high-impedance state)
⎯
⎯
1
(P40 to P47)
µA
3
(P50 to P57)
IOOL
VOL = VSS (in high-impedance state)
−1
⎯
⎯
(P60 to P63) *2
(P60 to P67) *1
Input current 1
(RESET_N)
IIH1
IIL1
IIH2
IIL2
VIH1 = VDD
VIL1 = VSS
⎯
-600
2
⎯
-300
300
⎯
1
-2
Input current 2
(TEST0)
VIH2 = VDD
600
⎯
VIL2 = Vss
-1
VIH3 = VDD, VDD = 1.8 to 3.6V
(when pulled-down)
VIH3 = VDD, VDD = 1.25 to 3.6V
(when pulled-down)
VIL3 = Vss, VDD = 1.8 to 3.6V
(when pulled-up)
2
30
30
200
200
-2
IIH3
IIL3
0.01
-200
-200
µA
4
Input current 3
(P00 to P04)
(P30 to P35)
(P40 to P47)
(P50 to P57)
-30
-30
VIL3 = Vss, VDD = 1.25 to 3.6V
(when pulled-up)
-0.01
IIH3Z
IIL3Z
VIH3 = VDD (in high-impedance state)
VIL3 = VSS (in high-impedance state)
⎯
⎯
⎯
1
−1
⎯
*1: Characteristics for ML610404
*2: Characteristics for ML610405
*3: Characteristics for ML610406
21/30
FEDL610406-05
ML610404/ML610405/ML610406
DC CHARACTERISTICS (5/5)
(VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Rating
Typ.
Measuring
circuit
Parameter
Symbol
Condition
Unit
Min.
Max.
VDD
Input voltage 1
(RESET_N)
(TEST0)
0.7
×VDD
VIH1
⎯
⎯
(P00 to P04)
(P30 to P35)
(P40 to P47)
(P50 to P57)
V
5
0.3
×VDD
0.2
VDD = 1.8 to 3.6V
VDD = 1.25 to 3.6V
0
0
⎯
⎯
VIL1
CIN
×VDD
Input pin
capacitance
(P00 to P04)
(P30 to P35)
(P40 to P47)
(P50 to P57)
f = 10kHz
Vrms = 50mV
Ta = 25°C
⎯
⎯
5
pF
⎯
22/30
FEDL610406-05
ML610404/ML610405/ML610406
MEASURING CIRCUITS
CGL
XT0
CDL
XT1
C2
C1
32.768kHz
crystal
resonator
C12
CV
CL
: 1µF
: 2.2uF
: 0.1µF
: 0.47µF
Ca,Cb,Cc
C12
VDD
VDDL
VL2 VL3
VSS
VL1
32.768kHz crystal resonator
: DT-26 (Load capacitance 6pF)
A
(Made by KDS:DAISHINKU CORP.)
CV
CL
Cc
Ca
CGL, CDL
: 6pF
MEASURING CIRCUIT 2
(Note 2)
VIH
(Note 1)
V
VIL
VDD VDDL
VL1 VL2
VSS
VL3
(Note 1) Input logic circuit to determine the specified measuring conditions.
(Note 2) Repeats for the specified output pin
23/30
FEDL610406-05
ML610404/ML610405/ML610406
MEASURING CIRCUIT 3
(Note 2)
VIH
(Note 1)
A
VIL
VDD VDDL
VL1 VL2
VSS
VL3
(Note 1) Input logic circuit to determine the specified measuring conditions.
(Note 2) Repeats for the specified output pin
MEASURING CIRCUIT 4
(Note 3)
A
VDD VDDL
VL1 VL2
VSS
VL3
(Note 3) Repeats for the specified input pin
MEASURING CIRCUIT 5
VIH
(Note 1)
VIL
VDD VDDL
VL1 VL2
VSS
VL3
(Note 1) Input logic circuit to determine the specified measuring conditions.
24/30
FEDL610406-05
ML610404/ML610405/ML610406
AC CHARACTERISTICS (External Interrupt)
(VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Rating
Parameter
Symbol
TNUL
Condition
Unit
Min.
76.8
Typ.
Max.
Interrupt: Enabled (MIE = 1),
CPU: NOP operation
External interrupt disable period
⎯
106.8
µs
System clock: 32.768kHz
P00 to P04
(Rising-edge interrupt mode)
tNUL
P00 to P04
(Falling-edge interrupt mode)
tNUL
P00 to P04
P50 to P57
(Both-edge interrupt mode)
tNUL
AC CHARACTERISTICS (UART)
(VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Rating
Parameter
Transmit baud rate
Receive baud rate
Symbol
Condition
Unit
Min.
Typ.
Max.
tTBRT
tRBRT
⎯
⎯
⎯
BRT*1
⎯
s
s
BRT*1
−3%
BRT*1
+3%
BRT*1
*1: Baud rate period (including the error of the clock frequency selected) set with the UART baud rate register (UA0BRTL,H) and
the UART mode register 0 (UA0MOD0).
tTBRT
TXD0*
tRBRT
RXD0*
*: Indicates the secondary function of the port.
25/30
FEDL610406-05
ML610404/ML610405/ML610406
AC CHARACTERISTICS (Synchronous Serial Port)
(VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
10
Typ.
Max.
In the 500kHz oscillation mode*2
In the 2MHz oscillation mode*3
VDD=1.8 to 3.6V
―
―
µs
µs
SCLK input cycle
(slave mode)
tSCYC
tSCYC
tSW
1
―
―
SCLK output cycle
(master mode)
―
―
4
SCLK*1
―
―
―
―
s
In the 500kHz oscillation mode*2
In the 2MHz oscillation mode*3
µs
µs
SCLK input pulse width
(slave mode)
0.4
―
V
DD=1.8 to 3.6V
SCLK output pulse width
(master mode)
SCLK*1 SCLK*1 SCLK*1
tSW
―
s
×0.4
×0.5
×0.6
In the 500kHz oscillation mode*2
Output load 10pF
In the 2MHz oscillation mode*3
―
―
500
SOUT output delay time
(slave mode)
tSD
ns
―
―
―
―
―
―
240
500
240
Output load 10pF
In the 500kHz oscillation mode*2
Output load 10pF
In the 2MHz oscillation mode*3
SOUT output delay time
(master mode)
tSD
ns
Output load 10pF, VDD=1.8 to 3.6V
SIN input
setup time
tSS
tSS
tSH
―
80
―
―
―
―
ns
ns
ns
(slave mode)
In the 500kHz oscillation mode*2
In the 2MHz oscillation mode*3
500
SIN input
setup time
240
300
80
―
―
―
―
―
―
(master mode)
V
DD=1.8 to 3.6V
In the 500kHz oscillation mode*2
In the 2MHz oscillation mode*3
VDD=1.8 to 3.6V
SIN input
hold time
*1: Clock cycle selected with SnCK2–0 of the serial port n mode register (SIOnMOD1) (n= 0, 1)
*2: When 500kHz oscillation is selected with OSCM2 of the frequency control register 0 (FCON0)
*3: When 2MHz oscillation is selected with OSCM2 of the frequency control register 0 (FCON0)
tSCYC
tSW
tSW
SCLKn*
SOUTn*
SINn*
tSD
tSD
tSS
tSH
*: Indicates the tertiary function of the port (n= 0,1)
26/30
FEDL610406-05
ML610404/ML610405/ML610406
AC CHARACTERISTICS (RC Oscillation A/D Converter)
Condition for VDD=1.8 to 3.6V
(VDD=1.8 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Rating
Typ.
Parameter
Symbol
Condition
Unit
Min.
1
Max.
RS0,RS1,RT0,
RT0-1,RT1
fOSC1
Oscillation resistor
―
―
CS0, CT0, CS1≥740pF
kΩ
457.3
53.48
5.43
7.972
0.981
0.099
525.2
58.18
5.89
9.028
1
575.1
62.43
6.32
9.782
1.019
0.104
kHz
kHz
kHz
⎯
⎯
⎯
Resistor for oscillation=1kΩ
Resistor for oscillation=10kΩ
Resistor for oscillation=100kΩ
RT0, RT0-1, RT1=1kΩ
RT0, RT0-1, RT1=10kΩ
RT0, RT0-1, RT1=100kΩ
Oscillation frequency
VDD = 3.0V
fOSC2
fOSC3
Kf1
Kf2
RS to RT oscillation
frequency ratio *1
VDD = 3.0V
Kf3
0.101
*1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the
same conditions.
fOSCX(RT0-CS0 oscillation)
fOSCX(RT0-1-CS0 oscillation)
fOSCX(RS0-CS0 oscillation)
fOSCX(RT1-CS1 oscillation)
fOSCX(RS1-CS1 oscillation)
Kfx =
f
OSCX(RS0-CS0 oscillation)
( x = 1, 2, 3 )
,
,
CVR0
CVR1
RT0, RT0-1, RT1: 1kΩ/10kΩ/100kΩ
RS0, RS1: 10kΩ
CS0, CT0, CS1: 560pF
CVR0, CVR1: 820pF
IN0 CS0
IN1 CS1 RS1 RT1
RCM
RCT0 RS0 RT0
VIH
Frequency measurement (fOSCX
)
(Note 1)
VIL
VDD VDDL
VSS
CV
CL
*1: Input logic circuit to determine the
27/30
FEDL610406-05
ML610404/ML610405/ML610406
Condition for VDD=1.25 to 3.6V
(VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Rating
Typ.
Parameter
Symbol
Condition
Unit
Min.
1
Max.
RS0,RS1,RT0,
RT0-1,RT1
Oscillation resistor
―
―
CS0, CT0, CS1≥740pF
kΩ
fOSC1
fOSC2
fOSC3
Kf1
Kf2
Kf3
fOSC1
fOSC2
fOSC3
Kf1
Kf2
Kf3
81.93
35.32
5.22
93.16
38.75
5.65
2.381
1
0.147
94.58
38.87
5.622
2.432
1
101.2
41.48
6.03
kHz
kHz
kHz
⎯
⎯
⎯
kHz
kHz
kHz
⎯
⎯
⎯
Resistor for oscillation=6kΩ
Resistor for oscillation=15kΩ
Resistor for oscillation=105kΩ
RT0, RT0-1, RT1=1kΩ
Oscillation frequency
VDD = 1.5V
2.139
0.973
0.142
85.28
35.72
5.189
2.227
0.982
0.141
2.632
1.028
0.152
103.3
41.78
6.012
2.626
1.018
0.149
RS to RT oscillation
frequency ratio *1
VDD = 1.5V
RT0, RT0-1, RT1=10kΩ
RT0, RT0-1, RT1=100kΩ
Resistor for oscillation=6kΩ
Resistor for oscillation=15kΩ
Resistor for oscillation=105kΩ
RT0, RT0-1, RT1=1kΩ
RT0, RT0-1, RT1=10kΩ
RT0, RT0-1, RT1=100kΩ
Oscillation frequency
VDD = 3.0V
RS to RT oscillation
frequency ratio *1
VDD = 3.0V
0.145
*1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the
same conditions.
fOSCX(RT0-CS0 oscillation)
fOSCX(RS0-CS0 oscillation)
( x = 1, 2, 3 )
fOSCX(RT0-1-CS0 oscillation)
fOSCX(RS0-CS0 oscillation)
fOSCX(RT1-CS1 oscillation)
fOSCX(RS1-CS1 oscillation)
Kfx =
,
,
CVR0
CVR1
RT0, RT0-1, RT1: 1kΩ/10kΩ/100kΩ
RA0, RA0-1, RA1: 5kΩ
RS0, RS1: 15kΩ
CS0, CT0, CS1: 560pF
CVR0, CVR1: 820pF
IN0 CS0 RCT0 RS0
IN1 CS1 RS1 RT1
RT0
VIH
RCM
Frequency measurement (fOSCX)
(Note 1)
VIL
VDD VDDL
VSS
CV
CL
*1: Input logic circuit to determine the
specified measuring conditions.
Note:
•Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors and IN0/IN1
pin), including CVR0/CVR1. Especially, do not have long wiring between IN0/IN1 and RS0/RS1. The coupling capacitance on the wires
may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise around the node.
•When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please have VSS(GND) trace next to the signal.
•Please make wiring to components (capacitor, resistor, and so on) necessary for objective measurement. Wiring to reserved components may
affect to the A/D conversion operation by noise the components itself may have.
28/30
FEDL610406-05
ML610404/ML610405/ML610406
Revision History
Page
Document No.
Date
Description
Previous Current
Edition
Edition
FEDL610406-01
FEDL610406-02
Dec.15,2011
Dec.5,2012
–
–
Final edition
15
15
Remove the word “appendixC” in the table.
Correct the symbol of capacitor at VDDL.
The notes about CV, CL were added.
The value of capacitor CL was changed to 2.2uF.
Change header and footer
17
17
19
19
19,25
All
19,25
All
FEDL610406-03
Feb.21,2014
Change from "Shipment" to " Product name – Supported
Function "
3
4
18
4
Correct minimum time of Power-on reset generated power
rise time
20
3,5,6,7,
Delete package products
31
4
FEDL610406-04
FEDL610406-05
Apr.18,2014
May.23,2014
4
Correct the “Product name – Supported Function”
Add Clock Generation Circuit Operating Conditions
Change "RESET" to " Reset pulse width (PRST)" and "
Power-on reset activation power rise time (TPOR )".
Correct minimum time of Power-on reset generated power
rise time
-
17
18
18
18
18
18
18
Correct the CGL’s value and the CDL’s value of
CHARACTERISTICS (1/5)’s note No.2
DC
29/30
FEDL610406-05
ML610404/ML610405/ML610406
NOTES
No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co.,
Ltd.
The content specified herein is subject to change for improvement without notice.
Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and
operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any
damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall bear no responsibility for such
damage.
The technical information specified herein is intended only to show the typical functions of and examples of application circuits
for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual
property or other rights held by LAPIS Semiconductor and other parties. LAPIS Semiconductor shall bear no responsibility
whatsoever for any dispute arising from the use of such technical information.
The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio
visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a Product may fail or
malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical
injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and
fail-safe designs. LAPIS Semiconductor shall bear no responsibility whatsoever for your use of any Product outside of the
prescribed scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely
high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human
injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller
or other safety device). LAPIS Semiconductor shall bear no responsibility in any way for use of any of the Products for the
above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales
representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign
Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
Copyright 2011-2014 LAPIS Semiconductor Co., Ltd.
30/30
ML610406 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| ML610407 | LAPIS | 8-bit Microcontroller with a Built-in LCD driver | 获取价格 |
|
| ML610408 | LAPIS | 8-bit Microcontroller with a Built-in LCD driver | 获取价格 |
|
| ML610409 | LAPIS | 8-bit Microcontroller with a Built-in LCD driver | 获取价格 |
|
| ML610426 | LAPIS | 8-bit Microcontroller with a Built-in LCD driver | 获取价格 |
|
| ML610471 | ETC | 8-bit Microcontroller with a Built-in LCD driver | 获取价格 |
|
| ML610472 | ETC | 8-bit Microcontroller with a Built-in LCD driver | 获取价格 |
|
| ML610473 | ETC | 8-bit Microcontroller with a Built-in LCD driver | 获取价格 |
|
| ML610482 | LAPIS | 8-bit Microcontroller | 获取价格 |
|
| ML610Q172 | ETC | The low power micro controller corresponding to 5v for household appliances | 获取价格 |
|
| ML610Q173 | ETC | The low power micro controller corresponding to 5v for household appliances | 获取价格 |
|
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