ML610471 [ETC]
8-bit Microcontroller with a Built-in LCD driver;
| 型号： | ML610471 |
| 厂家： | 
ETC |
| 描述： | 8-bit Microcontroller with a Built-in LCD driver CD 微控制器 |
| 文件： | 总41页 (文件大小：431K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL610473-07
Issue Date Jan. 7, 2013
ML610471/472/473/Q471/Q472/Q473
8-bit Microcontroller with a Built-in LCD driver
GENERAL DESCRIPTION
This LSI is a high performance CMOS 8-bit microcontroller equipped with an 8-bit CPU nX-U8/100 and integrated with
peripheral functions such as the UART, RC oscillation type A/D converter, and LCD driver.
The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture
parallel processing. Additionally, it adopts the low-/high-speed dual clock system, standby mode, and process that prohibits
leak current at high temperatures, and is most suitable for battery-driven applications.
MTP version (ML610Q471/ML610Q472/ML610Q473) can rewrite programs on-board, which can contribute to reduction in
product development TAT. The flash memory incorporated into this MTP version implements the mask ROM-equivalent
low-voltage operation (1.25V or higher) and low-power consumption (typically 5uA at low-speed operation), enabling volume
production by the MTP version.
For industrial use, ML610471P/ML610472P/ML610473P/ML610Q471P/ML610Q472P/ML610Q473P with the extended
operating ambient temperature ranging from -40°C to 85°C are available.
FEATURES
• CPU
- 8-bit RISC CPU (CPU name: nX-U8/100)
- Instruction system: 16-bit length instruction
- Instruction set: Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,
bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
- Flash Memory rewrite function (MTP version only)
- Minimum instruction execution time
30.5 μs (@ 32.768 kHz system clock)
2 μs (@ 500 kHz system clock)
• Internal memory
- ML610471/ML610472/ML610473
Internal 8KByte Mask ROM (4K x 16 bits) (including unusable 256Byte TEST area)
Internal 512Byte RAM (512 x 8 bits)
- ML610Q471/ML610Q472/ML610Q473
Internal 8KByte Flash ROM (4K x 16 bits) (including unusable 256Byte TEST area)
Internal 512Byte RAM (512 x 8 bits)
• Interrupt controller
- 1 non-maskable interrupt source:
Internal source: 1 (Watchdog Timer)
- 12 maskable interrupt sources:
Internal source: 8 (Timer 2, Timer 3, UART0, RC Oscillation type A/D converter, TBC128Hz, TBC32Hz, TBC16Hz,
TBC2Hz)
External source: 4 (P00, P01, P02, P03)
• Time base counter
- Low-speed time base counter x 1 channel
Frequency compensation (Compensation range: Approx. -488ppm to +488ppm. Compensation accuracy: Approx.
0.48ppm)
- High-speed time base counter x 1 channel
•
Watchdog timer
- Non-maskable interrupt and reset
- Free running
- Overflow period: 4 types selectable (125ms, 500ms, 2s, 8s)
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
• Timers
- 8 bits x 2 channels [also available is 16-bit configuration (using Timers 2 and 3) x 1 channels]
- Clock frequency measurement function mode (16-bit configuration using Timers 2 and 3 x 1 channel only)
• Capture
- Time base capture x 2 channels (4096 Hz to 32 Hz)
• UART
- TXD/RXD × 1 channel
- Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
- Positive logic/negative logic selectable
- Built-in baud rate generator
• RC oscillation type A/D converter
- 16-bit counter
- Time division x 1 channels
• General-purpose ports
- Input-only port: 4 channels (including secondary functions)
- Output-only port
Chip or 64-pin plastic TQFP
ML610471/ML610Q471: 10 channels (including secondary functions)
ML610472/ML610Q472: 6 channels (including secondary functions)
ML610473/ML610Q473: 2 channels (including secondary functions)
48-pin plastic TQFP
ML610471/ML610Q471: 9 channels (including secondary functions)
ML610472/ML610Q472: 5 channels (including secondary functions)
ML610473/ML610Q473: 1 channels (including secondary functions)
- Input/output port
Chip or 64-pin plastic TQFP: 7 channels (including secondary functions)
48-pin plastic TQFP:
6 channels (including secondary functions)
• LCD driver
- Number of segments
ML610471/ML610Q471:
Up to 55 dots (select among 11 segments x 5 commons, 12 segments x 4 commons, 13 segments x 3 commons, and 14
segments x 2 commons)
ML610472/ML610Q472:
Up to 75 dots (select among 15 segments x 5 commons, 16 segments x 4 commons, 17 segments x 3 commons, and 18
segments x 2 commons)
ML610473/ML610Q473:
Up to 95 dots (select among 19 segments x 5 commons, 20 segments x 4 commons, 21 segments x 3 commons, and 22
segments x 2 commons)
- 1/1 to 1/5 duty
- 1/2 or 1/3 bias (built-in bias generation circuit)
- Frame frequency selectable (approx. 64 Hz, 73 Hz, 85 Hz, and 102 Hz)
- Bias voltage multiplying clock selectable (8 types)
- LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable
• Reset
- Reset through the RESET_N pin
- Power-on reset generation when powered on
- Reset by the watchdog timer (WDT) overflow
•Clock
- Low-speed clock (Operation of this LSI is not guaranteed under a condition with no supply of low-speed crystal oscillation
clock)
Crystal oscillation (32.768 kHz)
- High-speed clock
Built-in RC oscillation (500 kHz)
2/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
• Power management
- HALT mode: Suspends the instruction execution by CPU (peripheral circuits are in operating states)
- STOP mode: Stops the low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are
stopped.)
- High-speed clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the
oscillation clock)
- Block control function: Completely stops the operation of any function block circuit that is not used (resets registers and
stops clock)
• Shipment
− Chip (Die)
ML610471-xxxWA / ML610Q471-xxxWA
ML610472-xxxWA / ML610Q472-xxxWA
ML610473-xxxWA / ML610Q473-xxxWA
ML610471P-xxxWA / ML610Q471P-xxxWA
ML610472P-xxxWA / ML610Q472P-xxxWA
ML610473P-xxxWA / ML610Q473P-xxxWA
− 48-pin plastic TQFP
ML610471-xxxTPZ03A / ML610Q471-xxxTPZ0AAL
ML610472-xxxTPZ03A / ML610Q472-xxxTPZ0AAL
ML610473-xxxTPZ03A / ML610Q473-xxxTPZ0AAL
ML610471P-xxxTPZ03A / ML610Q471P-xxxTPZ0AAL
ML610472P-xxxTPZ03A / ML610Q472P-xxxTPZ0AAL
ML610473P-xxxTPZ03A / ML610Q473P-xxxTPZ0AAL
− 64-pin plastic TQFP
ML610471-xxxTBZ03A / ML610Q471-xxxTBZ0ARL
ML610472-xxxTBZ03A / ML610Q472-xxxTBZ0ARL
ML610473-xxxTBZ03A / ML610Q473-xxxTBZ0ARL
ML610471P-xxxTBZ03A / ML610Q471P-xxxTBZ0ARL
ML610472P-xxxTBZ03A / ML610Q472P-xxxTBZ0ARL
ML610473P-xxxTBZ03A / ML610Q473P-xxxTBZ0ARL
xxx: ROM code number (xxx of the blank product is NNN, MTP version only)
Q: MTP version
P: Wide range temperature version (P version)
WA: Chip (Die)
TPZ0AAL: 48pin plastic TQFP
TBZ0ARL: 64pin plastic TQFP
• Guaranteed Operation Range
− Operating temperature: -20°C to +70°C (P version: -40°C to +85°C)
− Operating voltage: VDD = 1.25V to 3.6V
3/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
BLOCK DIAGRAM
ML610471/ML610472/ML610473
CPU (nX-U8/100)
EPSW1−3
ELR1−3
LR
ECSR1−3
DSR/CSR
PC
GREG
0−15
PSW
EA
Timing
Controller
ALU
SP
Program
Memory
(Mask)
BUS
Controller
Instruction
Decoder
Instruction
Register
8Kbyte
Data-bus
VDD
VSS
RESET_N
TEST0
RAM
512 byte
RESET &
TEST
Interrupt
Controller
XT0
XT1
INT
1
RXD0*
UART
OSC
INT
1
TXD0*
WDT
TBC
LSCLK*
INT
4
Power
VDDL
INT
1
Capture
×2
INT
5
P00 to P03
P20, P21
P35
INT
2
RC-ADC
8bit Timer
×1
×2
RCM*
IN1*
GPIO
P42 to P47
CS1*
RS1*
RT1*
P60 to P67 (ML610471)
P60 to P63 (ML610472)
COM0 to COM4 (*1)(*2)(*3)
LCD
Driver
SEG0 to SEG13 (ML610471) (*1)
SEG0 to SEG17 (ML610472) (*2)
SEG0 to SEG21 (ML610473) (*3)
VL1, VL2, VL3
Display
register
110bit
LCD
BIAS
C1, C2
* Secondary function or Tertiary function
(*1) Select among 11 segments x 5 commons, 12 segments x 4 commons, 13 segments x 3 commons, and 14
segments x 2 commons with the register
(*2) Select among 15 segments x 5 commons, 16 segments x 4 commons, 17 segments x 3 commons, and 18
segments x 2 commons with the register
(*3) Select among 19 segments x 5 commons, 20 segments x 4 commons, 21 segments x 3 commons, and 22
segments x 2 commons with the register
Figure 1 ML610471/ML610472/ML610473 Block Diagram
4/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
ML610Q471/ML610Q472/ML610Q473
CPU (nX-U8/100)
EPSW1−3
ELR1−3
LR
ECSR1−3
DSR/CSR
PC
GREG
0−15
PSW
EA
Timing
Controller
ALU
SP
Program
BUS
Controller
Memory
(Flash)
8Kbyte
VPP
Instruction
Decoder
Instruction
Register
Flash
Writer
Data-bus
VDD
VSS
RESET_N
TEST0
RAM
512 byte
RESET &
TEST
Interrupt
Controller
XT0
XT1
INT
1
RXD0*
TXD0*
OSC
INT
1
UART
WDT
TBC
LSCLK*
INT
4
Power
VDDL
INT
1
Capture
×2
INT
5
P00 to P03
P20, P21
P35
INT
2
RC-ADC
8bit Timer
×1
×2
RCM*
IN1*
GPIO
P42 to P47
CS1*
RS1*
RT1*
P60 to P67 (ML610Q471)
P60 to P63 (ML610Q472)
COM0 to COM4 (*1)(*2)(*3)
LCD
Driver
SEG0 to SEG13 (ML610Q471) (*1)
SEG0 to SEG17 (ML610Q472) (*2)
SEG0 to SEG21 (ML610Q473) (*3)
VL1, VL2, VL3
Display
register
110bit
LCD
BIAS
C1, C2
* Secondary function or Tertiary function
(*1) Select among 11 segments x 5 commons, 12 segments x 4 commons, 13 segments x 3 commons, and 14
segments x 2 commons with the register
(*2) Select among 15 segments x 5 commons, 16 segments x 4 commons, 17 segments x 3 commons, and 18
segments x 2 commons with the register
(*3) Select among 19 segments x 5 commons, 20 segments x 4 commons, 21 segments x 3 commons, and 22
segments x 2 commons with the register
Figure 2 ML610Q471/ML610Q472/ML610Q473 Block Diagram
5/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
PACKAGE PIN/CHIP PAD LAYOUT
ML610471/ML610Q471 48pin TQFP Package Pin Layout
P64
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
SEG4
P63
SEG3
P62
P61
COM4/SEG2
COM3/SEG1
COM2/SEG0
COM1
COM0
VL3
P60
P20
P43
P00
P01
P02
P03
VL2
VL1
C2
NC(*1) / VPP(*2)
C1
MIRROR FINISH
(NC): No Connection
(*1) : ML610471
(*2) : ML610Q471
Figure 3 ML610471/ML610Q471 48pin TQFP Package Pin Layout
6/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
ML610471/ML610Q471 64pin TQFP Package Pin Layout
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
P64
P63
P62
P61
P60
P20
P21
P42
P43
P00
P01
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
NC
SEG4
SEG3
COM4/SEG2
COM3/SEG1
COM2/SEG0
COM1
COM0
VL3
VL2
VL1
C2
C1
NC
NC
P02
P03
NC(*1) / VPP(*2)
NC
NC
MIRROR FINISH
(NC): No Connection
(*1) : ML610471
(*2) : ML610Q471
Figure 4 ML610471/ML610Q471 64pin TQFP Package Pin Layout
7/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
ML610472/ML610Q472 48pin TQFP Pin Layout
SEG17
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
SEG4
P63
P62
SEG3
COM4/SEG2
COM3/SEG1
P61
P60
COM2/SEG0
COM1
COM0
VL3
P20
P43
P00
P01
P02
VL2
VL1
C2
P03
NC(*1) / VPP(*2)
C1
MIRROR FINISH
(NC): No Connection
(*1) : ML610472
(*2) : ML610Q472
Figure 5 ML610472/ML610Q472 48pin TQFP Package Pin Layout
8/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
ML610472/ML610Q472 64pin TQFP Pin Layout
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
SEG17
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
NC
SEG4
SEG3
COM4/SEG2
COM3/SEG1
P63
P62
P61
P60
P20
P21
P42
P43
COM2/SEG0
COM1
COM0
VL3
VL2
VL1
C2
C1
NC
NC
P00
P01
P02
P03
NC(*1) / VPP(*2)
NC
NC
MIRROR FINISH
(NC): No Connection
(*1) : ML610472
(*2) : ML610Q472
Figure 6 ML610472/ML610Q472 64pin TQFP Package Pin Layout
9/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
ML610473/ML610Q473 48pin TQFP Pin Layout
SEG17
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
SEG4
SEG18
SEG19
SEG3
COM4/SEG2
COM3/SEG1
SEG20
SEG21
COM2/SEG0
COM1
COM0
VL3
P20
P43
P00
P01
P02
VL2
VL1
C2
P03
NC(*1) / VPP(*2)
C1
MIRROR FINISH
(NC): No Connection
(*1) : ML610473
(*2) : ML610Q473
Figure 7 ML610473/ML610Q473 48pin TQFP Package Pin Layout
10/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
ML610473/ML610Q473 64pin TQFP Pin Layout
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
SEG17
SEG18
SEG19
SEG20
SEG21
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
NC
SEG4
SEG3
COM4/SEG2
COM3/SEG1
COM2/SEG0
COM1
COM0
VL3
VL2
VL1
C2
C1
NC
NC
P20
P21
P42
P43
P00
P01
P02
P03
NC(*1) / VPP(*2)
NC
NC
MIRROR FINISH
(NC): No Connection
(*1) : ML610473
(*2) : ML610Q473
Figure 8 ML610473/ML610Q473 64pin TQFP Package Pin Layout
11/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
ML610471 Chip Pad Layout & Dimension
SEG4
SEG3
24
23
P64 37
P63
38
22 COM4/SEG2
P62 39
P61 40
COM3/SEG1
COM2/SEG0
COM1
21
20
19
P60
P20
P21
P42
P43
P00
P01
P02
41
42
43
44
45
46
47
48
18 COM0
1.77mm
17 VL3
VL2
VL1
C2
16
15
14
13
P03 49
C1
Y
1.61mm
X
Chip size: 1.61 mm × 1.77 mm
PAD count: 49 pins
Minimum PAD pitch: 80μm
PAD aperture: 70μm×70μm
Chip thickness: 350μm
Voltage of the rear side of chip: VSS level.
Figure 9 ML610471 Chip Pin Layout & Dimension
12/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
ML610472 Chip Pad Layout & Dimension
SEG4
SEG3
24
23
SEG17 37
P63
38
22 COM4/SEG2
P62 39
P61 40
COM3/SEG1
COM2/SEG0
COM1
21
20
19
P60
P20
P21
P42
P43
P00
P01
P02
41
42
43
44
45
46
47
48
18 COM0
1.77mm
17 VL3
VL2
VL1
C2
16
15
14
13
P03 49
C1
Y
1.61mm
X
Chip size: 1.61 mm × 1.77 mm
PAD count: 49 pins
Minimum PAD pitch: 80μm
PAD aperture: 70μm×70μm
Chip thickness: 350μm
Voltage of the rear side of chip: VSS level.
Figure 10 ML610472 Chip Pin Layout & Dimension
13/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
ML610473 Chip Pad Layout & Dimension
SEG4
SEG3
24
23
SEG17 37
SEG18
38
22 COM4/SEG2
SEG19 39
SEG20 40
COM3/SEG1
COM2/SEG0
COM1
21
20
19
SEG21
P20
41
42
43
44
45
46
47
48
18 COM0
P21
1.77mm
P42
P43
17 VL3
P00
VL2
VL1
C2
16
15
14
13
P01
P02
P03 49
C1
Y
1.61mm
X
Chip size: 1.61 mm × 1.77 mm
PAD count: 49 pins
Minimum PAD pitch: 80 μm
PAD aperture: 70 μm×70 μm
Chip thickness: 350 μm
Voltage of the rear side of chip: VSS level.
Figure 11 ML610473 Chip Pin Layout & Dimension
14/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
ML610Q471 Chip Pad Layout & Dimension
P64 37
SEG4
SEG3
24
23
P63
38
22 COM4/SEG2
P62 39
P61 40
COM3/SEG1
COM2/SEG0
COM1
21
20
19
P60
41
42
43
P20
18 COM0
P21
P42
P43
P00
P01
P02
P03 49
VPP
44
45
46
47
48
1.88mm
VL3
VL2
VL1
C2
17
16
15
14
13
50
C1
Y
1.95mm
X
(NC): No Connection
Chip size: 1.95 mm × 1.88 mm
PAD count: 50 pins
Minimum PAD pitch: 80μm
PAD aperture: 70μm×70μm
Chip thickness: 350μm
Voltage of the rear side of chip: VSS level.
Figure 12 ML610Q471 Chip Pin Layout & Dimension
15/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
ML610Q472 Chip Pad Layout & Dimension
SEG17 37
SEG4
24
23
SEG3
P63
38
22 COM4/SEG2
P62 39
P61 40
COM3/SEG1
COM2/SEG0
COM1
21
20
19
P60
41
42
43
P20
18 COM0
P21
P42
P43
P00
P01
P02
44
45
46
47
48
1.88mm
VL3
VL2
VL1
C2
17
16
15
14
13
P03 49
VPP
50
C1
Y
1.95mm
X
(NC): No Connection
Chip size: 1.95 mm × 1.88 mm
PAD count: 50 pins
Minimum PAD pitch: 80μm
PAD aperture: 70μm×70μm
Chip thickness: 350μm
Voltage of the rear side of chip: VSS level.
Figure 13 ML610Q472 Chip Pin Layout & Dimension
16/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
ML610Q473 Chip Pad Layout & Dimension
SEG17 37
SEG4
24
23
SEG3
SEG18
38
22 COM4/SEG2
SEG19 39
SEG20 40
COM3/SEG1
COM2/SEG0
COM1
21
20
19
SEG21
41
42
43
P20
18 COM0
P21
P42
P43
P00
P01
P02
44
45
46
47
48
1.88mm
VL3
VL2
VL1
C2
17
16
15
14
13
P03 49
VPP
50
C1
Y
1.95mm
X
(NC): No Connection
Chip size: 1.95 mm × 1.88 mm
PAD count: 50 pins
Minimum PAD pitch: 80 μm
PAD aperture: 70 μm×70 μm
Chip thickness: 350 μm
Voltage of the rear side of chip: VSS level.
Figure 14 ML610Q473 Chip Pin Layout & Dimension
17/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
PAD COORDINATES
ML610471/ML610472/ML610473 Pad Coordinates
Table 1 ML610471/ML610472/ML610473 Pad Coordinates
Chip Center: X=0,Y=0
ML610471/2/3
ML610471/2/3
PAD
No.
Pad
Name
PAD
No.
Pad
Name
X (μm)
Y (μm)
-779
-779
-779
-779
-779
-779
-779
-779
-779
-779
-779
-779
-468
-388
-308
-228
-148
133
X (μm)
Y (μm)
779
1
2
3
4
5
6
7
8
VDD
VSS
VDDL
XT0
30
31
32
33
SEG10
SEG11
SEG12
SEG13
P67(*1)
-410
-330
-250
-160
0
80
0
779
779
779
-80
-160
XT1
34
35
36
37
38
39
40
41
779
779
779
587
507
427
347
267
-310
-390
-470
-699
-699
-699
-699
-699
RESET_N
TEST0
P44
SEG14(*2) (*3)
P66(*1)
-80
160
260
340
420
500
580
699
699
699
699
699
699
699
699
699
699
699
699
480
400
320
240
160
SEG15(*2) (*3)
P65(*1)
9
P45
P46
P47
P35
C1
C2
VL1
VL2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
SEG16(*2) (*3)
P64(*1)
SEG17(*2) (*3)
P63(*1) (*2)
SEG18(*3)
P62(*1) (*2)
SEG19(*3)
P61(*1) (*2)
SEG20(*3)
P60(*1) (*2)
SEG21(*3)
P20
VL3
COM0
COM1
COM2/SEG0
COM3/SEG1
COM4/SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
213
293
373
453
533
613
42
43
44
45
46
47
48
49
-699
-699
-699
-699
-699
-699
-699
-699
167
87
-13
P21
P42
P43
P00
P01
P02
P03
-93
-173
-253
-333
-413
779
779
779
779
779
(*1) Pad for ML610471 . (*2) Pad for ML610472. (*3) Pad for ML610473.
18/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
ML610Q471/ML610Q472/ML610Q473 Pad Coordinates
Table 2 ML610Q471/ML610Q472/ML610Q473 Pad Coordinates
Chip Center: X=0,Y=0
ML610Q471/2/3
ML610Q471/2/3
PAD
No.
Pad
Name
PAD
No.
Pad
Name
X (μm)
Y (μm)
-834
-834
-834
-834
-834
-834
-834
-834
-834
-834
-834
-834
-523
-443
-363
-283
-203
175
X (μm)
Y (μm)
834
834
1
2
3
4
5
6
7
8
VDD
VSS
VDDL
XT0
30
31
32
33
34
SEG10
SEG11
SEG12
SEG13
P67(*1)
-580
-500
-420
-330
-170
-90
250
170
90
834
834
10
XT1
834
834
834
642
562
482
402
322
-480
-560
-640
-869
-869
-869
-869
-869
RESET_N
TEST0
P44
SEG14(*2) (*3)
P66(*1)
35
-10
SEG15(*2) (*3)
P65(*1)
430
510
590
670
750
869
869
869
869
869
869
869
869
869
869
869
869
650
570
490
410
330
9
P45
P46
P47
P35
C1
C2
VL1
VL2
36
37
38
39
40
41
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
SEG16(*2) (*3)
P64(*1)
SEG17(*2) (*3)
P63(*1) (*2)
SEG18(*3)
P62(*1) (*2)
SEG19(*3)
P61(*1) (*2)
SEG20(*3)
P60(*1) (*2)
SEG21(*3)
P20
VL3
COM0
COM1
COM2/SEG0
COM3/SEG1
COM4/SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
255
335
415
495
575
655
42
43
44
45
46
47
48
49
50
-869
-869
-869
-869
-869
-869
-869
-869
-869
222
142
42
P21
P42
P43
P00
P01
P02
P03
VPP
-38
-118
-198
-278
-358
-438
834
834
834
834
834
(*1) Pad for ML610Q471 . (*2) Pad for ML610Q472. (*3) Pad for ML610Q473.
19/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
PIN LIST
PAD PAD
PIN No.
Primary function
Function
Secondary function
No.
No.
48(*1)
64(*2)
Pin name
I/O
Pin name
I/O
Function
(MASK)
(FLASH)
2
1
3
2
2
1
2
1
VSS
VDD
Negative power supply pin
Positive power supply pin
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Power supply pin for internal
logic (internally generated)
3
4
3
3
VDDL
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
48
63
50
VPP(*3)
Power supply pin for Flash ROM
⎯
Power supply pin for LCD bias
(internally
generated
or
15
16
22
23
15
16
15
16
VL1
VL2
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
connected to positive power
supply pin)(*2)
Power supply pin for LCD bias
(internally
generated
or
connected to positive power
supply pin)(*2)
Power supply pin for LCD bias
(internally generated)
Capacitor connection pin for
LCD bias generation
Capacitor connection pin for
LCD bias generation
17
13
14
24
20
21
17
13
14
17
13
14
VL3
C1
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
C2
7
6
4
5
10
9
7
6
4
5
7
6
4
5
TEST0
RESET_N
XT0
I/O Test pin
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
I
I
Reset input pin
6
Low-speed clock oscillation pin
Low-speed clock oscillation pin
8
XT1
O
Input port,
P00/EXI0/
CAP0
44
45
59
60
46
47
46
47
I
I
External interrupt,
Capture 0 input
Input port,
External interrupt,
Capture 1 input
Input port,
External interrupt,
UART0 received data
Input port,
⎯
⎯
⎯
⎯
⎯
⎯
P01/EXI1/
CAP1
P02/EXI2/
RXD0
46
47
61
62
48
49
48
49
I
I
⎯
⎯
⎯
⎯
⎯
⎯
P03/EXI3
External interrupt
42
55
56
42
43
42
43
P20/LED0
P21/LED1
O
O
Output port
Output port
LSCLK
O
O
Low-speed clock output
High-speed clock output
OUTCLK
⎯
RC type ADC oscillation
monitor
12
15
57
12
44
12
44
P35
I/O Input/output port
I/O Input/output port
RCM
O
P42
P43
RXD0
UART0 received data
⎯
43
8
⎯
O
I
58
11
45
8
45
8
I/O Input/output port
Input/output port,
TXD0
IN1
UART data output
RC type ADC1 oscillation
input pin
P44/ T2CK I/O
P45/T3CK I/O
Timer 2 external clock input
Input/output port,
Timer 3 external clock input
RC type ADC1 reference
capacitor connection pin
RC type ADC1 reference
resistor connection pin
RC type ADC1
9
12
13
9
9
CS1
RS1
O
O
10
10
10
P46
I/O Input/output port
11
14
11
11
P47
I/O Input/output port
RT1
O
measurement resistor
sensor connection pin
(*1) 48pin TQFP. (*2) 64pin TQFP
(*3) Pad for ML610Q471/ML610Q472/ML610Q473
20/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
PAD PAD
PIN No.
Primary function
Function
Secondary function
No.
No.
48(*1)
64(*2)
Pin name
COM0
I/O
O
Pin name
I/O
Function
(MASK)
(FLASH)
18
19
25
18
19
18
19
LCD common pin
LCD common pin
⎯
⎯
⎯
⎯
⎯
⎯
26
COM1
O
COM2/
SEG0
COM3/
SEG1
COM4/
SEG2
20
21
22
27
28
29
20
21
22
20
21
22
O
O
O
LCD common/segment pin
LCD common/segment pin
LCD common/segment pin
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
23
24
25
26
27
28
29
30
31
32
33
30
31
34
35
36
37
38
39
40
41
42
23
24
25
26
27
28
29
30
31
32
33
23
24
25
26
27
28
29
30
31
32
33
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
P67(*4)
O
O
O
O
O
O
O
O
O
O
O
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
LCD segment pin
Output port
⎯
⎯
⎯
⎯
⎯
⎯
SEG14(*5)(*
34
35
36
37
44
45
46
50
34
35
36
37
34
35
36
37
O
O
O
O
LCD segment pin
Output port
⎯
⎯
⎯
⎯
⎯
⎯
6)
P66(*4)
SEG15(*5)
LCD segment pin
Output port
⎯
⎯
⎯
⎯
⎯
⎯
(*6)
P65(*4)
SEG16(*5)
LCD segment pin
Output port
⎯
⎯
⎯
⎯
⎯
⎯
(*6)
P64(*5)
SEG17(*5)
LCD segment pin
Output port
⎯
⎯
⎯
⎯
⎯
⎯
(*6)
P63(*4) (*5)
SEG18(*6)
P62(*4) (*5)
SEG19(*6)
P61(*4) (*5)
SEG20(*6)
P60(*4) (*5)
SEG21(*6)
38
39
40
41
51
52
53
54
38
39
40
41
38
39
40
41
O
O
O
O
LCD segment pin
Output port
⎯
⎯
⎯
⎯
⎯
⎯
LCD segment pin
Output port
⎯
⎯
⎯
⎯
⎯
⎯
LCD segment pin
Output port
⎯
⎯
⎯
⎯
⎯
⎯
LCD segment pin
⎯
⎯
⎯
(*1) 48pin TQFP. (*2) 64pin TQFP ,
(*3) Pad for ML610Q471/ML610Q472/ML610Q473
(*4) Pad for ML610471/ML610Q471
(*5) Pad for ML610472/ML610Q472
(*6) Pad for ML610473/ML610Q473.
21/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
PIN DESCRIPTION
Pin name
I/O
Description
Primary/
Logic
Secondary
System
RESET_N
I
Reset input pin. When this pin is set to a “L” level, system reset
mode is set and the internal section is initialized. When this pin is
set to a “H” level subsequently, program execution starts. A pull-up
resistor is internally connected.
—
Negative
—
XT0
I
Crystal connection pin for low-speed clock.
—
—
A 32.768 kHz crystal resonator is connected to this pin. Capacitors
XT1
O
O
O
C
DL and CGL are connected across this pin and VSS. (see appendix
—
—
C measuring circuit 1)
LSCLK
OUTCLK
Low-speed clock output. Assigned to the secondary function of the Secondary
P20 pin.
High-speed clock output pin. This pin is used as the secondary
function of the P21 pin.
Secondary
—
General-purpose input port
P00 to P03 General-purpose input port.
General-purpose output port
I
Primary
Positive
Positive
P20, P21
O
General-purpose output port.
Primary
This cannot be used as the general output port when used as the
secondary function.
General-purpose input/output port
P35
I/O General-purpose input/output port.
Primary
Primary
Positive
Positive
This cannot be used as the general input/output port when used as
the secondary function.
P42 to P47
P60 to P63
I/O General-purpose input/output port.
This cannot be used as the general input/output port when used as
the secondary function.
O
O
General-purpose output port.
Incorporated only into
ML610471/610Q471/ML610472/ML610Q472, and not into
ML610473/ML610Q473.
Primary
Primary
Positive
Positive
P64 to P67
General-purpose output port.
Incorporated only into ML610473/ML610Q473, and not into
ML610471/ML610Q471/ML610472/ ML610Q472.
UART
TXD0
O
I
UART data output pin. This pin is used as the secondary function of
the P43 pin.
Secondary Positive
RXD0
UART data input pin. This pin is used as the secondary function
of the P42 or the primary function of the P02 pin.
Primary
Positive
External interrupt
EXI0-3
I
External maskable interrupt input pins. Interrupt enable and edge
selection can be performed for each bit by software. These pins are
used as the primary functions of the P00 to P03 pins.
Primary/
Positive/
Secondary negative
22/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
Primary/
Logic
Pin name
Capture
I/O
Description
Secondary
CAP0
I
I
Capture trigger input pins. The value of the time base counter is
captured in the register synchronously with the interrupt edge
selected by software. These pins are used as the primary functions
of the P00 pin(CAP0) and P01 pin(CAP1).
Primary
Primary
Positive/
negative
Positive/
negative
CAP1
Timer
T2CK
I
I
External clock input pin used for Timer 2. This pin is used as the
primary function of the P44 pin.
Primary
Primary
—
—
T3CK
External clock input pin used for Timer 3. This pin is used as the
primary function of the P45 pin.
LED drive
LED0-1
O
N-channel open drain output pins to drive LED. This pin is used as
the primary function of the P20 pin and P21 pin.
Primary
Positive
/negative
RC oscillation type A/D converter
RCM
O
RC oscillation monitor pin. This pin is used as the secondary
function of the P35 pin.
Secondary
Secondary
Secondary
—
—
—
—
—
IN1
I
Oscillation input pin of Channel 1. This pin is used as the
secondary function of the P44 pin.
CS1
RS1
RT1
O
O
O
Reference capacitor connection pin of Channel 1. This pin is used
as the secondary function of the P45 pin.
Reference resistor connection pin of Channel 1. This pin is used as Secondary
the secondary function of the P46 pin.
Resistor sensor connection pin for measurement of Channel 1. This Secondary
pin is used as the secondary function of the P47 pin.
23/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
Primary/
Logic
Pin name
I/O
O
Description
Secondary
LCD drive signal
COM0 to COM4
Common output pins. COM2, COM3, and COM4 can be switched
to SEG0, SEG1, and SEG2, respectively, through the register
setting. To change the setting, switch between COM4 and SEG2
for one pin and switch between COM3, COM4 and SEG1, SEG2
for two pins.
—
—
SEG0 to
SEG13
O
O
Segment output pin. The SEG0, SEG1, and SEG2 pins are for
switching the register setting with the COM2, COM3, and COM4.
—
—
—
—
SEG14 to
SEG17
Segment output pin. Incorporated into
ML610472/ML610Q472/ML610473/ML610Q473, not into
ML610471/ML610Q471.
SEG18 to
SEG21
O
Segment output pin. Incorporated into ML610473/ML610Q473, not
into ML610471/ML610Q471/ML610472/ML610Q472.
—
—
LCD driver power supply
VL1
VL2
VL3
—
Power supply pin for LCD bias (internally generated) or power
supply connection pin. Depending on LCD Bias setting and VDD
voltage level, VDD or VDDL or capacitor is connected. For details of
the connection method, see measuring circuit 1.
—
—
—
—
—
—
—
—
C1
—
—
Power supply pins for LCD bias (internally generated). Capacitor
—
—
—
—
C12 (see measuring circuit 1) is connected between C1 and C2.
C2
Test
TEST0
Power supply
VSS
I/O Pin for testing. A pull-down resistor is internally connected.
—
Positive
—
—
—
Negative power supply pin.
Positive power supply pin.
—
—
—
—
—
—
VDD
VDDL
Positive power supply pin (internally generated) for internal logic.
Capacitors CL0 and CL1 (see measuring circuit 1) are connected
between this pin and VSS.
VPP
—
Power supply pin for programming Flash ROM. A pull-down resistor
is internally connected. This pin is only for
—
—
ML610Q471/ML610Q472/ML610Q473.
24/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
TERMINATION OF UNUSED PINS
Table 2 shows methods of terminating the unused pins.
Table 2 Termination of Unused Pins
Recommended pin handling
Pin
VPP
VL1
Open
Open
VL2
Open
VL3
Open
C1, C2
Open
RESET_N
TEST0
P00 to P03
P20, P21
P35
Open
Pull down(1kΩ to VSS)
VDD or VSS
Open
Open
P42 to P47
P60 to P67
COM0 to COM4
SEG0 to SEG21
Open
Open
Open
Open
Note:
It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or
the output mode since the supply current may become excessively large if the pins are left open in the high impedance input
setting.
25/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(VSS= 0V)
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage 1
Power supply voltage 2
Power supply voltage 3
Power supply voltage 4
Power supply voltage 5
Power supply voltage 6
Input voltage
VDD
VPP
Ta=25°C
Ta=25°C
-0.3 to +4.6
-0.3 to +9.5
-0.3 to +3.6
-0.3 to +2.0
-0.3 to +4.0
-0.3 to +6.0
-0.3 to VDD+0.3
-0.3 to VDD+0.3
-12 to +11
V
V
VDDL
VL1
Ta=25°C
V
Ta=25°C
V
VL2
Ta=25°C
V
VL3
Ta=25°C
V
VIN
Ta=25°C
V
Output voltage
VOUT
IOUT1
IOUT2
PD
Ta=25°C
V
Output current 1
Port 3 to 6, Ta=25°C
Port 2, Ta=25°C
Ta=25°C
mA
mA
W
°C
Output current 2
-12 to +20
Power dissipation
0.9
Storage temperature
TSTG
―
-55 to +150
Recommended Operating conditions
(VSS= 0V)
Unit
Parameter
Symbol
TOP
Condition
Range
without P version
P version
-20 to +70
-40 to +85
1.25 to 3.6
Operating temperature
Operating voltage
°C
fOP=30k to 625kHz
VDD
fOP
V
Operating frequency
(CPU)
Low-speed crystal
oscillation frequency
Low-speed crystal
oscillation
VDD=1.25 to 3.6V
30k to 625k
32.768k
Hz
fXTL
―
Hz
pF
CDL
CGL
―
―
3 to 18
3 to 18
external capacitance
VDD pin external
capacitance
CV
―
1.0±30% to 2.2±30%*1
μF
VDDL pin external
capacitance
CL
Ca,b,c
C12
―
―
―
0.47±30% to 2.2±30%*2
0.1±30%
μF
μF
μF
VL1, 2, or 3 pin external
capacitance
Pin-to-pin (C1 to C2)
external capacitance
0.47±30%
*1: Please select as CV is larger than CL or same as CL.
*2: When the load of VDD is small and the power rise time is too short, it may happen that the power-on reset is not
generated. In this case please select CL with larger capacitance
26/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
Operating conditions of FlashROM
(VSS= 0V)
Parameter
Symbol
TOP
VDD
VDDL
VPP
CEP
Condition
At write/erase
At write/erase
At write/erase*1
At write/erase
―
Range
0 to +40
2.75 to 3.6
2.5 to 2.75
7.7 to 8.3
80
Unit
°C
Operating temperature
Operating voltage
V
Rewrite count
Data retention
cycles
years
YDR
―
10
*1: When writing to and erasing on the flash Memory, the voltage in the specified range needs to be supplied to the VDDL pin.
The VPP pin has an internal pull-down resistor.
DC Characteristics (1/6)
(VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Measur
ement
circuit
Rating
Parameter
Symbol
Condition
Ta=25°C
Unit
Max.
Typ.
+10%
Typ.
Min.
Typ.
-10%
Typ.
Typ.
500
kHz
kHz
s
500kHz RC oscillation
frequency
VDD=1.25
to 3.6V
fRC
2
*
500
0.6
-25%
+25%
Low-speed crystal
TXTL
―
―
2
oscillation start time*1
1
500kHz RC oscillation start
time
Reset pulse width
Reset noise elimination
pulse width
TRC
PRST
PNRST
―
―
―
―
200
―
―
―
―
3
μs
―
μs
0.3
Power-on reset generated
power rise time
TPOR
―
―
―
10
ms
*1: 32.768kHz crystal resonator DT-26 (Load capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (CGL=CDL=12pF).
*2: Recommended operating temperature (Ta=-20 to 70°C, Ta=-40 to 85°C for P version)
RESET
VIL1
VIL1
PRST
RESET_N
RESET_N pin reset
0.9xVDD
VDD
0.1xVDD
TPOR
Power on reset
27/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
DC Characteristics (2/6)
(VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Measur
ement
circuit
Rating
Typ.
1.2
Parameter
Symbol
VDDL
Condition
Unit
V
Max.
1.3
Min.
1.1
VDDL voltage
fop=30k to 625kHz
VDDL
temperature
∆VDDL
VDD=3.0V
―
-1
―
mV/°C
1
deviation *1
VDDL voltage
―
5
20
∆VDDL
―
mV/V
dependency *1
*1: The maximum VDDL voltage becomes the VDD voltage level when the VDDL voltage determined by the temperature and voltage
deviations mathematically exceeds the VDD voltage.
28/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
DC Characteristics for ML610471/472/473 (3/6)
(VDD=3.0V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Measur
ement
circuit
Rating
Parameter
Symbol
IDD1
Condition
Unit
Max.
0.8
3
Min.
―
Typ.
0.3
―
CPU: In STOP state.
Low-speed/High-speed oscillation:
stopped.
Ta=25°C
Supply current 1
μA
5
*
―
CPU: In HALT state.
(LTBC, WDT: Operating)*3*4.
High-speed 500kHz oscillation:
Stopped.
Ta=25°C
―
―
―
―
0.8
―
3
1.8
4
Supply current 2
Supply current 3
IDD2
μA
5
*
LCD/BIAS circuits: Operating *6
1
CPU: In 32.768kHz operating
state.*1*3
Ta=25°C
6
IDD3
μA
μA
High-speed 500kHz oscillation:
Stopped,
LCD/BIAS circuits: Operating *2
5
*
―
9
CPU: In 500kHz RC operating
state.
Ta=25°C
―
―
50
70
80
Supply current
4-1
IDD4-1
5
LCD/BIAS circuits: Operating.*2
*
―
*1: When the CPU operating rate is 100% (no HALT state).
*2: All SEGs: off waveform, No LCD panel load, 1/3 bias, 1/3 duty, Frame frequency: Approx. 64 Hz, Bias voltage multiplying clock:
1/128 LSCLK (256Hz)
*3 : 32.768KHz crystal resonator DT-26 (Load capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (CGL=CDL=6pF)
*4 : Significant bits of BLKCON0 to BLKCON4 registers are all “1” except DLCD bit on BLKCON4.
*5 : Recommended operating temperature (Ta=-20 to 70°C, Ta=-40 to 85°C for P version)
*6: LCD stop mode, 1/3 bias, Bias voltage multiplying clock: 1/128 LSCLK (256Hz)
DC Characteristics for ML610Q471/Q472/Q473 (4/6)
(VDD=3.0V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Measur
ement
circuit
Rating
Parameter
Symbol
IDD1
Condition
Unit
Max.
1.25
5.5
Min.
―
Typ.
0.3
―
CPU: In STOP state.
Low-speed/High-speed oscillation:
stopped.
Ta=25°C
Supply current 1
μA
5
*
―
CPU: In HALT state.
(LTBC, WDT: Operating)*3*4.
High-speed 500kHz oscillation:
Stopped.
Ta=25°C
―
―
―
―
0.8
―
3.2
8.5
7.5
13
Supply current 2
Supply current 3
IDD2
μA
5
*
LCD/BIAS circuits: Operating *6
1
CPU: In 32.768kHz operating
state.*1*3
Ta=25°C
4.7
―
IDD3
μA
μA
High-speed 500kHz oscillation:
Stopped,
5
*
LCD/BIAS circuits: Operating *2
CPU: In 500kHz RC operating
state.
Ta=25°C
―
―
70
100
120
Supply current
4-1
IDD4-1
5
LCD/BIAS circuits: Operating.*2
*
―
*1: When the CPU operating rate is 100% (no HALT state).
*2: All SEGs: off waveform, No LCD panel load, 1/3 bias, 1/3 duty, Frame frequency: Approx. 64 Hz, Bias voltage multiplying clock:
1/128 LSCLK (256Hz)
*3 : 32.768KHz crystal resonator DT-26 (Load capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (CGL=CDL=6pF)
*4 : Significant bits of BLKCON0 to BLKCON4 registers are all “1” except DLCD bit on BLKCON4.
*5 : Recommended operating temperature (Ta=-20 to 70°C, Ta=-40 to 85°C for P version)
*6: LCD stop mode, 1/3 bias, Bias voltage multiplying clock: 1/128 LSCLK (256Hz)
29/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
DC Characteristics (5/6)
(VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Measur
ement
circuit
Rating
Parameter
Symbol
VOH1
Condition
Unit
Min.
Typ.
Max.
Output voltage 1
(P20, P21
(N-channel open
drain output
mode is not
selected))
(P35)
(P42 to P47)
(P60 to P63)
(P60 to P67)*1
Output voltage 2
(P20, P21
(N-channel open
drain output
mode is
VDD
-0.5
VDD
-0.3
IOH1=-0.5mA, VDD=1.8 to 3.6V
IOH1=-0.03mA, VDD=1.25 to 3.6V
―
―
―
―
―
IOL1=+0.5mA, VDD=1.8 to 3.6V
IOL1=+0.1mA, VDD=1.25 to 3.6V
―
0.5
VOL1
VOL2
*2
―
―
―
0.3
IOL2=+5mA, VDD=1.8 to 3.6V
―
0.5
2
V
selected))
VL3
-0.2
VOH3
VOML3
VOML3S
VOLM3
IOH3=-0.05mA, VL1=1.2V
IOML3=+0.05mA, VL1=1.2V
IOML3S=-0.05mA, VL1=1.2V
IOLM3=+0.05mA, VL1=1.2V
―
―
―
―
―
VL2
+0.2
―
Output voltage 3
(COM0 to 4)
VL2
-0.2
―
(SEG0 to 13)*1
(SEG0 to 17)*2
(SEG0 to 21)*3
VL1
+0.2
―
VL1
-0.2
VOLM3S
VOL3
IOLM3S=-0.05mA, VL1=1.2V
IOL3=+0.05mA, VL1=1.2V
―
―
―
―
―
0.2
Output leakage
(P20, P21)
(P35)
IOOH
VOH=VDD (in high-impedance state)
―
1
3
μA
(P42 to P47)
(P60 to P63)
(P60 to P67)*1
*2
IOOL
IIH1
VOL=VSS (in high-impedance state)
VIH1=VDD
-1
―
―
―
Input current 1
(RESET_N)
―
1
IIL1
IIH2
IIL2
VIL1=VSS
VIH2=VDD
VIL2=VSS
-600
2
-1
-300
300
―
-2
600
―
Input current 2
(TEST0)
VIH3=VDD, VDD=1.8 to 3.6V
(when pulled-down)
VIH3=VDD, VDD=1.25 to 3.6V
(when pulled-down)
VIL3=VSS, VDD=1.8 to 3.6V
(when pulled-up)
2
30
30
200
200
-2
IIH3
IIL3
4
0.01
-200
-200
μA
Input current 3
(P00 to P03)
(P35)
-30
-30
VIL3=VSS, VDD=1.25 to 3.6V
(when pulled-up)
(P42 to P47)
-0.01
IIH3Z
IIL3Z
VIH3=VDD (in high-impedance state)
―
―
―
1
VIL3=VSS (in high-impedance state)
-1
―
*1: Characteristics for ML610471/ML610Q471.
*2: Characteristics for ML610472/ML610Q472.
*3: Characteristics for ML610473/ML610Q473.
30/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
DC Characteristics (6/6)
(VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Measur
ement
circuit
Rating
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
VDD
Input voltage 1
(RESET_N)
(TEST0)
(P00 to P03)
(P35)
0.7
×VDD
VIH1
―
―
5
V
0.2
×VDD
VIL1
V
DD=1.25 to 3.6V
0
―
―
(P42 to P47)
Input pin
capacitance
(P00 to P03)
(P35)
f=10kHz
Vrms=50mV
Ta=25°C
CIN
―
5
pF
―
(P42 to P47)
31/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
Measuring Circuits
Measuring Circuit 1
CGL
XT0
CDL
XT1
C2
C1
32.768kHz
crystal
C12
resonator
CV
CL
: 1μF
: 2.2uF
Ca,Cb,Cc
C12
: 0.1μF
VDD
VDDL
VL2 VL3
VSS
VL1
: 0.47μF
32.768kHz crystal resonator
: DT-26 (Load capacitance 6pF)
A
(Made by KDS:DAISHINKU CORP.)
CV
CL
Cc
Ca
CGL, CDL
: 6pF
Measuring Circuit 2
(*2)
VIH
(*1)
V
VIL
VDD VDDL
VL1 VL2 VL3
VSS
*1: Input logic circuit to determine the specified measuring conditions.
*2: Repeats for the specified output pin
32/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
Measuring Circuit 3
(*2)
VIH
(*1)
A
VIL
VDD VDDL
VL1 VL2
VSS
VL3
*1: Input logic circuit to determine the specified measuring conditions.
*2: Repeats for the specified output pin
Measuring Circuit 4
(*1)
A
VDD VDDL
VL1 VL2
VSS
VL3
*1: Repeats for the specified input pin
33/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
Measuring Circuit 5
VIH
(*1)
VIL
VDD VDDL
VL1 VL2
VSS
VL3
*1: Input logic circuit to determine the specified measuring conditions.
34/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
AC Characteristics (External Interrupt)
(VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Rating
Parameter
Symbol
TNUL
Condition
Unit
Min.
76.8
Typ.
Max.
Interrupt: Enabled (MIE = 1),
CPU: NOP operation
External interrupt disable
period
―
106.8
μs
System clock: 32.768kHz
P00–P03
(Rising-edge interrupt)
tNUL
P00–P03
(Falling-edge interrupt)
tNUL
P00–P03
(Both-edge interrupt)
tNUL
AC Characteristics (UART)
(VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
Transmit baud rate
Receive baud rate
tTBRT
tRBRT
―
―
―
BRT*1
―
s
s
BRT*1
-3%
BRT*1
+3%
BRT*1
*1: Baud rate period (including the error of the clock frequency selected) set with the UART baud rate register (UA0BRTL,H) and
the UART mode register 0 (UA0MOD0).
tTBRT
TXD0*
tRBRT
RXD0*
*: Indicates the secondary function of the port.
35/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
AC Characteristics (RC Oscillation A/D Converter)
Condition for VDD=1.8 to 3.6V
(VDD=1.8 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
1
457.3
53.48
5.43
7.972
0.981
0.099
Typ.
―
Max.
―
575.1
62.43
6.32
9.782
1.019
0.104
Oscillation resistor
RS1,RT1
fOSC1
fOSC2
fOSC3
Kf1
CS0, CT0, CS1≥740pF
Resistor for oscillation=1kΩ
Resistor for oscillation=10kΩ
Resistor for oscillation=100kΩ
RT1=1kΩ
kΩ
kHz
kHz
kHz
⎯
525.2
58.18
5.89
9.028
1
Oscillation frequency
VDD = 3.0V
RS to RT oscillation
frequency ratio *1
VDD = 3.0V
Kf2
RT1=10kΩ
⎯
Kf3
0.101
RT1=100kΩ
⎯
*1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the
same conditions.
fOSCX(RT1-CS1 oscillation)
Kfx =
f
OSCX(RS1-CS1 oscillation)
( x = 1, 2, 3 )
,
CVR1
RT1: 1kΩ/10kΩ/100kΩ
RS1: 10kΩ
CS1: 560pF
CVR1: 820pF
IN1 CS1 RS1 RT1
RCM
VIH
Frequency measurement (fOSCX
)
(*1)
VIL
VDD VDDL
VSS
CV
CL
*1: Input logic circuit to determine the
specified measuring conditions.
36/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
Condition for VDD=1.25 to 3.6V
(VDD=1.25 to 3.6V, VSS=0V, Ta=-20 to +70°C, Ta=-40 to +85°C for P version, unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
1
81.93
35.32
5.22
2.139
0.973
0.142
85.28
35.72
5.189
2.227
0.982
0.141
Typ.
―
Max.
―
101.2
41.48
6.03
2.632
1.028
0.152
103.3
41.78
6.012
2.626
1.018
0.149
Oscillation resistor
RS1,RT1
fOSC1
fOSC2
fOSC3
Kf1
CS1≥740pF
Resistor for oscillation=6kΩ
Resistor for oscillation=15kΩ
Resistor for oscillation=105kΩ
RT1=1kΩ
kΩ
kHz
kHz
kHz
⎯
93.16
38.75
5.65
2.381
1
Oscillation frequency
VDD = 1.5V
RS to RT oscillation
frequency ratio *1
VDD = 1.5V
Kf2
RT1=10kΩ
⎯
Kf3
0.147
94.58
38.87
5.622
2.432
1
RT1=100kΩ
⎯
fOSC1
fOSC2
fOSC3
Kf1
kHz
kHz
kHz
⎯
Resistor for oscillation=6kΩ
Resistor for oscillation=15kΩ
Resistor for oscillation=105kΩ
RT1=1kΩ
Oscillation frequency
VDD = 3.0V
RS to RT oscillation
frequency ratio *1
VDD = 3.0V
Kf2
RT1=10kΩ
⎯
Kf3
0.145
RT1=100kΩ
⎯
*1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the
same conditions.
fOSCX(RT1-CS1 oscillation)
Kfx =
f
OSCX(RS1-CS1 oscillation)
( x = 1, 2, 3 )
,
CVR1
RT1: 1kΩ/10kΩ/100kΩ
RA1: 5kΩ
RS1: 15kΩ
CS1: 560pF
CVR1: 820pF
IN1 CS1 RS1 RT1
VIH
RCM
Frequency measurement (fOSCX)
(*1)
VIL
VDD VDDL
VSS
CV
CL
*1: Input logic circuit to determine the
specified measuring conditions.
Note:
･Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors and IN1 pin),
including CVR1. Especially, do not have long wiring between IN1 and RS1. The coupling capacitance on the wires may occur incorrect A/D
conversion. Also, please do not have signals which may be a source of noise around the node.
･When RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please have VSS(GND) trace next to the signal.
･Please make wiring to components (capacitor, resistor, and so on) necessary for objective measurement. Wiring to reserved components may
affect to the A/D conversion operation by noise the components itself may have.
37/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
PACKAGE DIMENSIONS
64pin TQFP Package
(Unit: mm)
P-TQFP64-1010-0.50-ZK9
Package material
Lead frame material
Lead finish
Epoxy resin
Cu alloy
Sn
Solder thickness
Package weight (g)
Rev. No./Last Revised
More than 5μm
0.26typ.
1 / Nov. 10,2011
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact ROHM’s responsible sales person for the product name, package name, pin
number, package code and desired mounting conditions (reflow method, temperature and times).
38/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
48 pin TQFP Package
(Unit: mm)
P-TQFP48-0707-0.50-K
Package material
Lead frame material
Lead finish
Solder thickness
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Sn-2Bi (Bi 2%typ.)
More than 5μm
0.13typ.
3 / Nov. 9,2011
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact ROHM’s responsible sales person for the product name, package name, pin
number, package code and desired mounting conditions (reflow method, temperature and times).
39/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
REVESION HISTORY
Page
Document No.
FEDL610473-01
Date
Description
Previous Current
Edition
Edition
Apr.25,2011
May.10,2011
Sep.13,2011
–
–
1,2,3
4
Formally edition 1
1,2,3
–
Add Mask ROM version(ML610471/ML610472/ML610473)
Add Block Diagram (Mask ROM version)
FEDL610473-02
FEDL610473-03
–
12,13,14 Add Chip Pad Layout and Dimensions (Mask ROM version)
15,16
3
20,21
3
Add Pad No of Mask ROM version into PIN list.
The package name of TQFP48 was changed.
15-17,
19-21
15-17,
19-21
The pads number were changed.
Add DC Characterristics
(ML610471/ML610472/ML610473)
The figures were revised.
28
29
FEDL610473-04
FEDL610473-05
FEDL610473-06
Sep.28,2011
Mar.27,2012
Jul.18,2012
15-17
26,32
25
15-17
26,32
25
The value of capacitor CL was changed to 2.2uF.
The pull down register(1kΩ to VSS) was added.
The notes about CV, CL were added.
The package dimension was changed.
26
26
38,39
38,39
The difference of the number of the port between chip, 48-pin
plastic TQFP and 64-pin plastic TQFP were added.
FEDL610473-07
Jan. 7,2013
2
2
40/41
FEDL610473-07
ML610471/472/473/Q471/Q472/Q473
NOTES
No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co.,
Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter "Products"). If you
wish to use any such Product, please be sure to refer to the specifications, which can be obtained from LAPIS Semiconductor
upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and
operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any
damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall bear no responsibility for such
damage.
The technical information specified herein is intended only to show the typical functions of and examples of application circuits
for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual
property or other rights held by LAPIS Semiconductor and other parties. LAPIS Semiconductor shall bear no responsibility
whatsoever for any dispute arising from the use of such technical information.
The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio
visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a Product may fail or
malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical
injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and
fail-safe designs. LAPIS Semiconductor shall bear no responsibility whatsoever for your use of any Product outside of the
prescribed scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely
high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human
injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller
or other safety device). LAPIS Semiconductor shall bear no responsibility in any way for use of any of the Products for the
above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales
representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign
Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
Copyright 2011 – 2013 LAPIS Semiconductor Co., Ltd.
41/41
相关型号：
ML610Q305
ML610Q305/ML610Q306是内置蓝碧石科技自有的RISC架构8位CPU“U8 Core”的、具有语音输出功能的高性能CMOS 8位微控制器。搭载了高音质的语音播放功能和高输出扬声器放大器，以单芯片实现了语音输出功能，非常适用于警报器和家电应用。 为了实现高音质的语音播放功能，利用新开发的高音质、高压缩比的语音压缩算法HQ-ADPCM，可以用比以往ADPCM更少的数据量来确保清晰的声音和宽广的音域，从而实现百听不厌、悦耳动听的声音。
ROHM
ML610Q306
ML610Q305/ML610Q306是内置蓝碧石科技自有的RISC架构8位CPU“U8 Core”的、具有语音输出功能的高性能CMOS 8位微控制器。搭载了高音质的语音播放功能和高输出扬声器放大器，以单芯片实现了语音输出功能，非常适用于警报器和家电应用。 为了实现高音质的语音播放功能，利用新开发的高音质、高压缩比的语音压缩算法HQ-ADPCM，可以用比以往ADPCM更少的数据量来确保清晰的声音和宽广的音域，从而实现百听不厌、悦耳动听的声音。
ROHM
ML610Q327
ML610Q327/ML610Q338/ML610Q339是内置蓝碧石科技自有的RISC架构8位CPU“U8 Core”的、具有语音输出功能的高性能8位微控制器。产品搭载了高音质的语音播放功能和高输出扬声器放大器，以单芯片实现了语音输出功能，非常适用于警报器和家电应用。为了实现高音质的语音播放功能，利用新开发的高音质、高压缩比的语音压缩算法HQ-ADPCM，可以用比以往ADPCM更少的数据量来确保清晰的声音和宽广的音域，从而实现百听不厌、悦耳动听的声音。ML610Q327的播放时间约为70秒*1，ML610Q338/ML610Q339的播放时间约为95秒*1。此外，还可以外接高达128Mbit的Flash存储器，因此也支持更长时间的播放。通过将这种出色的语音播放功能、低功耗高性能的U8 Core、支持3V/5V的电源以及丰富的外围控制功能集成于1枚芯片，为电池驱动和AC驱动的产品提供单芯片语音播放解决方案。*：程序区使用16KB、采样频率为6.4kHz、选择HQ-ADPCM时。
ROHM
ML610Q338
ML610Q327/ML610Q338/ML610Q339是内置蓝碧石科技自有的RISC架构8位CPU“U8 Core”的、具有语音输出功能的高性能8位微控制器。产品搭载了高音质的语音播放功能和高输出扬声器放大器，以单芯片实现了语音输出功能，非常适用于警报器和家电应用。为了实现高音质的语音播放功能，利用新开发的高音质、高压缩比的语音压缩算法HQ-ADPCM，可以用比以往ADPCM更少的数据量来确保清晰的声音和宽广的音域，从而实现百听不厌、悦耳动听的声音。ML610Q327的播放时间约为70秒*1，ML610Q338/ML610Q339的播放时间约为95秒*1。此外，还可以外接高达128Mbit的Flash存储器，因此也支持更长时间的播放。通过将这种出色的语音播放功能、低功耗高性能的U8 Core、支持3V/5V的电源以及丰富的外围控制功能集成于1枚芯片，为电池驱动和AC驱动的产品提供单芯片语音播放解决方案。*：程序区使用16KB、采样频率为6.4kHz、选择HQ-ADPCM时。
ROHM
ML610Q339
ML610Q327/ML610Q338/ML610Q339是内置蓝碧石科技自有的RISC架构8位CPU“U8 Core”的、具有语音输出功能的高性能8位微控制器。产品搭载了高音质的语音播放功能和高输出扬声器放大器，以单芯片实现了语音输出功能，非常适用于警报器和家电应用。为了实现高音质的语音播放功能，利用新开发的高音质、高压缩比的语音压缩算法HQ-ADPCM，可以用比以往ADPCM更少的数据量来确保清晰的声音和宽广的音域，从而实现百听不厌、悦耳动听的声音。ML610Q327的播放时间约为70秒*1，ML610Q338/ML610Q339的播放时间约为95秒*1。此外，还可以外接高达128Mbit的Flash存储器，因此也支持更长时间的播放。通过将这种出色的语音播放功能、低功耗高性能的U8 Core、支持3V/5V的电源以及丰富的外围控制功能集成于1枚芯片，为电池驱动和AC驱动的产品提供单芯片语音播放解决方案。*：程序区使用16KB、采样频率为6.4kHz、选择HQ-ADPCM时。
ROHM
©2020 ICPDF网 联系我们和版权申明