LTM9008-14_15_技术文档

LTM9008-14/

LTM9007-14/LTM9006-14

14-Bit, 65Msps/40Msps/

25Msps Low Power Octal ADCs

FeaTures

DescripTion

TheLTM^®9008-14/LTM9007-14/LTM9006-14are8-chan-

nel,simultaneoussampling14-bitA/Dconvertersdesigned

for digitizing high frequency, wide dynamic range signals.

AC performance includes 73dB SNR and 90dB spurious

free dynamic range (SFDR). Low power consumption per

channel reduces heat in high channel count applications.

Integrated bypass capacitance and flowthrough pinout

reduces overall board space requirements.

n

8-Channel Simultaneous Sampling ADC

n

73dB SNR

n

90dB SFDR

n

Low Power: 88mW/59mW/46mW per Channel

n

Single 1.8V Supply

n

Serial LVDS Outputs: 1 or 2 Bits per Channel

n

Selectable Input Ranges: 1V to 2V

P-P

n

800MHz Full Power Bandwidth S/H

Shutdown and Nap Modes

DC specs include 1LSB INL (typ), 0.3LSB DNL (typ)

and no missing codes over temperature. The transition

Serial SPI Port for Configuration

Internal Bypass Capacitance, No External

Components

noise is a low 1.2LSB

.

RMS

The digital outputs are serial LVDS to minimize the num-

ber of data lines. Each channel outputs two bits at a time

(2-lane mode). At lower sampling rates there is a one bit

per channel option (1-lane mode).

n

140-Pin (11.25mm × 9mm) BGA Package

applicaTions

n

Communications

+

–

The ENC and ENC inputs may be driven differentially

or single-ended with a sine wave, PECL, LVDS, TTL, or

CMOS inputs. An internal clock duty cycle stabilizer al-

lows high performance at full speed for a wide range of

clock duty cycles.

n

Cellular Base Stations

n

Software Defined Radios

n

Portable Medical Imaging

n

Multichannel Data Acquisition

n

Nondestructive Testing

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Typical applicaTion

LTM9008-14, 65Msps,

2-Tone FFT, f_IN= 70MHz and 75MHz

1.8V

OV

V

DD

CHANNEL 1

ANALOG

INPUT

0

–10

–20

–30

–40

14-BIT

OUT1A

OUT1B

S/H

ADC CORE

CHANNEL 2

ANALOG

INPUT

OUT2A

OUT2B

14-BIT

ADC CORE

DATA

SERIALIZER

–50

SERIALIZED

LVDS

–60

–70

OUTPUTS

CHANNEL 8

ANALOG

INPUT

OUT8A

OUT8B

14-BIT

ADC CORE

–80

–90

S/H

DATA

CLOCK

OUT

–100

–110

–120

ENCODE

INPUT

PLL

FRAME

0

20

10

FREQUENCY (MHz)

30

90067814 TA01

GND

90067814 TA01b

90067814fa

For more information www.linear.com/LTM9008-14

1

LTM9008-14/

LTM9007-14/LTM9006-14

absoluTe MaxiMuM raTings

pin conFiguraTion

(Notes 1, 2)

TOP VIEW

Supply Voltages

V , OV ................................................ –0.3V to 2V

DD

+

–

A

B

C

D

E

Analog Input Voltage (A , A

,

IN

PAR/SER, SENSE) (Note 3).......... –0.3V to (V + 0.2V)

DD

+

–

Digital Input Voltage (ENC , ENC , CS,

SDI, SCK) (Note 4).................................... –0.3V to 3.9V

SDO (Note 4)............................................. –0.3V to 3.9V

F

Digital Output Voltage................ –0.3V to (OV + 0.3V)

Operating Temperature Range

LTM9008C, LTM9007C, LTM9006C......... 0°C to 70°C

LTM9008I, LTM9007I, LTM9006I........–40°C to 85°C

Storage Temperature Range .................. –55°C to 125°C

DD

G

H

J

K

L

M

N

P

1

2

3

4

5

6

7

8

9

10

BGA PACKAGE

140-LEAD (11.25mm × 9.00mm × 2.72mm)

T

JMAX

= 150°C, θ = 30°C/W, θ = 25°C/W, θ = 15°C/W, θ

= 12°C/W

JA

JC

JB

JCbottom

orDer inForMaTion

LEAD FREE FINISH

LTM9008CY-14#PBF

LTM9008IY-14#PBF

LTM9007CY-14#PBF

LTM9007IY-14#PBF

LTM9006CY-14#PBF

LTM9006IY-14#PBF

TRAY

PART MARKING*

LTM9008Y14

LTM9007Y14

LTM9006Y14

PACKAGE DESCRIPTION

TEMPERATURE RANGE

0°C to 70°C

LTM9008CY-14#PBF

LTM9008IY-14#PBF

LTM9007CY-14#PBF

LTM9007IY-14#PBF

LTM9006CY-14#PBF

LTM9006IY-14#PBF

140-Lead (11.25mm × 9mm × 2.72mm) BGA

–40°C to 85°C

0°C to 70°C

–40°C to 85°C

0°C to 70°C

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

This product is only offered in trays. For more information go to: http://www.linear.com/packaging/

90067814fa

For more information www.linear.com/LTM9008-14

2

LTM9008-14/

LTM9007-14/LTM9006-14

converTer characTerisTics _{The l denotes the specifications which apply over the full operating}

temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

LTM9008-14

LTM9007-14

LTM9006-14

MIN TYP MAX

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

Bits

l

Resolution (No Missing Codes)

Integral Linearity Error

Differential Linearity Error

Offset Error

14

–2.75

–0.8

–12

14

Differential Analog Input (Note 6)

Differential Analog Input

(Note 7)

–4.1

–0.9

–12

1.2

0.3

3

4.1

0.9

12

1

0.3

3

2.75 –2.75

1

0.3

3

2.75

0.8

12

LSB

mV

0.8

12

–0.8

–12

Gain Error

Internal Reference

External Reference

–1.3

%FS

l

–2.5

0.5

–2.5

0.5

–2.6

0.5

Offset Drift

20

µV/°C

Full-Scale Drift

Internal Reference

External Reference

35

25

35

25

35

25

ppm/°C

Gain Matching

Offset Matching

Transition Noise

External Reference

0.2

3

0.2

3

0.2

3

%FS

mV

External Reference

1.2

LSB

RMS

analog inpuT ^Thel denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

1.7V < V < 1.9V

MIN

TYP

MAX

UNITS

+

–

l

V

Analog Input Range (A – A

)

+

1 to 2

V

P-P

IN

DD

–

Analog Input Common Mode (A + A )/2 Differential Analog Input (Note 8)

V

CM

– 100mV

0.625

V

CM

V

CM

+ 100mV

1.300

V

IN(CM)

SENSE

INCM

IN

External Voltage Reference Applied to SENSE External Reference Mode

1.250

V

I

Analog Input Common Mode Current

Per Pin, 65Msps

Per Pin, 40Msps

Per Pin, 25Msps

81

50

31

µA

+

–

l

I

t

Analog Input Leakage Current

0 < A , A < V , No Encode

–1

–3

–6

1

3

6

µA

ns

IN1

IN

DD

PAR/SER Input Leakage Current

SENSE Input Leakage Current

0 < PAR/SER < V

IN2

DD

0.625 < SENSE < 1.3V

IN3

Sample-and-Hold Acquisition Delay Time

Sample-and-Hold Acquisition Delay Jitter

Analog Input Common Mode Rejection Ratio

Full-Power Bandwidth

0

AP

0.15

80

ps

RMS

JITTER

CMRR

BW-3B

dB

Figure 6 Test Circuit

800

MHz

90067814fa

For more information www.linear.com/LTM9008-14

3

LTM9008-14/

LTM9007-14/LTM9006-14

DynaMic accuracy ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C. A_IN= –1dBFS. (Note 5)

LTM9008-14

LTM9007-14

LTM9006-14

MIN TYP MAX UNITS

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

SNR

Signal-to-Noise Ratio

5MHz Input

73.7

73.5

73

73.5

73.4

72.8

72.9

72.8

72.3

dBFS

l

30MHz Input

70MHz Input

140MHz Input

71.8

74

69.6

76.8

84

69.6

76.8

84

SFDR

Spurious Free Dynamic Range 5MHz Input

2nd or 3rd Harmonic

90

89

84

90

89

84

90

89

84

dBFS

30MHz Input

70MHz Input

140MHz Input

Spurious Free Dynamic Range 5MHz Input

4th Harmonic or Higher

90

dBFS

30MHz Input

70MHz Input

140MHz Input

84

S/(N+D) Signal-to-Noise Plus

Distortion Ratio

5MHz Input

73.6

73.5

73.2

72.5

73.3

73.2

73.1

72.3

72.8

72.7

72.5

71.9

dBFS

30MHz Input

70MHz Input

140MHz Input

71

69.5

Crosstalk, Near Channel

Crosstalk, Far Channel

10MHz Input (Note 12)

–90

dBc

–105

inTernal reFerence characTerisTics ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C. A_IN= –1dBFS. (Note 5)

PARAMETER

CONDITIONS

= 0

MIN

TYP

0.5 • V

25

MAX

UNITS

V

CM

V

CM

V

CM

V

REF

V

REF

V

REF

V

REF

Output Voltage

I

0.5 • V – 25mV

0.5 • V + 25mV

OUT

DD

Output Temperature Drift

Output Resistance

Output Voltage

ppm/°C

Ω

–600µA < I

< 1mA

4

OUT

I

= 0

1.225

1.250

25

1.275

V

OUT

Output Temperature Drift

Output Resistance

Line Regulation

ppm/°C

Ω

–400µA < I

7

OUT

1.7V < V < 1.9V

0.6

mV/V

DD

90067814fa

For more information www.linear.com/LTM9008-14

4

LTM9008-14/

LTM9007-14/LTM9006-14

DigiTal inpuTs anD ouTpuTs ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

–

ENCODE INPUTS (ENC , ENC )

–

Differential Encode Mode (ENC Not Tied to GND)

l

V

Differential Input Voltage

(Note 8)

0.2

V

ID

Common Mode Input Voltage

Internally Set

Externally Set (Note 8)

1.2

V

ICM

l

1.1

0.2

1.6

3.6

+

–

V

IN

Input Voltage Range

Input Resistance

ENC , ENC to GND

(See Figure 10)

V

kΩ

pF

R

10

IN

C

Input Capacitance

3.5

–

Single-Ended Encode Mode (ENC Tied to GND)

V

High Level Input Voltage

Low Level Input Voltage

Input Voltage Range

Input Resistance

V

= 1.8V

1.26

0.54

0 to 3.6

30

V

IH

IL

IN

DD

+

ENC to GND

V

R

(See Figure 11)

kΩ

pF

IN

C

Input Capacitance

3.5

IN

DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)

l

V

High Level Input Voltage

Low Level Input Voltage

Input Current

V

= 1.8V

1.3

V

IH

IL

DD

IN

l

= 1.8V

0.6

10

I

IN

= 0V to 3.6V

–10

µA

pF

C

IN

Input Capacitance

3

200

3

SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO Is Used)

R

Logic Low Output Resistance to GND

Logic High Output Leakage Current

Output Capacitance

V

= 1.8V, SDO = 0V

DD

Ω

µA

pF

OL

l

I

SDO = 0V to 3.6V

–10

10

OH

C

OUT

DIGITAL DATA OUTPUTS

l

V

Differential Output Voltage

100Ω Differential Load, 3.5mA Mode

100Ω Differential Load, 1.75mA Mode

247

125

350

175

454

250

mV

OD

l

V

Common Mode Output Voltage

On-Chip Termination Resistance

100Ω Differential Load, 3.5mA Mode

100Ω Differential Load, 1.75mA Mode

1.125

1.250

1.375

V

OS

R

Termination Enabled, OV = 1.8V

100

Ω

TERM

DD

90067814fa

For more information www.linear.com/LTM9008-14

5

LTM9008-14/

LTM9007-14/LTM9006-14

power requireMenTs ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 9)

LTM9008-14

LTM9007-14

LTM9006-14

SYMBOL PARAMETER

CONDITIONS

(Note 10)

MIN TYP MAX MIN

TYP

MAX MIN TYP MAX UNITS

l

V

Analog Supply Voltage

Output Supply Voltage

Analog Supply Current

Digital Supply Current

1.7

1.8

1.9

1.7

1.8

1.9

1.7

1.8

1.9

V

DD

OV

(Note 10)

1.8

DD

I

Sine Wave Input

357

400

232

275

175

250

mA

VDD

OVDD

1-Lane Mode, 1.75mA Mode

1-Lane Mode, 3.5mA Mode

2-Lane Mode, 1.75mA Mode

2-Lane Mode, 3.5mA Mode

32

60

50

94

32

58

48

92

30

56

48

90

mA

l

58

54

104

102

100

P

Power Dissipation

1-Lane Mode, 1.75mA Mode

1-Lane Mode, 3.5mA Mode

2-Lane Mode, 1.75mA Mode

2-Lane Mode, 3.5mA Mode

700

751

733

812

475

522

504

583

369

416

401

477

mW

DISS

l

824

907

592

679

547

630

P

Sleep Mode Power

Nap Mode Power

2

mW

SLEEP

NAP

170

40

170

40

170

40

Power Decrease With Single-Ended Encode Mode Enabled

(No Decrease for Sleep Mode)

DIFFCLK

TiMing characTerisTics ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 5)

LTM9008-14

LTM9007-14

MIN TYP MAX

LTM9006-14

MIN TYP MAX UNITS

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

65

100 11.88 12.5

100 12.5

l

f

t

Sampling Frequency

(Notes 10,11)

5

40

5

25

MHz

S

l

ENC Low Time (Note 8) Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

7.3

2

7.69

100

19

2

20

100

ns

ENCL

2

l

t

ENC High Time (Note 8) Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

7.3

2

7.69

100 11.88 12.5

100

19

2

20

100

ns

ENCH

AP

100

2

12.5

t

Sample-and-Hold

Acquisition Delay Time

0

ns

SYMBOL PARAMETER

Digital Data Outputs (R

CONDITIONS

= 100Ω Differential, C = 2pF to GND on Each Output)

MIN

TYP

MAX

UNITS

TERM

L

t

Serial Data Bit Period

2-Lanes, 16-Bit Serialization

2-Lanes, 14-Bit Serialization

2-Lanes, 12-Bit Serialization

1-Lane, 16-Bit Serialization

1-Lane, 14-Bit Serialization

1-Lane, 12-Bit Serialization

1/(8 • f )

s

SER

S

1/(7 • f )

S

1/(6 • f )

S

1/(16 • f )

S

1/(14 • f )

S

1/(12 • f )

S

l

t

FR to DCO Delay

DATA to DCO Delay

Propagation Delay

Output Rise Time

Output Fall Time

(Note 8)

0.35 • t

0.5 • t

0.65 • t

s

FRAME

DATA

PD

SER

(Note 8)

SER

(Note 8)

0.7n + 2 • t

1.1n + 2 • t

1.5n + 2 • t

SER

s

SER

Data, DCO, FR, 20% to 80%

0.17

60

ns

R

F

DCO Cycle-Cycle Jitter

Pipeline Latency

t

= 1ns

ps

P-P

SER

6

Cycles

90067814fa

For more information www.linear.com/LTM9008-14

6

LTM9008-14/

LTM9007-14/LTM9006-14

TiMing characTerisTics ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

SPI Port Timing (Note 8)

CONDITIONS

MIN

TYP

MAX

UNITS

l

t

SCK Period

Write Mode

40

ns

SCK

Read Back Mode, C

= 20pF,

250

SDO

R

= 2k

PULLUP

l

t

CS to SCK Setup Time

SCK to CS Setup Time

SDI Setup Time

5

ns

S

H

DS

DH

DO

SDI Hold Time

SCK Falling to SDO Valid

Read Back Mode, C

125

SDO

R

= 2k

PULLUP

Note 7: Offset error is the offset voltage measured from –0.5 LSB when

the output code flickers between 00 0000 0000 0000 and 11 1111 1111

1111 in 2’s complement output mode.

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 8: Guaranteed by design, not subject to test.

Note 2: All voltage values are with respect to GND (unless otherwise

noted).

Note 9: V = OV = 1.8V, f

= 65MHz (LTM9008), 40MHz

DD

SAMPLE

(LTM9007), or 25MHz (LTM9006), 2-lane output mode, differential

+

–

ENC /ENC = 2V sine wave, input range = 2V with differential

Note 3: When these pin voltages are taken below GND or above V , they

P-P

DD

drive, unless otherwise noted. The supply current and power dissipation

specifications are totals for the entire device, not per channel.

will be clamped by internal diodes. This product can handle input currents

of greater than 100mA below GND or above V without latchup.

DD

Note 10: Recommended operating conditions.

Note 4: When these pin voltages are taken below GND they will be

clamped by internal diodes. When these pin voltages are taken above V

they will not be clamped by internal diodes. This product can handle input

currents of greater than 100mA below GND without latchup.

DD

Note 11: The maximum sampling frequency depends on the speed grade

of the part and also which serialization mode is used. The maximum serial

data rate is 1000Mbps so t

must be greater than or equal to 1ns.

SER

Note 5: V = OV = 1.8V, f

= 65MHz (LTM9008), 40MHz

DD

SAMPLE

Note 12: Near-channel crosstalk refers to Ch. 1 to Ch.2, and Ch.7 to Ch.8.

Far-channel crosstalk refers to Ch.1 to Ch.7, Ch.1 to Ch.8, Ch.2 to Ch.7, and

Ch.2 to Ch.8.

+

(LTM9007), or 25MHz (LTM9006), 2-lane output mode, differential ENC /

–

ENC = 2V sine wave, input range = 2V with differential drive, unless

P-P

otherwise noted.

Note 6: Integral nonlinearity is defined as the deviation of a code from a

best fit straight line to the transfer curve. The deviation is measured from

the center of the quantization band.

90067814fa

For more information www.linear.com/LTM9008-14

7

LTM9008-14/

LTM9007-14/LTM9006-14

TiMing DiagraMs

2-Lane Output Mode, 16-Bit Serialization*

t

AP

N+1

ANALOG

INPUT

N

t

ENCL

ENCH

–

ENC

+

ENC

t

SER

–

DCO

+

DCO

t

SER

FRAME

DATA

–

FR

+

FR

t

SER

PD

–

OUT#A

D5 D3 D1

0

D13 D11 D9 D7 D5 D3 D1

0

D13 D11 D9

D12 D10 D8

+

OUT#A

–

OUT#B

D4 D2 D0

SAMPLE N-6

D12 D10 D8 D6 D4 D2 D0

SAMPLE N-5

0

+

OUT#B

SAMPLE N-4

90067814 TD01

*SEE THE DIGITAL OUTPUTS SECTION

2-Lane Output Mode, 14-Bit Serialization

t

AP

N+2

ANALOG

INPUT

N

N+1

t

ENCL

ENCH

–

ENC

+

ENC

t

SER

–

DCO

+

DCO

t

SER

FRAME

DATA

–

FR

+

FR

t

SER

PD

–

OUT#A

D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9

+

OUT#A

–

OUT#B

D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8

+

OUT#B

SAMPLE N-6

SAMPLE N-5

–

SAMPLE N-4

SAMPLE N-3

90067814 TD02

+

–

NOTE THAT IN THIS MODE FR /FR HAS TWO TIMES THE PERIOD OF ENC /ENC

90067814fa

For more information www.linear.com/LTM9008-14

8

LTM9008-14/

LTM9007-14/LTM9006-14

TiMing DiagraMs

2-Lane Output Mode, 12-Bit Serialization

t

AP

ANALOG

INPUT

N

N+1

t

ENCL

ENCH

–

ENC

+

ENC

t

SER

–

DCO

+

DCO

t

SER

FRAME

DATA

+

FR

–

FR

t

PD

SER

–

OUT#A

D9 D7 D5 D3 D13 D11 D9 D7 D5 D3 D13 D11 D9

+

OUT#A

–

OUT#B

D8 D6 D4 D2 D12 D10 D8 D6 D4 D2 D12 D10 D8

+

OUT#B

SAMPLE N-6

SAMPLE N-5

SAMPLE N-4

90067814 TD03

1-Lane Output Mode, 16-Bit Serialization

t

AP

N+1

ANALOG

INPUT

N

t

ENCL

ENCH

–

ENC

+

ENC

t

SER

–

DCO

+

DCO

t

SER

FRAME

DATA

–

FR

+

FR

t

SER

PD

–

OUT#A

D1 D0

0

D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0

D13 D12 D11 D10

+

OUT#A

90067814 TD04

SAMPLE N-6

SAMPLE N-5

SAMPLE N-4

+

–

OUT#B , OUT#B ARE DISABLED

1-Lane Output Mode, 14-Bit Serialization

t

AP

N+1

ANALOG

INPUT

N

t

ENCL

ENCH

–

ENC

+

ENC

t

SER

–

DCO

+

DCO

t

SER

FRAME

DATA

–

FR

+

FR

t

SER

PD

–

OUT#A

D3 D2 D1 D0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D13 D12 D11 D10

+

OUT#A

90067814 TD06

SAMPLE N-6

SAMPLE N-5

SAMPLE N-4

+

–

OUT#B , OUT#B ARE DISABLED

90067814fa

For more information www.linear.com/LTM9008-14

9

LTM9008-14/

LTM9007-14/LTM9006-14

TiMing DiagraMs

1-Lane Output Mode, 12-Bit Serialization

t

AP

N+1

ANALOG

INPUT

N

t

ENCL

ENCH

–

ENC

+

ENC

t

SER

–

DCO

+

DCO

t

SER

FRAME

DATA

–

FR

+

FR

t

SER

PD

–

OUT#A

D5 D4 D3 D2 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D13 D12 D11

+

OUT#A

SAMPLE N-6

SAMPLE N-5

SAMPLE N-4

90067814 TD07

+

–

OUT#B , OUT#B ARE DISABLED

SPI Port Timing (Readback Mode)

t

S

t

DS

t

DH

t

H

SCK

CS

SCK

t

DO

SDI

A6

A5

A4

A3

A2

A1

A0

XX

D6

XX

D5

XX

D4

XX

D3

XX

D2

XX

D1

XX

R/W

SDO

D7

D0

HIGH IMPEDANCE

SPI Port Timing (Write Mode)

CS

SCK

SDI

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

R/W

SDO

90067814 TD08

HIGH IMPEDANCE

90067814fa

For more information www.linear.com/LTM9008-14

10

LTM9008-14/

LTM9007-14/LTM9006-14

Typical perForMance characTerisTics

LTM9008-14: Integral

Nonlinearity (INL) vs Output Code

LTM9008-14: Differential

Nonlinearity (DNL) vs Output Code

LTM9008-14: 64k Point FFT,

f_IN= 5MHz, –1dBFS, SENSE = V_DD

0

–10

0.5

0.4

2.0

1.5

–20

0.3

–30

1.0

0.2

–40

0.5

0.1

–50

–60

0

–70

–0.1

–0.2

–0.3

–0.4

–0.5

–1.0

–1.5

–2.0

–80

–90

–100

–110

–120

8192

0

4096

12288

16384

20

FREQUENCY (MHz)

35

0

8192

12288

0

10

15

25

30

4096

16384

5

OUTPUT CODE

90067814 G01

90067814 G02

90067814 G03

LTM9008-14: 64k Point FFT,

f_IN= 30MHz, –1dBFS, SENSE = V_DD

LTM9008-14: 64k Point FFT,

f_IN= 70MHz, –1dBFS, SENSE = V_DD

0

–10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–100

–110

–120

0

10

15

20

25

30

35

5

0

10

15

20

25

30

35

5

FREQUENCY (MHz)

90067814 G04

90067814 G05

LTM9008-14: 64k Point 2-Tone FFT,

f_IN= 28.5MHz and f_IN= 31.5MHz,

–7dBFS per Tone, SENSE = V_DD

LTM9008-14: Shorted Input

Histogram

0

–10

6000

5000

4000

3000

–20

–30

–40

–50

–60

–70

–80

2000

1000

0

–90

–100

–110

–120

8197

8201

8203

8205

8199

0

10

15

20

25

30

35

5

OUTPUT CODE

FREQUENCY (MHz)

90067814 G07

90067814 G06

90067814fa

For more information www.linear.com/LTM9008-14

11

LTM9008-14/

LTM9007-14/LTM9006-14

Typical perForMance characTerisTics

LTM9008-14: SNR vs Input

Frequency, –1dBFS, 2V Range,

65Msps

LTM9008-14: SFDR vs Input

Frequency, –1dBFS, 2V Range,

65Msps

LTM9008-14: SFDR vs Input Level,

f

_IN= 70MHz, 2V Range, 65Msps

74

73

72

71

70

95

90

85

80

75

70

65

110

100

90

dBFS

80

70

60

dBc

50

40

30

20

10

0

69

68

67

66

0

100 150 200 250 300 350

INPUT FREQUENCY (MHz)

0

100 150 200 250 300 350

INPUT FREQUENCY (MHz)

–80

–70

–60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

50

90067814 G08

90067814 G09

90067814 G11

LTM9008-14: SNR vs Input Level,

LTM9008-14: I_VDDvs Sample Rate,

5MHz Sine Wave Input, –1dBFS

f

_IN= 70MHz, 2V Range, 65Msps

320

310

80

70

60

50

40

30

20

10

0

dBFS

300

290

280

270

260

250

240

230

220

dBc

0

10

20

30

40

50

60

–60

–50

–40

–30

–20

–10

0

SAMPLE RATE (Msps)

INPUT LEVEL (dBFS)

90067814 G12

90067814 G11

I_OVDDvs Sample Rate, 5MHz Sine

Wave Input, –1dBFS

LTM9008-14: SNR vs SENSE,

_IN= 5MHz, –1dBFS

f

50

40

30

75

74

73

72

71

70

2-LANE, 3.5mA

1-LANE, 3.5mA

2-LANE, 1.75mA

1-LANE, 1.75mA

20

10

0

69

68

67

0.6 0.7 0.8 0.9

1

1.1 1.2 1.3

0

20

40

60

SENSE PIN (V)

SAMPLE RATE (Msps)

90067814 G14

90067814 G13

90067814fa

For more information www.linear.com/LTM9008-14

12

LTM9008-14/

LTM9007-14/LTM9006-14

Typical perForMance characTerisTics

LTM9007-14: Integral Nonlinearity

(INL) vs Output Code

LTM9007-14: Differential

Nonlinearity (DNL) vs Output Code

LTM9007-14: 64k Point FFT,

f_IN= 5MHz, –1dBFS, SENSE = V_DD

0.5

0.4

2.0

1.5

0

–10

–20

0.3

–30

–40

–50

1.0

0.2

0.5

0.1

0

–60

–70

0

–0.1

–0.2

–0.3

–0.4

–0.5

–1.0

–1.5

–2.0

–80

–90

–100

–110

–120

8192

0

5

10

15

20

0

4096

12288

16384

0

8192

12288

4096

16384

OUTPUT CODE

FREQUENCY (MHz)

90067814 G15

90067814 G17

90067814 G16

LTM9007-14: 64k Point FFT,

f_IN= 30MHz, –1dBFS, SENSE = V_DD

LTM9007-14: 64k Point FFT,

f_IN= 70MHz, –1dBFS, SENSE = V_DD

0

–10

–20

0

–10

–20

–30

–40

–50

–30

–40

–50

–60

–70

–80

–90

–60

–70

–80

–90

–100

–110

–120

–100

–110

–120

10

0

5

15

20

0

5

15

20

FREQUENCY (MHz)

90067814 G19

90067814 G18

LTM9007-14: 64k Point 2-Tone FFT,

f_IN= 28.5MHz and f_IN= 31.5MHz,

–7dBFS per Tone, SENSE = V_DD

LTM9007-14: Shorted Input

Histogram

6000

5000

4000

3000

0

–10

–20

–30

–40

–50

–60

–70

–80

2000

1000

0

–90

–100

–110

–120

8

10 12

8198

8202

8204

8206

0

2

4

6

14 16 18 20

8200

OUTPUT CODE

FREQUENCY (MHz)

90067814 G20

90067814 G21

90067814fa

For more information www.linear.com/LTM9008-14

13

LTM9008-14/

LTM9007-14/LTM9006-14

Typical perForMance characTerisTics

LTM9007-14: SNR vs Input

Frequency, –1dBFS, 2V Range,

40Msps

LTM9007-14: SFDR vs Input

Frequency, –1dBFS, 2V Range,

40Msps

LTM9007-14: SFDR vs Input Level,

f

_IN= 70MHz, 2V Range, 40Msps

74

73

72

71

70

95

90

85

80

75

70

65

110

100

90

dBFS

80

70

60

dBc

50

40

30

20

10

0

69

68

67

66

0

100 150 200 250 300 350

INPUT FREQUENCY (MHz)

0

100 150 200 250 300 350

INPUT FREQUENCY (MHz)

–80

–70

–60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

50

90067814 G22

90067814 G23

90067814 G24

LTM9007-14: I_VDDvs Sample Rate,

5MHz Sine Wave Input, –1dBFS

LTM9007-14: SNR vs SENSE,

_IN= 5MHz, –1dBFS

f

200

190

180

170

160

150

140

74

73

72

71

70

69

68

67

66

0.6 0.7 0.8 0.9

1

1.1 1.2 1.3

0

10

20

30

40

SENSE PIN (V)

SAMPLE RATE (Msps)

90067814 G26

90067814 G25

90067814fa

For more information www.linear.com/LTM9008-14

14

LTM9008-14/

LTM9007-14/LTM9006-14

Typical perForMance characTerisTics

LTM9006-14: Integral Nonlinearity

(INL) vs Output Code

LTM9006-14: Differential

Nonlinearity (DNL) vs Output Code

LTM9006-14: 64k Point FFT,

f_IN= 5MHz, –1dBFS, SENSE = V_DD

0.5

0.4

2.0

1.5

0

–10

–20

0.3

–30

–40

–50

1.0

0.2

0.5

0.1

0

–60

–70

0

–0.1

–0.2

–0.3

–0.4

–0.5

–1.0

–1.5

–2.0

–80

–90

–100

–110

–120

8192

8

10

12

0

4096

12288

16384

0

8192

12288

0

2

4

6

14

4096

16384

OUTPUT CODE

FREQUENCY (MHz)

90067814 G27

90067814 G28

90067814 G29

LTM9006-14: 64k Point FFT,

f_IN= 70MHz, –1dBFS, SENSE = V_DD

f

_IN= 30MHz, –1dBFS, SENSE = V_DD

0

–10

–20

0

–10

–20

–30

–40

–50

–30

–40

–50

–60

–70

–60

–70

–80

–90

–100

–110

–120

–100

–110

–120

8

10

12

0

2

4

6

14

8

10

12

0

2

4

6

14

FREQUENCY (MHz)

90067814 G30

90067814 G31

LTM9006-14: 64k Point 2-Tone FFT,

_IN= 28.5MHz and 31.5MHz, –7dBFS

per Tone, SENSE = V_DD

f

LTM9006-14: Shorted Input

Histogram

6000

5000

4000

3000

0

–10

–20

–30

–40

–50

–60

–70

–80

2000

1000

0

–90

–100

–110

–120

8

10

12

8198

8202

8204

8206

0

2

4

6

14

8200

OUTPUT CODE

FREQUENCY (MHz)

90067814 G32

90067814 G33

90067814fa

For more information www.linear.com/LTM9008-14

15

LTM9008-14/

LTM9007-14/LTM9006-14

Typical perForMance characTerisTics

LTM9006-14: SNR vs Input

Frequency, –1dBFS, 2V Range,

25Msps

LTM9006-14: SFDR vs Input

Frequency, –1dBFS, 2V Range,

25Msps

LTM9006-14: SFDR vs Input Level,

f_IN= 70MHz, 2V Range, 25Msps

74

73

72

71

70

95

90

85

80

75

70

65

110

100

90

dBFS

80

70

dBc

60

50

40

30

20

10

0

69

68

67

66

0

100 150 200 250 300 350

INPUT FREQUENCY (MHz)

0

100 150 200 250 300 350

INPUT FREQUENCY (MHz)

–80

–70

–60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

50

90067814 G34

90067814 G35

90067814 G36

LTM9006-14: I_VDDvs Sample Rate,

5MHz Sine Wave Input, –1dBFS

LTM9006-14: SNR vs SENSE,

_IN= 5MHz, –1dBFS

DCO Cycle-Cycle Jitter vs Serial

Data Rate

f

350

300

250

200

150

160

150

140

130

74

73

72

71

70

69

100

50

0

68

67

66

120

0

5

10

15

20

25

0

200

400

600

800

1000

0.6 0.7 0.8 0.9

1

1.1 1.2 1.3

SAMPLE RATE (Msps)

SERIAL DATA RATE (Mbps)

SENSE PIN (V)

90067814 G37

90067814 G39

90067814 G38

90067814fa

For more information www.linear.com/LTM9008-14

16

LTM9008-14/

LTM9007-14/LTM9006-14

pin FuncTions

+

–

A

V

(B2): Channel 1 Positive Differential Analog Input.

A

IN8

A

IN8

V

DD

(N1): Channel 8 Positive Differential Analog Input.

(N2): Channel 8 Negative Differential Analog Input

IN1

–

(B1): Channel 1 Negative Differential Analog Input.

IN1

(B3): Common Mode Bias Output, Nominally Equal

(D3, D4, E3, E4, K3, K4, L3, L4): 1.8V Analog Power

CM12

to V /2. V should be used to bias the common mode

Supply. V is internally bypassed to ground with 0.1μF

DD

CM

DD

of the analog inputs of channels 1 and 2. V is internally

ceramic capacitors.

CM

bypassed to ground with a 0.1µF ceramic capacitor. No

+

ENC (P5): Encode Input. Conversion starts on the rising

external capacitance is required.

edge.

+

A

IN2

A

IN2

A

IN3

A

IN3

V

(C2): Channel 2 Positive Differential Analog Input.

(C1): Channel 2 Negative Differential Analog Input.

(E2): Channel 3 Positive Differential Analog Input.

(E1): Channel 3 Negative Differential Analog Input.

(F3): Common Mode Bias Output, Nominally Equal

–

ENC (P6): Encode Complement Input. Conversion starts

–

+

–

on the falling edge.

CSA (L5): In serial programming mode, (PAR/SER = 0V),

CSA is the serial interface chip select input for registers

controlling channels 1, 4, 5 and 8. When CS is low, SCK

is enabled for shifting data on SDI into the mode control

CM34

to V /2. V should be used to bias the common mode

registers.Inparallelprogrammingmode(PAR/SER=V ),

DD

CM

DD

of the analog inputs of channels 3 and 4. V is internally

CS selects 2-lane or 1-lane output mode. CS can be driven

CM

bypassed to ground with a 0.1µF ceramic capacitor. No

with 1.8V to 3.3V logic.

external capacitance is required.

CSB (M5): In serial programming mode, (PAR/SER = 0V),

CSB is the serial interface chip select input for registers

controlling channels 2, 3, 6 and 7. When CS is low, SCK

is enabled for shifting data on SDI into the mode control

+

A

IN4

A

IN4

A

IN5

A

IN5

V

(G2): Channel 4 Positive Differential Analog Input.

(G1): Channel 4 Negative Differential Analog Input.

(H1): Channel 5 Positive Differential Analog Input.

(H2): Channel 5 Negative Differential Analog Input.

–

+

–

registers.Inparallelprogrammingmode(PAR/SER=V ),

DD

CS selects 2-lane or 1-lane output mode. CS can be driven

with 1.8V to 3.3V logic.

(J3): Common Mode Bias Output, Nominally Equal

CM56

SCK (L6): In serial programming mode, (PAR/SER =

to V /2. V should be used to bias the common mode

DD

CM

0V), SCK is the serial interface clock input. In parallel

of the analog inputs of channels 5 and 6. V is internally

CM

programmingmode(PAR/SER=V ),SCKselects3.5mA

bypassed to ground with a 0.1µF ceramic capacitor. No

DD

or 1.75mA LVDS output currents. SCK can be driven with

external capacitance is required.

1.8V to 3.3V logic.

+

A

IN6

A

IN6

A

IN7

A

IN7

V

(K1): Channel 6 Positive Differential Analog Input.

(K2): Channel 6 Negative Differential Analog Input.

(M1): Channel 7 Positive Differential Analog Input.

(M2): Channel 7 Negative Differential Analog Input.

(N3): Common Mode Bias Output, Nominally Equal

SDI (M6): In serial programming mode, (PAR/SER = 0V),

SDIistheserialinterfacedataInput.DataonSDIisclocked

into the mode control registers on the rising edge of SCK.

–

+

–

In parallel programming mode (PAR/SER = V ), SDI can

DD

be used to power down the part. SDI can be driven with

1.8V to 3.3V logic.

CM78

to V /2. V should be used to bias the common mode

DD

CM

GND (See Pin Configuration Table): ADC Power Ground.

Use multiple vias close to pins.

of the analog inputs of channels 7 and 8. V is internally

CM

bypassed to ground with a 0.1µF ceramic capacitor. No

external capacitance is required.

90067814fa

For more information www.linear.com/LTM9008-14

17

LTM9008-14/

LTM9007-14/LTM9006-14

pin FuncTions

OV (G9, G10): Output Driver Supply. OV is internally

LVDS Outputs

DD

bypassed to ground with a 0.1µF ceramic capacitor.

All pins in this section are differential LVDS outputs.

The output current level is programmable. There is an

optionalinternal100Ωterminationresistorbetweenthe

pins of each LVDS output pair.

SDOA(E6):Inserialprogrammingmode,(PAR/SER=0V),

SDOA is the optional serial interface data output for

registers controlling channels 1, 4, 5 and 8. Data on SDO

is read back from the mode control registers and can be

latched on the falling edge of SCK. SDO is an open-drain

N-channel MOSFET output that requires an external 2k

pull-up resistor from 1.8V to 3.3V. If read back from the

mode control registers is not needed, the pull-up resis-

tor is not necessary and SDO can be left unconnected. In

–

+

–

+

OUT1A /OUT1A ,OUT1B /OUT1B (E7/E8,C8/D8):Serial

Data Outputs for Channel 1. In 1-lane output mode only

–

+

OUT1A /OUT1A are used.

–

+

–

+

OUT2A /OUT2A ,OUT2B /OUT2B (B8/A8,D7/C7):Serial

Data Outputs for Channel 2. In 1-lane output mode only

–

+

OUT2A /OUT2A are used.

parallelprogrammingmode(PAR/SER=V ), SDOAisan

DD

–

+

–

+

input that enables internal 100Ω termination resistors on

the digital outputs of channels 1, 4, 5 and 8. When used

as an input, SDO can be driven with 1.8V to 3.3V logic

through a 1k series resistor.

OUT3A /OUT3A , OUT3B /OUT3B (D10/D9, E10/E9):

Serial Data Outputs for Channel 3. In 1-lane output mode

only OUT3A /OUT3A are used.

–

+

–

+

–

+

OUT4A /OUT4A ,OUT4B /OUT4B (C9/C10,F7/F8):Serial

SDOB (D6): Serial Data Output Pin for Channels 2, 3, 6

and 7. See description for SDOA.

Data Outputs for Channel 4. In 1-lane output mode only

–

+

OUT4A /OUT4A are used.

–

+

–

+

PAR/SER(A7):ProgrammingModeSelectionPin.Connect

to ground to enable the serial programming mode. CSA,

CSB, SCK, SDI, SDOA and SDOB become a serial interface

OUT5A /OUT5A ,OUT5B /OUT5B (J8/J7,K8/K7):Serial

Data Outputs for Channel 5. In 1-lane output mode only

–

+

OUT5A /OUT5A are used.

that control the A/D operating modes. Connect to V to

DD

–

+

–

+

OUT6A /OUT6A , OUT6B /OUT6B (K9/K10, L9/L10):

enableparallelprogrammingmodewhereCSA, CSB, SCK,

SDI, SDOA and SDOB become parallel logic inputs that

control a reduced set of the A/D operating modes. PAR/

Serial Data Outputs for Channel 6. In 1-lane output mode

–

+

only OUT6A /OUT6A are used.

–

+

–

+

SER should be connected directly to ground or the V

OUT7A /OUT7A ,OUT7B /OUT7B (M7/L7,P8/N8):Serial

DD

of the part and not be driven by a logic signal.

Data Outputs for Channel 7. In 1-lane output mode only

–

+

OUT7A /OUT7A are used.

V

(B6): Reference Voltage Output. V

is internally

REF

–

+

–

+

bypassed to ground with a 1μF ceramic capacitor, nomi-

OUT8A /OUT8A , OUT8B /OUT8B (L8/M8, M10/M9):

nally 1.25V.

Serial Data Outputs for Channel 8. In 1-lane output mode

–

+

only OUT8A /OUT8A are used.

SENSE (C5): Reference Programming Pin. Connecting

–

+

SENSE to V selects the internal reference and a 1V

FRA /FRA (H7/H8): Frame Start Outputs for Channels

1, 4, 5 and 8.

DD

input range. Connecting SENSE to ground selects the

internal reference and a 0.5V input range. An external

reference between 0.625V and 1.3V applied to SENSE

–

+

FRB /FRB (J9/J10): Frame Start Outputs for Channels

2, 3, 6 and 7.

selectsaninputrangeof±0.8•V

. SENSEisinternally

SENSE

–

+

bypassed to ground with a 0.1µF ceramic capacitor.

DCOA /DCOA (G8/G7): Data Clock Outputs for Channels

1, 4, 5 and 8.

–

+

DCOB /DCOB (F10, F9): Data Clock Outputs for Chan-

nels 2, 3, 6 and 7.

90067814fa

For more information www.linear.com/LTM9008-14

18

LTM9008-14/

LTM9007-14/LTM9006-14

pin conFiguraTion Table

1

2

3

4

5

6

7

8

9

10

+

–

+

A

B

C

D

E

GND

PAR/SER

O2A

GND

–

+

A_IN1

V

REF

GND

CM12

–

+

–

+

A_IN2

GND

SENSE

GND

CSA

GND

SDOB

SDOA

GND

SCK

O2B

O1B

O1A

O4B

O4A

O3A

O3B

O4A

O3A

O3B

–

+

–

GND

V

O2B

DD

–

+

–

A_IN3

O1A

–

+

–

F

GND

V

GND

O4B

DCOB

OV

DCOB

OV

CM34

–

+

–

G

H

J

A_IN4

GND

DCOA

DD

+

–

+

A_IN5

GND

FRA

GND

+

–

+

GND

V

O5A

O5B

O8A

O7B

FRB

CM56

+

–

+

–

+

–

+

K

L

A_IN6

V

DD

V

DD

V

O5B

O6A

O6B

O8B

O6A

O6B

O8B

DD

+

–

+

–

GND

O7A

+

–

M

N

P

A_IN7

GND

CSB

SDI

O7A

+

–

A_IN8

V

GND

CM78

+

–

GND

CLK

Top View of BGA Package (Looking Through Component).

90067814fa

For more information www.linear.com/LTM9008-14

19

LTM9008-14/

LTM9007-14/LTM9006-14

FuncTional block DiagraM

V

DD

= 1.8V

OV = 1.8V

DD

+

–

+

–

OUT1A

OUT1B

CH 1

ANALOG

INPUT

14-BIT

S/H

ADC CORE

+

–

+

–

OUT2A

OUT2B

CH 2

ANALOG

INPUT

14-BIT

ADC CORE

+

–

+

–

OUT3A

OUT3B

CH 3

ANALOG

INPUT

14-BIT

ADC CORE

+

–

+

–

OUT4A

OUT4B

CH 4

ANALOG

INPUT

14-BIT

ADC CORE

DATA

SERIALIZER

+

–

+

–

OUT5A

OUT5B

CH 5

ANALOG

INPUT

14-BIT

ADC CORE

+

–

+

–

OUT6A

OUT6B

CH 6

ANALOG

INPUT

14-BIT

ADC CORE

+

–

+

–

OUT7A

OUT7B

CH 7

ANALOG

INPUT

14-BIT

ADC CORE

+

–

+

–

OUT8A

OUT8B

CH 8

ANALOG

INPUT

14-BIT

ADC CORE

+

ENC

DCOA

DCOB

FRA

PLL

–

FRB

1.25V

REFERENCE

SDOA

SDOB

SDI

V

REF

REFH

REFL

MODE

CONTROL

REGISTERS

SCK

RANGE

SELECT

CSA

CSB

PAR/SER

REF

BUFFER

V /2

DD

DIFF

REF

AMP

GND

90067814 F01

SENSE

VCM12

VCM34

VCM56

VCM78

Figure 1. Functional Block Diagram

90067814fa

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CONVERTER OPERATION

INPUT DRIVE CIRCUITS

The LTM9008-14/LTM9007-14/LTM9006-14 are low

power, 8-channel, 14-bit, 65Msps/40Msps/25Msps A/D

converters that are powered by a single 1.8V supply. The

analog inputs should be driven differentially. The encode

input can be driven differentially for optimal jitter perfor-

mance,orsingle-endedforlowerpowerconsumption.The

digital outputs are serial LVDS to minimize the number

of data lines. Each channel outputs two bits at a time

(2-lane mode) or one bit at a time (1-lane mode). Many

additional features can be chosen by programming the

mode control registers through a serial SPI port.

Input Filtering

If possible, there should be an RC low pass filter right at

the analog inputs. This lowpass filter isolates the drive

circuitryfromtheA/Dsample-and-holdswitching,andalso

limits wideband noise from the drive circuitry. Figure 3

showsanexampleofaninputRCfilter.TheRCcomponent

values should be chosen based on the application’s input

frequency.

Transformer Coupled Circuits

Figure 3 shows the analog input being driven by an RF

transformer with a center-tapped secondary. The center

ANALOG INPUT

tap is biased with V , setting the A/D input at its opti-

CM

The analog inputs are differential CMOS sample-and-hold

circuits(Figure2).Theinputsshouldbedrivendifferentially

around a common mode voltage set by the appropriate

mal DC level. At higher input frequencies a transmission

line balun transformer (Figures 4 to 6) has better balance,

resulting in lower A/D distortion.

V

output pins, which are nominally V /2. For the 2V

CM

DD

input range, the inputs should swing from V – 0.5V

CM

50Ω

V

CM

to V + 0.5V. There should be 180° phase difference

CM

0.1µF

between the inputs.

0.1µF

T1

1:1

+

25Ω

A

IN

ANALOG

INPUT

Theeightchannelsaresimultaneouslysampledbyashared

encode circuit (Figure 2).

LTM9008-14

0.1µF

25Ω

12pF

–

LTM9008-14

10Ω

V

25Ω

DD

A

IN

C

SAMPLE

3.5pF

R

ON

T1: MA/COM MABAES0060

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

25Ω

90067814 F03

+

–

A

IN

C

PARASITIC

1.8pF

V

DD

C

SAMPLE

3.5pF

Figure 3. Analog Input Circuit Using a Transformer.

Recommended for Input Frequencies from 5MHz to 70MHz

R

ON

10Ω

25Ω

A

C

PARASITIC

1.8pF

V

DD

1.2V

10k

+

–

ENC

10k

1.2V

90067814 F02

Figure 2. Equivalent Input Circuit. Only One

of the Eight Analog Channels Is Shown

90067814fa

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21

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applicaTions inForMaTion

Amplifier Circuits

At very high frequencies an RF gain block will often have

lower distortion than a differential amplifier. If the gain

blockissingle-ended,thenatransformercircuit(Figures4

to 6) should convert the signal to differential before driv-

ing the A/D.

Figure 7 shows the analog input being driven by a high

speed differential amplifier. The output of the amplifier is

AC-coupled to the A/D so the amplifier’s output common

mode voltage can be optimally set to minimize distortion.

See back page for a DC-coupled example.

50Ω

V

CM

0.1µF

+

A

ANALOG

INPUT

IN

T2

LTM9008-14

T1

0.1µF

25Ω

4.7pF

0.1µF

–

A

IN

90067814 F04

T1: MA/COM MABA-007159-000000

T2: MA/COM MABAES0060

RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

Figure 4. Recommended Front End Circuit for Input

Frequencies from 70MHz to 170MHz

50Ω

V

CM

0.1µF

+

A

ANALOG

INPUT

IN

T2

LTM9008-14

T1

0.1µF

25Ω

1.8pF

–

A

IN

90067814 F05

T1: MA/COM MABA-007159-000000

T2: COILCRAFT WBC1-1LB

RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

Figure 5. Recommended Front End Circuit for Input

Frequencies from 170MHz to 300MHz

90067814fa

For more information www.linear.com/LTM9008-14

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LTM9008-14/

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applicaTions inForMaTion

50Ω

V

CM

0.1µF

2.7nH

0.1µF

+

A

IN

ANALOG

INPUT

LTM9008-14

25Ω

T1

0.1µF

–

2.7nH

A

90067814 F06

T1: MA/COM ETC1-1-13

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

Figure 6. Recommended Front End Circuit for Input

Frequencies Above 300MHz

V

CM

HIGH SPEED

DIFFERENTIAL

AMPLIFIER

0.1µF

200Ω 200Ω

25Ω

0.1µF

+

–

A

IN

LTM9008-14

ANALOG

INPUT

+

12pF

–

25Ω

A

IN

90067814 F07

Figure 7. Front End Circuit Using a High Speed

Differential Amplifier

90067814fa

For more information www.linear.com/LTM9008-14

23

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applicaTions inForMaTion

Reference

The input range can be adjusted by applying a voltage to

SENSE that is between 0.625V and 1.30V. The input range

TheLTM9008-14/LTM9007-14/LTM9006-14hasaninter-

nal 1.25V voltage reference. For a 2V input range using

will then be 1.6 • V

. The reference is shared by all

SENSE

eight ADC channels, so it is not possible to independently

adjust the input range of individual channels.

the internal reference, connect SENSE to V . For a 1V

DD

input range using the internal reference, connect SENSE

to ground. For a 2V input range with an external reference,

apply a 1.25V reference voltage to SENSE (Figure 9).

The V , SENSE, REFH and REFL pins are internally

REF

bypassed, as shown in Figure 8.

V

LTM9008-14

REF

5Ω

1.25V

1.25V BANDGAP

REFERENCE

1µF

0.625V

RANGE

DETECT

AND

CONTROL

TIE TO V FOR 2V RANGE;

DD

SENSE

TIE TO GND FOR 1V RANGE;

RANGE = 1.6 • V

FOR

SENSE

0.1µF

INTERNAL ADC

HIGH REFERENCE

0.65V < V

< 1.300V

BUFFER

SENSE

0.1µF

2.2µF

0.1µF

0.8x

DIFF AMP

INTERNAL ADC

LOW REFERENCE

90067814 F08

Figure 8. Reference Circuit

LTM9008-14

SENSE

1.25V

EXTERNAL

REFERENCE

1µF

90067814 F09

Figure 9. Using an External 1.25V Reference

90067814fa

For more information www.linear.com/LTM9008-14

24

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applicaTions inForMaTion

Encode Input

The encode inputs are internally biased to 1.2V through

10k equivalent resistance. The encode inputs can be taken

The signal quality of the encode inputs strongly affects

the A/D noise performance. The encode inputs should

be treated as analog signals—do not route them next to

digital traces on the circuit board. There are two modes

of operation for the encode inputs: the differential encode

mode (Figure 10), and the single-ended encode mode

(Figure 11).

above V (up to 3.6V), and the common mode range is

DD

–

from 1.1V to 1.6V. In the differential encode mode, ENC

should stay at least 200mV above ground to avoid falsely

triggering the single-ended encode mode. For good jitter

+

performance ENC should have fast rise and fall times.

Thesingle-endedencodemodeshouldbeusedwithCMOS

–

encode inputs. To select this mode, ENC is connected

The differential encode mode is recommended for sinu-

soidal, PECL, or LVDS encode inputs (Figures 12 and 13).

+

to ground and ENC is driven with a square wave encode

LTM9008-14

V

DD

DIFFERENTIAL

COMPARATOR

V

DD

15k

30k

+

–

ENC

LTM9008-14

1.8V TO

+

3.3V

0V

ENC

–

30k

ENC

CMOS LOGIC

BUFFER

90067814 F10

90067814 F11

Figure 10. Equivalent Encode Input Circuit

for Differential Encode Mode

Figure 11. Equivalent Encode Input Circuit for

Single-Ended Encode Mode

0.1µF

+

T1

ENC

LTM9008-14

50Ω

100Ω

0.1µF

+

ENC

–

0.1µF

ENC

PECL OR

LTM9008-14

LVDS

CLOCK

90067814 F12

0.1µF

–

ENC

T1 = MA/COM ETC1-1-13

RESISTORS AND CAPACITORS

ARE 0402 PACKAGE SIZE

90067814 F13

Figure 12. Sinusoidal Encode Drive

Figure 13. PECL or LVDS Encode Drive

90067814fa

For more information www.linear.com/LTM9008-14

25

LTM9008-14/

LTM9007-14/LTM9006-14

applicaTions inForMaTion

+

input. ENC can be taken above V (up to 3.6V) so 1.8V

details). Note that with 12-bit serialization the two LSBs

are not available—this mode is included for compatibility

with 12-bit versions of these parts.

DD

+

to3.3VCMOSlogiclevelscanbeused.TheENC threshold

is0.9V. ForgoodjitterperformanceENC shouldhavefast

+

rise and fall times.

The output data should be latched on the rising and falling

edges of the data clock out (DCO). A data frame output

(FR) can be used to determine when the data from a new

conversionresultbegins. Inthe2-lane, 14-bitserialization

mode, the frequency of the FR output is halved.

Clock PLL and Duty Cycle Stabilizer

Theencodeclockismultipliedbyaninternalphase-locked

loop (PLL) to generate the serial digital output data. If the

encode signal changes frequency or is turned off, the PLL

requires 25µs to lock onto the input clock.

The maximum serial data rate for the data outputs is

1Gbps, so the maximum sample rate of the ADC will de-

pend on the serialization mode as well as the speed grade

of the ADC (see Table 1). The minimum sample rate for

all serialization modes is 5Msps.

A clock duty cycle stabilizer circuit allows the duty cycle

of the applied encode signal to vary from 30% to 70%.

In the serial programming mode it is possible to disable

the duty cycle stabilizer, but this is not recommended. In

the parallel programming mode the duty cycle stabilizer

is always enabled.

By default the outputs are standard LVDS levels: 3.5mA

output current and a 1.25V output common mode volt-

age. An external 100Ω differential termination resistor

is required for each LVDS output pair. The termination

resistors should be located as close as possible to the

LVDS receiver.

DIGITAL OUTPUTS

The digital outputs of the LTM9008-14/LTM9007-14/

LTM9006-14 are serialized LVDS signals. Each channel

outputs two bits at a time (2-lane mode) or one bit at a

time (1-lane mode). The data can be serialized with 16, 14,

or12-bitserialization(seetheTimingDiagramssectionfor

The outputs are powered by OV which is independent

DD

from the A/D core power.

Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTM9008-14.

The Sampling Frequency for the Slower Speed Grades Cannot Exceed 40MHz (LTM9007-14) or 25MHz (LTM9006-14)

MAXIMUM SAMPLING

SERIALIZATION MODE

FREQUENCY, f (MHz)

DCO FREQUENCY

4 • f

FR FREQUENCY

SERIAL DATA RATE

S

2-Lane

1-Lane

16-Bit Serialization

65

f

8 • f

7 • f

6 • f

S

14-Bit Serialization

12-Bit Serialization

16-Bit Serialization

14-Bit Serialization

12-Bit Serialization

3.5 • f

0.5 • f

S

65

3 • f

8 • f

7 • f

6 • f

f

S

62.5

65

16 • f

14 • f

12 • f

S

65

90067814fa

For more information www.linear.com/LTM9008-14

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Table 2. Output Codes vs Input Voltage

Programmable LVDS Output Current

+

–

A

– A

D13-D0

(OFFSET BINARY)

D13-D0

(2’s COMPLEMENT)

IN

The default output driver current is 3.5mA. This current

can be adjusted by control register A2 in the serial pro-

gramming mode. Available current levels are 1.75mA,

2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. In the

parallel programming mode, the SCK pin can select either

3.5mA or 1.75mA.

(2V RANGE)

>1.000000V

+0.999878V

+0.999756V

11 1111 1111 1111

11 1111 1111 1110

01 1111 1111 1111

01 1111 1111 1110

+0.000122V

+0.000000V

–0.000122V

–0.000244V

10 0000 0000 0001

10 0000 0000 0000

01 1111 1111 1111

01 1111 1111 1110

00 0000 0000 0001

00 0000 0000 0000

11 1111 1111 1111

11 1111 1111 1110

Optional LVDS Driver Internal Termination

In most cases, using just an external 100Ω termina-

tion resistor will give excellent LVDS signal integrity. In

addition, an optional internal 100Ω termination resistor

can be enabled by serially programming mode con-

trol register A2. The internal termination helps absorb

any reflections caused by imperfect termination at the

receiver. When the internal termination is enabled, the

output driver current is doubled to maintain the same

output voltage swing. In the parallel programming

mode the SDO pin enables internal termination. Internal

termination should only be used with 1.75mA, 2.1mA or

2.5mA LVDS output current modes.

–0.999878V

–1.000000V

<–1.000000V

00 0000 0000 0001

00 0000 0000 0000

10 0000 0000 0001

10 0000 0000 0000

Digital Output Randomizer

Interference from the A/D digital outputs is sometimes

unavoidable.Digitalinterferencemaybefromcapacitiveor

inductive coupling or coupling through the ground plane.

Even a tiny coupling factor can cause unwanted tones

in the ADC output spectrum. By randomizing the digital

output before it is transmitted off chip, these unwanted

tones can be randomized which reduces the unwanted

tone amplitude.

DATA FORMAT

The digital output is randomized by applying an exclusive-

OR logic operation between the LSB and all other data

output bits. To decode, the reverse operation is applied

—an exclusive-OR operation is applied between the LSB

andallotherbits.TheFRandDCOoutputsarenotaffected.

Theoutputrandomizerisenabledbyseriallyprogramming

mode control register A1.

Table 2 shows the relationship between the analog input

voltage and the digital data output bits. By default the

output data format is offset binary. The 2’s complement

format can be selected by serially programming mode

control register A1.

90067814fa

For more information www.linear.com/LTM9008-14

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Digital Output Test Pattern

DEVICE PROGRAMMING MODES

To allow in-circuit testing of the digital interface to the

A/D, there is a test mode that forces the A/D data outputs

(D13-D0) of all channels to known values. The digital

output test patterns are enabled by serially programming

mode control registers A3 and A4. When enabled, the test

patterns override all other formatting modes: 2’s comple-

ment and randomizer.

The operating modes of the LTM9008-14/LTM9007-14/

LTM9006-14 can be programmed by either a parallel

interface or a simple serial interface. The serial interface

has more flexibility and can program all available modes.

Theparallelinterfaceismorelimitedandcanonlyprogram

some of the more commonly used modes.

Parallel Programming Mode

Output Disable

To use the parallel programming mode, PAR/SER should

The digital outputs may be disabled by serially program-

ming mode control register A2. The current drive for all

digital outputs including DCO and FR are disabled to save

powerorenablein-circuittesting.Whendisabledthecom-

mon mode of each output pair becomes high impedance,

but the differential impedance may remain low.

be tied to V . The CS, SCK, SDI and SDO pins are binary

logic inputs that set certain operating modes. These pins

DD

can be tied to V or ground, or driven by 1.8V, 2.5V, or

DD

3.3V CMOS logic. When used as an input, SDO should

be driven through a 1k series resistor. Table 3 shows the

modes set by CS, SCK, SDI and SDO.

Table 3. Parallel Programming Mode Control Bits

Sleep and Nap Modes

(PAR/SER = V_DD

)

The A/D may be placed in sleep or nap modes to conserve

power. In sleep mode the entire device is powered down,

resulting in 2mW power consumption. Sleep mode is

enabled by mode control register A1 (serial programming

mode), or by SDI (parallel programming mode). The time

required to recover from sleep mode is about 2ms.

DESCRIPTION

CS

2-Lane / 1-Lane Selection Bit

0 = 2-Lane, 16-Bit Serialization Output Mode

1 = 1-Lane, 14-Bit Serialization Output Mode

LVDS Current Selection Bit

0 = 3.5mA LVDS Current Mode

1 = 1.75mA LVDS Current Mode

Power Down Control Bit

SCK

SDI

In nap mode any combination of A/D channels can be

powereddownwhiletheinternalreferencecircuitsandthe

PLL stay active, allowing faster wakeup than from sleep

mode. Recovering from nap mode requires at least 100

clock cycles. If the application demands very accurate DC

settling then an additional 50µs should be allowed so the

on-chip references can settle from the slight temperature

shift caused by the change in supply current as the A/D

leaves nap mode. Nap mode is enabled by mode control

register A1 in the serial programming mode.

0 = Normal Operation

1 = Sleep Mode

SDO

Internal Termination Selection Bit

0 = Internal Termination Disabled

1 = Internal Termination Enabled

90067814fa

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Serial Programming Mode

If the R/W bit is low, the serial data (D7:D0) will be writ-

ten to the register set by the address bits (A6:A0). If the

R/W bit is high, data in the register set by the address

bits (A6:A0) will be read back on the SDO pin (see the

Timing Diagrams section). During a read back command

the register is not updated and data on SDI is ignored.

To use the serial programming mode, PAR/SER should be

tied to ground. The CS, SCK, SDI and SDO pins become a

serialinterfacethatprogramtheA/Dmodecontrolregisters.

Data is written to a register with a 16-bit serial word. Data

can also be read back from a register to verify its contents.

The SDO pin is an open-drain output that pulls to ground

with a 200Ω impedance. If register data is read back

through SDO, an external 2k pull-up resistor is required.

If serial data is only written and read back is not needed,

then SDO can be left floating and no pull-up resistor is

needed.Table4showsamapofthemodecontrolregisters.

Serial data transfer starts when CS is taken low. The data

on the SDI pin is latched at the first 16 rising edges of

SCK. Any SCK rising edges after the first 16 are ignored.

The data transfer ends when CS is taken high again.

The first bit of the 16-bit input word is the R/W bit. The

next seven bits are the address of the register (A6:A0).

The final eight bits are the register data (D7:D0).

Table 4. Serial Programming Mode Register Map (PAR/SER = GND)

REGISTER A0: RESET REGISTER (ADDRESS 00h)

D7

D6

X

D5

X

D4

X

D3

X

D2

X

D1

X

D0

X

RESET

Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7.

Bit 7

RESET

Software Reset Bit

0 = Not Used

1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC Is Momentarily Placed in SLEEP Mode.

After the Reset SPI Write Command Is Complete, Bit D7 Is Automatically Set Back to Zero. The Reset Register Is Write Only.

Bits 6-0

Unused, Don’t Care Bits.

REGISTER A1 (CSA): FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h with CSA = GND)

D7

D6

D5

D4

D3

D2

D1

D0

DCSOFF

RAND

TWOSCOMP

SLEEP

NAP_8

NAP_5

NAP_4

NAP_1

Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7.

Bit 7

DCSOFF

Clock Duty Cycle Stabilizer Bit

0 = Clock Duty Cycle Stabilizer On

1 = Clock Duty Cycle Stabilizer Off. This Is Not Recommended.

Bit 6

RAND

Data Output Randomizer Mode Control Bit

0 = Data Output Randomizer Mode Off

1 = vData Output Randomizer Mode On

Bit 5

TWOSCOMP Two’s Complement Mode Control Bit

0 = Offset Binary Data Format

1 = Two’s Complement Data Format

Bits 4-0

SLEEP: NAP_X Sleep/Nap Mode Control Bits

00000 = Normal Operation

0XXX1 = Channel 1 in Nap Mode

0XX1X = Channel 4 in Nap Mode

0X1XX = Channel 5 in Nap Mode

01XXX = Channel 8 in Nap Mode

1XXXX = Sleep Mode. Channels 1, 4, 5 and 8 Are Disabled

Note: Any Combination of Channels Can Be Placed in Nap Mode.

90067814fa

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REGISTER A1 (CSB): FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h with CSB = GND)

D7

D6

D5

D4

D3

D2

D1

D0

DCSOFF

RAND

TWOSCOMP

SLEEP

NAP_7

NAP_6

NAP_3

NAP_2

Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7.

Bit 7

DCSOFF

Clock Duty Cycle Stabilizer Bit

0 = Clock Duty Cycle Stabilizer On

1 = Clock Duty Cycle Stabilizer Off. This Is Not Recommended.

Bit 6

RAND

Data Output Randomizer Mode Control Bit

0 = Data Output Randomizer Mode Off

1 = Data Output Randomizer Mode On

Bit 5

TWOSCOMP Two’s Complement Mode Control Bit

0 = Offset Binary Data Format

1 = Two’s Complement Data Format

Bits 4-0

SLEEP: NAP_4:NAP_1 Sleep/Nap Mode Control Bits

00000 = Normal Operation

0XXX1 = Channel 2 in Nap Mode

0XX1X = Channel 3 in Nap Mode

0X1XX = Channel 6 in Nap Mode

01XXX = Channel 7 in Nap Mode

1XXXX = Sleep Mode. Channels 2, 3, 6 and 7 Are Disabled

Note: Any Combination of Channels Can Be Placed in Nap Mode.

REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h)

D7

D6

D5

D4

D3

D2

D1

D0

ILVDS2

ILVDS1

ILVDS0

TERMON

OUTOFF

OUTMODE2

OUTMODE1

OUTMODE0

Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7.

Bits 7-5

ILVDS2:ILVDS0 LVDS Output Current Bits

000 = 3.5mA LVDS Output Driver Current

001 = 4.0mA LVDS Output Driver Current

010 = 4.5mA LVDS Output Driver Current

011 = Not Used

100 = 3.0mA LVDS Output Driver Current

101 = 2.5mA LVDS Output Driver Current

110 = 2.1mA LVDS Output Driver Current

111 = 1.75mA LVDS Output Driver Current

Bit 4

TERMON LVDS Internal Termination Bit

0 = Internal Termination Off

1 = Internal Termination On. LVDS Output Driver Current Is 2x the Current Set by ILVDS2:ILVDS0. Internal Termination Should Only Be

Used with 1.75mA, 2.1mA or 2.5mA LVDS Output Current Modes.

Bit 3

OUTOFF Output Disable Bit

0 = Digital Outputs Are Enabled.

1 = Digital Outputs Are Disabled.

Bits 2-0

OUTMODE2:OUTMODE0 Digital Output Mode Control Bits

000 = 2-Lanes, 16-Bit Serialization

001 = 2-Lanes, 14-Bit Serialization

010 = 2-Lanes, 12-Bit Serialization

011 = Not Used

100 = Not Used

101 = 1-Lane, 14-Bit Serialization

110 = 1-Lane, 12-Bit Serialization

111 = 1-Lane, 16-Bit Serialization

90067814fa

For more information www.linear.com/LTM9008-14

30

LTM9008-14/

LTM9007-14/LTM9006-14

applicaTions inForMaTion

REGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h)

D7

D6

X

D5

D4

D3

D2

D1

D0

OUTTEST

TP13

TP12

TP11

TP10

TP9

TP8

Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7.

Bit 7

OUTTEST

Digital Output Test Pattern Control Bit

0 = Digital Output Test Pattern Off

1 = Digital Output Test Pattern On

Bit 6

Unused, Don’t Care Bit.

Bit 5-0

TP13:TP8

Test Pattern Data Bits (MSB)

TP13:TP8 Set the Test Pattern for Data Bit 13 (MSB) Through Data Bit 8.

REGISTER A4: TEST PATTERN LSB REGISTER (ADDRESS 04h)

D7

D6

D5

D4

D3

D2

D1

D0

TP7

TP6

TP5

TP4

TP3

TP2

TP1

TP0

Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7.

Bit 7-0

TP7:TP0

Test Pattern Data Bits (LSB)

TP7:TP0 Set the Test Pattern for Data Bit 7 Through Data Bit 0 (LSB).

Software Reset

Bypass capacitors are integrated inside the package; ad-

ditional capacitance is optional.

If serial programming is used, the mode control registers

shouldbeprogrammedassoonaspossibleafterthepower

supplies turn on and are stable. The first serial command

must be a software reset which will reset all register data

bits to logic 0. To perform a software reset, bit D7 in the

reset register is written with a logic 1. After the reset SPI

write command is complete, bit D7 is automatically set

back to zero.

The analog inputs, encode signals, and digital outputs

should not be routed next to each other. Ground fill and

grounded vias should be used as barriers to isolate these

signals from each other.

The pin assignments of the LTM9008-14/LTM9007-14/

LTM9006-14 allow a flow-through layout that makes

it possible to use multiple parts in a small area when

a large number of ADC channels are required. The

device has similar layout rules to other BGA pack-

ages. The layout can be implemented with 6mil blind vias

and5miltraces.Thepinouthasbeendesignedtominimize

the space required to route the analog and digital traces.

The analog and digital traces can essentially be routed

within the width of the package. This allows multiple

packages to be located close together for high channel

count applications. Trace lengths for the analog inputs

and digital outputs should be matched as well as possible.

GROUNDING AND BYPASSING

The LTM9008-14/LTM9007-14/LTM9006-14 requires a

printed circuit board with a clean unbroken ground plane.

A multilayer board with an internal ground plane in the

first layer beneath the ADC is recommended. Layout for

the printed circuit board should ensure that digital and

analog signal lines are separated as much as possible. In

particular, care should be taken not to run any digital track

alongside an analog signal track or underneath the ADC.

90067814fa

For more information www.linear.com/LTM9008-14

31

LTM9008-14/

LTM9007-14/LTM9006-14

applicaTions inForMaTion

Table 5 lists the trace lengths for the analog inputs and

digital outputs inside the package from the die pad to the

package pad. These should be added to the PCB trace

lengths for best matching.

HEAT TRANSFER

MostoftheheatgeneratedbytheLTM9008-14/LTM9007-14/

LTM9006-14 is transferred from the die through the bot-

tom of the package onto the printed circuit board. The

ground pins should be connected to the internal ground

planes by multiple vias.

The material used for the substrate is BT (bismaleimide-

triazine), supplied by Mitsubishi Gas and Chemical. In

the DC to 125MHz range, the speed for the analog input

signals is 198ps/in or 7.795ps/mm. The speed for the

digital outputs is 188.5ps/in or 7.417ps/mm.

Table 5. Internal Trace Lengths

LENGTH

(mm)

LENGTH

(mm)

LENGTH

(mm)

LENGTH

(mm)

E7

NAME

K8

K7

K9

NAME

E1

NAME

F10

F9

NAME

–

01A

1.775

1.947

1.847

1.850

3.233

3.246

0.179

1.127

2.126

2.177

1.811

1.812

3.199

3.196

0.706

0.639

0.392

0.436

05B

0.379

0.528

1.866

1.865

2.268

2.267

1.089

0.179

3.281

3.149

1.862

1.847

4.021

4.016

4.689

4.709

4.724

4.769

A

2.491

2.505

3.376

3.372

3.301

3.346

2.506

2.533

3.198

3.214

4.726

4.691

4.106

0.919

1.162

1.157

1.088

DCOB

1.811

1.812

1.117

1.038

1.644

1.643

IN3

+

–

+

–

+

–

+

–

+

–

+

–

+

–

+

–

+

–

+

–

+

–

+

–

+

–

+

–

+

E8

01A

01B

02A

02B

03A

03B

04A

04B

05A

05B

06A

E2

DCOB

IN3

–

C8

D8

B8

A8

D7

C7

D10

D9

E10

E9

G1

G2

H2

H1

K2

K1

M2

M1

N2

N1

P6

P5

L5

H7

H8

J9

FRA

IN4

+

K10 06A

L9 06B

L10 06B

FRA

IN4

–

FRB

IN5

+

J10

A7

L6

FRB

IN5

–

M7

L7

07A

07B

08A

PAR/SER 3.838

IN6

+

SCK

0.240

0.453

0.274

1.069

3.914

0.123

0.079

3.915

IN6

–

P8

N8

L8

E6

SDOA

SDOB

SDI

IN7

+

D6

M6

B3

F3

IN7

–

IN8

+

M8

V

IN8

CM12

CM34

CM56

CM78

–

C9

C10

F7

M10 08B

CLK

+

M9

B1

B2

C1

C2

08B

J3

–

A

CSA

N3

IN1

IN2

+

–

+

F8

M5

G8

G7

CSB

–

+

J8

DCOA

J7

90067814fa

For more information www.linear.com/LTM9008-14

32

LTM9008-14/

LTM9007-14/LTM9006-14

Typical applicaTions

Silkscreen Top

Top Side

Inner Layer 2

Inner Layer 3

90067814fa

For more information www.linear.com/LTM9008-14

33

LTM9008-14/

LTM9007-14/LTM9006-14

Typical applicaTions

Inner Layer 4

Inner Layer 5

Bottom Side

Silkscreen Bottom

90067814fa

For more information www.linear.com/LTM9008-14

34

LTM9008-14/

LTM9007-14/LTM9006-14

Typical applicaTion

G N D

P 1 0

G N D

P 9

G N D

N 1 0

G N D

N 9

G N D

H 1 0

G N D

H 9

G N D

B 1 0

G N D

B 9

G N D

A 1 0

G N D

A 9

P 7

G N D

D 6

G N D P 4

G N D P 3

G N D P 2

G N D P 1

G N D N 7

G N D N 6

G N D N 5

G N D N 4

G N D M 4

G N D M 3

G N D L 2

G N D L 1

G N D K 6

G N D K 5

G N D J 6

G N D J 5

G N D J 4

G N D J 2

G N D J 1

G N D H 6

G N D H 5

G N D H 4

G N D H 3

G N D G 6

G N D G 5

G N D G 4

G N D G 3

G N D F 6

G N D F 5

G N D F 4

G N D F 2

G N D F 1

G N D E 5

G N D D 5

G N D D 2

G N D D 1

G N D C 6

G N D C 4

G N D C 3

G N D B 7

G N D B 5

G N D B 4

G N D A 6

G N D A 5

G N D A 4

G N D A 3

G N D A 2

G N D A 1

E 6

M 5

L 5

L 6

M 6

B 6

C 5

A 7

90067814fa

For more information www.linear.com/LTM9008-14

35

LTM9008-14/

LTM9007-14/LTM9006-14

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

/ / b b b

Z

3 . 6 0 0

2 . 8 0 0

2 . 0 0 0

1 . 2 0 0

0 . 4 0 0

1 . 2 0 0

2 . 0 0 0

2 . 8 0 0

3 . 6 0 0

0 . 0 0 0

a a a

Z

90067814fa

For more information www.linear.com/LTM9008-14

36

LTM9008-14/

LTM9007-14/LTM9006-14

revision hisTory

REV

DATE

DESCRIPTION

PAGE NUMBER

A

03/15 Removed mention of OGND

26

90067814fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTM9008-14

37

LTM9008-14/

LTM9007-14/LTM9006-14

Typical applicaTion

Single-Ended to Differential Conversion Using LTC6409 and 50MHz

Lowpass Filter (Only One Channel Shown). Filter for Use at 61.44Msps

3.3V

0.1µF

0.8pF

1.8V

150Ω

474Ω

C5

B6

180nH

68pF

180nH

150pF

37.4Ω

+

V

66.9Ω

+

–

IN

OUT

75Ω

+

–

+

–

A

B2

B1

E8

E7

O1A

IN1

LTC6409

33pF

75Ω

100pF

–

IN

0.1µF

68pF

150pF

180nH

–

+

OUT

180nH

37.4Ω

V

OCM

+

–

+

–

B3

C2

C1

F2

F1

F3

G2

G1

G7

G8

H8

H7

DCO

FR

150Ω

474Ω

V

A

V

A

SHDN

CM12

+

IN2

LTM9008-14

0.8pF

49.9Ω 66.9Ω

–

IN2

FR

+

IN3

GND

50Ω

–

IN3

CM34

+

IN4

–

IN4

N1

N2

+

A

IN8

–

IN8

P5 P6

90067814 TA03

relaTeD parTs

PART NUMBER

ADCs

DESCRIPTION

COMMENTS

LTC2170-14/LTC2171-14/ 14-Bit, 25Msps/40Msps/65Msps

LTC2172-14 1.8V Quad ADCs, Ultralow Power

178mW/234mW/360mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs,

7mm × 8mm QFN-52

LTC2173-14/LTC2174-14/ 14-Bit, 80Msps/105Msps/125Msps

LTC2175-14 1.8V Quad ADCs, Ultralow Power

412mW/481mW/567mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs,

7mm × 8mm QFN-52

LTM9009-14/LTM9010-14/ 14-Bit, 80Msps/105Msps/125Msps 1.8V 801mW/950mW/1145mW, 73.1dB SNR, 85dB SFDR, Serial LVDS Outputs,

LTM9011-14

Amplifiers/Filters

LTC6412

Octal ADCs, Ultralow Power

11.25mm × 9mm BGA-140

800MHz, 31dB Range, Analog-Controlled Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise

Variable Gain Amplifier Figure, 4mm × 4mm QFN-24

LTC6420-20

LTC6421-20

1.8GHz Dual Low Noise, Low Distortion Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 80mA Supply Current per Amplifier,

Differential ADC Drivers for 300MHz IF 3mm × 4mm QFN-20

1.3GHz Dual Low Noise, Low Distortion Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 40mA Supply Current per Amplifier,

Differential ADC Drivers

3mm × 4mm QFN-20

LTC6605-7/ LTC6605-10/ Dual Matched 7MHz/10MHz/14MHz

Dual Matched 2nd Order Lowpass Filters with Differential Drivers,

Pin-Programmable Gain, 6mm × 3mm DFN-22

LTC6605-14

Filters with ADC Drivers

Signal Chain Receivers

LTM9002

14-Bit Dual Channel IF/Baseband

Receiver Subsystem

Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers

90067814fa

LT 0315 REV A • PRINTED IN USA

38 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

For more information www.linear.com/LTM9008-14

●

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTM9008-14


型号：	LTM9008-14_15
厂家：	Linear
描述：	14-Bit, 65Msps/40Msps/ 25Msps Low Power Octal ADCs
文件：	总38页 (文件大小：740K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTM9008-14_15 [Linear]

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