LTM9012IY-AB#PBF_技术文档

LTM9012

Quad 14-Bit, 125Msps ADC

with Integrated Drivers

FeaTures

DescripTion

n

4-Channel Simultaneous Sampling ADC with

The LTM^®9012 is a 4-channel, simultaneous sampling

14-bit µModule^®analog-to-digital converter (ADC) with

integrated, fixed gain, differential ADC drivers. The low

noise amplifiers are suitable for single-ended drive and

pulse train signals such as imaging applications. Each

channel includes a lowpass filter between the driver out-

put and ADC input.

Integrated, Fixed Gain, Differential Drivers

n

68.3dB SNR

n

78dB SFDR

n

Low Power: 1.27W Total, ꢃ18mW per Channel

n

1.8V ADC Core and ꢃ.ꢃV Analog ꢁnput ꢀupplꢂ

n

ꢀerial LVDꢀ Outputs: 1 or 2 Sits per Channel

n

ꢀhutdown and Iap Modes

DC specs include 1.2LꢀS ꢁIL (tꢂp), 0.ꢃLꢀS DIL (tꢂp)

and no missing codes over temperature. The transition

n

11.25mm × 15mm SGA Package

noise is a low 1.2LꢀS

.

RMꢀ

applicaTions

The digital outputs are serial LVDꢀ and each channel out-

puts two bits at a time (2-lane mode). At lower sampling

rates there is a one bit option (1-lane mode). The LVDꢀ

drivers have optional internal termination and adjustable

output levels to ensure clean signal integritꢂ.

n

ꢁndustrial ꢁmaging

n

Medical ꢁmaging

Multichannel Data Acquisition

n

Iondestructive Testing

+

–

L, LT, LTC, LTM, Linear Technologꢂ, the Linear logo and µModule are registered trademarks of

Linear Technologꢂ Corporation. All other trademarks are the propertꢂ of their respective owners.

The EIC and EIC inputs maꢂ be driven differentiallꢂ

or single-ended with a sine wave, PECL, LVDꢀ, TTL or

CMOꢀ inputs. An internal clock dutꢂ cꢂcle stabilizer al-

lows high performance at full speed for a wide range of

clock dutꢂ cꢂcles.

Typical applicaTion

Single-Ended Sensor Digitization

LTM9012, 125Msps, 70MHz FFT

3.3V

1.8V

0

V

OV

DD

CC

DD

LTM9012

–10

–20

14

PIPELINE

ADC

DATA

SERIALIZER

ENCODER

AND

LVDS

DRIVERS

–30

CHANNEL 1

CHANNEL 2

–40

–50

PIPELINE

ADC

IMAGE

SENSOR

•

–60

FPGA

–70

CHANNEL 3

CHANNEL 4

PIPELINE

ADC

–80

–90

–100

–110

–120

PIPELINE

ADC

+

–

FR

INTERNAL

REFERENCE & SUPPLY

BYPASS CAPACITORS

35 40

0

5

10 15 20 25 30

45 50 55 60

+

–

V

REF

PLL

+

DCO

FREQUENCY (MHz)

9012 TA01b

–

SCK SDI SDO CS PAR/SER ENC

ENC

9012 TA01a

ENCODE CLOCK

9012fa

1

For more information www.linear.com/LTM9012

LTM9012

absoluTe MaxiMuM raTings

pin conFiguraTion

(Notes 1, 2)

TOP VIEW

ꢀupplꢂ Voltages

1

2

3

4

5

6

7

8

9

10 11 12 13

V , OV ................................................ –0.ꢃV to 2V

DD

+

–

+

–

+

–

+

–

CH4 CH4

CH3 CH3

CH2 CH2

CH1 CH1

A

B

C

D

E

V ........................................................ –0.ꢃV to 5.5V

CC

+

–

Analog ꢁnput Voltage (CHn , CHn , SHDNn )

(Iote ꢃ).......................................................–0.ꢃV to V

Analog ꢁnput Voltage (PAR/SER, ꢀEIꢀE)

V

CC3

CC2

CC

SHDN2

SHDN3

(Iote 4)........................................ –0.ꢃV to (V + 0.2V)

DD

F

+

–

Digital ꢁnput Voltage (EIC , EIC , CS, ꢀDꢁ, ꢀCK)

(Iote 5)..................................................... –0.ꢃV to ꢃ.9V

ꢀDO (Iote 5)............................................. –0.ꢃV to ꢃ.9V

SHDN4

SHDN1

G

H

J

V

CC4

V

CC1

Digital Output Voltage................ –0.ꢃV to (OV + 0.ꢃV)

Operating Temperature Range

LTM9012C ............................................... 0°C to 70°C

LTM9012ꢁ.............................................–40°C to 85°C

ꢀtorage Temperature Range .................. –65°C to 150°C

DD

K

L

SENSE

SDI

M

N

P

Q

R

S

V

DD

V

DD

+

–

ENC

SDO

PAR/SER

REF

CS

+

–

+

OUT1A

OUT4B

–

OUT1A

–

+

–

+

FR

DCO DCO

+

–

OUT1B

OUT4A

OUT3A

OUT4A

–

+

OUT2B

SCK

OV

DD

OUT3B

OUT2A

+

–

OUT1B

+

OUT2A

OUT3B

+

–

OUT3A

OUT2B

ALL ELSE = GND

BGA PACKAGE

221-LEAD (15mm × 11.25mm)

T

= 125°C, θ = 16.5°C/W, θ = 15°C/W,

JMAX

θ

JA

JCtop

= 10.4°C/W

= 6.ꢃ°C/W, θ

JCbottom

JSOARD

θ VALUEꢀ DETERMꢁIED PER JEꢀD 51-9

WEꢁGHT = 1.07g

http://www.linear.com/product/LTM9012#orderinfo

orDer inForMaTion

LEAD FREE FINISH

LTM9012CY-AS#PSF

LTM9012ꢁY-AS#PSF

TRAY

PART MARKING*

LTM9012YAS

PACKAGE DESCRIPTION

TEMPERATURE RANGE

0°C to 70°C

LTM9012CY-AS#PSF

LTM9012ꢁY-AS#PSF

221-Lead (15mm × 11.25mm) Plastic SGA

LTM9012YAS

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified bꢂ a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. ꢀome packages are available in 500 unit reels through

designated sales channels with #TRMPSF suffix.

9012fa

2

For more information www.linear.com/LTM9012

LTM9012

converTer characTerisTics ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 6)

PARAMETER

CONDITIONS

MIN

14

TYP

MAX

UNITS

Sits

l

Resolution (Io Missing Codes)

ꢁntegral Linearitꢂ Error

Differential Linearitꢂ Error

Offset Error

Differential Analog ꢁnput (Iote 7)

Differential Analog ꢁnput

(Iote 8)

–5

1.2

0.ꢃ

ꢃ

5

LꢀS

mV

–0.9

–ꢃ7

0.9

ꢃ7

Gain Error

ꢁnternal Reference

External Reference

–1.ꢃ

%Fꢀ

l

–ꢃ.6

ꢃ.0

Offset Drift

20

µV/°C

Full-ꢀcale Drift

ꢁnternal Reference

External Reference

ꢃ5

25

ppm/°C

Gain Matching

Offset Matching

Transition Ioise

External Reference

0.2

ꢃ

%Fꢀ

mV

External Reference

1.2

LꢀS

RMꢀ

analog inpuT ^Thel denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T_A= 25°C. (Note 6)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

–

l

V

Differential Analog ꢁnput Range (CH – CH ) LTM9012-AS

at –1dSFꢀ

0.2

V

P-P

ꢁI

+

–

V

Analog ꢁnput Common Mode (CH + CH )/2 Differential Analog ꢁnput (Iote 9)

External Voltage Reference Applied to ꢀEIꢀE External Reference Mode

0 to 1.5

1.250

100

V

ꢁI(CM)

0.625

1.ꢃ00

ꢀEIꢀE

R

Differential ꢁnput Resistance

LTM9012-AS

Ω

ꢁI

l

ꢁ

t

ꢁnput Leakage Current

0 < PAR/SER < V

–ꢃ

–6

ꢃ

6

µA

ns

ꢁI(P/ꢀ)

ꢁI(ꢀEIꢀE)

AP

DD

ꢁnput Leakage Current

0.625V < ꢀEIꢀE < 1.ꢃV

ꢀample-and-Hold Acquisition Delaꢂ Time

ꢀample-and-Hold Acquisition Delaꢂ Jitter

Analog ꢁnput Common Mode Rejection Ratio

ꢃdS Corner of ꢁnternal Lowpass Filter

0

0.15

90

ps

JꢁTTER

RMꢀ

CMRR

dS

SW-ꢃdS

90

MHz

DynaMic accuracy ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C. (Note 6)

SYMBOL

ꢀIR

PARAMETER

CONDITIONS

70MHz ꢁnput

MIN

66.5

66.9

TYP

68.ꢃ

78

MAX

UNITS

dSFꢀ

l

ꢀignal-to-Ioise Ratio

ꢀFDR

ꢀpurious Free Dꢂnamic Range

2nd or ꢃrd Harmonic

l

ꢀpurious Free Dꢂnamic Range

4th Harmonic or Higher

70MHz ꢁnput

76.9

64.7

86

dSFꢀ

ꢀ/I+D

ꢀignal-to-Ioise Plus Distortion Ratio

Crosstalk, Iear Channel

70MHz ꢁnput

66.7

70

dSFꢀ

dSc

10MHz (Iote 12)

Crosstalk, Far Channel

90

dSc

9012fa

3

For more information www.linear.com/LTM9012

LTM9012

inTernal reFerence characTerisTics ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C.

PARAMETER

CONDITIONS

= 0

MIN

TYP

1.250

25

MAX

UNITS

V

Output Voltage

ꢁ

1.225

1.275

REF

OUT

Output Temperature Drift

Output Resistance

Line Regulation

ppm/°C

Ω

–400μA < ꢁ

< 1mA

7

OUT

1.7V < V < 1.9V

0.6

mV/V

DD

DigiTal inpuTs anD ouTpuTs ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 6)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

–

ENCODE INPUTS (ENC , ENC )

–

Differential Encode Mode (ENC Not Tied to GND)

l

V

Differential ꢁnput Voltage

(Iote 9)

0.2

V

ꢁD

Common Mode ꢁnput Voltage

ꢁnternallꢂ ꢀet

Externallꢂ ꢀet (Iote 9)

1.2

V

ꢁCM

l

1.1

0.2

1.6

ꢃ.6

+

–

V

ꢁnput Voltage Range

ꢁnput Resistance

EIC , EIC to GID

(ꢀee Figure ꢃ)

V

kΩ

pF

ꢁI

R

10

ꢁI

C

ꢁnput Capacitance

ꢃ.5

ꢁI

–

Single-Ended Encode Mode (ENC Tied to GND)

V

High Level ꢁnput Voltage

Low Level ꢁnput Voltage

ꢁnput Voltage Range

ꢁnput Resistance

V

= 1.8V

1.26

0.54

0 to ꢃ.6

ꢃ0

V

ꢁH

ꢁL

ꢁI

DD

+

EIC to GID

(ꢀee Figure 4)

V

R

kΩ

pF

ꢁI

C

ꢁnput Capacitance

ꢃ.5

ꢁI

Digital Inputs (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)

l

V

High Level ꢁnput Voltage

Low Level ꢁnput Voltage

ꢁnput Current

V

= 1.8V

1.ꢃ

V

ꢁH

ꢁL

DD

ꢁI

l

= 1.8V

0.6

10

ꢁ

= 0V to ꢃ.6V

–10

µA

pF

ꢁI

C

ꢁnput Capacitance

ꢃ

200

ꢃ

ꢁI

SDO Output (Serial Programming Mode. Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)

R

Logic Low Output Resistance to GID

Logic High Output Leakage Current

Output Capacitance

V

DD

= 1.8V, ꢀDO = 0V

Ω

µA

pF

OH

l

ꢁ

ꢀDO = 0V to ꢃ.6V

–10

10

OH

C

OUT

Digital Input (SHDN)

l

V

High Level ꢁnput Voltage

Low Level ꢁnput Voltage

SHDN Pull-Up Resistor

V

= ꢃ.ꢃV

0.97

0.95

150

1.4

V

ꢁH

ꢁL

CC

0.6

90

CC

R

= 0V to 0.5V

SHDN

210

kΩ

SHDN

Digital Data Outputs

l

V

OD

Differential Output Voltage

100Ω Differential Load, ꢃ.5mA Mode

100Ω Differential Load, 1.75mA Mode

247

125

ꢃ50

175

454

250

mV

l

V

Common Mode Output Voltage

On-Chip Termination Resistance

100Ω Differential Load, ꢃ.5mA Mode

100Ω Differential Load, 1.75mA Mode

1.125

1.250

1.ꢃ75

V

Oꢀ

R

Termination Enabled, OV = 1.8V

100

Ω

TERM

DD

9012fa

4

For more information www.linear.com/LTM9012

LTM9012

power requireMenTs ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 6)

SYMBOL

PARAMETER

CONDITIONS

(Iote 10)

MIN

1.7

2.7

TYP

1.8

ꢃ.ꢃ

298

MAX

1.9

UNITS

l

V

DD

ADC ꢀupplꢂ Voltage

V

OV

DD

ADC Output ꢀupplꢂ Voltage

Amplifier ꢀupplꢂ Voltage

ADC ꢀupplꢂ Current

(Iote 10)

1.9

V

CC

(Iote 10)

ꢃ.6

V

ꢁ

ꢀine Wave ꢁnput

ꢃ20

mA

VDD

l

ADC Output ꢀupplꢂ Current

2-Lane Mode, 1.75mA Mode

2-Lane Mode, ꢃ.5mA Mode

27

49

ꢃ1

54

mA

OVDD

l

ꢁ

Amplifier ꢀupplꢂ Current

208

224

mA

VCC

l

P

2-Lane Mode, 1.75mA Mode

2-Lane Mode, ꢃ.5mA Mode

1271

1ꢃ11

147ꢃ

1517

mW

Dꢁꢀꢀ

P

ꢃ

mW

ꢀLEEP

IAP

85

20

Power Decrease with ꢀingle-Ended

Encode Mode Enabled

DꢁFFCLK

TiMing characTerisTics ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 6)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

f

t

ꢀampling Frequencꢂ

(Iote 10, Iote 11)

5

125

MHz

ꢀ

l

EIC Low Time (Iote 9)

Dutꢂ Cꢂcle ꢀtabilizer Off

Dutꢂ Cꢂcle ꢀtabilizer On

ꢃ.8

2

4

100

ns

EICL

l

t

EIC High Time (Iote 9)

Dutꢂ Cꢂcle ꢀtabilizer Off

Dutꢂ Cꢂcle ꢀtabilizer On

ꢃ.8

2

4

100

ns

EICH

AP

ꢀample-and-Hold

Acquisition Delaꢂ Time

0

ns

Digital Data Outputs (R

= 100Ω Differential, C = 2pF to GND on Each Output)

L

TERM

t

ꢀerial Data Sit Period

2-Lanes, 16-Sit ꢀerialization

2-Lanes, 14-Sit ꢀerialization

2-Lanes, 12-Sit ꢀerialization

1-Lane, 16-Sit ꢀerialization

1-Lane, 14-Sit ꢀerialization

1-Lane, 12-Sit ꢀerialization

1/(8•f )

sec

ꢀER

ꢀ

1/(7•f )

ꢀ

1/(6•f )

ꢀ

1/(16•f )

ꢀ

1/(14•f )

ꢀ

1/(12•f )

ꢀ

l

t

FR to DCO Delaꢂ

DATA to DCO Delaꢂ

Propagation Delaꢂ

Output Rise Time

Output Fall Time

(Iote 9)

0.35•t

0.5•t

0.65•t

sec

ns

FRAME

DATA

PD

ꢀER

(Iote 9)

ꢀER

(Iote 9)

0.7n + 2•t

1.1n + 2•t

1.5n + 2•t

ꢀER

Data, DCO, FR, 20% to 80%

0.17

60

R

ns

F

DCO Cꢂcle-Cꢂcle Jitter

Pipeline Latencꢂ

t

= 1ns

ps

P-P

ꢀER

6

Cꢂcles

SPI Port Timing (Note 9)

l

t

ꢀCK Period

Write Mode

40

ns

ꢀCK

Read Sack Mode, C

= 20pF, R

= 2k

250

ꢀDO

PULLUP

l

t

CS to ꢀCK ꢀetup Time

ꢀCK to CS ꢀetup Time

ꢀDꢁ ꢀetup Time

5

ns

ꢀ

H

ns

Dꢀ

DH

DO

ꢀDꢁ Hold Time

ns

ꢀCK Falling to ꢀDO Valid

Read Sack Mode, C

= 20pF, R

125

ns

9012fa

5

For more information www.linear.com/LTM9012

LTM9012

elecTrical characTerisTics

Note 1: ꢀtresses beꢂond those listed under Absolute Maximum Ratings

maꢂ cause permanent damage to the device. Exposure to anꢂ Absolute

Maximum Rating condition for extended periods maꢂ affect device

reliabilitꢂ and lifetime.

Note 6: V = ꢃ.ꢃV, V = OV = 1.8V, f

= 125MHz, 2-lane output

ꢀAMPLE

CC

DD

+

DD

–

mode, differential EIC /EIC = 2V sine wave, input range = 200mV

P-P

with differential drive, unless otherwise noted.

Note 7: ꢁntegral nonlinearitꢂ is defined as the deviation of a code from a

best fit straight line to the transfer curve. The deviation is measured from

the center of the quantization band.

Note 2: All voltage values are with respect to GID (unless otherwise

noted).

Note 3: ꢁnput pins are protected bꢂ steering diodes to either supplꢂ. ꢁf

Note 8: Offset error is the offset voltage measured from –0.5 LꢀS when

the output code flickers between 00 0000 0000 0000 and 11 1111 1111

1111 in 2’s complement output mode.

Note 9: Guaranteed bꢂ design, not subject to test.

Note 10: Recommended operating conditions.

the inputs should exceed either supplꢂ voltage, the input current should

+

–

be limited to less than 10mA. ꢁn addition, the inputs CHn , CHn are

protected bꢂ a pair of back-to-back diodes. ꢁf the differential input voltage

exceeds 1.4V, the input current should be limited to less than 10mA.

Note 4: When these pin voltages are taken below GID or above V , theꢂ

DD

Note 11: The maximum sampling frequencꢂ depends on the speed grade

of the part and also which serialization mode is used. The maximum serial

will be clamped bꢂ internal diodes. This product can handle input currents

greater than 100mA below GID or above V without latchup.

DD

data rate is 1000Mbps so t

must be greater than or equal to 1ns.

ꢀER

Note 5: When these pin voltages are taken below GID theꢂ will be

clamped bꢂ internal diodes. When these pin voltages are taken above V

theꢂ will not be clamped bꢂ internal diodes. This product can handle input

currents greater than 100mA below GID without latchup.

Note 12: Iear-channel crosstalk refers to CH1 and CH2. Far channel

crosstalk refers to CH1 to CH4.

DD

TiMing DiagraMs

2-Lane Output Mode, 16-Bit Serialization*

t

AP

N+1

ANALOG

INPUT

N

t

ENCL

ENCH

–

ENC

+

ENC

t

SER

–

DCO

+

DCO

t

SER

FRAME

DATA

–

FR

+

FR

t

SER

PD

–

OUT#A

D5 D3 D1

0

D13 D11 D9 D7 D5 D3 D1

0

D13 D11 D9

D12 D10 D8

+

OUT#A

–

OUT#B

D4 D2 D0

SAMPLE N-6

D12 D10 D8 D6 D4 D2 D0

SAMPLE N-5

0

+

OUT#B

SAMPLE N-4

9012 TD01

*SEE THE DIGITAL OUTPUTS SECTION

9012fa

6

For more information www.linear.com/LTM9012

LTM9012

TiMing DiagraMs

2-Lane Output Mode, 14-Bit Serialization

t

AP

N+2

ANALOG

N

INPUT

N+1

t

ENCL

ENCH

–

ENC

+

ENC

t

SER

–

DCO

+

DCO

t

SER

FRAME

DATA

–

FR

+

FR

t

SER

PD

–

OUT#A

D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9

+

OUT#A

–

OUT#B

D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8

+

OUT#B

SAMPLE N-6

SAMPLE N-5

–

SAMPLE N-4

SAMPLE N-3

9012 TD02

+

–

NOTE THAT IN THIS MODE FR /FR HAS TWO TIMES THE PERIOD OF ENC /ENC

2-Lane Output Mode, 12-Bit Serialization

t

AP

ANALOG

INPUT

N

N+1

t

ENCL

ENCH

–

ENC

+

ENC

t

SER

–

DCO

+

DCO

t

SER

FRAME

DATA

+

FR

–

FR

t

PD

SER

–

OUT#A

D9 D7 D5 D3 D13 D11 D9 D7 D5 D3 D13 D11 D9

+

OUT#A

–

OUT#B

D8 D6 D4 D2 D12 D10 D8 D6 D4 D2 D12 D10 D8

+

OUT#B

SAMPLE N-6

SAMPLE N-5

SAMPLE N-4

9012 TD03

9012fa

7

For more information www.linear.com/LTM9012

LTM9012

TiMing DiagraMs

1-Lane Output Mode, 16-Bit Serialization

t

AP

N+1

ANALOG

INPUT

N

t

ENCL

ENCH

–

ENC

+

ENC

t

SER

–

DCO

+

DCO

t

SER

FRAME

DATA

–

FR

+

FR

t

SER

PD

–

OUT#A

D1 D0

0

D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0

D13 D12 D11 D10

+

OUT#A

9012 TD04

SAMPLE N-6

SAMPLE N-5

SAMPLE N-4

+

–

OUT#B , OUT#B ARE DISABLED

1-Lane Output Mode, 14-Bit Serialization

t

AP

N+1

ANALOG

INPUT

N

t

ENCL

ENCH

–

ENC

+

ENC

t

SER

–

DCO

+

DCO

t

SER

FRAME

DATA

–

FR

+

FR

t

SER

PD

–

OUT#A

D3 D2 D1 D0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D13 D12 D11 D10

+

OUT#A

9012 TD05

SAMPLE N-6

SAMPLE N-5

SAMPLE N-4

+

–

OUT#B , OUT#B ARE DISABLED

9012fa

8

For more information www.linear.com/LTM9012

LTM9012

TiMing DiagraMs

1-Lane Output Mode, 12-Bit Serialization

t

AP

N+1

ANALOG

INPUT

N

t

ENCL

ENCH

–

ENC

+

ENC

t

SER

–

DCO

+

DCO

t

SER

FRAME

DATA

–

FR

+

FR

t

SER

PD

–

OUT#A

D5 D4 D3 D2 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D13 D12 D11

+

OUT#A

SAMPLE N-6

SAMPLE N-5

SAMPLE N-4

9012 TD06

+

–

OUT#B , OUT#B ARE DISABLED

SPI Port Timing (Readback Mode)

t

S

t

DS

t

DH

t

H

SCK

CS

SCK

t

DO

SDI

A6

A5

A4

A3

A2

A1

A0

XX

D6

XX

D5

XX

D4

XX

D3

XX

D2

XX

D1

XX

R/W

SDO

D7

D0

HIGH IMPEDANCE

SPI Port Timing (Write Mode)

CS

SCK

SDI

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

R/W

SDO

9012 TD07

HIGH IMPEDANCE

9012fa

9

For more information www.linear.com/LTM9012

LTM9012

Typical perForMance characTerisTics

I_OVDDvs Sample Rate, 5MHz Sine

Wave Input –1dBFS

64K Point FFT, f_IN= 5MHz,

–1dBFS, SENSE = V_DD

64K Point FFT, f_IN= 70MHz,

–1dBFS, SENSE = V_DD

0

–10

60

50

40

30

20

10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

1-LANE 1.75mA

1-LANE 3.5mA

2-LANE 1.75mA

2-LANE 3.5mA

–100

–110

–120

–100

–110

–120

35 40

45 50 55 60

50

SAMPLE RATE (Msps)

35 40

0

5

10 15 20 25 30

0

25

75

100

125

0

5

10 15 20 25 30

45 50 55 60

FREQUENCY (MHz)

9012 G03

9012 G01

9012 G02

64K Point 2-Tone FFT, f_IN= 4.8MHz

and f_IN= 5.2MHz, –7dBFS per Tone,

SENSE = V_DD

64K Point 2-Tone FFT, f_IN= 70MHz

and f_IN= 75MHz, –7dBFS per Tone,

SENSE = V_DD

Differential Non-Linearity (DNL)

vs Output Code

0

–10

0

–10

0.5

0.4

–20

0.3

–30

0.2

–40

0.1

–50

–60

0

–70

–0.1

–0.2

–0.3

–0.4

–0.5

–80

–90

–100

–110

–120

–100

–110

–120

35 40

45 50 55 60

0

5

10 15 20 25 30

45 50 55 60

0

5

10 15 20 25 30

4096

8192

12288

16384

0

FREQUENCY (MHz)

OUTPUT CODE

9012 G04

9012 G05

9012 G06

Integral Non-Linearity (INL)

vs Output Code

Pulse Response

Frequency Response

2.0

1.5

16000

14000

12000

10000

8000

6000

4000

2000

0

–5

1.0

–10

–15

–20

–25

–30

–35

–40

0.5

0

–0.5

–1.0

–1.5

–2.0

0

4096

8192

12288

16384

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

TIME (µs)

1

10

100

1000

OUTPUT CODE

BASEBAND FREQUENCY (MHz)

9012 G07

9012 G08

9012 G09

9012fa

10

For more information www.linear.com/LTM9012

LTM9012

pin FuncTions

V

(H10, H13): Channel 1 Amplifier ꢀupplꢂ. V is

operating mode. Connecting SHDN2 to GID results in a

CC1

CC

internallꢂ bꢂpassed to ground with 0.1µF in parallel with

0.01µF ceramic capacitors, additional bꢂpass capacitance

is optional. The recommended operating voltage is ꢃ.ꢃV.

low power shutdown state on amplifier 2.

SHDN3 (D3): Channel ꢃ Amplifier ꢀhutdown. Connect-

ing SHDN3 to V or floating results in normal (active)

CC

V

CC2

(C8, C12): Channel 2 Amplifier ꢀupplꢂ. V is in-

operating mode. Connecting SHDN3 to GID results in a

CC

ternallꢂ bꢂpassed to ground with 0.1µF in parallel with

0.01µF ceramic capacitors, additional bꢂpass capacitance

is optional. The recommended operating voltage is ꢃ.ꢃV.

low power shutdown state on amplifier ꢃ.

SHDN4 (G1): Channel 4 Amplifier ꢀhutdown. Connect-

ing SHDN4 to V or floating results in normal (active)

CC

V

(C2, C6): Channel ꢃ Amplifier ꢀupplꢂ. V is in-

operating mode. Connecting SHDN4 to GID results in a

CC3

CC

ternallꢂ bꢂpassed to ground with 0.1µF in parallel with

0.01µF ceramic capacitors, additional bꢂpass capacitance

is optional. The recommended operating voltage is ꢃ.ꢃV.

low power shutdown state on amplifier 4.

+

ENC (N1): Encode ꢁnput. Conversion starts on the rising

edge.

V

(H1, H4): Channel 4 Amplifier ꢀupplꢂ. V is in-

CC

–

CC4

ENC (P1): Encode Complement ꢁnput. Conversion starts

ternallꢂ bꢂpassed to ground with 0.1µF in parallel with

0.01µF ceramic capacitors, additional bꢂpass capacitance

is optional. The recommended operating voltage is ꢃ.ꢃV.

on the falling edge.

CS (P4): ꢁn serial programming mode, (PAR/SER = 0V),

CS is the serial interface chip select input. When CS is

low, ꢀCK is enabled for shifting data on ꢀDꢁ into the mode

controlregisters.ꢁntheparallelprogrammingmode(PAR/

V

DD

(N4, N5, N9, N10): ADC Analog ꢀupplꢂ. V is inter-

DD

nallꢂ bꢂpassed to ground with 0.1µF ceramic capacitors,

additional bꢂpass capacitance is optional. The recom-

mended operating voltage is 1.8V.

SER = V ), CS selects 2-lane or 1-lane output mode. CS

DD

can be driven with 1.8V to ꢃ.ꢃV logic.

OV (R7, R8, S8): ADC Digital Output ꢀupplꢂ. OV

DD

SCK (P5): ꢁn serial programming mode, (PAR/SER =

is internallꢂ bꢂpassed to ground with 0.1µF ceramic ca-

pacitors, additional bꢂpass capacitance is optional. The

recommended operating voltage is 1.8V.

0V), ꢀCK is the serial interface clock input. ꢁn the parallel

programmingmode(PAR/SER=V ),ꢀCKselectsꢃ.5mA

DD

or 1.75mA LVDꢀ output currents. ꢀCK can be driven with

1.8V to ꢃ.ꢃV logic.

GND: Ground. Use multiple vias close to pins.

+

CH1 (A11): Channel 1 Ioninverting Analog ꢁnput.

SDI (P3): ꢁn serial programming mode, (PAR/SER = 0V),

ꢀDꢁistheserialinterfacedataꢁnput.DataonꢀDꢁisclocked

into the mode control registers on the rising edge of ꢀCK.

–

CH1 (A12): Channel 1 ꢁnverting Analog ꢁnput.

+

CH2 (A8): Channel 2 Ioninverting Analog ꢁnput.

ꢁn the parallel programming mode (PAR/SER = V ), ꢀDꢁ

DD

can be used to power down the part. ꢀDꢁ can be driven

with 1.8V to ꢃ.ꢃV logic.

–

CH2 (A9): Channel 2 ꢁnverting Analog ꢁnput.

+

CH3 (A5): Channel ꢃ Ioninverting Analog ꢁnput.

SDO (P9): ꢁn serial programming mode, (PAR/SER = 0V),

ꢀDO is the optional serial interface data output. Data on

ꢀDO is read back from the mode control registers and can

be latched on the falling edge of ꢀCK. ꢀDO is an open-

drain IMOꢀ output that requires an external 2k pull-up

resistor to 1.8V – ꢃ.ꢃV. ꢁf read back from the mode control

registers is not needed, the pull-up resistor is not neces-

sarꢂ and ꢀDO can be left unconnected. ꢁn the parallel

–

CH3 (A6): Channel ꢃ ꢁnverting Analog ꢁnput.

+

CH4 (A2): Channel 4 Ioninverting Analog ꢁnput.

–

CH4 (A3): Channel 4 ꢁnverting Analog ꢁnput.

SHDN1 (G11): Channel 1 Amplifier ꢀhutdown. Connect-

ing SHDN1 to V or floating results in normal (active)

CC

operating mode. Connecting SHDN1 to GID results in a

programming mode (PAR/SER = V ), ꢀDO is an input

low power shutdown state on amplifier 1.

DD

that enables internal 100Ω termination resistors. When

used as an input, ꢀDO can be driven with 1.8V to ꢃ.ꢃV

SHDN2 (D9): Channel 2 Amplifier ꢀhutdown. Connect-

ing SHDN2 to V or floating results in normal (active)

CC

logic through a 1k series resistor.

9012fa

11

For more information www.linear.com/LTM9012

LTM9012

pin FuncTions

PAR/SER (P10): Programming Mode ꢀelection Pin. Con-

necttogroundtoenabletheserialprogrammingmode.CS,

ꢀCK, ꢀDꢁ and ꢀDO become a serial interface that controls

LVDS Outputs

All pins in this section are differential LVDꢀ outputs. The

output current level is programmable. There is an optional

internal 100Ω termination resistor between the pins of

each LVDꢀ output pair.

the A/D operating modes. Connect to V to enable the

DD

parallel programming mode where CS, ꢀCK, ꢀDꢁ and ꢀDO

become parallel logic inputs that control a reduced set of

the A/D operating modes. PAR/SER should be connected

–

+

–

+

OUT1A /OUT1A , OUT1B /OUT1B (Q9/Q10, R11/R12):

ꢀerial data outputs for Channel 1. ꢁn 1-lane output mode

directlꢂ to ground or the V of the part and not be driven

bꢂ a logic signal.

DD

–

+

onlꢂ OUT1A /OUT1A are used.

–

+

–

+

OUT2A /OUT2A , OUT2B /OUT2B (R9/R10, S11/S12):

V

(P11): Reference Voltage Output. V

is internallꢂ

REF

ꢀerial data outputs for Channel 2. ꢁn 1-lane output mode

bꢂpassed to ground with a 2.2μF ceramic capacitor, nomi-

nallꢂ 1.25V.

–

+

onlꢂ OUT2A /OUT2A are used.

–

+

–

+

OUT3A /OUT3A , OUT3B /OUT3B (S2/S3, R4/R5): ꢀe-

SENSE (N11): Reference Programming Pin. Connecting

rial data outputs for Channel ꢃ. ꢁn 1-lane output mode

ꢀEIꢀE to V selects the internal reference and a 0.1V

DD

–

+

onlꢂ OUTꢃA /OUTꢃA are used.

input range. Connecting ꢀEIꢀE to ground selects the

internal reference and a 0.05V input range. An external

reference between 0.625V and 1.ꢃV applied to ꢀEIꢀE

–

+

–

+

OUT4A /OUT4A , OUT4B /OUT4B (R2/R3, Q4/Q5): ꢀe-

rial data outputs for Channel 4. ꢁn 1-lane output mode

selects an input range of ±0.08 • V

nallꢂ bꢂpassed to ground with a 0.1μF ceramic capacitor.

. ꢀEIꢀE is inter-

ꢀEIꢀE

–

+

onlꢂ OUT4A /OUT4A are used.

–

+

FR /FR (S4/S5): Frame ꢀtart Output.

–

+

DCO /DCO (S9/S10): Data Clock Output.

pin conFiguraTion Table

1

2

3

4

5

6

7

8

9

10

11

12

13

+

–

+

–

+

–

+

–

A

B

C

D

E

GID

SHDN4

CH4

GID

CHꢃ

GID

OVDD

GID

CH2

GID

CH1

GID

SHDN3

GID

ꢀDꢁ

GID

SHDN2

GID

SHDN1

GID

ꢀEIꢀE

REF

GID

V

CC2

CCꢃ

CC2

GID

OUT4A

OUTꢃA

GID

OVDD

GID

F

GID

G

H

J

GID

V

CC1

GID

V

CC1

CC4

GID

K

L

GID

M

N

P

Q

R

S

GID

+

EIC

EIC–

GID

V

DD

V

DD

V

DD

GID

DD

CS

ꢀCK

OUT4S

OUTꢃS

ꢀDO

OUT1A

OUT2A

PAR/SER

GID

–

+

–

+

GID

OUT4S

OUTꢃS

OUT1A

GID

–

+

–

+

OUT4A

OUTꢃA

OUT2A

OUT1S

OUT2S

OUT1S

OUT2S

+

–

+

–

+

–

FR

DCO

9012fa

12

For more information www.linear.com/LTM9012

LTM9012

block DiagraM

3.3V

1.8V

V

CC

V

OV

DD

LTM9012

+

OUT1A

–

CH 1

ANALOG

INPUT

OUT1A

14-BIT

ADC CORE

+

OUT1B

–

OUT1B

DATA

SERIALIZER

SHDN1

V

DD/2

+

OUT2A

CH 2

ANALOG

INPUT

–

OUT2A

14-BIT

ADC CORE

+

OUT2B

–

OUT2B

SHDN2

+

OUT3A

CH 3

ANALOG

INPUT

–

OUT3A

14-BIT

ADC CORE

+

OUT3B

–

OUT3B

SHDN3

V

DD/2

+

OUT4A

CH 4

ANALOG

INPUT

–

OUT4A

14-BIT

ADC CORE

+

OUT4B

–

OUT4B

SHDN4

+

ENC

DCO

FR

PLL

–

ENC

V

REF

1.25V

REFERENCE

SDO

SDI

REFH REFL

MODE

CONTROL

REGISTERS

SCK

CS

PAR/SER

RANGE

SELECT

REF

BUFFER

DIFF. REF.

AMP.

SENSE

GND

9012 BD

Figure 1. Block Diagram

9012fa

13

For more information www.linear.com/LTM9012

LTM9012

applicaTions inForMaTion

CONVERTER OPERATION

The gain of the LTM9012 maꢂ also be decreased from

the nominal value bꢂ adding resistance in series with

the signal inputs. The internal op amps are fed bꢂ 49.9Ω

series resistors and emploꢂ 511Ω feedback resistors. The

voltage gain of the stage is set bꢂ the ratio of the feedback

resistance to the total series resistance. Unitꢂ gain, for

example, can be realized bꢂ adding a 464Ω resistor in

series with each input.

The LTM9012 is a low power, 4-channel, 14-bit, 125Msps

A/D converter that is powered bꢂ a 1.8V ADC supplꢂ and

ꢃ.ꢃV driver supplies. Each input includes a fixed gain,

differential amplifier. The analog inputs can be driven dif-

ferentiallꢂorsingle-ended.Theencodeinputcanbedriven

differentiallꢂforoptimaljitterperformance,orsingle-ended

forlowerpowerconsumption.Thedigitaloutputsareserial

LVDꢀ to minimize the number of data lines. Each channel

outputstwobitsatatime(2-lanemode).Atlowersampling

rates there is a one bit per channel option (1-lane mode).

Manꢂ additional features can be chosen bꢂ programming

the mode control registers through a serial ꢀPꢁ port.

Reference

The LTM9012 has an internal 1.25V voltage reference. For

a 2V input range using the internal reference with a unitꢂ

gaininternalamplifierconfiguration,connectꢀEIꢀEtoV .

DD

For a 1V input range using the internal reference, connect

ꢀEIꢀE to ground. For a 2V input range with an external

reference, applꢂ a 1.25V reference voltage to ꢀEIꢀE.

Analog Inputs

The analog inputs for each channel of the LTM9012 con-

sist of a differential amplifier with fixed gain followed bꢂ

a lowpass filter. The 10x gain version has 49.9Ω series

resistance in each input.

The input range can be adjusted bꢂ applꢂing a voltage to

ꢀEIꢀE that is between 0.625V and 1.ꢃ0V. The input range

will then be 1.6 • V

.

ꢀEIꢀE

The differential input can support single-ended operation

bꢂ connecting the inverting input to a fixed DC voltage or

ground. However, if ground is used, there will be a 6dS

lossofdꢂnamicrange. Formaximumdꢂnamicrange, con-

nect the inverting inputs of the LTM9012 to a DC voltage

equal to the median of the voltage excursions of the non-

inverting input. An op amp provides an excellent means

of providing a low impedance voltage source capable of

sourcing and sinking small amounts of current. Iote the

value of this DC voltage should fall between the limits of

allowable input common mode voltages. ꢀee Figure 2 for

an example.

The reference is shared bꢂ all four ADC channels, so it is

not possible to independentlꢂ adjust the input range of

individual channels.

Encode Input

The signal qualitꢂ of the encode inputs stronglꢂ affects

the A/D noise performance. The encode inputs should be

treatedasanalogsignals—donotroutethemnexttodigital

traces on the circuit board. There are two modes of opera-

tion for the encode inputs: the differential encode mode

(Figure ꢃ), and the single-ended encode mode (Figure 4).

Thedifferentialencodemodeisrecommendedforsinusoi-

dal, PECL, or LVDꢀ encode inputs (Figure 5 and Figure 6).

The encode inputs are internallꢂ biased to 1.2V through

10k equivalent resistance. The encode inputs can be taken

LTM9012

(1 CHANNEL SHOWN)

SIGNAL

–

+

above V (up to ꢃ.6V), and the common mode range is

DD

–

from 1.1V to 1.6V. ꢁn the differential encode mode, EIC

should staꢂ at least 200mV above ground to avoid falselꢂ

triggering the single-ended encode mode. For good jitter

¼LTC6254

V

REF

–

+

9012 F02

+

performance EIC should have fast rise and fall times.

0.1µF

R

F

SET V

EQUAL TO THE DC MEDIAN OF THE SIGNAL VOLTAGE

REF

Figure 2. Single-Ended Operation

9012fa

14

For more information www.linear.com/LTM9012

LTM9012

applicaTions inForMaTion

Thesingle-endedencodemodeshouldbeusedwithCMOꢀ

LTM9012

V

DD

–

encode inputs. To select this mode, EIC is connected

DIFFERENTIAL

COMPARATOR

+

to ground and EIC is driven with a square wave encode

V

DD

+

input. EIC can be taken above V (up to ꢃ.6V) so 1.8V

DD

+

toꢃ.ꢃVCMOꢀlogiclevelscanbeused.TheEIC threshold

15k

30k

+

is 0.9V. For good jitter performance EIC should have fast

+

–

ENC

rise and fall times.

ENC

Clock PLL and Duty Cycle Stabilizer

Theencodeclockismultipliedbꢂaninternalphase-locked

loop (PLL) to generate the serial digital output data. ꢁf the

encode signal changes frequencꢂ or is turned off, the PLL

requires 25μs to lock onto the input clock.

9012 F03

Figure 3. Equivalent Encode Input Circuit

for Differential Encode Mode

A clock dutꢂ cꢂcle stabilizer circuit allows the dutꢂ cꢂcle

of the applied encode signal to varꢂ from ꢃ0% to 70%.

ꢁn the serial programming mode it is possible to disable

the dutꢂ cꢂcle stabilizer, but this is not recommended. ꢁn

the parallel programming mode the dutꢂ cꢂcle stabilizer

is alwaꢂs enabled.

LTM9012

+

1.8V TO 3.3V

0V

ENC

–

30k

ENC

CMOS LOGIC

BUFFER

9012 F04

Figure 4. Equivalent Encode Input Circuit

for Single-Ended Encode Mode

DIGITAL OUTPUTS

The digital outputs of the LTM9012 are serialized LVDꢀ

signals. Each channel outputs two bits at a time (2-lane

mode). At lower sampling rates there is a one bit per chan-

nel option (1-lane mode). The data can be serialized with

16-, 14-, or 12-bit serialization (see the Timing Diagrams

fordetails).Iotethatwith12-bitserializationthetwoLꢀSs

are not available—this mode is included for compatibilitꢂ

with potential 12-bit versions of these parts.

0.1µF

+

T1

ENC

LTM9012

50Ω

100Ω

0.1µF

–

0.1µF

ENC

The output data should be latched on the rising and falling

edges of the data clock out (DCO). A data frame output

(FR) can be used to determine when the data from a new

conversionresultbegins. ꢁnthe2-lane, 14-bitserialization

mode, the frequencꢂ of the FR output is halved.

9012 F05

T1 = MA/COM ETC1-1-13

RESISTORS AND CAPACITORS

ARE 0402 PACKAGE SIZE

Figure 5. Sinusoidal Encode Drive

Themaximumserialdatarateforthedataoutputsis1Gbps,

so the maximum sample rate of the ADC will depend on

the serialization mode as well as the speed grade of the

0.1µF

+

ENC

PECL OR

LTM9012

LVDS

CLOCK

0.1µF

–

ENC

9012 F06

Figure 6. PECL or LVDS Encode Drive

9012fa

15

For more information www.linear.com/LTM9012

LTM9012

applicaTions inForMaTion

ADC (see Table 1). The minimum sample rate for all seri-

alization modes is 5Msps.

DATA FORMAT

Table 2 shows the relationship between the analog input

voltage and the digital data output bits. Sꢂ default the

output data format is offset binarꢂ. The 2’s complement

format can be selected bꢂ seriallꢂ programming mode

control register A1.

Sꢂ default the outputs are standard LVDꢀ levels: ꢃ.5mA

output current and a 1.25V output common mode volt-

age. An external 100Ω differential termination resistor

is required for each LVDꢀ output pair. The termination

resistors should be located as close as possible to the

LVDꢀ receiver.

Table 2. Output Codes vs Input Voltage

+

–

CHn TO CHn

D13 TO D0

(OFFSET BINARY)

D13 TO D0

(2’s COMPLEMENT)

(0.2V RANGE)

The outputs are powered bꢂ OV which is isolated from

DD

>0.1000000V

+0.0999878V

+0.0999756V

11 1111 1111 1111

11 1111 1111 1110

01 1111 1111 1111

01 1111 1111 1110

the A/D core power.

Programmable LVDS Output Current

+0.0000122V

+0.0000000V

–0.0000122V

–0.0000244V

10 0000 0000 0001

10 0000 0000 0000

01 1111 1111 1111

00 0000 0000 0001

00 0000 0000 0000

11 1111 1111 1111

11 1111 1111 1110

The default output driver current is ꢃ.5mA. This current

can be adjusted bꢂ control register A2 in the serial pro-

gramming mode. Available current levels are 1.75mA,

2.1mA, 2.5mA, ꢃmA, ꢃ.5mA, 4mA and 4.5mA. ꢁn the

parallel programming mode the ꢀCK pin can select either

ꢃ.5mA or 1.75mA.

–0.0999878V

–0.1000000V

<–0.1000000V

00 0000 0000 0000

10 0000 0000 0001

10 0000 0000 0000

Digital Output Randomizer

Optional LVDS Driver Internal Termination

ꢁnterference from the A/D digital outputs is sometimes

unavoidable.Digitalinterferencemaꢂbefromcapacitiveor

inductive coupling or coupling through the ground plane.

Even a tinꢂ coupling factor can cause unwanted tones

in the ADC output spectrum. Sꢂ randomizing the digital

output before it is transmitted off chip, these unwanted

tones can be randomized which reduces the unwanted

tone amplitude.

ꢁn most cases using just an external 100Ω termination

resistor will give excellent LVDꢀ signal integritꢂ. ꢁn addi-

tion, an optional internal 100Ω termination resistor can

beenabledbꢂseriallꢂprogrammingmodecontrolregister

A2. The internal termination helps absorb anꢂ reflections

caused bꢂ imperfect termination at the receiver. When the

internalterminationisenabled, theoutputdrivercurrentis

doubled to maintain the same output voltage swing. ꢁn the

parallel programming mode the ꢀDO pin enables internal

termination. ꢁnternalterminationshouldonlꢂbeusedwith

1.75mA, 2.1mA or 2.5mA LVDꢀ output current modes.

The digital output is randomized bꢂ applꢂing an exclusive-

OR logic operation between the LꢀS and all other data

output bits. To decode, the reverse operation is applied

—an exclusive-OR operation is applied between the LꢀS

andallotherbits.TheFRandDCOoutputsarenotaffected.

Table 1. Maximum Sampling Frequency for All Serialization Modes. The Sampling Frequency for Potential Slower Speed Grades

Cannot Exceed f_SAMPLE(MAX)

.

MAXIMUM SAMPLING

SERIALIZATION MODE

16-Sit ꢀerialization

FREQUENCY, f (MHz)

DCO FREQUENCY

4 • f

FR FREQUENCY

SERIAL DATA RATE

S

2-Lane

1-Lane

125

62.5

71.4

8ꢃ.ꢃ

f

8 • f

7 • f

6 • f

ꢀ

14-Sit ꢀerialization

12-Sit ꢀerialization

16-Sit ꢀerialization

14-Sit ꢀerialization

12-Sit ꢀerialization

3.5 • f

0.5 • f

ꢀ

3 • f

8 • f

7 • f

6 • f

f

ꢀ

f

ꢀ

f

ꢀ

f

ꢀ

16 • f

14 • f

12 • f

ꢀ

9012fa

16

For more information www.linear.com/LTM9012

LTM9012

applicaTions inForMaTion

Theoutputrandomizerisenabledbꢂseriallꢂprogramming

mode control register A1.

ADCdriverhasanindependentSHDNpinbutitisexpected

that all four will be tied together.

Digital Output Test Pattern

DEVICE PROGRAMMING MODES

To allow in-circuit testing of the digital interface to the

A/D, there is a test mode that forces the A/D data outputs

(D1ꢃ-D0) of all channels to known values. The digital

output test patterns are enabled bꢂ seriallꢂ programming

mode control registers Aꢃ and A4. When enabled, the test

patterns override all other formatting modes: 2’s comple-

ment and randomizer.

TheoperatingmodesoftheLTM9012canbeprogrammed

bꢂ either a parallel interface or a simple serial interface.

The serial interface has more flexibilitꢂ and can program

all available modes. The parallel interface is more limited

and can onlꢂ program some of the more commonlꢂ used

modes.

Parallel Programming Mode

Output Disable

To use the parallel programming mode, PAR/SER should

The digital outputs maꢂ be disabled bꢂ seriallꢂ program-

ming mode control register A2. The current drive for all

digital outputs including DCO and FR are disabled to save

powerorenablein-circuittesting.Whendisabledthecom-

mon mode of each output pair becomes high impedance,

but the differential impedance maꢂ remain low.

be tied to V . The CS, ꢀCK, ꢀDꢁ and ꢀDO pins are binarꢂ

DD

logic inputs that set certain operating modes. These pins

can be tied to V or ground, or driven bꢂ 1.8V, 2.5V, or

DD

ꢃ.ꢃV CMOꢀ logic. When used as an input, ꢀDO should

be driven through a 1k series resistor. Table ꢃ shows the

modes set bꢂ CS, ꢀCK, ꢀDꢁ and ꢀDO.

Sleep and Nap Modes

Table 3. Parallel Programming Mode Control Bits

(PAR/SER = V_DD

)

The A/D maꢂ be placed in sleep or nap modes to conserve

power. ꢁn sleep mode the entire chip is powered down, re-

sultinginꢃmWpowerconsumption.ꢀleepmodeisenabled

bꢂ mode control register A1 (serial programming mode),

or bꢂ ꢀDꢁ (parallel programming mode). The amount of

time required to recover from sleep mode depends on the

size of the bꢂpass capacitors on V , REFH, and REFL.

Fortheinternalcapacitorvaluesandnoadditionalexternal

capacitance, the A/D will stabilize after 2ms.

DESCRIPTION

CS

2-Lane/1-Lane Selection Bit

0 = 2-Lane, 16-Sit ꢀerialization Output Mode

1 = 1-Lane, 14-Sit ꢀerialization Output Mode

ꢀCK

ꢀDꢁ

LVDS Current Selection Bit

0 = ꢃ.5mA LVDꢀ Current Mode

1 = 1.75mA LVDꢀ Current Mode

REF

Power Down Control Bit

0 = Iormal Operation

1 = ꢀleep Mode

ꢁn nap mode anꢂ combination of A/D channels can be

powereddownwhiletheinternalreferencecircuitsandthe

PLL staꢂ active, allowing faster wakeup than from sleep

mode. Recovering from nap mode requires at least 100

clock cꢂcles. ꢁf the application demands verꢂ accurate DC

settling then an additional 50μs should be allowed so the

on-chip references can settle from the slight temperature

shift caused bꢂ the change in supplꢂ current as the A/D

leaves nap mode. Iap mode is enabled bꢂ mode control

register A1 in the serial programming mode.

ꢀDO

Internal Termination Selection Bit

0 = ꢁnternal Termination Disabled

1 = ꢁnternal Termination Enabled

Serial Programming Mode

To use the serial programming mode, PAR/SER should be

tied to ground. The CS, ꢀCK, ꢀDꢁ and ꢀDO pins become a

serialinterfacethatprogramtheA/Dmodecontrolregisters.

Data is written to a register with a 16-bit serial word. Data

can also be read back from a register to verifꢂ its contents.

ꢀerial data transfer starts when CS is taken low. The data

on the ꢀDꢁ pin is latched at the first 16 rising edges of

ꢀCK. Anꢂ ꢀCK rising edges after the first 16 are ignored.

Driver Amplifier Shutdown (SHDN)

The ADC drivers maꢂ be placed in shutdown mode to

conserve power independentlꢂ from the ADC core. Each

The data transfer ends when CS is taken high again.

9012fa

17

For more information www.linear.com/LTM9012

LTM9012

applicaTions inForMaTion

The first bit of the 16-bit input word is the R/W bit. The

next seven bits are the address of the register (A6:A0).

The final eight bits are the register data (D7:D0).

The ꢀDO pin is an open-drain output that pulls to ground

with a 200Ω impedance. ꢁf register data is read back

through ꢀDO, an external 2k pull-up resistor is required. ꢁf

serialdataisonlꢂwrittenandreadbackisnotneeded, then

ꢀDO can be left floating and no pull-up resistor is needed.

Table 4 shows a map of the mode control registers.

ꢁf the R/W bit is low, the serial data (D7:D0) will be writ-

ten to the register set bꢂ the address bits (A6:A0). ꢁf the

R/W bit is high, data in the register set bꢂ the address bits

(A6:A0) will be read back on the ꢀDO pin (see the Timing

Diagrams sections). During a read back command the

register is not updated and data on ꢀDꢁ is ignored.

Software Reset

ꢁf serial programming is used, the mode control registers

shouldbeprogrammedassoonaspossibleafterthepower

supplies turn on and are stable. The first serial command

Table 4. Serial Programming Mode Register Map (PAR/SER = GND)

REGISTER A0: RESET REGISTER (ADDRESS 00h) WRITE ONLY

D7

D6

X

D5

X

D4

X

Dꢃ

X

D2

X

D1

X

D0

X

REꢀET

Sit 7

RESET

0 = Iot Used

ꢀoftware Reset Sit

1 = ꢀoftware Reset. All mode control registers are reset to 00h. The ADC is momentarilꢂ placed in ꢀleep mode.

This bit is automaticallꢂ set back to zero at the end of the ꢀPꢁ Write command. The Reset register is Write onlꢂ.

Data read back from the reset register will be random.

Sits 6-0

Unused, Don’t Care Sits.

REGISTER A1: FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h with CS = GND)

D7

D6

D5

D4

Dꢃ

D2

D1

D0

DCꢀOFF

RAID

TWOꢀCOMP

ꢀLEEP

IAP_4

IAP_ꢃ

IAP_2

IAP_1

Sit 7

Sit 6

Sit 5

DCSOFF

0 = Clock Dutꢂ Cꢂcle ꢀtabilizer On

Clock Dutꢂ Cꢂcle ꢀtabilizer Sit

1 = Clock Dutꢂ Cꢂcle ꢀtabilizer Off. This is not recommended.

RAND Data Output Randomizer Mode Control Sit

0 = Data Output Randomizer Mode Off

1 = Data Output Randomizer Mode On

TWOSCOMP

Two’s Complement Mode Control Sit

0 = Offset Sinarꢂ Data Format

1 = Two’s Complement Data Format

SLEEP: NAP_X

Sits 4-0

ꢀleep/Iap Mode Control Sits

00000 = Iormal Operation

0XXX1 = Channel 1 in Iap Mode

0XX1X = Channel 2 in Iap Mode

0X1XX = Channel ꢃ in Iap Mode

01XXX = Channel 4 in Iap Mode

1XXXX = ꢀleep Mode. Channels 1, 2, ꢃ and 4 are Disabled

Iote: Anꢂ combination of these channels can be placed in Iap mode.

9012fa

18

For more information www.linear.com/LTM9012

LTM9012

applicaTions inForMaTion

REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h)

D7

D6

D5

D4

Dꢃ

D2

D1

D0

ꢁLVDꢀ2

ꢁLVDꢀ1

ꢁLVDꢀ0

TERMOI

OUTOFF

OUTMODE2

OUTMODE1

OUTMODE0

Sits 7-5

ILVDS2:ILVDS0

LVDꢀ Output Current Sits

000 = ꢃ.5mA LVDꢀ Output Driver Current

001 = 4.0mA LVDꢀ Output Driver Current

010 = 4.5mA LVDꢀ Output Driver Current

011 = Iot Used

100 = ꢃ.0mA LVDꢀ Output Driver Current

101 = 2.5mA LVDꢀ Output Driver Current

110 = 2.1mA LVDꢀ Output Driver Current

111 = 1.75mA LVDꢀ Output Driver Current

Sit 4

TERMON

LVDꢀ ꢁnternal Termination Sit

0 = ꢁnternal Termination Off

1 = ꢁnternal Termination On. LVDꢀ Output Driver Current is 2× the Current ꢀet bꢂ ꢁLVDꢀ2:ꢁLVDꢀ0. ꢁnternal termination should onlꢂ

be used with 1.75mA, 2.1mA or 2.5mA LVDꢀ output current modes.

Sit ꢃ

OUTOFF

Output Disable Sit

0 = Digital Outputs are Enabled.

1 = Digital Outputs are Disabled.

OUTMODE2:OUTMODE0

Sits 2-0

Digital Output Mode Control Sits

000 = 2-Lanes, 16-Sit ꢀerialization

001 = 2-Lanes, 14-Sit ꢀerialization

010 = 2-Lanes, 12-Sit ꢀerialization

011 = Iot Used

100 = Iot Used

101 = 1-Lane, 14-Sit ꢀerialization

110 = 1-Lane, 12-Sit ꢀerialization

111 = 1-Lane, 16-Sit ꢀerialization

REGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h)

D7

OUTTEꢀT

D6

X

D5

TP1ꢃ

D4

TP12

Dꢃ

TP11

D2

TP10

D1

TP9

D0

TP8

Sit 7

Sit 6

OUTTEST

Digital Output Test Pattern Control Sit

0 = Digital Output Test Pattern Off

1 = Digital Output Test Pattern On

Unused, Don’t Care Sit.

TP13:TP8

Sit 5-0

Test Pattern Data Sits (MꢀS)

TP1ꢃ:TP8 ꢀet the Test Pattern for Data Sit 1ꢃ(MꢀS) Through Data Sit 8.

REGISTER A4: TEST PATTERN LSB REGISTER (ADDRESS 04h)

D7

D6

D5

D4

Dꢃ

D2

D1

D0

TP7

TP6

TP5

TP4

TPꢃ

TP2

TP1

TP0

Sit 7-0

TP7:TP0

Test Pattern Data Sits (LꢀS)

TP7:TP0 ꢀet the Test Pattern for Data Sit 7 Through Data Sit 0(LꢀS).

For more information www.linear.com/LTM9012

9012fa

19

LTM9012

applicaTions inForMaTion

HEAT TRANSFER

must be a software reset which will reset all register data

bits to logic 0. To perform a software reset, bit D7 in the

reset register is written with a logic 1. After the reset is

complete, bit D7 is automaticallꢂ set back to zero.

Most of the heat generated bꢂ the LTM9012 is transferred

from the die through the bottom side of the package

through numerous ground pins onto the printed circuit

board. Forgoodelectricalandthermalperformance, these

pins should be connected to the internal ground planes

bꢂ an arraꢂ of vias.

GROUNDING AND BYPASSING

The LTM9012 requires a printed circuit board with a

clean unbroken ground plane. A multilaꢂer board with an

internal ground plane in the first laꢂer beneath the ADC is

recommended. Laꢂoutfortheprintedcircuitboard should

ensure that digital and analog signal lines are separated as

much as possible. ꢁn particular, care should be taken not

to run anꢂ digital track alongside an analog signal track

or underneath the ADC.

Table 5. Internal Trace Lengths

Q9

NAME

(mm)

0.5ꢃ5

0.ꢃ50

2.185

2.216

0.174

0.667

2.976

2.972

ꢃ.0ꢃꢃ

ꢃ.0ꢃ1

0.752

0.ꢃ70

2.1ꢃ0

2.125

0.ꢃꢃ2

0.527

7.741

7.72ꢃ

4.6ꢃ2

4.629

ꢃ.987

ꢃ.988

7.892

7.896

ꢃ.ꢃ17

ꢃ.ꢃ25

0.241

1.912

1.927

2.097

2.082

0.226

1.55ꢃ

0.957

1.184

–

OUT1A

OUT1S

OUT2A

OUT2S

OUTꢃA

OUTꢃS

OUT4A

OUT4S

+

–

+

–

+

–

+

–

+

–

+

–

+

–

+

Q10

R11

R12

R9

R10

ꢀ11

ꢀ12

ꢀ2

Sꢂpass capacitors are integrated inside the package; ad-

ditional capacitance is optional.

The analog inputs, encode signals, and digital outputs

should not be routed next to each other. Ground fill and

grounded vias should be used as barriers to isolate these

signals from each other.

ꢀꢃ

R4

R5

R2

LAYOUT RECOMMENDATIONS

Rꢃ

Q4

ThepinassignmentsoftheLTM9012allowaflow-through

laꢂout that makes it possible to use multiple parts in a

small area when a large number of ADC channels are

required. The LTM9012 has similar laꢂout rules to other

SGA packages. The laꢂout can be implemented with 6mil

blind vias and 5mil traces. The pinout has been designed

to minimize the space required to route the analog and

digital traces. The analog and digital traces can essentiallꢂ

be routed within the width of the package. This allows

multiple packages to be located close together for high

channel count applications. Trace lengths for the analog

inputs and digital outputs should be matched as well as

possible.Table5liststhetracelengthsfortheanaloginputs

and digital outputs inside the package from the die pad to

the package pad. These should be added to the PCS trace

lengths for best matching.

Q5

–

A12

A11

A9

CH1

+

CH1

–

CH2

+

A8

CH2

–

A6

CHꢃ

+

A5

CHꢃ

–

Aꢃ

CH4

+

A2

CH4

–

P1

EIC

+

I1

EIC

P4

CS

–

ꢀ9

DCO

+

ꢀ10

ꢀ4

DCO

–

FR

+

ꢀ5

FR

Figures 7 through Figure 11 show an example of a good

PCS laꢂout.

P10

P5

PAR/SER

ꢀCK

P9

ꢀDO

Pꢃ

ꢀDꢁ

9012fa

20

For more information www.linear.com/LTM9012

LTM9012

applicaTions inForMaTion

Figure 7. Layer 1 Component Side

9012fa

21

For more information www.linear.com/LTM9012

LTM9012

applicaTions inForMaTion

Figure 8. Layer 2

9012fa

22

For more information www.linear.com/LTM9012

LTM9012

applicaTions inForMaTion

Figure 9. Layer 3

9012fa

23

For more information www.linear.com/LTM9012

LTM9012

applicaTions inForMaTion

Figure 10. Back Side

9012fa

24

For more information www.linear.com/LTM9012

LTM9012

Typical applicaTion

D D

V

D D

V

D D

V

D D

V

D D

O V

S E N S E

R E F

V

S D I

S D O

S C K

C S

S E R A P R /

C C 4

V

C C 4

V

C C 3

V

C C 3

V

C C 2

V

C C 2

V

C C 1

V

C C 1

V

•

9012fa

25

For more information www.linear.com/LTM9012

LTM9012

package DescripTion

Please refer to http://www.linear.com/product/LTM9012#packaging for the most recent package drawings.

Z

/ / b b b

Z

4 . 8 0

4 . 0 0

3 . 2 0

2 . 4 0

1 . 6 0

0 . 8 0

0 . 0 0

0 . 8 0

1 . 6 0

2 . 4 0

3 . 2 0

4 . 0 0

4 . 8 0

3 . 7 5

4 . 2 5

9012fa

26

For more information www.linear.com/LTM9012

LTM9012

revision hisTory

REV

DATE

DESCRIPTION

PAGE NUMBER

A

01/17 Corrected pin names

2, 12, 20,

25, 28

9012fa

ꢁnformation furnished bꢂ Linear Technologꢂ Corporation is believed to be accurate and reliable.

However, no responsibilitꢂ is assumed for its use. Linear Technologꢂ Corporation makes no representa-

27

For more information www.linear.com/LTM9012

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTM9012

Typical applicaTion

Single-Ended Drive with Unity Gain Example

3.3V

1.8V

LTM9012

464Ω

1%

+

–

+

–

CH1

OUT1A

0V TO 3V PULSE SIGNAL

464Ω

1%

•

SHDN1

SHDN2

SHDN3

SHDN4

PAR/SER

SDO

3V

FR–

+IN

–IN

+

1.5V REFERENCE

+

FR

–

¼LTC6254

0.1µF

DCO

+

–

DCO

V

REF

1k

1%

9012 TA02

relaTeD parTs

PART NUMBER

DESCRIPTION

COMMENTS

LTC2170-14/LTC2171-14/

LTC2172-14

14-Sit, 25Msps/40Msps/65Msps

1.8V Quad ADCs, Ultralow Power

178mW/2ꢃ4mW/ꢃ60mW, 7ꢃ.4dS ꢀIR, 85dS ꢀFDR, ꢀerial LVDꢀ Outputs,

7mm × 8mm QFI-52

LTC217ꢃ-14/LTC2174-14/

LTC2175-14

14-Sit, 80Msps/105Msps/125Msps

1.8V Quad ADCs, Ultralow Power

ꢃ76mW/450mW/558mW, 7ꢃ.4 dS ꢀIR, 88dS ꢀFDR, ꢀerial LVDꢀ Outputs,

7mm × 8mm QFI-52

LTC226ꢃ-14/LTC2264-14/

LTC2265-14

14-Sit, 25Msps/40Msps/65Msps

1.8V Dual ADCs, Ultralow Power

99mW/126mW/191mW, 7ꢃ.4dS ꢀIR, 85dS ꢀFDR, ꢀerial LVDꢀ Outputs,

6mm × 6mm QFI-40

LTC2266-14/LTC2267-14/

LTC2268-14

14-Sit, 80Msps/105Msps/125Msps

1.8V Dual ADCs, Ultralow Power

216mW/250mW/29ꢃmW, 7ꢃ.4dS ꢀIR, 85dS ꢀFDR, ꢀerial LVDꢀ Outputs,

6mm × 6mm QFI-40

LTM9009-14/LTM9010-14/

LTM9011-14

14-Sit, 80Msps/105Msps/125Msps

1.8V Octal ADCs, Ultralow Power

752mW/900mW/1116mW, 7ꢃ.1dS ꢀIR, 88dS ꢀFDR, ꢀerial LVDꢀ Outputs,

11.25mm × 9mm SGA-140

9012fa

LT 0117 REV A • PRINTED IN USA

LinearTechnology Corporation

16ꢃ0 McCarthꢂ Slvd., Milpitas, CA 950ꢃ5-7417

28

For more information www.linear.com/LTM9012

(408)4ꢃ2-1900 FAX: (408) 4ꢃ4-0507 www.linear.com/LTM9012

●

 LINEAR TECHNOLOGY CORPORATION 2012


型号：	LTM9012IY-AB#PBF
厂家：	Linear
描述：	LTM9012 - Quad 14-Bit, 125Msps ADC with Integrated Drivers; Package: BGA; Pins: 221; Temperature Range: -40°C to 85°C 转换器
文件：	总28页 (文件大小：2022K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTM9012IY-AB#PBF [Linear]

相关型号：

LTM9013

LTM9013CY-AA#PBF

LTM9013IY-AA#PBF

LTM9100CY#PBF

LTM9100HY#PBF

LTM9100IY#PBF

LTMA

LTMF

LTMG3-01-L2C-Z

LTMG3-01-L2M-Z

LTMG3-01-L2R-Z

LTMG3-01-L2Y-Z