LT1640 [Linear]
Negative Voltage Hot Swap Controller; 负电压热插拔控制器
| 型号： | LT1640 |
| 厂家： | 
Linear |
| 描述： | Negative Voltage Hot Swap Controller |
| 文件： | 总12页 (文件大小：295K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1640L/LT1640H
Negative Voltage
Hot Swap Controller
U
DESCRIPTION
FEATURES
■
Allows Safe Board Insertion and Removal
The LT®1640L/LT1640H is an 8-pin, negative voltage Hot
SwapTM controller that allows a board to be safely inserted
and removed from a live backplane. Inrush current is
limited to a programmable value by controlling the gate
voltage of an external N-channel pass transistor. The pass
transistor is turned off if the input voltage is less than the
programmable undervoltage threshold or greater than the
overvoltage threshold. A programmable electronic circuit
breaker protects the system against shorts. The PWRGD
(LTC1640L)orPWRGD(LTC1640H)signalcanbeusedto
directly enable a power module. The LT1640L is designed
for modules with a low enable input and the LT1640H for
modules with a high enable input.
from a Live –48V Backplane
■
Operates from –10V to –80V
■
Programmable Inrush Current
■
Programmable Electronic Circuit Breaker
■
Programmable Overvoltage Protection
■
Programmable Undervoltage Lockout
■
Power Good Control Output
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APPLICATIONS
■
Central Office Switching
■
–48V Distributed Power Systems
■
Negative Power Supply Control
The LT1640L/LT1640H is available in 8-pin PDIP and SO
packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
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TYPICAL APPLICATION
Input Inrush Current
GND
8
R4
562k
1%
V
DD
CONTACT
BOUNCE
3
2
UV = 37V
OV = 71V
UV
OV
R5
9.09k
1%
1
LT1640L
PWRGD
R6
10k
1%
V
SENSE
5
GATE
6
DRAIN
7
EE
4
R2
C1
33nF
24V
R3
10k
5%
10Ω
C2
3.3nF
100V
R1
0.02Ω
5%
5%
–48V
Q1
2
IRF530
ON/OFF
1
9
8
+
–
+
+
5V
V
V
V
IN
IN
OUT
SENSE
C3
0.1µF
100V
+
C4
+
C5
7
6
5
100µF
TRIM
100µF
16V
100V
–
SENSE
4
–
V
OUT
1640 F07b
1640 TA01
LUCENT
JW050A1-E
1
LT1640L/LT1640H
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ABSOLUTE MAXIMUM RATINGS
(Note 1), All Voltages Referred to VEE
Supply Voltage (VDD – VEE) .................... –0.3V to 100V
DRAIN, PWRGD, PWRGD Pins ............... –0.3V to 100V
SENSE, GATE Pins.................................... –0.3V to 20V
UV, OV Pins .............................................. –0.3V to 60V
Maximum Junction Temperature ......................... 125°C
Operating Temperature Range
LT1640LC/LT1640HC ............................. 0°C to 70°C
LT1640LI/LT1640HI .......................... –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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PACKAGE RDER I FOR ATIO
ORDER PART
ORDER PART
NUMBER
NUMBER
TOP VIEW
TOP VIEW
PWRGD
OV
1
2
3
4
8
7
6
5
V
DD
PWRGD
OV
1
2
3
4
8
7
6
5
V
DD
LT1640LCN8
LT1640LCS8
LT1640LIN8
LT1640LIS8
LT1640HCN8
LT1640HCS8
LT1640HIN8
LT1640HIS8
DRAIN
GATE
DRAIN
GATE
UV
UV
V
SENSE
V
SENSE
EE
EE
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
8-LEAD PLASTIC SO
S8 PART MARKING
S8 PART MARKING
TJMAX = 125°C, θJA = 120°C/W (N8)
TJMAX = 125°C, θJA = 150°C/W (S8)
TJMAX = 125°C, θJA = 120°C/W (N8)
JMAX = 125°C, θJA = 150°C/W (S8)
1640L
1640LI
T
1640H
1640HI
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS (Note 2), VDD = 48V, VEE = 0V, TA = 25°C unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC
V
Supply Voltage
●
●
●
●
10
80
5
V
mA
mV
µA
DD
CB
I
Supply Current
UV = 3V, OV = V , SENSE = V
EE
1.3
50
DD
EE
V
Circuit Breaker Trip Voltage
GATE Pin Pull-Up Current
GATE Pin Pull-Down Current
SENSE Pin Current
V
CB
= (V
– V )
EE
40
–30
24
60
–60
70
SENSE
I
I
I
Gate Drive On, V
= V
EE
–45
50
PU
GATE
Any Fault Condition
= 50mV
mA
µA
PD
V
SENSE
–20
SENSE
∆V
GATE
External Gate Drive
(V
GATE
(V
GATE
– V ), 15V ≤ V ≤ 80V
●
●
10
6
13.5
8
18
15
V
V
EE
DD
– V ), 10V ≤ V < 15V
EE
DD
V
V
V
UV Pin High Threshold Voltage
UV Pin Low Threshold Voltage
UV Pin Hysteresis
UV Low to High Transition
UV High to Low Transition
●
●
1.213
1.198
1.243
1.223
20
1.272
1.247
V
V
UVH
UVL
UVHY
INUV
mV
µA
V
I
UV Pin Input Current
V
UV
= V
●
●
●
–0.02
1.223
1.203
20
–0.5
1.247
1.232
EE
V
V
V
OV Pin High Threshold Voltage
OV Pin Low Threshold Voltage
OV Pin Hysteresis
OV Low to High Transition
OV High to Low Transition
1.198
1.165
OVH
OVL
V
mV
µA
OVHY
INOV
I
OV Pin Input Current
V
OV
= V
●
–0.03
–0.5
EE
2
LT1640L/LT1640H
ELECTRICAL CHARACTERISTICS VDD = 48V, VEE = 0V, TA = 25°C unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
V
Power Good Threshold
V
– V , High to Low Transition
1.1
1.4
2.0
V
V
V
PG
DRAIN
EE
Power Good Threshold Hysteresis
Output Low Voltage
0.4
PGHY
OL
PWRGD (LT1640L), I
(V
= 1mA,
●
●
0.48
0.8
OUT
– V ) < V
DRAIN
EE PG
R
Power Good Output Impedance
PWRGD (LT1460H), (V
– V ) < V
PG
2
2
6.5
kΩ
OUT
DRAIN
EE
AC
t
t
t
t
t
t
OV High to GATE Low
UV Low to GATE Low
OV Low to GATE High
UV High to GATE High
SENSE High to Gate Low
Figures 1, 2
Figures 1, 3
Figures 1, 2
Figures 1, 3
Figures 1, 4
1.7
1.5
5.5
6.5
3
µs
µs
µs
µs
µs
PHLOV
PHLUV
PLHOV
PLHUV
PHLSENSE
PHLPG
4
DRAIN Low to PWRGD Low
DRAIN Low to (PWRGD – DRAIN) High
(LT1640L) Figures 1, 5
(LT1640H) Figures 1, 5
0.5
0.5
µs
µs
t
DRAIN High to PWRGD High
DRAIN High to (PWRGD – DRAIN) Low
(LT1640L) Figures 1, 5
(LT1640H) Figures 1, 5
0.5
0.5
µs
µs
PLHPG
The
●
denotes specifications which apply over the full operating
Note 2: All currents into device pins are positive; all currents out of device
temperature range.
pins are negative. All voltages are referenced to V unless otherwise
EE
specified.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
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TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Supply Voltage
Supply Current vs Temperature
Gate Voltage vs Supply Voltage
1.6
1.5
1.4
1.3
1.2
1.1
1.0
15
14
13
12
11
10
9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
0
8
7
6
20
40
SUPPLY VOLTAGE (V)
80
–50 –25
0
25
50
75
100
0
100
60
0
80
100
20
40
60
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
1640 G02
1640 G01
1640 G03
3
LT1640L/LT1640H
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Circuit Breaker Trip Voltage
Gate Pull-Up Current
vs Temperature
Gate Voltage vs Temperature
vs Temperature
48
47
46
45
44
43
42
41
40
15.0
14.5
55
54
53
14.0
13.5
52
51
50
49
13.0
12.5
12.0
48
–50 –25
0
25
50
75
100
–50
–25
0
25
50
75
100
–50
0
25
50
75
100
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1640 G04
1640 G06
1640 G05
Gate Pull-Down Current
vs Temperature
PWRGD Output Impedance
vs Temperature (LT1640H)
PWRGD Output Low Voltage
vs Temperature (LT1640L)
55
52
49
0.5
0.4
0.3
0.2
0.1
0
8
7
6
5
46
43
40
4
3
2
–50 –25
0
25
50
75
100
–50 –25
25
50
75
100
–50 –25
0
25
50
75
100
0
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1640 G07
1640 G08
1640 G09
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PIN FUNCTIONS
PWRGD/PWRGD(Pin1):PowerGoodOutputPin.Thispin
will toggle when VDRAIN is within VPG of VEE. This pin can
be connected directly to the enable pin of a power module.
pin which pulls the module’s enable pin low, forcing it off.
When VDRAIN drops below VPG, the PWRGD sink current
is turned off and a 5k resistor is connected between
PWRGD and DRAIN, allowing the module’s pull-up cur-
rent to pull the enable pin high and turn on the module.
When the DRAIN pin of the LT1640L is above VEE by more
thanVPG,thePWRGDpinwillbehighimpedance,allowing
the pull-up current of the module’s enable pin to pull the
pin high and turn the module off. When VDRAIN drops
below VPG, the PWRGD pin sinks current to VEE, pulling
the enable pin low and turning on the module.
OV (Pin 2): Analog Overvoltage Input. When OV is pulled
above the 1.223V low to high threshold, an overvoltage
conditionisdetectedandtheGATEpinwillbeimmediately
pulled low. The GATE pin will remain low until OV drops
below the 1.203V high to low threshold.
When the DRAIN pin of the LT1640H is above VEE by more
than VPG, the PWRGD pin will sink current to the DRAIN
4
LT1640L/LT1640H
U
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PIN FUNCTIONS
UV (Pin 3): Analog Undervoltage Input. When UV is If the circuit breaker trip current is set to twice the normal
pulled below the 1.223V high to low threshold, an under- operating current, only 25mV is dropped across the
voltage condition is detected and the GATE pin will be sense resistor during normal operation. To disable the
immediately pulled low. The GATE pin will remain low circuit breaker, VEE and SENSE can be shorted together.
until UV rises above the 1.243 low to high threshold.
GATE (Pin 6): Gate Drive Output for the External
The UV pin is also used to reset the electronic circuit N-Channel. The GATE pin will go high when the following
breaker. If the UV pin is cycled low and high following the start-upconditionsaremet:theUVpinishigh, theOVpin
trip of the circuit breaker, the circuit breaker is reset and is low and (VSENSE – VEE) < 50mV. The GATE pin is pulled
a normal power-up sequence will occur.
high by a 45µA current source and pulled low with a
50mA current source.
VEE (Pin 4): Negative Supply Voltage Input. Connect to
the lower potential of the power supply.
DRAIN (Pin 7): Analog Drain Sense Input. Connect this
pin to the drain of the external N-channel and the V– pin
of the power module. When the DRAIN pin is below VPG,
the PWRGD or PWRGD pin will toggle.
SENSE (Pin 5): Circuit Breaker Sense Pin. With a sense
resistor placed in the supply path between VEE and
SENSE, the circuit breaker will trip when the voltage
across the resistor exceeds 50mV. Noise spikes of less VDD (Pin 8): Positive Supply Voltage Input. Connect this
than 2µs are filtered out and will not trip the circuit pin to the higher potential of the power supply inputs and
breaker.
the V+ pin of the power module. The input supply voltage
ranges from 10V to 80V.
W
BLOCK DIAGRA
V
DD
–
+
UV
V
CC
V
AND
CC
REFERENCE
GENERATOR
REF
OUTPUT
DRIVE
PWRGD/PWRGD
REF
–
+
LOGIC
AND
GATE DRIVE
50mV
OV
–
+
+
–
+
–
+
V
PG
–
V
EE
1640 BD
V
EE
SENSE
GATE
DRAIN
5
LT1640L/LT1640H
TEST CIRCUIT
R
5k
+
V
PWRGD/PWRGD
OV
V
DD
5V
+
–
48V
DRAIN
V
OV
V
V
DRAIN
LT1640L/LT1460H
UV
GATE
C
V
UV
0.033µF
V
SENSE
EE
SENSE
1640 F01
Figure 1. Test Circuit
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TIMING DIAGRAMS
2V
1.223V
OV
50mV
1.203V
SENSE
0V
t
PHLSENSE
1V
t
t
PLHOV
PHLOV
GATE
GATE
1V
1V
1640 F02
1640 F04
Figure 2. OV to GATE Timing
Figure 4. SENSE to GATE Timing
1.8V
2V
0V
1.4V
1.223V
1.243V
DRAIN
PWRGD
DRAIN
UV
V
EE
t
t
PLHPG
PHLPG
1V
t
t
PHLUV
PLHUV
1V
1V
GATE
V
EE
1V
1640 F03
1.8V
0V
1.4V
Figure 3. UV to GATE Timing
t
t
PLHPG
1V
PHLPG
PWRGD
1V
1640 F05
V
– V
= 0V
DRAIN
PWRGD
Figure 5. DRAIN to PWRGD/PWRGD Timing
6
LT1640L/LT1640H
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APPLICATIONS INFORMATION
Hot Circuit Insertion
IINRUSH = (45µA • CL)/C2
Whencircuitboardsareinsertedintoalive–48Vbackplane,
the bypass capacitors at the input of the board’s power
module or switching power supply can draw huge tran-
sient currents as they charge up. The transient currents
can cause permanent damage to the board’s components
and cause glitches on the system power supply.
where CL is the total load capacitance.
Capacitor C1 and resistor R3 prevent Q1 from momen-
tarily turning on when the power pins first make contact.
Without C1 and R3, capacitor C2 would pull the gate of Q1
uptoavoltageroughlyequaltoVEE •C2/CG(Q1)beforethe
LT1640 could power up and actively pull the gate low. By
placing capacitor C1 parallel with the gate capacitance of
Q1 and isolating them from C2 using resistor R3 the
problem is solved. The value of C1 should be 10 times the
value of C and R3 • C1 ≈ 300µs.
The LT1640 is designed to turn on a board’s supply
voltage in a controlled manner, allowing the board to be
safely inserted or removed from a live backplane. The chip
also provides undervoltage, overvoltage and overcurrent
protection while keeping the power module off until its
input voltage is stable and within tolerance.
Power Supply Ramping
The input to the power module on a board is controlled by
placing an external N-channel pass transistor (Q1) in the
power path (Figure 6a, all waveforms are with respect to
the VEE pin of the LT1640). R1 provides current fault
detection and R2 prevents high frequency oscillations.
Resistors R4, R5 and R6 provide undervoltage and over-
voltage sensing. By ramping the gate of Q1 up at a slow
rate, the surge current charging load capacitors C3 and C4
can be limited to a safe value when the board makes
connection.
Resistor R3 and capacitor C2 act as a feedback network to
accurately control the inrush current. The inrush current
can be calculated with the following equation:
1640 F07b
Figure 6b. Inrush Control Waveforms
GND
VICOR
8
R4
562k
1%
VI-J3D-CY
C3
0.1µF
100V
C4
100µF
100V
+
V
+
+
–
DD
5V
V
V
IN
OUT
3
2
UV = 37V
OV = 71V
UV
OV
+
C5
R5
9.09k
1%
1
LT1640H
PWRGD
GATE IN
–
100µF
16V
V
V
R6
10k
1%
IN
OUT
V
EE
SENSE
5
GATE
DRAIN
7
4
6
R2
C1
0.033µF
24V
R3
10k
5%
10Ω
C2
3.3nF
100V
R1
0.02Ω
5%
5%
1640 F06a
–48V
Q1
IRF530
Figure 6a. Inrush Control Circuitry
7
LT1640L/LT1640H
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APPLICATIONS INFORMATION
The waveforms are shown in Figure 6b. When the power
pins make contact, they bounce several times. While the
contactsarebouncing,theLT1640sensesanundervoltage
condition and the GATE is immediately pulled low when
the power pins are disconnected.
GATE pin will remain low until the circuit breaker is reset
by pulling UV low, then high or cycling power to the part.
If more than 3µs deglitching time is needed to reject
current noise, an external resistor and capacitor can be
added to the sense circuit as shown in Figure 8. R7 and C3
act as a lowpass filter that will slow down the SENSE pin
voltage from rising too fast. Since the SENSE pin will
source current, typically 20µA, there will be a voltage drop
on R7. This voltage will be counted into the circuit breaker
trip voltage just as the voltage across the sense resistor.
A small resistor is recommended for R7. A 100Ω for R7
willcausea2mVerror.Thefollowingequationcanbeused
to estimate the delay time at the SENSE pin:
Once the power pins stop bouncing, the GATE pin starts to
ramp up. When Q1 turns on, the GATE voltage is held
constant by the feedback network of R3 and C2. When the
DRAIN voltage has finished ramping, the GATE pin then
ramps to its final value.
Electronic Circuit Breaker
The LT1640 features an electronic circuit breaker function
that protects against short circuits or excessive supply
currents. By placing a sense resistor between the VEE and
SENSEpin, thecircuitbreakerwillbetrippedwheneverthe
voltage across the sense resistor is greater than 50mV for
more than 3µs as shown in Figure 7.
V(t)– V(tO)
t = –R •C •In 1–
V – V(tO)
i
Where V(t) is the circuit breaker trip voltage, typically
50mV. V(tO) is the voltage drop across the sense resistor
before the short or over current condition occurs. Vi is the
voltage across the sense resistor when the short current
or over current is applied on it.
Example: A system has a 1A current load and a 0.02Ω
sense resistor is used. An extended delay circuit needs to
be designed for a 50µs delay time after the load jumps to
5A. In this case:
V(t) = 50mV
V(tO) = 20mV
Vi = 5A • 0.02Ω = 100mV
If we choose R = 100Ω, we will get C = 1µF.
GND
8
R4
562k
1%
V
DD
3
2
Figure 7. Short-Circuit Protection Waveforms
UV
OV
UV = 37V
OV = 71V
R5
9.09k
1%
1
PWRGD/
PWRGD
LT1640L/LT1640H
+
C
L
Note that the circuit breaker threshold should be set
sufficiently high to account for the sum of the load current
andtheinrushcurrent.Iftheloadcurrentcanbecontrolled
bythePWRGD/PWRGDpin(asinFigure6a),thethreshold
can be set lower, since it will never need to accommodate
inrush current and load current simultaneously.
100µF
R6
10k
1%
100V
V
SENSE
5
GATE
6
DRAIN
7
EE
C3
R1
4
R2
10Ω
5%
C1
R3
10k
5%
C2
0.033µF
24V
3.3nF
0.02Ω
R7
100V
5%
–48V
1640 F08
Q1
IRF530
Whenthecircuitbreakertrips,theGATEpinisimmediately
pulled to VEE and the external N-channel turns off. The
Figure 8. Extending the Short-Circuit Protection Delay
8
LT1640L/LT1640H
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APPLICATIONS INFORMATION
Under some conditions, a short circuit at the output can
cause the input supply to dip below the UV threshold,
resetting the circuit breaker immediately.
the GATE pin is pulled high and Q3 is turned on, pulling
node 2 to VEE. Resistor R8 turns off Q2. When a short
occurs, the GATE pin is pulled low and Q3 turns off. Node
2 starts to charge C4 and Q2 turns on, pulling the UV pin
low and resetting the circuit breaker. As soon as C4 is fully
charged, R8 turns off Q2, UV goes high and the GATE
starts to ramp up. Q3 turns back on and quickly pulls node
2 back to VEE. Diode D1 clamps node 3 one diode drop
below VEE. The duty cycle is set to 10% to prevent Q1 from
overheating.
The LT1640 then cycles on and off repeatedly until the
short is removed. This can be minimized by adding a
deglitching delay to the UV pin with a capacitor from UV to
VEE. This capacitor forms an RC time constant with the
resistorsatUV,allowingtheinputsupplytorecoverbefore
the UV pin resets the circuit breaker.
A circuit that automatically resets the circuit breaker after
a current fault is shown in Figure 9.
Undervoltage and Overvoltage Detection
Transistors Q2 and Q3 along with R7, R8, C4 and D1 form
a programmable one-shot circuit. Before a short occurs,
The UV (Pin 3) and OV (Pin 2) pins can be used to detect
undervoltage and overvoltage conditions at the power
GND
8
R7
1M
5%
R4
562k
1%
V
DD
2
3
2
UV
OV
C4
R5
9.09k
1%
1
1µF
LT1640L
PWRGD
C3
100µF
100V
+
100V
R6
10k
1%
V
SENSE
5
GATE
DRAIN
7
EE
Q2
3
4
6
2N2222
Q3
ZVN3310
R2
C1
R3
10k
5%
10Ω
C2
3.3nF
100V
0.033µF
24V
R8
510k
5%
R1
5%
D1
1N4148
0.02Ω
5%
–48V
1640 F09a
Q1
IRF530
1640 F09b
Figure 9. Automatic Restart After Current Fault
9
LT1640L/LT1640H
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APPLICATIONS INFORMATION
supply input. The UV and OV pins are internally connected
to analog comparators with 20mV of hysteresis. When the
UV pin falls below its threshold or the OV pin rises above
its threshold, the GATE pin is immediately pulled low. The
GATE pin will be held low until UV is high and OV is low.
With R4 = 506k, R5 = 8.87k and VOVH = 1.223V, the
overvoltage threshold will be 71V.
GND
8
R4
V
DD
3
2
R4 + R5+ R6
R5 + R6
V
V
= 1.223
= 1.223
UV
OV
UV
OV
(
(
)
)
The undervoltage and overvoltage trip voltages can be
programmed using a three resistor divider as shown in
Figure 10a. With R4 = 562k, R5 = 9.09k and R6 = 10K, the
undervoltage threshold is set to 37V and the overvoltage
threshold is set to 71V. The resistor divider will also gain
up the 20mV hysteresis at the UV pin and OV pin to 0.6V
and 1.2V at the input respectively.
LT1640L
LT1640H
R5
R6
R4 + R5+ R6
R6
V
EE
4
–48V
1640 F10a
Figure 10a. Undervoltage and Overvoltage Sensing
More hysteresis can be added to the UV threshold by
connecting resistor R3 between the UV pin and the GATE
pin as shown in Figure 10b.
GND
8
R4
506k
1%
V
DD
2
3
OV
UV = 37.6V
Thenewthresholdvoltagewhentheinputmovesfromlow
to high is:
R1
562k
1%
LT1640L/LT1640H
UV = 43V
OV = 71V
UV
R5
R2
R3
V
SENSE
GATE
6
EE
8.87k 16.9k 1.62M
R2 •R3 +R1•R3 +R1•R2
V
UV,LH = V
1%
1%
1%
UVH
4
5
R2 •R3
R6
C1
10Ω
0.033µF
R1
0.02Ω
5%
5%
24V
where VUVH is typically 1.243V.
–48V
The new threshold voltage when the input moves from
high to low is:
1640 F10b
Q1
IRF530
Figure 10b. Programmable Hysteresis
for Undervoltage Detection
R2 •R3 +R1•R3 +R1•R2
R1
R3
V
UV,HL = V
– VGATE
•
UVL
R2 •R3
PWRGD/PWRGD Output
where VUVL is typically 1.223V.
The new hysteresis value will be:
The PWRGD/PWRGD output can be used to directly en-
able a power module when the input voltage to the module
is within tolerance. The LT1640L has a PWRGD output for
modules with an active low enable input, and the LT1640H
has a PWRGD output for modules with an active high
enable input.
R2 •R3 +R1•R3 +R1•R2
R1
R3
V
= V
+ VGATE
•
HYS
UVHY
R2 •R3
With R1 = 562k, R2 = 16.9k and R3 = 1.62M, VGATE
=
135mV and VUVHY = 20mV, the undervoltage threshold
will be 43V (from low to high) and 37.6V (from high to
low). The hysteresis is 5.4V. A separate resistor divider
should be used to set the overvoltage threshold given by:
When the DRAIN voltage of the LT1640H is high with
respect to VEE (Figure 11), the internal transistor Q3 is
turned off and R7 and Q2 clamp the PWRGD pin one diode
drop (≈0.7V) above the DRAIN pin. Transistor Q2 sinks
the module’s pull-up current and the module turns off.
R4 + R5
VOV = VOVH
WhentheDRAINvoltagedropsbelowVPG, Q3willturnon,
shorting the bottom of R7 to VEE and turning Q2 off. The
R5
10
LT1640L/LT1640H
U
W U U
APPLICATIONS INFORMATION
ACTIVE LOW
ENABLE MODULE
ACTIVE LOW
ENABLE MODULE
+
+
+
+
GND
V
V
OUT
GND
V
IN
V
OUT
IN
8
8
V
LT1640H
UV
V
DD
LT1640L
UV
DD
PWRGD
Q2
1
7
PWRGD
Q2
1
7
R4
R4
R7
5k
+
ON/OFF
+
ON/OFF
3
2
3
2
+
–
C3
C3
+
–
+
V
+
PG
R5
R6
R5
R6
Q3
EE
V
–
V
EE
PG
–
OV
OV
DRAIN
–
–
V
DRAIN
V
IN
V
OUT
–
–
V
V
OUT
IN
V
4
SENSE
5
GATE
6
V
SENSE
5
GATE
6
EE
EE
4
R3
R3
C2
C1
C2
C1
R2
R2
R1
R1
1640 F11
1640 F12
–48V
–48V
Q1
Q1
Figure 11. Active High Enable Module
Figure 12. Active Low Enable Module
pull-up current in the module then flows through R7,
pulling the PWRGD pin high and enabling the module.
Gate Pin Voltage Regulation
When the supply voltage to the chip is more than 15.5V,
theGATEpinvoltageisregulatedat13.5VaboveVEE. Ifthe
supply voltage is less than 15.5V, the GATE voltage will be
about 2V below the supply voltage. At the minimum 10V
supplyvoltage,thegatevoltageisguaranteedtobegreater
than 6V. The gate voltage will be no greater than 18V for
supply voltages up to 80V.
When the DRAIN voltage of the LT1640L is high with
respect to VEE, the internal pull-down transistor Q2 is off
and the PWRGD pin is in a high impedance state (Figure
12). The PWRGD pin will be pulled high by the module’s
internal pull-up current source, turning the module off.
When the DRAIN voltage drops below VPG, Q2 will turn on
and the PWRGD pin will pull low, enabling the module.
The PWRGD signal can also be used to turn on an LED or
optoisolator to indicate that the power is good as shown in
Figure 13.
GND
R7
51k
PWRGD
5%
8
R4
562k
1%
+
C3
V
DD
100µF
3
2
100V
UV
OV
4N25
R5
9.09k
1%
1
LT1640L
PWRGD
R6
10k
1%
V
SENSE
5
GATE
DRAIN
7
EE
4
6
R2
C1
0.033µF
24V
R3
10k
5%
10Ω
C2
3.3nF
100V
R1
0.02Ω
5%
5%
–48V
1640 F13
Q1
IRF530
Figure 13. Using PWRGD to Drive an Optoisolator
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
11
LT1640L/LT1640H
U
TYPICAL APPLICATION
Using an EMI Filter Module
using the Lucent FLTR100V10 filter module is shown in
Figure 14. When using a filter, a capacitor (C6) is required
acrosstheenablepinandVIN– pinofthemoduletoprevent
noise from momentarily disabling the module.
Many applications place an EMI filter module in the power
path to prevent switching noise of the module from being
injected back onto the power supply. A typical application
LUCENT
JW050A1-E
GND
1
2
9
8
7
8
1
+
+
+
R4
562k
1%
5V
V
V
IN
OUT
SENSE
PWRGD
V
DD
+
C7
7
6
3
2
+
+
V
V
ON/OFF
TRIM
UV
DRAIN
100µF
16V
IN
OUT
C2
3.3nF
100V
R5
9.09k
1%
C3
0.1µF
100V
C4
0.1µF
100V
C5
100µF
100V
C6
0.1µF
100V
+
6
5
LT1640L
LUCENT
FLTR100V10
–
SENSE
R3
10k
5%
OV
V
GATE
4
–
–
–
–
V
V
V
V
R6
10k
1%
IN
OUT
CASE
OUT
IN
SENSE
5
EE
CASE
R2
10Ω
5%
C1
0.033µF
24V
4
3
R1
1640 F14
0.02Ω
5%
–48V
Q1
IRF530
Figure 14. Typical Application Using a Filter Module
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.400*
(10.160)
MAX
0.189 – 0.197*
(4.801 – 5.004)
7
5
8
6
8
7
6
5
4
0.255 ± 0.015*
(6.477 ± 0.381)
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
2
3
0.130 ± 0.005
0.300 – 0.325
0.045 – 0.065
1
0.053 – 0.069
(1.346 – 1.752)
2
3
4
(3.302 ± 0.127)
(1.143 – 1.651)
(7.620 – 8.255)
0.010 – 0.020
(0.254 – 0.508)
× 45°
0.004 – 0.010
(0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254)
0.065
(1.651)
TYP
0°– 8° TYP
0.009 – 0.015
0.125
(3.175)
MIN
(0.229 – 0.381)
0.016 – 0.050
0.406 – 1.270
0.050
0.020
0.014 – 0.019
(0.355 – 0.483)
+0.035
(1.270)
TYP
SO8 0996
(0.508)
MIN
0.325
–0.015
0.100 ± 0.010
(2.540 ± 0.254)
0.018 ± 0.003
(0.457 ± 0.076)
+0.889
8.255
*
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
N8 1197
(
)
–0.381
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
RELATED PARTS
PART NUMBER
LTC®1421
LTC1422
DESCRIPTION
COMMENTS
Dual Channel, Hot Swap Controller
Operates from 3V to 12V
High Side Drive, Hot Swap Controller in SO-8
PCI Hot Swap Controller
System Reset Output with Programmable Delay
3.3V, 5V, 12V, –12V Supplies for PCI Bus
LTC1643
1640lhf LT/TP 1198 4K • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
12
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 1998
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