LT1801 [Linear]
Single/Dual/Quad 60MHz, 20V/us, Low Power, Rail-to-Rail Input and Output Precision Op Amps; 单/双/四路为60MHz , 20V / us的,低功耗,轨到轨输入和输出精密运算放大器型号: | LT1801 |
厂家: | Linear |
描述: | Single/Dual/Quad 60MHz, 20V/us, Low Power, Rail-to-Rail Input and Output Precision Op Amps |
文件: | 总20页 (文件大小:280K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LT6220/LT6221/LT6222
Single/Dual/Quad 60MHz,
20V/µs, Low Power, Rail-to-Rail Input
and Output Precision Op Amps
U
FEATURES
DESCRIPTIO
The LT®6220/LT6221/LT6222 are single/dual/quad, low
■
Gain Bandwidth Product: 60MHz
■
Input Common Mode Range Includes Both Rails
Output Swings Rail-to-Rail
power, high speed rail-to-rail input and output operational
amplifiers with excellent DC performance. The LT6220/
LT6221/LT6222 feature reduced supply current, lower
input offset voltage, lower input bias current and higher
DC gain than other devices with comparable bandwidth.
■
■
■
■
■
■
■
■
■
■
■
■
■
Low Quiescent Current: 1mA Max
Input Offset Voltage: 350µV Max
Input Bias Current: 150nA Max
Wide Supply Range: 2.2V to 12.6V
Large Output Current: 50mA Typ
Low Voltage Noise: 10nV√Hz Typ
Slew Rate: 20V/µs Typ
Typically, the LT6220/LT6221/LT6222 have an input off-
setvoltageoflessthan100µV, aninputbiascurrentofless
than 15nA and an open-loop gain of 100V/mV. The parts
have an input range that includes both supply rails and an
outputthatswingswithin10mVofeithersupplyrailtomaxi-
mize the signal dynamic range in low supply applications.
Common Mode Rejection: 102dB Typ
Power Supply Rejection: 105dB Typ
Open-Loop Gain: 100V/mV Typ
Operating Temperature Range: – 40°C to 85°C
Single in the 8-Pin SO and 5-Pin Low Profile
(1mm) ThinSOTTM Packages
The LT6220/LT6221/LT6222 maintain performance for
supplies from 2.2V to 12.6V and are specified at 3V, 5V
and ±5V supplies. The inputs can be driven beyond the
supplies without damage or phase reversal of the output.
■
■
Dual in the 8-Pin SO and (3mm x 3mm) DFN
Packages
The LT6220 is housed in the 8-pin SO package with the
standard op amp pinout as well as the 5-pin SOT-23
package. The LT6221 is available in 8-pin SO and DFN
(3mm × 3mm low profile dual fine pitch leadless) pack-
ages with the standard op amp pinout. The LT6222 fea-
tures the standard quad op amp configuration and is
availableinthe16-PinSSOPpackage.TheLT6220/LT6221/
LT6222 can be used as plug-in replacements for many op
amps to improve input/output range and performance.
Quad in the 16-PUin SSOP Package
APPLICATIO S
■
Low Voltage, High Frequency Signal Processing
■
Driving A/D Converters
■
Rail-to-Rail Buffer Amplifiers
■
Active Filters
■
Video Amplifiers
, LTC and LT are registered trademarks of Linear Technology Corporation.
ThinSOT is a trademark of Linear Technology Corporation.
■
Fast Current Sensing Amplifiers
U
TYPICAL APPLICATIO
VOS Distribution, VCM = 0V
(S8, PNP Stage)
Stepped-Gain Photodiode Amplifier
50
V
V
= 5V, 0V
CM
S
+
V
S
45
40
35
30
25
20
15
10
5
= 0V
10k
30pF
3.24k
+
V
S
1pF
100k
+
V
S
I
PD
–
33k
LT1634-1.25
–
V
S
PHOTODIODE
~4pF
LT6220
V
OUT
0
–250
–150
–50
0
50
150
250
+
V
S
= ±1.5V TO ±5V
INPUT OFFSET VOLTAGE (µV)
–
622012 TA01
V
S
622012 G01
sn622012 622012fs
1
LT6220/LT6221/LT6222
W W U W
ABSOLUTE AXI U RATI GS (Note 1)
+
Total Supply Voltage (VS– to VS ) ......................... 12.6V
Maximum Junction Temperature .......................... 150°C
(DD Package) ................................................... 125°C
Storage Temperature .............................–65°C to 150°C
(DD Package) ....................................–65°C to 125°C
Lead Temperature (Soldering, 10 sec.)................. 300°C
Input Voltage (Note 2) ..............................................±VS
Input Current (Note 2) ........................................ ±10mA
Output Short Circuit Duration (Note 3) ............ Indefinite
Operating Temperature Range (Note 4) ...–40°C to 85°C
Specified Temperature Range (Note 5)....–40°C to 85°C
U
W
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
ORDER PART
TOP VIEW
NUMBER
TOP VIEW
+
OUT A
–IN A
+IN A
1
2
3
4
V
S
8
7
6
5
+
V
1
2
5 V
LT6220CS5
LT6220IS5
LT6220CS8
LT6220IS8
OUT
–
S
OUT B
–IN B
+IN B
V
A
S
+
–
+IN 3
4 –IN
B
–
V
S
S8 PART
MARKING
S5 PART*
MARKING
S5 PACKAGE
5-LEAD PLASTIC TSOT-23
S8 PACKAGE
8-LEAD PLASTIC SO
T
JMAX = 150°C, θJA = 250°C/W (NOTE 10)
6220
6220I
LTAFP
TJMAX = 150°C, θJA = 190°C/W
TOP VIEW
TOP VIEW
OUT A
OUT D
16
1
2
3
4
5
6
7
8
TOP VIEW
–IN A
+IN A
–IN D
15
+
OUT A
–IN A
+IN A
1
2
3
4
8
7
6
5
V
S
A
D
C
NC
1
2
3
4
NC
8
7
6
5
+IN D
14
OUT B
–IN B
+IN B
+
A
–
+
–IN
V
V
+
V
–
S
13
V
S
S
B
+IN
–
–
V
OUT
+IN B
–IN B
OUT B
NC
12 +IN C
–IN C
S
B
V
S
NC
11
10 OUT C
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
S8 PACKAGE
8-LEAD PLASTIC SO
9
NC
TJMAX = 125°C, θJA = 160°C/W (NOTE 10)
EXPOSED PAD INTERNALLY CONNECTED TO VS
(PCB CONNECTION OPTIONAL)
TJMAX = 150°C, θJA = 190°C/W
–
GN PACKAGE
16-LEAD NARROW PLASTIC SSOP
TJMAX = 150°C, θJA = 135°C/W
ORDER PART
NUMBER
DD PART*
MARKING
ORDER PART
NUMBER
S8 PART
MARKING
ORDER PART
NUMBER
SSOP PART
MARKING
LT6221CDD
LT6221IDD
LADZ
LT6221CS8
LT6221IS8
6221
6221I
LT6222CGN
LT6222IGN
6222
6222I
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grades are identified by a label on the shipping container.
sn622012 622012fs
2
LT6220/LT6221/LT6222
ELECTRICAL CHARACTERISTICS
TA = 25°C, VS = 5V, 0V; VS = 3V, 0V; VCM = VOUT = half supply, unless otherwise noted
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Offset Voltage
V
V
V
V
V
= 0V
70
150
200
0.5
0.5
350
700
850
2.5
3
µV
µV
µV
mV
mV
OS
CM
CM
CM
CM
CM
= 0V (DD Package)
= 0V (S5 Package)
= V
S
= V (S5 Package)
S
∆V
OS
Input Offset Voltage Shift
V = 5V, V = 0V to 3.5V
30
15
195
120
µV
µV
S
CM
V = 3V, V = 0V to 1.5V
S
CM
Input Offset Voltage Match (Channel-to-Channel)
(Note 9)
V
V
= 0V
100
150
600
1100
µV
µV
CM
CM
= 0V (DD Package)
I
I
Input Bias Current
V
V
= 1V
15
250
150
600
nA
nA
B
CM
CM
= V
S
Input Bias Current Match (Channel-to-Channel)
(Note 9)
V
V
= 1V
15
20
175
250
nA
nA
CM
CM
= V
S
Input Offset Current
V
V
= 1V
15
15
100
100
nA
nA
OS
CM
CM
= V
S
Input Noise Voltage
0.1Hz to 10Hz
f = 10kHz
0.5
10
0.8
2
µV
P-P
e
Input Noise Voltage Density
Input Noise Current Density
Input Capacitance
nV/√Hz
pA/√Hz
pF
n
i
f = 10kHz
n
C
A
IN
Large Signal Voltage Gain
V = 5V, V = 0.5V to 4.5V, R = 1k at V /2
35
3.5
30
100
10
90
V/mV
V/mV
V/mV
VOL
S
O
L
S
V = 5V, V = 1V to 4V, R = 100Ω at V /2
S
O
L
S
V = 3V, V = 0.5V to 2.5V, R = 1k at V /2
S
O
L
S
CMRR
PSRR
Common Mode Rejection Ratio
V = 5V, V = 0V to 3.5V
85
82
102
102
dB
dB
S
CM
V = 3V, V = 0V to 1.5V
S
CM
CMRR Match (Channel-to-Channel) (Note 9)
V = 5V, V = 0V to 3.5V
79
76
100
100
dB
dB
S
CM
V = 3V, V = 0V to 1.5V
S
CM
Input Common Mode Range
0
V
V
dB
dB
V
S
Power Supply Rejection Ratio
V = 2.5V to 10V, V = 0V
84
79
105
105
2.2
S
CM
PSRR Match (Channel-to-Channel) (Note 9)
Minimum Supply Voltage (Note 6)
Output Voltage Swing LOW (Note 7)
2.5
V
V
No Load
5
100
325
40
200
650
mV
mV
mV
OL
OH
I
I
= 5mA
= 20mA
SINK
SINK
Output Voltage Swing HIGH (Note 7)
Short-Circuit Current
No Load
5
130
475
40
250
900
mV
mV
mV
I
I
= 5mA
= 20mA
SOURCE
SOURCE
I
I
V = 5V
20
20
45
35
mA
mA
SC
S
V = 3V
S
Supply Current Per Amplifier
Gain-Bandwidth Product
Slew Rate
0.9
60
1
mA
MHz
V/µs
MHz
dBc
ns
S
GBW
SR
V = 5V, Frequency = 1MHz
S
35
10
V = 5V, A = –1, R = 1k, V = 4V
20
S
V
L
O
FPBW
HD
Full Power Bandwidth
Harmonic Distortion
Settling Time
V = 5V, A = 1, V = 4V
p-p
1.6
S
V
O
V = 5V, A = 1, R = 1k, V = 2V , f = 500kHz
–77.5
300
0.3
S
V
L
O
P-P C
t
0.01%, V = 5V, V
= 2V, A = 1, R = 1k
STEP V L
S
S
∆G
Differential Gain (NTSC)
Differential Phase (NTSC)
V = 5V, A = 2, R = 1k
%
S
V
L
∆θ
V = 5V, A = 2, R = 1k
0.3
Deg
S
V
L
sn622012 622012fs
3
LT6220/LT6221/LT6222
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the 0°C ≤ TA ≤ 70°C
temperature range. VS = 5V, 0V; VS = 3V, 0V; VCM = VOUT = half supply, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Offset Voltage
V
V
V
V
V
= 0V
●
●
●
●
●
90
180
230
0.5
0.5
500
850
1250
3
µV
µV
µV
mV
mV
OS
CM
CM
CM
CM
CM
= 0V (DD Package)
= 0V (S5 Package)
= V
S
= V (S5 Package)
3.5
S
∆V
OS
Input Offset Voltage Shift
V = 5V, V = 0V to 3.5V
●
●
30
15
280
190
µV
µV
S
CM
V = 3V, V = 0V to 1.5V
S
CM
Input Offset Voltage Match (Channel-to-Channel) V = 0V
●
●
110
180
850
1400
µV
µV
CM
(Note 9)
V
= 0V (DD Package)
CM
V
TC
Input Offset Voltage Drift (Note 8)
●
●
1.5
3.5
5
10
µV/°C
µV/°C
OS
(S5 Package)
I
Input Bias Current
V
V
= 1V
●
●
20
275
175
800
nA
nA
B
CM
CM
= V – 0.2V
S
Input Bias Current Match (Channel-to-Channel)
(Note 9)
V
V
= 1V
●
●
15
20
200
300
nA
nA
CM
CM
= V – 0.2V
S
I
Input Offset Current
V
V
= 1V
●
●
15
15
125
125
nA
nA
OS
CM
CM
= V – 0.2V
S
A
Large Signal Voltage Gain
V = 5V, V = 0.5V to 4.5V, R = 1kat V /2
●
●
●
30
3
25
90
9
80
V/mV
V/mV
V/mV
VOL
S
O
L
S
V = 5V, V = 1V to 4V, R = 100Ωat V /2
S
O
L
S
V = 3V, V = 0.5V to 2.5V, R = 1kat V /2
S
O
L
S
CMRR
Common Mode Rejection Ratio
V = 5V, V = 0V to 3.5V
●
●
82
78
100
100
dB
dB
S
CM
V = 3V, V = 0V to 1.5V
S
CM
CMRR Match (Channel-to-Channel) (Note 9)
V = 5V, V = 0V to 3.5V
●
●
77
73
100
100
dB
dB
S
CM
V = 3V, V = 0V to 1.5V
S
CM
Input Common Mode Range
●
●
●
●
0
V
V
dB
dB
V
S
PSRR
Power Supply Rejection Ratio
V = 2.5V to 10V, V = 0V
81
76
104
104
2.2
S
CM
PSRR Match (Channel-to-Channel) (Note 9)
Minimum Supply Voltage (Note 6)
Output Voltage Swing LOW (Note 7)
2.5
V
V
No Load
●
●
●
8
110
375
50
220
750
mV
mV
mV
OL
OH
I
I
= 5mA
= 20mA
SINK
SINK
Output Voltage Swing HIGH (Note 7)
Short-Circuit Current
No Load
●
●
●
8
150
600
50
300
1100
mV
mV
mV
I
I
= 5mA
= 20mA
SOURCE
SOURCE
I
I
V = 5V
●
●
20
20
40
30
mA
mA
SC
S
V = 3V
S
Supply Current Per Amplifier
Gain-Bandwidth Product
Slew Rate
●
●
●
1
1.4
mA
MHz
V/µs
S
GBW
SR
V = 5V, Frequency = 1MHz
S
30
9
60
18
V = 5V, A = –1, R = 1k, V = 4V
S P-P
V
L
O
sn622012 622012fs
4
LT6220/LT6221/LT6222
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the –40°C ≤ TA ≤ 85°C
temperature range. VS = 5V, 0V; VS = 3V, 0V; VCM = VOUT = half supply unless otherwise noted. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Offset Voltage
V
V
V
V
V
= 0V
●
●
●
●
●
125
300
350
0.75
1
700
1300
2000
3.5
µV
µV
µV
mV
mV
OS
CM
CM
CM
CM
CM
= 0V (DD Package)
= 0V (S5 Package)
= V
S
= V (S5 Package)
4.5
S
∆V
OS
Input Offset Voltage Shift
V = 5V, V = 0V to 3.5V
●
●
30
30
300
210
µV
µV
S
CM
V = 3V, V = 0V to 1.5V
S
CM
Input Offset Voltage Match (Channel-to-Channel) V = 0V
●
●
175
300
1200
2200
µV
µV
CM
(Note 9)
V
= 0V (DD Package)
CM
V
TC
Input Offset Voltage Drift (Note 8)
●
●
1.5
3.5
7.5
15
µV/°C
µV/°C
OS
(S5 Package)
I
Input Bias Current
V
V
= 1V
●
●
25
300
200
900
nA
nA
B
CM
CM
= V – 0.2V
S
Input Bias Current Match (Channel-to-Channel)
(Note 9)
V
V
= 1V
●
●
15
20
250
350
nA
nA
CM
CM
= V – 0.2V
S
I
Input Offset Current
V
V
= 1V
●
●
20
20
150
150
nA
nA
OS
CM
CM
= V – 0.2V
S
A
Large Signal Voltage Gain
V = 5V, V = 0.5V to 4.5V, R = 1k at V /2
●
●
●
25
2.5
20
70
8
60
V/mV
V/mV
V/mV
VOL
S
O
L
S
V = 5V, V = 1.5V to 3.5V, R = 100Ω at V /2
S
O
L
S
V = 3V, V = 0.5V to 2.5V, R = 1k at V /2
S
O
L
S
CMRR
Common Mode Rejection Ratio
V = 5V, V = 0V to 3.5V
●
●
81
77
100
100
dB
dB
S
CM
V = 3V, V = 0V to 1.5V
S
CM
CMRR Match (Channel-to-Channel) (Note 9)
V = 5V, V = 0V to 3.5V
●
●
76
72
100
100
dB
dB
S
CM
V = 3V, V = 0V to 1.5V
S
CM
Input Common Mode Range
●
●
●
●
0
V
V
dB
dB
V
S
PSRR
Power Supply Rejection Ratio
V = 2.5V to 10V, V = 0V
79
74
104
104
2.2
S
CM
PSRR Match (Channel-to-Channel) (Note 9)
Minimum Supply Voltage (Note 6)
Output Voltage Swing LOW (Note 7)
2.5
V
V
No Load
●
●
●
10
120
220
60
240
450
mV
mV
mV
OL
I
I
= 5mA
= 10mA
SINK
SINK
Output Voltage Swing HIGH (Note 7)
Short-Circuit Current
No Load
●
●
●
10
160
325
60
325
650
mV
mV
mV
OH
I
I
= 5mA
= 10mA
SOURCE
SOURCE
I
I
V = 5V
●
●
12.5
12.5
30
25
mA
mA
SC
S
V = 3V
S
Supply Current Per Amplifier
Gain-Bandwidth Product
Slew Rate
●
●
●
1.1
50
15
1.5
mA
MHz
V/µs
S
GBW
SR
V = 5V, Frequency = 1MHz
S
25
8
V = 5V, A = –1, R = 1k, V = 4V
S
V
L
O
sn622012 622012fs
5
LT6220/LT6221/LT6222
ELECTRICAL CHARACTERISTICS
TA = 25°C, VS = ±5V, VCM = 0V, VOUT = 0V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Offset Voltage
V
V
V
V
V
= –5V
80
150
200
0.7
0.7
500
750
900
2.5
3
µV
µV
µV
mV
mV
OS
CM
CM
CM
CM
CM
= –5V (DD Package)
= –5V (S5 Package)
= 5V
= 5V (S5 Package)
∆V
OS
Input Offset Voltage Shift
V
= –5V to 3.5V
70
675
µV
CM
Input Offset Voltage Match (Channel-to-Channel) V = –5V
100
150
850
1300
µV
µV
CM
V
= –5V (DD Package)
CM
I
I
Input Bias Current
V
V
= –4V
= 5V
20
250
150
700
nA
nA
B
CM
CM
Input Bias Current Match (Channel-to-Channel)
Input Offset Current
V
V
= –4V
= 5V
15
20
175
250
nA
nA
CM
CM
V
V
= –4V
= 5V
15
15
100
100
nA
nA
OS
CM
CM
Input Noise Voltage
0.1Hz to 10Hz
f = 10kHz
0.5
10
0.8
2
µV
P-P
e
Input Noise Voltage Density
Input Noise Current Density
Input Capacitance
nV/√Hz
pA/√Hz
pF
n
i
f = 10kHz
n
C
A
f = 100kHz
IN
Large Signal Voltage Gain
V = – 4V to 4V, R = 1k
35
3.5
95
10
V/mV
V/mV
VOL
O
L
V = –2V to 2V, R = 100Ω
O
L
CMRR
Common Mode Rejection Ratio
CMRR Match (Channel-to-Channel)
Input Common Mode Range
V
= –5V to 3.5V
82
102
100
dB
dB
V
CM
77
–
+
V
V
S
S
+
–
PSRR
Power Supply Rejection Ratio
V
= 2.5V to 10V, V = 0V, V = 0V
84
79
105
105
dB
dB
S
S
CM
PSRR Match (Channel-to-Channel)
Output Voltage Swing LOW (Note 7)
V
V
No Load
SINK
SINK
5
100
325
40
200
650
mV
mV
mV
OL
OH
I
I
= 5mA
= 20mA
Output Voltage Swing HIGH (Note 7)
No Load
SOURCE
SOURCE
5
130
475
40
250
900
mV
mV
mV
I
I
= 5mA
= 20mA
I
I
Short-Circuit Current
Supply Current Per Amplifier
Gain-Bandwidth Product
Slew Rate
25
50
1
mA
mA
SC
1.5
S
GBW
SR
Frequency = 1MHz
A = –1, R = 1k,V = ±4V,
60
20
MHz
V/µs
V
L
O
Measure at V = ±2V
O
FPBW
HD
Full Power Bandwidth
Harmonic Distortion
Settling Time
V = 8V
0.8
–77.5
375
MHz
dBc
ns
O
P-P
A = 1, R = 1k, V = 2V , f = 500kHz
V
L
O
p-p
c
t
0.01%, V
= 5V, A = 1, R = 1k
STEP V L
S
∆G
Differential Gain (NTSC)
Differential Phase (NTSC)
A = 2, R = 1k
0.15
0.6
%
V
L
∆θ
A = 2, R = 1k
Deg
V
L
sn622012 622012fs
6
LT6220/LT6221/LT6222
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the 0°C ≤ TA ≤ 70°C
temperature range. VS = ±5V, VCM = 0V, VOUT = 0V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Offset Voltage
V
V
V
V
V
= –5V
●
●
●
●
●
100
180
230
0.75
0.75
650
900
1300
3
µV
µV
µV
mV
mV
OS
CM
CM
CM
CM
CM
= –5V (DD Package)
= –5V (S5 Package)
= 5V
= 5V (S5 Package)
3.5
∆V
OS
Input Offset Voltage Shift
V
= –5V to 3.5V
●
90
850
µV
CM
Input Offset Voltage Match (Channel-to-Channel) V = –5V
●
●
90
180
1100
1500
µV
µV
CM
(Note 9)
V
= –5V (DD Package)
CM
V
TC
Input Offset Voltage Drift (Note 8)
●
●
1.5
3.5
5
10
µV/°C
µV/°C
OS
(S5 Package)
I
Input Bias Current
V
V
= –4V
= 4.8V
●
●
20
275
175
800
nA
nA
B
CM
CM
Input Bias Current Match (Channel-to-Channel)
(Note 9)
V
V
= –4V
= 4.8V
●
●
15
20
200
300
nA
nA
CM
CM
I
Input Offset Current
V
V
= –4V
= 4.8V
●
●
15
15
125
125
nA
nA
OS
CM
CM
A
Large Signal Voltage Gain
V = – 4V to 4V, R = 1k
●
●
30
3
90
9
V/mV
V/mV
VOL
O
L
V = –2V to 2V, R =100Ω
O
L
CMRR
Common Mode Rejection Ratio
V
= –5V to 3.5V
●
●
●
●
●
80
100
100
dB
dB
V
CM
CMRR Match (Channel-to-Channel) (Note 9)
Input Common Mode Range
75
–
+
V
V
S
S
+
–
PSRR
Power Supply Rejection Ratio
V
= 2.5V to 10V, V = 0V, V = 0V
81
76
104
104
dB
dB
S
S
CM
PSRR Match (Channel-to-Channel) (Note 9)
Output Voltage Swing LOW (Note 7)
V
V
No Load
●
●
●
8
110
375
50
220
750
mV
mV
mV
OL
OH
I
I
= 5mA
= 20mA
SINK
SINK
Output Voltage Swing HIGH (Note 7)
No Load
●
●
●
8
150
600
50
300
1100
mV
mV
mV
I
I
= 5mA
= 20mA
SOURCE
SOURCE
I
I
Short-Circuit Current
Supply Current Per Amplifier
Gain-Bandwidth Product
Slew Rate
●
●
●
●
20
40
1.2
60
18
mA
mA
SC
2
S
GBW
SR
Frequency = 1MHz
A = –1, R = 1k, V = ±4V,
MHz
V/µs
V
L
O
Measure at V = ±2V
O
sn622012 622012fs
7
LT6220/LT6221/LT6222
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the –40°C ≤ TA ≤ 85°C
temperature range. VS = ±5V, VCM = 0V, VOUT = 0V, unless otherwise noted. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input Offset Voltage
V
V
V
V
V
= –5V
●
●
●
●
●
150
300
350
0.75
1
800
1300
2000
3.5
µV
µV
µV
mV
mV
OS
CM
CM
CM
CM
CM
= –5V (DD Package)
= –5V (S5 Package)
= 5V
= 5V (S5 Package)
4.5
∆V
OS
Input Offset Voltage Shift
V
= – 5V to 3.5V
●
90
950
µV
CM
Input Offset Voltage Match (Channel-to-Channel) V = –5V
●
●
175
300
1350
2200
µV
µV
CM
(Note 9)
V
= –5V (DD Package)
CM
V
TC
Input Offset Voltage Drift (Note 8)
●
●
1.5
3.5
7.5
15
µV/°C
µV/°C
OS
(S5 Package)
I
Input Bias Current
V
V
= –4V
= 4.8V
●
●
25
300
200
900
nA
nA
B
CM
CM
Input Bias Current Match (Channel-to-Channel)
(Note 9)
V
V
= –4V
= 4.8V
●
●
15
20
250
350
nA
nA
CM
CM
I
Input Offset Current
V
V
= –4V
= 4.8V
●
●
20
20
150
150
nA
nA
OS
CM
CM
A
Large Signal Voltage Gain
V = –4V to 4V, R = 1k
●
●
25
2.5
70
8
V/mV
V/mV
VOL
O
L
V = –1V to 1V, R = 100Ω
O
L
CMRR
Common Mode Rejection Ratio
V
= –5V to 3.5V
●
●
●
●
●
79
74
–5
79
74
100
100
dB
dB
V
CM
CMRR Match (Channel-to-Channel) (Note 9)
Input Common Mode Range
5
+
–
PSRR
Power Supply Rejection Ratio
V
= 2.5V to 10V, V = 0V, V = 0V
104
104
dB
dB
S
S
CM
PSRR Match (Channel-to-Channel) (Note 9)
Output Voltage Swing LOW (Note 7)
V
V
No Load
●
●
●
10
120
220
60
240
450
mV
mV
mV
OL
OH
I
I
= 5mA
= 10mA
SINK
SINK
Output Voltage Swing HIGH (Note 7)
No Load
●
●
●
10
160
325
60
325
650
mV
mV
mV
I
I
= 5mA
= 10mA
SOURCE
SOURCE
I
I
Short-Circuit Current
Supply Current
●
●
●
●
12.5
30
1.4
50
15
mA
mA
SC
2.25
S
GBW
SR
Gain-Bandwidth Product
Slew Rate
Frequency = 1MHz
A = –1, R = 1k,V = ±4V,
MHz
V/µs
V
L
O
Measure at V = ±2V
O
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
LT6220I/LT6221I/LT6222I are guaranteed to meet specified performance
from –40°C to 85°C.
Note 2: The inputs are protected by back-to-back diodes. If the differential
input voltage exceeds 1.4V, the input current should be limited to less than
10mA.
Note 3: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefinitely.
Note 6: Minimum supply voltage is guaranteed by power supply rejection
ratio test.
Note 7: Output voltage swings are measured between the output and
power supply rails.
Note 8: This parameter is not 100% tested.
Note 9: Matching parameters are the difference between amplifiers A and
D and between B and C on the LT6222; between the two amplifiers on the
LT6221.
Note 4: The LT6220C/LT6221C/LT6222C and LT6220I/LT6221I/LT6222I
are guaranteed functional over the temperature range of –40°C and 85°C.
Note 5: The LT6220C/LT6221C/LT6222C are guaranteed to meet specified
performance from 0°C to 70°C. The LT6220C/LT6221C/LT6222C are
designed, characterized and expected to meet specified performance from
–40°C to 85°C but is not tested or QA sampled at these temperatures. The
Note 10: Thermal resistance (θ ) varies with the amount of PC board
JA
metal connected to the package. The specified values are for short traces
connected to the leads. If desired, the thermal resistance can be
substantially reduced by connecting Pin 2 of the LT6220CS5/LT6220IS5 or
–
the underside metal of DD packages to a larger metal area (V trace).
S
sn622012 622012fs
8
LT6220/LT6221/LT6222
U W
TYPICAL PERFOR A CE CHARACTERISTICS
VOS Distribution, VCM = 0V
(S8, PNP Stage)
VOS Distribution, VCM = 0V
(SOT5, PNP Stage)
VOS Distribution, VCM = 5V
(S8, NPN Stage)
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
50
V
V
= 5V, 0V
CM
V
V
= 5V, 0V
CM
V
V
= 5V, 0V
CM
S
S
S
= 0V
= 0V
45
40
35
30
25
20
15
10
5
= 5V
0
0
0
–250
–150
–50
0
50
150
250
–1000
–600
–200
0
200
600
1000
–2000 –1200
–400
0
400
1200
2000
INPUT OFFSET VOLTAGE (µV)
INPUT OFFSET VOLTAGE (µV)
INPUT OFFSET VOLTAGE (µV)
622012 G01
622012 G02
622012 G03
VOS Distribution, VCM = 5V
(SOT5, NPN Stage)
Offset Voltage
vs Input Common Mode Voltage
Supply Current vs Supply Voltage
700
500
3
2
1
0
50
45
40
35
30
25
20
15
10
5
V = 5V, 0V
S
TYPICAL PART
V
V
= 5V, 0V
CM
S
= 5V
300
T
= –55°C
= 25°C
A
T
= 125°C
A
100
T
A
T
= 25°C
A
–100
–300
–500
–700
T
= 125°C
A
T
= –55°C
A
0
0
1
4
5
6
7
8
9
10 11 12
0
1
2
3
4
5
2
3
–3000 –1800
–600
0
600
1800
3000
TOTAL SUPPLY VOLTAGE (V)
INPUT COMMON MODE VOLTAGE (V)
INPUT OFFSET VOLTAGE (µV)
622012 G05
622012 G06
622012 G04
Input Bias Current
vs Common Mode Voltage
Input Bias Current
vs Temperature
Output Saturation Voltage
vs Load Current (Output Low)
10
1
0.6
0.5
0.4
0.3
0.2
0.1
0
400
300
V
= 5V, 0V
V = 5V, 0V
S
V
S
= 5V, 0V
S
T
= 25°C
A
T
= –55°C
A
200
100
NPN ACTIVE
= 5V
T
= 125°C
A
V
CM
0
T
A
= 125°C
0.1
–100
–200
–300
–400
–500
–600
PNP ACTIVE
= 1V
T
A
= 25°C
V
CM
0.01
0.001
T
A
= –55°C
–0.1
–0.2
1
2
3
4
5
6
–55
–25
35
5
TEMPERATURE (°C)
65
95
125
0.01
0.1
1
10
100
0
LOAD CURRENT (mA)
COMMON MODE VOLTAGE (V)
622012 G09
622012 G07
622012 G08
sn622012 622012fs
9
LT6220/LT6221/LT6222
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Output Saturation Voltage
vs Load Current (Output High)
Output Short-Circuit Current
vs Power Supply Voltage
Minimum Supply Voltage
0.6
0.4
10
1
70
60
50
40
30
20
10
0
–10
–20
–30
–40
–50
–60
–70
V
= 5V, 0V
T
= 25°C
S
A
T
= 125°C
= –55°C
A
SINKING
T
A
0.2
0
T
T
= –55°C
A
T
= 25°C
A
T
= 125°C
A
0.1
= 125°C
A
T
= 25°C
–0.2
–0.4
–0.6
A
T
= –55°C
A
0.01
0.001
SOURCING
T
= –55°C
A
T
A
= 125°C
T
= 25°C
A
0
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
0.01
0.1
1
10
100
1.5
2
2.5
3
3.5
4
4.5
5
TOTAL SUPPLY VOLTAGE (V)
LOAD CURRENT (mA)
POWER SUPPLY VOLTAGE (±V)
622012 G10
622012 G11
622012 G12
Open-Loop Gain
Open-Loop Gain
Open-Loop Gain
1000
800
1000
800
1000
800
V
= 5V, 0V
TO GND
V = ±5V
S
R TO GND
L
V
= 3V, 0V
TO GND
S
L
S
L
R
R
600
600
600
400
400
400
200
200
200
R
= 1k
R
R
= 1k
R
L
= 1k
L
L
0
0
0
= 100Ω
–200
–400
–600
–800
–1000
–200
–400
–600
–800
–1000
–200
–400
–600
–800
–1000
L
R
1
= 100Ω
R
= 100Ω
L
L
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
6
–5 –4 –3 –2 –1
0
2
3
4
5
0
0.5
1.5
2
2.5
3
1
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
622012 G14
622012 G15
622012 G13
Offset Voltage vs Output Current
Warm-Up Drift vs Time
Input Noise Voltage vs Frequency
40
35
30
25
20
15
10
5
2.0
1.5
10
8
V
= 5V, 0V
V
= ±5V
S
S
6
1.0
4
0.5
LT6222
GN16
S
LT6220
SOT5
S
LT6221
2
T
= –55°C
T = 25°C
A
A
S8
0
V
= ±2.5V
V
= ±2.5V
0
V
= ±2.5V
S
NPN ACTIVE
= 4.25V
V
CM
–2
–4
–6
–8
–10
–0.5
–1.0
–1.5
–2.0
T
= 125°C
A
PNP ACTIVE
LT6222
GN16
S
LT6221
S8
LT6220
SOT5
S
V
= 2.5V
CM
V
= ±5V
V
= ±5V
V
= ±5V
S
0
0.01
0.1
1
10
100
–75 –60 –45 –30 –15
0
15 30 45 60 75
0
5
10 15 20 25 30 35 40 45 50
FREQUENCY (kHz)
OUTPUT CURRENT (mA)
TIME AFTER POWER-UP (SECONDS)
622012 G18
622012 G16
622012 G17
sn622012 622012fs
10
LT6220/LT6221/LT6222
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Gain Bandwidth and Phase
Margin vs Supply Voltage
Input Current Noise vs Frequency
0.1Hz to 10Hz Output Voltage Noise
3.0
800
600
90
80
70
60
50
V
= 5V, 0V
T
= 25°C
S
V = 5V, 0V
S
A
2.5
2.0
GAIN BANDWIDTH PRODUCT
PHASE MARGIN
400
200
0
1.5
1.0
70
60
50
40
30
20
PNP ACTIVE
= 2.5V
–200
–400
–600
–800
V
CM
NPN ACTIVE
0.5
0
V
CM
= 4.25V
0.01
0.1
1
10
100
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (kHz)
TIME (SECONDS)
TOTAL SUPPLY VOLTAGE (V)
622012 G19
622012 G20
622012 G21
Gain Bandwidth and Phase
Margin vs Temperature
Gain and Phase vs Frequency
Slew Rate vs Temperature
80
120
100
80
30
90
80
70
60
50
A
R
R
= –1
G
= 1k
V
F
L
70
60
50
= R = 1k
GAIN BANDWIDTH PRODUCT
PHASE
V
= ±2.5V
V
= ±5V
S
S
V
= ±5V
S
60
25
20
15
V
= ±5V
S
40
30
40
20
V
= ±2.5V
= ±2.5V
S
70
V
GAIN
PHASE MARGIN
S
V
= ±5V
S
V
= ±2.5V
20
10
0
S
60
50
40
30
20
V
= ±5V
S
–20
–40
–60
–80
V
= ±2.5V
S
0
–10
–20
10k
100k
1M
10M
100M
–55
5
35
65
95
125
–25
–55
–25
5
35
65
95
125
TEMPERATURE (°C)
FREQUENCY (Hz)
TEMPERATURE (°C)
622012 G23
622012 G24
622012 G22
Gain vs Frequency (AV = 1)
Gain vs Frequency (AV = 2)
Output Impedance vs Frequency
15
15
1000
100
10
V
= ±2.5V
A
C
= 1
= 10pF
= 1k
S
V
L
L
12
9
12
9
R
6
6
A
= 10
= 1
V
3
0
3
0
V
S
= ±2.5V
V
S
= ±2.5V
1
V
S
= ±5V
V
= ±5V
S
A
= 2
V
–3
–6
–3
–6
A
0.1
V
A
= 2
V
R
= R = 1k
F
F
L
G
–9
–9
C
C
= 20pF
= 10pF
= 1k
0.01
0.001
–12
–12
R
L
–15
–15
0.1
1
10
100
0.1
1
10
100
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
622012 G25
622012 G26
620012 G27
sn622012 622012fs
11
LT6220/LT6221/LT6222
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Common Mode Rejection Ratio
vs Frequency
Power Supply Rejection Ratio
vs Frequency
Series Output Resistor
vs Capacitive Load
120
120
100
80
60
40
20
0
50
45
40
35
V
= 5V, 0V
V
= 5V, 0V
S
V
A
= 5V, 0V
S
S
V
L
= 1
100
80
R
= ∞, UNLESS NOTED
POSITIVE
SUPPLY
R
= 10Ω
OS
30
25
60
40
R
= 20Ω
NEGATIVE
SUPPLY
OS
20
15
10
5
R
= R = 50Ω
L
OS
20
0
0
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
10
100
1000
10000
FREQUENCY (MHz)
FREQUENCY (MHz)
CAPACITIVE LOAD (pF)
622012 G28
622012 G29
622012 G31
Series Output Resistor
vs Capacitive Load
Distortion vs Frequency
Distortion vs Frequency
50
45
40
35
–30
–40
–30
–40
V
A
= 5V, 0V
V
A
V
= 5V, 0V
= 1
V
A
V
= 5V, 0V
= 2
S
V
L
S
V
S
V
= 2
R
= ∞, UNLESS NOTED
= 2V
= 2V
OUT
P-P
OUT
P-P
–50
–50
R
= 150Ω,
L
R
L
= 150Ω,
3RD
R = 1k,
L
2ND
–60
2ND
–60
30
25
R
L
= 150Ω,
R
= 150Ω,
L
–70
–70
3RD
2ND
R
= 10Ω
OS
R
= 1k,
20
15
10
5
L
–80
–80
R = 1k,
L
3RD
2ND
–90
–90
R
= 1k,
L
3RD
R
= 20Ω
OS
–100
–100
R
= R = 50Ω
L
OS
0
–110
–110
10
100
1000
10000
0.01
0.1
1
10
0.01
0.1
1
10
CAPACITIVE LOAD (pF)
FREQUENCY (MHz)
FREQUENCY (MHz)
622012 G32
622012 G33
622012 G34
Maximum Undistorted Output
Signal vs Frequency
5V Small-Signal Response
5V Large-Signal Response
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
50mV/DIV
2.5V
A
= –1
A = 2
V
V
1V/DIV
0V
V
S = 5V, 0V
AV = 1
L = 1k
50ns/DIV
622012 G37
VS = 5V, 0V
AV = 1
100ns/DIV
622012 G36
V
= 5V, 0V
= 1k
S
L
R
R
RL = 1k
0
0.01
0.1
1
10
FREQUENCY (MHz)
622012 G35
sn622012 622012fs
12
LT6220/LT6221/LT6222
U W
TYPICAL PERFOR A CE CHARACTERISTICS
±5V Large-Signal Response
±5V Small-Signal Response
Output Overdriven Recovery
VIN
1V/DIV
50mV/DIV
0V
2V/DIV
0V
0V
VOUT
2V/DIV
0V
VS = ±5V
AV = 1
RL = 1k
200ns/DIV
622012 G38
VS = ±5V
AV = 1
RL = 1k
50ns/DIV
622012 G39
V
S = 5V, 0V
200ns/DIV
622012 G40
AV = 2
RL = 1k
W U U
U
APPLICATIO S I FOR ATIO
Circuit Description
tail current, I1, to the current mirror, Q6/Q7, activating the
NPN differential pair and the PNP pair becomes inactive
for the rest of the input common mode range up to the
positive supply. Also, at the input stage, devices Q17 to
Q19 act to cancel the bias current of the PNP input pair.
When Q1/Q2 are active, the current in Q16 is controlled to
be the same as the current Q1/Q2. Thus, the base current
of Q16 is nominally equal to the base current of the input
devices. The base current of Q16 is then mirrored by
devices Q17-Q19 to cancel the base current of the input
devices Q1/Q2.
The LT6220/LT6221/LT6222 have an input and output
signalrangethatcoversfromthenegativepowersupplyto
the positive power supply. Figure 1 depicts a simplified
schematic of the amplifier. The input stage comprises two
differential amplifiers, a PNP stage, Q1/Q2, and an NPN
stage, Q3/Q4, that are active over different ranges of
common mode input voltage. The PNP stage is active
between the negative supply to approximately 1.2V below
the positive supply. As the input voltage moves closer
toward the positive supply, the transistor Q5 will steer the
+
V
R3
R4
R5
–
+
V
V
+
+
D1
ESDD1
ESDD2
Q12
I
I
1
Q11
Q15
2
Q13
C2
+IN
–IN
+
D6
D5
D8
D7
Q5
V
BIAS
I
3
D2
OUT
C
–
C
V
Q4 Q3
Q1 Q2
D3
BUFFER
AND
OUTPUT BIAS
ESDD4
ESDD3
Q10
–
+
V
V
D4
Q9
R1
Q8
Q16
C1
Q17
Q18
Q14
Q7
Q6
Q19
R2
–
V
622012 F01
Figure 1. LT6220/LT6221/LT6222 Simplified Schematic Diagram
sn622012 622012fs
13
LT6220/LT6221/LT6222
W U U
U
APPLICATIO S I FOR ATIO
Input Offset Voltage
ApairofcomplementarycommonemitterstagesQ14/Q15
that enable the output to swing from rail-to-rail construct
the output stage. The capacitors C2 and C3 form the local
feedback loops that lower the output impedance at high
frequency. These devices are fabricated by Linear
Technology’s proprietary high speed complementary bi-
polar process.
Theoffsetvoltagewillchangedependinguponwhichinput
stage is active. The PNP input stage is active from the
negative supply rail to 1.2V below the positive supply rail,
then the NPN input stage is activated for the remaining
input range up to the positive supply rail during which the
PNP stage remains inactive. The offset voltage is typically
less than 70µV in the range that the PNP input stage is
active.
Power Dissipation
The LT6222, with four amplifiers, is housed in a small
16-lead SSOP package and typically has a thermal resis-
tance (θJA) of 135°C/W. It is necessary to ensure that the
die’s junction temperature does not exceed 150°C. The
junction temperature, TJ, is calculated from the ambient
temperature,TA,powerdissipation,PD,andthermalresis-
tance, θJA:
Input Bias Current
The LT6220/LT6221/LT6222 employ a patent pending
technique to trim the input bias current to less than 150nA
for the input common mode voltage of 0.2V above the
negative supply rail to 1.2V below the positive rail. The low
input offset voltage and low input bias current of the
LT6220/LT6221/LT6222 provide precision performance
especially for high source impedance applications.
TJ = TA + (PD • θJA)
ThepowerdissipationintheICisthefunctionofthesupply
voltage,outputvoltageandtheloadresistance.Foragiven
supply voltage, the worst-case power dissipation PD(MAX)
occurs when the maximum supply current and the output
voltage is at half of either supply voltage for a given load
resistance. PD(MAX) is given by:
Output
The LT6220/LT6221/LT6222 can deliver a large output
current, so the short-circuit current limit is set around
50mA to prevent damage to the device. Attention must be
paid to keep the junction temperature of the IC below the
absolute maximum rating of 150°C (refer to the Power
Dissipation section) when the output is in continuous
short circuit. The output of the amplifier has reverse-
biased diodes connected to each supply. If the output is
forced beyond either supply, unlimited current will flow
throughthesediodes. Ifthecurrentistransientandlimited
to several hundred milliamperes, no damage will occur to
the device.
2
V
2
⎛
⎜
⎝
⎞
⎟
⎠
S
PD(MAX) = V •I
+
/ RL
(
)
S
S(MAX)
Example: For an LT6222 in a 16-lead SSOP package
operating on ±5V supplies and driving a 100Ω load, the
worst-case power dissipation is given by:
2
PD(MAX)/Amp = 10 •1.8mA + 2.5 / 100
(
) (
)
= 0.018 + 0.0625 = 80.5mW
Overdrive Protection
If all four amplifiers are loaded simultaneously, then the
total power dissipation is 322mW.
When the input voltage exceeds the power supplies, two
pair of crossing diodes, D1 to D4, will prevent the output
from reversing polarity. If the input voltage exceeds either
power supply by 700mV, diode D1/D2 or D3/D4 will turn
on to keep the output at the proper polarity. For the phase
reversal protection to perform properly, the input current
must be limited to less than 5mA. If the amplifier is
The maximum ambient temperature at which the part is
allowed to operate is:
TA = TJ – (PD(MAX) • 135°C/W)
= 150°C – (0.322W • 135°C/W) = 106.5°C
sn622012 622012fs
14
LT6220/LT6221/LT6222
W U U
APPLICATIO S I FOR ATIO
U
severelyoverdriven, anexternalresistorshouldbeusedto
limit the overdriven current.
capacitive load, a resistor of 10Ω to 50Ω should be
connected between the output and the capacitive load to
avoid ringing or oscillation. The feedback should still be
taken from the output so that the resistor will isolate the
capacitive load to ensure stability. Graphs on capacitive
loads show the transient response of the amplifier when
driving capacitive load with specified series resistors.
The LT6220/LT6221/LT6222’s input stages are also pro-
tected against a large differential input voltage of 1.4V or
higher by a pair of back-to-back diodes, D5/D8, to prevent
the emitter-base breakdown of the input transistors. The
current in these diodes should be limited to less than
10mA when they are active. The worse-case differential
inputvoltageusuallyoccurswhentheinputisdrivenwhile
the output is shorted to ground in a unity-gain configura-
tion. In addition, the amplifier is protected against ESD
strikes up to 3kV on all pins by a pair of protection diodes
on each pin that are connected to the power supplies as
shown in Figure 1.
Feedback Components
Whenfeedbackresistorsareusedtosetupgain,caremust
be taken to ensure that the pole formed by the feedback
resistors and the total capacitance at the inverting input
does not degrade stability. For instance, the LT6220/
LT6221/LT6222, set up with a noninverting gain of 2, two
5kresistorsandacapacitanceof5pF(partplusPCboard),
will probably oscillate. The pole is formed at 12.7MHz that
will reduce phase margin by 52 degrees when the cross-
overfrequencyoftheamplifierisaround10MHz.Acapaci-
tor of 10pF or higher connecting across the feedback
resistor will eliminate any ringing or oscillation.
Capacitive Load
The LT6220/LT6221/LT6222 are optimized for high band-
width, low power and precision applications. They can
drive a capacitive load up to 100pF in a unity-gain configu-
ration and more for higher gain. When driving a larger
U
TYPICAL APPLICATIO S
Stepped-Gain Photodiode Amplifier
ground, so Q1 is reverse biased and no current flows
through R2. So for small signals, the only feedback path
is R1 (and C1) and the circuit is a simple transimpedance
amplifier with 100kΩ gain.
The circuit of Figure 2 is a stepped gain transimpedance
photodiode amplifier. At low signal levels, the circuit has
a high 100kΩ gain, but at high signal levels the circuit
automatically and smoothly changes to a low 3.2kΩ gain.
The benefit of a stepped gain approach is that it maximizes
dynamic range, which is very useful on limited supplies.
Put another way, in order to get 100kΩ sensitivity and still
handle a 1mA signal level without resorting to gain reduc-
tion, the circuit would need a 100V negative voltage
supply.
+
V
S
R4
10k
R2
3.24k
PHILIPS
BCV62
C2
30pF
3
4
+
V
S
R1
100k
C1
1pF
Q1
V
Q2
+
V
S
I
PD
2
1
R3
33k
The operation of the circuit is quite simple. At low photo-
diode currents (below 10µA) the output and inverting
input of the op amp will be no more than 1V below ground.
The LT1634 in parallel with R3 and Q2 keep a constant
current though Q2 of about 20µA. R4 maintains quiescent
current through the LT1634 and pulls Q2’s emitter above
–
LT1634-1.25
–
S
PHOTODIODE
~4pF
LT6220
V
OUT
+
V
S
= ±1.5V TO ±5V
–
622012 F02
V
S
Figure 2. Stepped-Gain Photodiode Amplifier
sn622012 622012fs
15
LT6220/LT6221/LT6222
U
PACKAGE DESCRIPTIO
20
0
As the signal level increases though, the output of the op
amp goes more negative. At 12.5µA of photodiode cur-
rent, the 100kΩ gain dictates that the LT6220 output will
be about 1.25V below ground. However, at that point the
emitter of Q2 will be at ground, and the base of Q1 will be
1V below ground. Thus, Q1 turns on and photodiode
current starts to flow through R2. The transimpedance
gain is therefore now reduced to R1||R2, or about 3.1kΩ.
ThecircuitresponseisshowninFigure3.Notethesmooth
transition between the two operating gains, as well as the
linearity.
–20
–40
–60
–80
–100
–120
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
622012 F05
PHOTO
CURRENT
100µA/DIV
Figure 5. Frequency Response of Filter
Differential-In/Differential-Out Amplifier
The circuit of Figure 6 shows the LT6222 applied as a
buffered differential-in differential-out amplifier with a
gain of 2. Op amps A and B are configured as simple unity-
gain buffers, offering high input impedance to upstream
circuitry. Resistors R1 and R2 perform an averaging
function on the common mode input voltage and R3
attenuates it by a factor of 2/3 and references it to the
voltage source VOCM. The resultant voltage, VMID = 2/3 •
VICM, isplacedatthenoninvertinginputsofopampsCand
D. The other four resistors set gains of +3 from the
noninvertinginputand–2throughtheinvertingpath.Thus
the output voltage of the upper path is:
V
OUT
0.5V/DIV
622012 F03
5µs/DIV
Figure 3. Stepped-Gain Photodiode Amplifier Response
Single 3V Supply, 1MHz, 4th Order Butterworth Filter
The circuit shown in Figure 4 makes use of the low voltage
operation and the wide bandwidth of the LT6221 to create
aDCaccurate1MHz4thorderlowpassfilterpoweredfrom
a 3V supply. The amplifiers are configured in the inverting
mode for the lowest distortion and the output can swing
rail-to-rail for maximum dynamic range. Figure 5 displays
the frequency response of the filter. Stopband attenuation
is greater than 100dB at 50MHz.
–OUT = 3 • (2/3 • VICM + 1/3 • VOCM) – 2
• (VICM + VDIFF/2)
= 2VICM + VOCM – 2VICM – VDIFF
= VOCM – VDIFF
909Ω
2.67k
220pF
47pF
1.1k
2.21k
470pF
22pF
909Ω
–
3V
V
IN
1.1k
–
1/2 LT6221
+
1/2 LT6221
V
OUT
+
V /2
S
622012 F04
Figure 4. 3V, 1MHz, 4th Order Butterworth Filter
sn622012 622012fs
16
LT6220/LT6221/LT6222
U
PACKAGE DESCRIPTIO
and the output of the lower path is:
risetotheeffectivedifferentialgainof2.Calculationsshow
that using 1% resistors gives worst-case input common
mode feedthrough better than –31dB, whether looking at
the output common mode or difference mode. Consider-
ing the 6dB of gain, worst-case common mode rejection
ratio is 37dB. (Remember this is assuming 1% resistors.
Of course, this can be improved with more precise resis-
tors.) Results achieved on the bench with typical 1%
resistors showed 67dB of CMRR at low frequency and
40dB CMRR at 1MHz. Gains other than 2 can be achieved
by setting R3 = α• (R1||R2), R5 = α• R4 and R7 = α• R6
where gain = α.
+OUT = 3 • (2/3 • VICM + 1/3 • VOCM) – 2
• (VICM – VDIFF/2)
= 2VICM + VOCM – 2VICM + VDIFF
= VOCM + VDIFF
Notethattheinputcommonmodevoltagedoesnotappear
in the output as either a common mode or a difference
mode term. However the voltage VOCM does appear in the
output terms, and with the same polarity, so it sets up the
output DC level. Also, the differential input voltage VDIFF
appearsfullyatbothoutputswithoppositepolarity, giving
U
PACKAGE DESCRIPTIO
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115
0.38 ± 0.10
TYP
5
8
0.675 ±0.05
3.5 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PACKAGE
OUTLINE
(DD8) DFN 1203
4
1
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.25 ± 0.05
0.50 BSC
0.50
BSC
2.38 ±0.05
(2 SIDES)
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
sn622012 622012fs
17
LT6220/LT6221/LT6222
U
PACKAGE DESCRIPTIO
S5 Package
5-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1635)
0.62
MAX
0.95
REF
2.90 BSC
(NOTE 4)
1.22 REF
1.50 – 1.75
(NOTE 4)
2.80 BSC
1.4 MIN
3.85 MAX 2.62 REF
PIN ONE
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45 TYP
5 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
DATUM ‘A’
0.01 – 0.10
1.00 MAX
0.30 – 0.50 REF
1.90 BSC
0.09 – 0.20
(NOTE 3)
S5 TSOT-23 0302
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
3. DIMENSIONS ARE INCLUSIVE OF PLATING 6. JEDEC PACKAGE REFERENCE IS MO-193
sn622012 622012fs
18
LT6220/LT6221/LT6222
U
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 – .197
(4.801 – 5.004)
.045 ±.005
NOTE 3
.050 BSC
7
5
8
6
.245
MIN
.160 ±.005
.150 – .157
(3.810 – 3.988)
NOTE 3
.228 – .244
(5.791 – 6.197)
.030 ±.005
TYP
1
3
4
2
RECOMMENDED SOLDER PAD LAYOUT
.010 – .020
(0.254 – 0.508)
× 45°
.053 – .069
(1.346 – 1.752)
.004 – .010
(0.101 – 0.254)
.008 – .010
(0.203 – 0.254)
0°– 8° TYP
.016 – .050
(0.406 – 1.270)
.050
(1.270)
BSC
.014 – .019
(0.355 – 0.483)
TYP
NOTE:
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
SO8 0303
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
sn622012 622012fs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
19
LT6220/LT6221/LT6222
U
TYPICAL APPLICATIO
R5
2k
5.6pF
V
ICM
+ V
/2
+
DIFF
V
R4
1k
S
+
+IN
A
–
1/4 LT6222
D
–OUT
–
1/4 LT6222
R1
2k
+
R3
2k
V
MID
V
OCM
R2
2k
R6
1k
+
V
ICM
– V
/2
DIFF
C
+OUT
–IN
+
1/4 LT6222
B
–
1/4 LT6222
R7
2k
–
–
V
S
5.6pF
622012 F06
V
= ±1.3V TO ±6V
S
BW ≅ 11MHz
Figure 6. Buffered Gain of 2 Differential-In/Differential-Out Amplifier
RELATED PARTS
PART NUMBER
DESCRIPTION
Dual/Quad 10MHz, 6V/µs Rail-to-Rail Input/
Output C Op Amps
COMMENTS
LT1498/LT1499
High DC Accuracy, 475µV V
Wide Supply Range, 2.2V to 30V
Max Supply Current 2.2mA/Amp,
, Max Supply Current 2mA/Amp
BIAS(MAX)
OS(MAX)
LOAD
LT1800/LT1801/LT1802 Single/Dual/Quad 80MHz, 25V/µs,
Low Power Rail-to-Rail Input/Output Precision Op Amps
350µV V , 250nA I
OS(MAX)
LT1803/LT1804/LT1805 Single/Dual/Quad 85MHz, 100V/µs
2mV V , Max Supply Current 3mA/Amp
OS(MAX)
Rail-to-Rail Input/Output Op Amps
LT1806/LT1807
LT1809/LT1810
Single/Dual 325MHz, 140V/µs Rail-to-Rail Input/
Output Op Amps
High DC Accuracy, 550µV V
Low Distortion –80dBc at 5MHz, Power Down (LT1806)
Max Low Noise 3.5nV/√Hz
OS(MAX)
Single/Dual 180MHz, Rail-to-Rail Input/Output Op Amps 350V/µs Slew Rate, Low Distortion –90dBc at 5MHz,
Power Down (LT1809)
sn622012 622012fs
LT/TP 0204 1K • PRINTED IN USA
20 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
©LINEAR TECHNOLOGY CORPORATION 2003
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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