LT1970IFE#PBF [Linear]
LT1970 - 500mA Power Op Amp with Adjustable Precision Current Limit; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C;
| 型号： | LT1970IFE#PBF |
| 厂家： | 
Linear |
| 描述： | LT1970 - 500mA Power Op Amp with Adjustable Precision Current Limit; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C 放大器 光电二极管 |
| 文件： | 总24页 (文件大小：522K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1970
500mA Power Op Amp with
Adjustable Precision Current Limit
U
FEATURES
DESCRIPTIO
The LT®1970 is a ± 500mA power op amp with precise
externally controlled current limiting. Separate control
voltages program the sourcing and sinking current limit
sense thresholds with 2% accuracy. Output current may
be boosted by adding external power transistors.
■
±500mA Minimum Output Current
■
Independent Adjustment of Source and
Sink Current Limits
2% Current Limit Accuracy
■
■
Operates with Single or Split Supplies
■
Shutdown/Enable Control Input
Thecircuitoperateswithsingleorsplitpowersuppliesfrom
5V to 36V total supply voltage. In normal operation, the
inputstagesuppliesandtheoutputstagesuppliesarecon-
nected (VCC to V+ and VEE to V–). To reduce power dissi-
pationitispossibletopowertheoutputstage(V+,V–)from
independent,lowervoltagerails.Theamplifierisunity-gain
stable with a 3.6MHz gain bandwidth product and slews at
1.6V/µs. The current limit circuits operate with a 2MHz re-
sponse between the VCSRC or VCSNK control inputs and
the amplifier output.
■
Open Collector Status Flags:
Sink Current Limit
Source Current Limit
Thermal Shutdown
■
Fail Safe Current Limit and Thermal Shutdown
■
1.6V/µs Slew Rate
3.6MHz Gain Bandwidth Product
■
■
Fast Current Limit Response: 2MHz Bandwidth
■
Specified Temperature Range: –40°C to 85°C
■
Available in a 20-Lead TSSOP Package
Open collector status flags signal current limit circuit
activation,aswellasthermalshutdownoftheamplifier.An
enable logic input puts the amplifier into a low power, high
impedance output state when pulled low. Thermal shut-
down and a ±800mA fixed current limit protect the chip
under fault conditions.
U
APPLICATIO S
■
Automatic Test Equipment
Laboratory Power Supplies
■
■
Motor Drivers
■
Thermoelectric Cooler Driver
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
The LT1970 is packaged in a 20-lead TSSOP package with
a thermally conductive copper bottom plate to facilitate
heat sinking.
U
TYPICAL APPLICATIO
A = 2 Amplifier with Adjustable ±500mA Full-Scale
V
Current Limit and Fault Indication
Current Limited Sinewave Into 10Ω Load
V
LIMIT
0V TO 5V
15V
15V
3k
V
LIMIT
10 • R
I
=
±
OUT(LIMIT)
V
CC
CS
+
V
4V
EN
VC
2V
SRC
VC
V
+IN
IN
VLOAD
SNK
ISNK
R
CS
0V
1Ω
I
ISRC
OUT
1/4W
–2V
TSD
+
LT1970
OUT
SENSE
–
SENSE
V
–
LOAD
R1
–IN
COMMON
V
EE
10k
VCSRC = 4V
VCSNK = 2V
RCS = 1Ω
20µs/DIV
1970 TA02
R2
10k
–15V
1970 TA01
1970fb
1
LT1970
W W U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
ORDER PART
TOP VIEW
Supply Voltage (VCC to VEE).................................... 36V
Positive High Current Supply (V+) .................. V– to VCC
Negative High Current Supply(V–) ................... VEE to V+
Amplifier Output (OUT)..................................... V– to V+
Current Sense Pins
NUMBER
V
1
2
20
19
18
17
16
15
14
13
12
11
V
V
EE
–
EE
+
V
21
LT1970CFE
LT1970IFE
OUT
3
TSD
+
SENSE
4
ISNK
(SENSE+, SENSE–, FILTER) .......................... V– to V+
Logic Outputs (ISRC, ISNK, TSD)....... COMMON to VCC
Input Voltage (–IN, +IN).......... VEE – 0.3V to VEE + 36V
Input Current ....................................................... 10mA
Current Control Inputs
FILTER
5
ISRC
–
+
–
SENSE
6
ENABLE
COMMON
V
7
CC
–IN
+IN
8
VC
SRC
9
VC
SNK
V
10
V
EE
EE
(VCSRC, VCSNK) .............COMMON to COMMON + 7V
Enable Logic Input .............................. COMMON to VCC
COMMON ..................................................... VEE to VCC
Output Short-Circuit Duration......................... Indefinite
Operating Temperature Range (Note 2) .. –40°C to 85°C
Specified Temperature Range (Note 3)... –40°C to 85°C
Maximum Junction Temperature ......................... 150°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
FE PACKAGE
20-LEAD PLASTIC TSSOP
TJMAX = 150°C, θJA = 40°C/ W (NOTE 8)
EXPOSED PAD (PIN 21) IS CONNECTED TO VEE
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The
●
denotes specifications which apply over the full operating
temperature range, otherwise specifications are T = 25°C. See Test Circuit for standard test conditions.
A
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Op Amp Characteristics
V
Input Offset Voltage
200
600
1000
1300
µV
µV
µV
OS
0°C < T < 70°C
●
●
A
–40°C < T < 85°C
A
Input Offset Voltage Drift (Note 4)
Input Offset Current
●
●
●
–10
–100
–600
–4
10
µV/°C
nA
I
I
V
V
= 0V
= 0V
100
OS
CM
CM
Input Bias Current
–160
3
nA
B
Input Noise Voltage
0.1Hz to 10Hz
1kHz
µV
P-P
e
Input Noise Voltage Density
Input Noise Current Density
Input Resistance
15
3
nV/√Hz
pA/√Hz
n
i
1kHz
n
R
Common Mode
Differential Mode
500
100
kΩ
kΩ
IN
C
V
Input Capacitance
Pin 8 and Pin 9 to Ground
6
pF
IN
Input Voltage Range
Typical
Guaranteed by CMRR Test
–14.5
–12.0
13.6
12.0
V
V
CM
●
●
CMRR
PSRR
Common Mode Rejection Ratio
Power Supply Rejection Ratio
–12V < V < 12V
92
105
dB
CM
–
+
V
V
V
V
= V = –5V, V = V = 3V to 30V
●
●
●
●
90
110
90
100
130
100
130
dB
dB
dB
dB
EE
EE
EE
EE
CC
–
+
= V = –5V, V = 30V, V = 2.5V to 30V
CC
–
+
= V = –3V to –30V, V = V = 5V
CC
–
+
= –30V, V = –2.5V to –30V, V = V = 5V
110
CC
1970fb
2
LT1970
ELECTRICAL CHARACTERISTICS
The
●
denotes specifications which apply over the full operating
temperature range, otherwise specifications are T = 25°C. See Test Circuit for standard test conditions.
A
SYMBOL
PARAMETER
CONDITIONS
R = 1k, –12.5V < V < 12.5V
OUT
MIN
TYP
MAX
UNITS
A
Large-Signal Voltage Gain
100
75
150
V/mV
V/mV
VOL
L
●
●
●
●
R = 100Ω, –12.5V < V
< 12.5V
80
40
120
45
V/mV
V/mV
L
OUT
+
–
R = 10Ω, –5V < V
L
< 5V, V = –V = 8V
20
5
V/mV
V/mV
OUT
–
V
V
Output Sat Voltage Low
Output Sat Voltage High
Output Short-Circuit Current
V
= V
– V
OUT
OL
OH
OL
+
–
R = 100, V = V = 15V, V = V = –15V
1.9
0.8
2.5
2.3
V
V
L
CC
EE
+
–
R = 10, V = –V = 15V, V = –V = 5V
L
CC
EE
+
V
= V – V
OUT
OH
+
–
R = 100, V = V = 15V, V = V = –15V
●
1.7
1.0
V
V
L
CC
EE
+
–
R = 10, V = –V = 15V, V = –V = 5V
L
CC
EE
I
Output Low, R
Output High, R
= 0Ω
SENSE
SENSE
500
–1000
800
–800
1200
–500
mA
mA
SC
= 0Ω
SR
Slew Rate
–10V < V
< 10V, R = 1k
0.7
11
1.6
V/µs
kHz
MHz
µs
OUT
L
FPBW
GBW
Full Power Bandwidth
Gain Bandwidth Product
Settling Time
V
= 10V
(Note 5)
OUT
PEAK
f = 10kHz
0.01%, V
3.6
8
t
= 0V to 10V, A = –1, R = 1k
S
OUT
V
L
Current Sense Characteristics
V
Minimum Current Sense Voltage
VC
= VC
= 0V
0.1
0.1
4
7
10
mV
mV
SENSE(MIN)
SRC
SNK
●
●
●
V
V
V
Current Sense Voltage 4% of Full Scale
Current Sense Voltage 10% of Full Scale
VC
VC
= VC
= VC
= VC
= 0.2V
= 0.5V
= 5V
15
45
20
50
25
55
mV
mV
SENSE(4%)
SENSE(10%)
SENSE(FS)
SRC
SRC
SRC
SNK
SNK
SNK
Current Sense Voltage 100% of Full Scale VC
490
480
500
500
510
520
mV
mV
●
●
●
●
I
I
I
I
Current Limit Control Input Bias Current
VC , VC Pins
SNK
–1
–0.2
0.1
500
500
µA
nA
nA
BI
SENSE
FILTER
SRC
–
–
SENSE Input Current
0V < (VC , VC ) < 5V
–500
–500
SRC
SNK
FILTER Input Current
0V < (VC , VC ) < 5V
SRC SNK
+
+
SENSE Input Current
VC = VC
VC
VC = 0V, VC
VC
= 0V
●
●
●
●
–500
200
–300
500
300
–200
25
nA
µA
µA
µA
SENSE
SRC
SRC
SNK
= 5V, VC
= 0V
= 5V
250
–250
SNK
SNK
SRC
= VC
= 5V
–25
SRC
SRC
SRC
SNK
SNK
SNK
Current Sense Change with Output Voltage VC
= VC
= 5V, –12.5V < V
< 12.5V
±0.1
%
OUT
+
Current Sense Change with Supply Voltage VC
= VC
= 5V, 6V < (V , V ) < 18V
±0.05
±0.01
±0.05
±0.01
%
%
%
%
CC
+
2.5V < V < 18V, V = 18V
–18V < (V , V ) < –2.5V
–18V < V < –2.5V, V = –18V
CC
–
EE
–
EE
Current Sense Bandwidth
2
MHz
–
R
CSF
Resistance FILTER to SENSE
●
750
1000
1250
Ω
Logic I/O Characteristics
Logic Output Leakage ISRC, ISNK, TSD
Logic Low Output Level
V = 15V
●
●
1
µA
V
I = 5mA (Note 6)
0.2
25
0.4
Logic Output Current Limit
Enable Logic Threshold
mA
V
V
●
●
0.8
–1
1.9
2.5
1
ENABLE
I
Enable Pin Bias Current
µA
ENABLE
1970fb
3
LT1970
ELECTRICAL CHARACTERISTICS
The
●
denotes specifications which apply over the full operating
temperature range, otherwise specifications are T = 25°C. See Test Circuit for standard test conditions.
A
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
7
MAX
13
UNITS
mA
mA
mA
µs
+
–
I
I
I
t
t
Total Supply Current
Supply Current
V
V
V
, V and V , V Connected
●
●
●
SUPPLY
CC
CC
CC
CC
EE
+
–
V
, V and V , V Separate
3
7
CC
EE
+
–
Supply Current Disabled
Turn-On Delay
, V and V , V Connected, V ≤ 0.8V
ENABLE
0.6
10
10
1.5
CC(STBY)
ON
EE
(Note 7)
(Note 7)
Turn-Off Delay
µs
OFF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT1970C is guaranteed functional over the operating
temperature range of –40°C and 85°C.
Note 4: This parameter is not 100% tested.
Note 5: Full power bandwidth is calculated from slew rate measurements:
FPBW = SR/(2 • π • V )
P
Note 6: The logic low output level of pin TSD is guaranteed by correlating
the output level of pin ISRC and pin ISNK over temperature.
Note 7: Turn-on and turn-off delay are measured from V
crossing
ENABLE
Note 3: The LT1970C is guaranteed to meet specified performance from
0°C to 70°C. The LT1970C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but is not tested or QA
sampled at these temperatures. The LT1970I is guaranteed to meet
specified performance from –40°C to 85°C.
1.6V to the OUT pin at 90% of normal output voltage.
Note 8: Thermal resistance varies depending upon the amount of PC board
metal attached to the device. If the maximum dissipation of the package is
exceeded, the device will go into thermal shutdown and be protected.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Total Supply Current
vs Supply Voltage
Warm-Up Drift V vs Time
Input Bias Current vs V
CM
IO
–100
–120
–140
–160
–180
–200
–220
–240
–260
14
12
10
8
6
4
V
= ±15V
S
+
I
+ I
125°C
25°C
CC
V
–I
BIAS
–55°C
–55°C
2
0
+I
BIAS
–
I
+ I
EE
V
–2
–4
–6
–8
–10
–12
–14
0V
25°C
TIME (100ms/DIV)
1970 G01
125°C
–15 –12 –9 –6 –3
0
3
6
9
12 15
0
2
4
6
8
10 12 14 16 18
SUPPLY VOLTAGE (±V)
COMMON MODE INPUT VOLTAGE (V)
1970 G03
1970 G02
1970fb
4
LT1970
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Open-Loop Gain and Phase
Supply Current vs Supply Voltage
vs Frequency
Phase Margin vs Supply Voltage
70
60
50
40
100
90
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
60
58
56
54
52
50
48
46
44
42
40
+
A
= –1
V
I
V
R = R = 1k
F
G
–
I
T
= 25°C
V
A
80
V
= V /2
S
GAIN
PHASE
OUT
70
I
VCC
30
20
60
50
I
VEE
10
0
40
30
20
10
0
–10
–20
–30
T
= 25°C
CC
A
+
–
V
= V = –V = –V
EE
0
100
1k
10k 100k
1M
10M 100M
2
4
6
8
10 12
20
0
4
8
12 16 20 24 28 32 36
14 16 18
FREQUENCY (Hz)
SUPPLY VOLTAGE (±V)
TOTAL SUPPLY VOLTAGE (V)
1970 G05
1870 G04
1970 G06
Gain Bandwidth vs Supply Voltage
Gain vs Frequency
Gain vs Frequency with C
LOAD
10
0
10
0
5
V
A
= ±15V
= 1
A
V
= 100
A = 1
V
S
V
30nF
10nF
4
3
1nF
V
= ±15V
S
–10
–20
–30
–40
–10
V
= ±5V
S
0nF
–20
–30
–40
2
1
0
10k
100k
1M
10M
0
4
8
12 16 20 24 28 32 36
10k
100k
1M
10M
FREQUENCY (Hz)
TOTAL SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
1970 G09
1970 G08
1970 G07
Output Impedance
Disabled Output Impedance
Slew Rate vs Supply Voltage
600k
100k
100
10
1.8
V
V
= ±15V
ENABLE
V
S
= ±15V
S
= 0.8V
1.7
1.6
FALLING
RISING
A
= 100
V
10k
1k
1.5
1.4
1.3
1.2
1.1
1
A
= 10
V
0.1
A
V
= 1
100
10
1
0.01
0.001
A
= –1
V
F
R
= R = 1k
G
T
A
= 25°C
1.0
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
6
8
12
14
16
18
4
10
FREQUENCY (Hz)
FREQUENCY (Hz)
SUPPLY VOLTAGE (±V)
1970 G10
1970 G11
1970 G12
1970fb
5
LT1970
TYPICAL PERFOR A CE CHARACTERISTICS
U W
Large-Signal Response, A = –1
Slew Rate vs Temperature
Large-Signal Response, A = 1
V
V
2.5
2.0
1.5
1.0
0.5
0
V
= ±15V
S
FALLING
10V
0V
10V
RISING
0V
–10V
–10V
R
L = 1k
20µs/DIV
1970 G15
RL = 1k
20µs/DIV
1970 G14
CL = 1000pF
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
1970 G13
Small-Signal Response, A = 1
Small-Signal Response, A = –1
Output Overdriven
V
V
VOUT
0V
0V
5V/DIV
VIN
5V/DIV
VS = ±5V
AV = 1
200µs/DIV
1970 G18
RL = 1k
500ns/DIV
1970 G16
RL = 1k
CL = 1000pF
2µs/DIV
1970 G17
Full Range Current Sense
Transfer Curve
Undistorted Output Swing
vs Frequency
% Overshoot vs C
LOAD
30
25
20
15
10
5
60
50
40
30
20
10
0
500
400
V
S
= ±15V
300
SOURCING
CURRENT
A
= 1
V
200
100
0
A
= –1
V
–100
–200
–300
–400
–500
SINKING
CURRENT
V
A
= ±15V
S
V
= –5
1% THD
0
100
1k
10k
100k
10
100
1k
10k
0
1
2
3
4
5
FREQUENCY (Hz)
C
LOAD
(pF)
V
CSNK
= V
CSRC
(V)
1970 G20
1970 G19
1970 G21
1970fb
6
LT1970
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Low Level Current Sense
Transfer Curve
Logic Output Level
Maximum Output Current
vs Sink Current (Output Low)
vs Temperature
25
20
1.0
0.9
0.8
0.7
1600
1400
1200
1000
800
600
400
200
0
+
–
+
–
V
V
= 15V
= –15V
V
V
= 15V
= –15V
15
SOURCING
CURRENT
10
SOURCE
SINK
5
0.6
0.5
25°C
0
125°C
–5
–10
–15
–20
–25
0.4
0.3
0.2
0.1
0
SINKING
CURRENT
–55°C
0
25 50 75 100 125 150 175 200 225 250
0.001
0.01
0.1
1
10
100
–75 –50
25 50
–25
0
75 100
125
V
CSNK
= V
CSRC
(mV)
SINK CURRENT (mA)
TEMPERATURE (°C)
1970 G23
1970 G22
1970 G24
Output Stage Quiescent Current
vs Supply Voltage
Safe Operating Area
1200
1000
800
600
400
200
0
10
8
I
AT 10% DUTY CYCLE
OUT
+
125°C
I
V
6
25°C
4
–55°C
2
0
–
I
V
–55°C
–2
–4
–6
–8
–10
25°C
125°C
25 30
10 15 20
SUPPLY VOLTAGE (V)
0
5
35 40
0
2
4
6
8
10 12 14 16 18
SUPPLY VOLTAGE (±V)
1970 G25
1970 G26
Control Stage Quiescent Current
vs Supply Voltage
Supply Current vs Supply Voltage
in Shutdown
5
4
800
700
600
500
400
300
200
100
0
V
= 0V
I
ENABLE
CC
85°C
125°C
25°C
–55°C
3
25°C
2
–55°C
1
0
I
EE
–1
–2
–3
–4
–5
–55°C
25°C
125°C
8
10
0
2
4
6
12 14 16 18
0
2
4
6
8
10 12 14 16 18
SUPPLY VOLTAGE (±V)
SUPPLY VOLTAGE (V)
1970 G27
1970 G28
1970fb
7
LT1970
U
U
U
PI FU CTIO S
VEE (Pins 1, 10, 11, 20, Package Base): Minus Supply
Voltage. VEE connects to the substrate of the integrated
circuitdie,andthereforemustalwaysbethemostnegative
voltage applied to the part. Decouple VEE to ground with a
low ESR capacitor. VEE may be a negative voltage or it may
equal ground potential. Any or all of the VEE pins may be
used. Unused VEE pins must remain open.
V– (Pin 2): Output Stage Negative Supply. V– may equal
VEE or may be smaller in magnitude. Only output stage
current flows out of V–, all other current flows out of VEE.
V– may be used to drive the base/gate of an external power
device to boost the amplifier’s output current to levels
above the rated 500mA of the on-chip output devices.
Unless used to drive boost transistors, V– should be
decoupled to ground with a low ESR capacitor.
FILTER (Pin 5): Current Sense Filter Pin. This pin is
normallynotusedandshouldbeleftopenorshortedtothe
SENSE– pin. The FILTER pin can be used to adapt the
response time of the current sense amplifiers with a 1nF
to 100nF capacitor connected to the SENSE– input. An
internal 1k resistor sets the filter time constant.
SENSE– (Pin 6): Negative Current Sense Pin. This pin is
normally connected to the load end of the external sense
resistor. Sourcing current limit operation is activated
when the voltage VSENSE (VSENSE+ – VSENSE–) equals 1/
10 of the programming control voltage at VCSRC (Pin 13).
Sinking current limit operation is activated when the
voltage VSENSE equals –1/10 of the programming control
voltage at VCSNK (Pin 12).
VCC (Pin 7): Positive Supply Voltage. All circuitry except
the output transistors draw power from VCC. Total supply
voltage from VCC to VEE must be between 3.5V and 36V.
VCC mustalwaysbegreaterthanorequaltoV+. VCCshould
always be decoupled to ground with a low ESR capacitor.
OUT (Pin 3): Amplifier Output. The OUT pin provides the
force function as part of a Kelvin sensed load connection.
OUT is normally connected directly to an external load
current sense resistor and the SENSE+ pin. Amplifier
feedback is directly connected to the load and the other
end of the current sense resistor. The load connection is
also wired directly to the SENSE– pin to monitor the load
current.
–IN (Pin 8): Inverting Input of Amplifier. –IN may be any
voltage from VEE – 0.3V to VEE + 36V. –IN and +IN remain
highimpedanceatalltimestopreventcurrentflowintothe
inputs when current limit mode is active. Care must be
taken to insure that –IN or +IN can never go to a voltage
The OUT pin is current limited to ±800mA typical. This
current limit protects the output transistor in the event below VEE – 0.3V even during transient conditions or
thatconnectionstotheexternalsenseresistorareopened damage to the circuit may result. A Schottky diode from
or shorted which disables the precision current limit VEE to –IN can provide clamping if other elements in the
function.
circuit can allow –IN to go below VEE.
SENSE+ (Pin 4): Positive Current Sense Pin. This lead is
normally connected to the driven end of the external sense
resistor. Sourcing current limit operation is activated
when the voltage VSENSE (VSENSE+ – VSENSE–) equals 1/
10 of the programming control voltage at VCSRC (Pin 13).
Sinking current limit operation is activated when the
voltage VSENSE equals –1/10 of the programming control
voltage at VCSNK (Pin 12).
+IN (Pin 9): Noninverting Input of Amplifier. +IN may be
any voltage from VEE – 0.3V to VEE + 36V. –IN and +IN
remain high impedance at all times to prevent current flow
into the inputs when current limit mode is active. Care
must be taken to insure that –IN or +IN can never go to a
voltage below VEE – 0.3V even during transient conditions
or damage to the circuit may result. A Schottky diode from
VEE to +IN can provide clamping if other elements in the
circuit can allow +IN to go below VEE.
1970fb
8
LT1970
U
U
U
PI FU CTIO S
VCSNK (Pin 12): Sink Current Limit Control Voltage Input.
The current sink limit amplifier will activate when the
sense voltage between SENSE+ and SENSE– equals
–1.0 • VVCSNK/10. VCSNK may be set between VCOMMON
and VCOMMON + 6V. The transfer function between VCSNK
and VSENSE is linear except for very small input voltages at
VCSNK < 60mV. VSENSE limits at a minimum set point of
4mV typical to insure that the sink and source limit
amplifiers do not try to operate simultaneously. To force
zero output current, the ENABLE pin can be taken low.
current limit is not active. ISRC, ISNK and TSD may be
wired “OR” together if desired. ISRC may be left open if
this function is not monitored.
ISNK (Pin 17): Sinking Current Limit Digital Output Flag.
ISNK is an open collector digital output. ISNK pulls low
whenever the sinking current limit amplifier assumes
control of the output. This pin can sink up to 10mA of
current. The current limit flag is off when the source
current limit is not active. ISRC, ISNK and TSD may be
wired “OR” together if desired. ISNK may be left open if
this function is not monitored.
VCSRC (Pin 13): Source Current Limit Control Voltage
Input. The current source limit amplifier will activate
when the sense voltage between SENSE+ and SENSE–
equals VVCSRC/10. VCSRC may be set between VCOMMON
and VCOMMON + 6V. The transfer function between VCSRC
and VSENSE is linear except for very small input voltages
at VCSRC < 60mV. VSENSE limits at a minimum set point
of 4mV typical to insure that the sink and source limit
amplifiers do not try to operate simultaneously. To force
zero output current, the ENABLE pin can be taken low.
TSD (Pin 18): Thermal Shutdown Digital Output Flag. TSD
isanopencollectordigitaloutput. TSDpullslowwhenever
theinternalthermalshutdowncircuitactivates, typicallyat
a die temperature of 160°C. This pin can sink up to 10mA
of output current. The TSD flag is off when the die
temperature is within normal operating temperatures.
ISRC, ISNK and TSD may be wired “OR” together if
desired. ISNK may be left open if this function is not
monitored. Thermal shutdown activation should prompt
the user to evaluate electrical loading or thermal environ-
mental conditions.
V+ (Pin 19): Output Stage Positive Supply. V+ may equal
VCC or may be smaller in magnitude. Only output stage
current flows through V+, all other current flows into VCC.
V+ maybeusedtodrivethebase/gateofanexternalpower
device to boost the amplifier’s output current to levels
above the rated 500mA of the on-chip output devices.
Unless used to drive boost transistors, V+ should be
decoupled to ground with a low ESR capacitor.
COMMON (Pin 14): Control and ENABLE inputs and flag
outputs are referenced to the COMMON pin. COMMON
may be at any potential between VEE and VCC – 3V. In
typical applications, COMMON is connected to ground.
ENABLE (Pin 15): ENABLE Digital Input Control. When
taken low this TTL-level digital input turns off the amplifier
output and drops supply current to less than 1mA. Use the
ENABLE pin to force zero output current. Setting VCSNK
VCSRC = 0V allows IOUT = ±4mV/RSENSE to flow in or out
of VOUT
=
.
ISRC (Pin 16): Sourcing Current Limit Digital Output Flag.
ISRC is an open collector digital output. ISRC pulls low
whenever the sourcing current limit amplifier assumes
control of the output. This pin can sink up to 10mA of
current. The current limit flag is off when the source
Package Base: The exposed backside of the package is
electrically connected to the VEE pins on the IC die. The
package base should be soldered to a heat spreading pad
on the PC board that is electrically connected to VEE.
1970fb
9
LT1970
W U
BLOCK DIAGRA A D TEST CIRCUIT
R
V
FB
CC
+
7
1k
V
15V
19
+IN
9
8
+
–
Q1
Q2
OUT
+
V
IN
1×
GM1
3
–
–IN
R
G
1k
10k
10k
10k
ISNK
ISRC
TSD
17
16
18
–
+
D1
D2
R
1Ω
CS
+
–
I
V
SINK
SNK
SRC
+
SENSE
FILTER
15V
4
5
6
ENABLE
+
–
V
ENABLE
15
12
–
SENSE
VC
SNK
5V
VC
SNK
–
+
R
FIL
1k
R
–
VC
SRC
LOAD
V
I
SRC
VC
1k
13
14
SRC
2
V
COMMON
EE
–15V
2, 10, 11, 20
1970TC
W U U
U
APPLICATIO S I FOR ATIO
The LT1970 power op amp with precision controllable
current limit is a flexible voltage and current source
module. The drawing on the front page of this data sheet
is representative of the basic application of the circuit,
however many alternate uses are possible with proper
understanding of the subcircuit capabilities.
between –IN and +IN. No current will flow at the inputs
when differential input voltage is present. This feature is
important when the precision current sense amplifiers
“ISINK” and “ISRC” become active.
Current Limit Amplifiers
Amplifierstages“ISINK”and“ISRC”areveryhightranscon-
ductanceamplifierstageswithindependentlycontrolledoff-
setvoltages.Theseamplifiersmonitorthevoltagebetween
input pins SENSE+ and SENSE– which usually sense the
voltage across a small external current sense resistor. The
transconductance amplifiers outputs connect to the same
high impedance node as the main input stage GM1 ampli-
fier.SmallvoltagedifferencesbetweenSENSE+andSENSE–
, smallerthantheusersetVCSNK/10andVCSRC/10inmag-
nitude, cause the current limit amplifiers to decouple from
the signal path. This is functionally indicated by diodes D1
and D2 in the Block Diagram. When the voltage VSENSE
increasesinmagnitudesufficienttoequalorovercomeone
oftheoffsetvoltagesVCSNK/10orVCSRC/10, theappropri-
ate current limit amplifier becomes active and because of
1970fb
CIRCUIT DESCRIPTION
Main Operational Amplifier
Subcircuit block GM1, the 1X unity-gain current buffer
and output transistors Q1 and Q2 form a standard opera-
tionalamplifier.Thisamplifierhas±500mAcurrentoutput
capability and a 3.6MHz gain bandwidth product. Most
applicationsoftheLT1970willusethisopampinthemain
signalpath.Allconventionalopampcircuitconfigurations
are supported. Inverting, noninverting, filter, summation
or nonlinear circuits may be implemented in a conven-
tional manner. The output stage includes current limiting
at ±800mA to protect against fault conditions. The input
stage has high differential breakdown of 36V minimum
10
LT1970
W U U
APPLICATIO S I FOR ATIO
U
itsveryhightransconductance,takescontrolfromtheinput
The transfer function from VC to the associated VOS is
linear from about 0.1V to 5V in, or 10mV to 500mV at the
current limit amplifier inputs. An intentional nonlinearity
is built into the transfer functions at low levels. This non-
linearity insures that both the sink and source limit ampli-
fierscannotbecomeactivesimultaneously.Simultaneous
activation of the limit amplifiers could result in uncon-
trolled outputs. As shown in the Typical Performance
Characteristics curves, the control inputs have a “hockey
stick” shape, to keep the minimum limit threshold at 4mV
for each limit amplifier.
stage, GM1. The output current is regulated to a value of
I
OUT = VSENSE/RSENSE = (VCSRC or VCSNK)/(10 • RSENSE).
The time required for the current limit amplifiers to take
control of the output is typically 4µs.
Linear operation of the current limit sense amplifier oc-
curs with the inputs SENSE+ and SENSE– ranging be-
tween VCC – 1.5V and VEE + 1.5V. Most applications will
connect pins SENSE+ and OUT together, with the load on
the opposite side of the external sense resistor and pin
SENSE–.FeedbacktotheinvertinginputofGM1shouldbe
connected from SENSE– to –IN. Ground side sensing of
load current may be employed by connecting the load
between pins OUT and SENSE+. Pin SENSE– would be
connected to ground in this instance. Load current would
be regulated in exactly the same way as the conventional
connection. However, voltage mode accuracy would be
Figure 1 illustrates an interesting use of the current sense
input pins. Here the current limit control amplifiers are
used to produce a symmetrically limited output voltage
swing. Instead of monitoring the output current, the
output voltage is divided down by a factor of 20 and
applied to the SENSE+ input, with the SENSE– input
grounded. When the threshold voltage between SENSE+
and SENSE– (VCLAMP/10) is reached, the current limit
stagetakescontroloftheoutputandclampsitalevelof±2
• VCLAMP. With control inputs VCSRC and VCSNK tied
together, a single polarity input voltage sets the same +
and – output limit voltage for symmetrical limiting. In this
circuit the output will current limit at the built-in fail-safe
level of typically 800mA.
degraded in this case due to the voltage across RSENSE
.
Creative applications are possible where pins SENSE+ and
SENSE– monitor a parameter other than load current. The
operating principle that at most one of the current limit
stages may be active at one time, and that when active, the
current limit stages take control of the output from GM1,
can be used for many different signals.
Current Limit Threshold Control Buffers
Input pins VCSNK and VCSRC are used to set the response
thresholds of current limit amplifiers “ISINK” and “ISRC”.
Each of these inputs may be independently driven by a
voltage of 0V to 5V above the COMMON reference pin. The
0V to 5V input voltage is attenuated by a factor of 10 and
applied as an offset to the appropriate current limit ampli-
fier. AC signals may be applied to these pins. The AC
bandwidth from a VC pin to the output is typically 2MHz.
For proper operation of the LT1970, these control inputs
cannot be left floating.
12V
80mV
TO
V
CLAMP
R3
3k
10V
OV TO 5V
–80mV
TO
–10V
±CLAMP
VC
SRC
VC
REACHED
SNK
OUTPUT CLAMPS
EN
AT 2× V
CLAMP
+IN
V
IN
V
CC
+
V
ISRC
ISNK
TSD
+
OUT
LT1970
SENSE
–
R1
21.5k
SENSE
FILTER
R
L
–
V
–IN
For low VCC supply applications it is important to keep the
maximum input control voltages, VCSRC and VCSNK, at
least 2.5V below the VCC potential. This ensures linear
controlofthecurrentlimitthreshold.Reducingthecurrent
limit sense resistor value allows high output current from
a smaller control voltage which may be necessary if the
VCC supply is only 5V.
V
R2
1.13k
EE
COMMON
–12V
R
R
F
G
1970 F01
Figure 1. Symmetrical Output Voltage Limiting
1970fb
11
LT1970
W U U
U
APPLICATIO S I FOR ATIO
indicate activation of the associated current limit ampli-
fier. The TSD output indicates excessive die temperature
has caused the circuit to enter thermal shutdown. The
three digital outputs may be wire “OR’d” together, moni-
tored individually or left open. These outputs do not affect
circuit operation, but provide an indication of the present
operational status of the chip.
ENABLE Control
The ENABLE input pin puts the LT1970 into a low supply
current, high impedance output state. The ENABLE pin
responds to TTL threshold levels with respect to the
COMMONpin.PullingtheENABLEpinlowisthebestway
toforcezerocurrentattheoutput.SettingVCSNK =VCSRC
= 0V allows the output current to remain as high as
Forslowvaryingoutputsignals,theassertionofalowlevel
at the current limit output flags occurs when the current
limit threshold is reached. For fast moving signals where
the LT1970 output is moving at the slew limit, typically
1.6V/µs, the flag assertion can be somewhat premature at
typically 75% of the actual current limit value.
±4mV/RSENSE
.
In applications such as circuit testers (ATE), it may be
preferable to apply a predetermined test voltage with a
preset current limit to a test node simultaneously. The
ENABLE pin can be used to provide this gating action as
shown in Figure 2. While the LT1970 is disabled, the load
is essentially floating and the input voltage and current
limit control voltages can be set to produce the load test
levels. Enabling the LT1970 then drives the load. The
LT1970enablesanddisablesinjustafewmicroseconds.
The actual enable and disable times at the load are a
function of the load reactance.
The operating status flags are designed to drive LEDs to
provide a visual indication of current limit and thermal
conditions. As such, the transition edges to and from the
activelowstatearenotparticularlysharpandmayexhibit
some uncertainty. Adding some positive feedback to the
current limit control inputs helps to sharpen these
transitions.
Operating Status Flags
With the values shown in Figure 3, the current limit
threshold is reduced by approximately 0.5% when either
current limit status flag goes low. With sharp logic transi-
tions, the status outputs can be used in a system control
The LT1970 has three digital output indicators; TSD, ISRC
and ISNK. These outputs are open collector drivers re-
ferredtotheCOMMONpin.Theoutputshave36Vcapabili-
ties and can sink in excess of 10mA. ISRC and ISNK
ENABLE
5V
V
OUT
DISABLE
0V
1V/DIV
0V
5V
12V
EN
10V/DIV
VC
SRC
VC
0V
SNK
V
IN
= 0.5V
V
= –0.5V
IN
EN
+IN
V
V
CC
IN
5µs/DIV
+
V
ISRC
R
S
ISNK
1Ω
TSD
OUT
LT1970
+
SENSE
–
R
L
SENSE
10Ω
FILTER
–
V
–IN
V
EE
COMMON
R
R
F
10k
–12V
G
10k
1970 F02
Figure 2. Using the ENABLE pin
1970fb
12
LT1970
W U U
APPLICATIO S I FOR ATIO
U
loop to take protective measures when a current limit
initially sets a high value of current limit (500mA). The
circuitoperatesnormallyuntilthesignalislargeenoughto
entercurrentlimit. Wheneithercurrentlimitflaggoeslow,
the current limit control voltage is reduced by a factor of
10. This then forces a low level of output current (50mA)
until the signal is reduced in magnitude. When the load
current drops below the lower level, the current limit is
then restored to the higher value. This action is similar to
a self resettable fuse that trips at dangerously high current
levels and resets only when conditions are safe to do so.
condition is detected automatically.
The current limit status flag can also be used to produce
a dramatic change in the current limit value of the ampli-
fier. Figure 4 illustrates a “snap-back” current limiting
characteristic. In this circuit, a simple resistor network
R1
100Ω
R3
20k
CURRENT
LIMIT
CONTROL
VOLTAGE
(0.1V TO 5V)
I
I
FLAG
SOURCE
R2
100Ω
R4
20k
FLAG
SINK
12V
THERMAL MANAGEMENT
WHEN CURRENT LIMIT
VC
SRC
IS FLAGGED, I
LIMIT
TRESHOLD IS REDUCED
BY 0.5%
VC
SNK
EN
Minimizing Power Dissipation
+IN
V
IN
V
CC
+
V
ISRC
ISNK
The LT1970 can operate with up to 36V total supply
voltage with output currents up to ±500mA. The amount
ofpowerdissipatedinthechipcouldapproach18Wunder
worst-case conditions. This amount of power will cause
die temperature to rise until the circuit enters thermal
shutdown. While the thermal shutdown feature prevents
damage to the circuit, normal operation is impaired.
Thermal design of the LT1970 operating environment is
essential to getting maximum utility from the circuit.
R
S
1Ω
TSD
+
OUT
LT1970
SENSE
–
SENSE
FILTER
R
L
–
V
–IN
V
EE
COMMON
–12V
R
G
R
F
1970 F03
The first concern for thermal management is minimizing
the heat which must be dissipated. The separate power
pins V+ and V– can be a great aid in minimizing on-chip
power. The output pin can swing to within 1.0V of V+ or V–
even under maximum output current conditions. Using
separate power supplies, or voltage regulators, to set V+
Figure 3. Adding Positive Feedback to Sharpen the Transition
Edges of the Current Limit Status Flags
12V
R1
54.9k
R2
39.2k
R3
2.55k
VC
SRC
VC
SNK
500mA
EN
I
MAX
+IN
V
IN
V
CC
+
V
ISRC
ISNK
50mA
0
I
LOW
R
S
I
OUT
1Ω
TSD
+
OUT
LT1970
SENSE
–
–500mA
SENSE
R
L
FILTER
V
–
V
CC
• R2
(R1 + R2) • 10 • R
–IN
V
I
I
≈
≈
EE
MAX
S
COMMON
V
• (R2||R3)
CC
[R1 + (R2||R3)] • 10 • R
LOW
S
R
R
F
10k
G
–12V
10k
1970 F04
Figure 4. “Snap-Back” Current Limiting
1970fb
13
LT1970
W U U
U
APPLICATIO S I FOR ATIO
and V– to their minimum values for the required output
swing will minimize power dissipation. The supplies VCC
and VEE may also be reduced to a minimal value, but these
supply pins do not carry high currents, and the power
saving is much less. VCC and VEE must be greater than the
maximum output swing by 1.5V or more.
very effective. Expanding the area on various layers sig-
nificantly reduces the overall thermal resistance. The
addition of vias (small 13 mil holes which fill during PCB
plating) connecting all layers of metal also helps reduce
the operating temperature of the LT1970. These are also
shown in Figure 5.
WhenV– andV+ areprovidedseparatelyfromVCC andVEE,
care must be taken to insure that V– and V+ are always less
than or equal to the main supplies in magnitude. Protec-
tion Schottky diodes may be required to insure this in all
cases, including power on/off transients.
OperationwithreducedV+ andV– suppliesdoesnotaffect
any performance parameters except maximum output
swing.AllDCaccuracyandACperformancespecifications
guaranteed with VCC = V+ and VEE = V– are still valid with
the reduced output signal swing range.
It is important to note that the metal planes used for heat
sinking are connecting electrically to VEE. These planes
must be isolated from any other power planes used in the
PCB design.
Another effective way to control the power amplifier oper-
ating temperature is to use airflow over the board. Airflow
can significantly reduce the total thermal resistance as
also shown in Figure 5.
DRIVING REACTIVE LOADS
Capacitive Loads
Heat Sinking
The power dissipated in the LT1970 die must have a path
to the environment. With 100°C/W thermal resistance in
free air with no heat sink, the package power dissipation is
limited to only 1W. The 20-pin TSSOP package with
exposed copper underside is an efficient heat conductor if
it is effectively mounted on a PC board. Thermal resis-
tances as low as 40°C/W can be obtained by soldering the
bottom of the package to a large copper pattern on the PC
board. For operation at 85°C, this allows up to 1.625W of
power to be dissipated on the LT1970. At 25°C operation,
up to 3.125W of power dissipation can be achieved. The
PC board heat spreading copper area must be connected
to VEE.
The LT1970 is much more tolerant of capacitive loading
thanmostoperationalamplifiers. Inaworst-caseconfigu-
ration as a voltage follower, the circuit is stable for capaci-
tive loads less than 2.5nF. Higher gain configurations
improve the CLOAD handling. If very large capacitive loads
are to be driven, a resistive decoupling of the amplifier
fromthecapacitiveloadiseffectiveinmaintainingstability
and reducing peaking. The current sense resistor, usually
connected between the output pin and the load can serve
as a part of the decoupling resistance.
Inductive Loads
Load inductance is usually not a problem at the outputs of
operational amplifiers, but the LT1970 can be used as a
high output impedance current source. This condition
may be the main operating mode, or when the circuit
entersaprotectivecurrentlimitmode. Justasloadcapaci-
tance degrades the phase margin of normal op amps, load
inductance causes a peaking in the loop response of the
feedback controlled current source. The inductive load
maybecausedbylongleadlengthsattheamplifieroutput.
If the amplifier will be driving inductive loads or long lead
lengths (greater than 4 inches) a 500pF capacitor from the
SENSE– pin to the ground plane will cancel the inductive
Figure5showsexamplesofPCBmetalbeingusedforheat
spreading. These are provided as a reference for what
might be expected when using different combinations of
metalareaondifferentlayersofaPCB.Theseexamplesare
with a 4-layer board using 1oz copper on each layer. The
most effective layers for spreading heat are those closest
to the LT1970 junction. Soldering the exposed thermal
padoftheTSSOPpackagetotheboardproducesathermal
resistancefromjunction-to-caseofapproximately3°C/W.
Asaminimum, theareadirectlybeneaththepackageonall
PCB layers can be used for heat spreading. However,
limiting the area to that of the metal heat sinking pad is not
load and ensure stability.
1970fb
14
LT1970
W U U
APPLICATIO S I FOR ATIO
U
STILL AIR θ
PACKAGE
TOP LAYER
2ND LAYER
3RD LAYER
BOTTOM LAYER
JA
TSSOP
100°C/W
TSSOP
50°C/W
TSSOP
45°C/W
1970 F05a
Typical Reduction in θ with
JA
Laminar Airflow Over the Device
0
–10
–20
–30
–40
–50
–60
% REDUCTION RELATIVE
TO θ IN STILL AIR
JA
0
100 200 300 400 500 600 700 800 900 1000
AIRFLOW (LINEAR FEET PER MINUTE, lfpm)
1970 F05b
Figure 5. Examples of PCB Metal Used for Heat Dissipation. Driver Package Mounted on Top
Layer. Heat Sink Pad Soldered to Top Layer Metal. Metal Areas Drawn to Scale of Package Size
1970fb
15
LT1970
W U U
U
APPLICATIO S I FOR ATIO
Figure 6 shows the LT1970 driving an inductive load with
a controlled amount of current. This load is shown as a
generic magnetic transducer, which could be used to
create and modulate a magnetic field. Driving the current
limit control inputs directly forces a current through the
load that could range up to 2MHz in modulation. Biasing
the input stage to the midpoint of the modulation signal
allows symmetrical bidirectional current flow through the
load.ClampdiodesareaddedtoprotecttheLT1970output
from large inductive flyback potentials caused by rapid
di/dt changes.
Figure 7 shows the connection of these back-to-back
clampdiodesbetweentheFILTERpinandtheSENSE+ pin.
With this connection, the internal 1k resistor between the
SENSE– pin and the FILTER pin limits the diode current.
The BAV99 diodes are small SOT-23 packaged general
purpose silicon diodes. The maximum current limit sense
voltage is now the diode voltage drop, determined by the
voltage across the sense resistor and the 1k internal
resistor. As the diode begins to conduct current, with a
voltage drop of around 300mV, an error in the expected
current limit level at the high end of the control becomes
Abrupt Load Short Protection
R
SENSE
MAIN
AMPLIFIER
OUT
3
An abrupt short-circuit connection, often referred to as
screwdriver or crowbar short, to ground or other supply
potentialsistheworst-caseloadconditionfortheLT1970.
The current limit sense amplifier normally operates with
an input voltage differential equal to the voltage across the
sense resistor, which is only 500mV maximum in a typical
application. During an abrupt load short to ground, the
load end of the sense resistor is immediately connected to
ground while the amplifier output remains at the normal
outputvoltage. Thiscanimposealargedifferentialvoltage
to the sense amplifier inputs for a brief period. If this delta
V can be greater than ±2V, it is beneficial to add clamps
between the current limit sense amplifier inputs. These
clamps ensure a smooth transition from the main ampli-
fier control to the current limit amplifier control under all
load short conditions that may arise.
LOAD
CURRENT
LIMIT SENSE
AMPLIFIER
3
+
SENSE
BAV99
+
–
4
5
1
2
FILTER
100Ω*
1nF TO 10nF
–
1k
SENSE
6
+
SENSE
*OPTIONAL—SEE TEXT
2N3904
2N3904
FILTER
1970 F07
HIGHER CLAMP VOLTAGE
ALTERNATIVE
Figure 7. Adding Protection for Abrupt Load Shorts
5V
V
IN
12V
0V
VC
SRC
VC
SNK
D1
EN
1N4001
+IN
V
CC
+
V
ISRC
ISNK
R
1Ω
S
±500mA
TSD
+
OUT
LT1970
12V
SENSE
–
MAGNETIC
TRANSDUCER
R1
95.3K
SENSE
FILTER
V
2.5V
–
–IN
V
EE
LT1634-2.5
D2
1N4001
COMMON
1970 F06
C1
500pF
–12V
Figure 6. Current Modulation of a Magnetic Transducer
1970fb
16
LT1970
W U U
APPLICATIO S I FOR ATIO
U
apparent, asVDIODE islessthanthevoltageacrossRSENSE
.
current limit amplifier to go to the incorrect current limit
direction and hang up. Adding a small filter capacitor
between the SENSE– and FILTER pins, 1nF to 10nF is fairly
typical, which charges through the clamp diodes forces
the correct current limit polarity at the instant of the load
short. This holds the amplifier in current limit until the
capacitor discharges through the internal 1k resistor,
eliminating transient induced behavior and creating a
smooth transition into current limit.
Adding an optional external 100Ω resistor in parallel with
the internal 1k resistor forces the diode voltage closer to
the sensed current limit voltage and reduces the current
limit error.
Alternatively, the base-emitter junctions of back-to-back
2N3904NPNtransistorscanprovidethisclampingaction.
These diodes begin to conduct at a higher voltage level
nearer to 600mV. With a 500mV maximum current limit
threshold very little error will be noticed. Comparisons of
typical current limit error with three ways of adding
clamping protection are shown in Figure 8. Scaling the
currentsenseresistorandthecurrentlimitcontrolvoltage
down so that a 0V to 300mV current limit sense voltage
range also prevents these accuracy errors caused by the
abrupt-short clamping diodes.
Supply Bypassing
The LT1970 can supply large currents from the power
suppliestoaloadatfrequenciesupto4MHz.Powersupply
impedance must be kept low enough to deliver these
currents without causing supply rails to droop. Low ESR
capacitors, such as 0.1µF or 1µF ceramics, located close
to the pins are essential in all applications. When large,
high speed transient currents are present additional ca-
pacitance may be needed near the chip. Check supply rails
with a scope and if signal related ripple is seen on the
supply rail, increase the decoupling capacitor as needed.
Also shown in Figure 7 is a small filtering capacitor. This
too provides an extra measure of control under abrupt
load shorting conditions. A fast short-circuit makes ap-
parentallparasiticinterconnectleadinductancesbetween
the LT1970 and the load. These distributed parasitic
elements can cause significant transient voltage spikes in
the short time after the application or removal of a short
circuit. These uncontrolled voltage transients could actu-
ally couple back to the current limit amplifier and cause
polarity reversal from sourcing current limit to sinking or
vice versa. This can act as positive feedback and cause the
To ensure proper start-up biasing of the LT1970, it is
recommended that the rate of change of the supply volt-
ages at turn-on be limited to be no faster than 6V/µs.
Application Circuit Ideas
The digitally controlled analog pin driver is shown in
Figure 9. All of the control signals are provided by an
LTC®1664 quad, 10-bit DAC by way of a 3-wire serial
interface. The LT1970 is configured as a simple difference
amplifier with a gain of 3. This gain is required to produce
±15V from the 0V to 5V outputs from DACs C and D. To
providevoltageheadroom,thesuppliesfortheLT1970are
settothemaximumvalueof±18V. As±18Vistheabsolute
maximum rating of supply voltage for the LT1970, care
must be taken to not allow the supply voltage to increase.
DACs A and B separately control the sinking and sourcing
current limit to the load over the range of ±4mA to
±500mA. An optional ON/OFF control for the pin driver
using the ENABLE input is shown. If always enabled the
ENABLE pin should be tied to VCC.
25
20
BAV99 w 1kΩ
15
10
BAV99 w 100Ω
5
0
2N3904 w 1kΩ
–5
–10
50
200
300 350 400 450 500
100 150
250
±V SENSE (mV)
CL
1970 F08
Figure 8. Current Limit Accuracy with Different Clamps
1970fb
17
LT1970
W U U
U
APPLICATIO S I FOR ATIO
OPTIONAL TEST PIN
ON/OFF CONTROL
APPLY LOAD
DRIVE
5V
Hi-Z
0V
5V
CODE C – CODE D
V
= 15V
≈ ±15V
OUT
(
)
1024
V
CLR
V
CC
REF
0.5 • CODE B
I
I
=
≈ –4mA TO –500mA
≈ 4mA TO 500mA
SOURCE(MAX)
1024 • R
S
DAC A
0.5 • CODE A
=
SINK(MAX)
1024 • R
S
18V
+
3-WIRE
DAC B
DAC C
R5
R6
3k
10µF
0.1µF
SERIAL
3k
INTERFACE
CS/LD
SCK
DI
DECODER
VC
SRC
VC
R1
SNK
3.4k
EN
+IN
V
CC
+
V
R2
10.2k
ISRC
ISNK
R
S
1Ω
FORCE
TSD
+
OUT
LT1970
SENSE
–
TEST PIN
LOAD
SENSE
R3
3.4k
FILTER
V
–
DAC D
–IN
V
EE
COMMON
SENSE
10µF
0.1µF
+
–18V
R4
10.2k
LTC1664
QUAD 10-BIT DAC
1970 F09
Figure 9. Digitally Controlled Analog Pin Driver
Insomeapplicationsitmaybenecessarytoknowwhatthe
current into the load is at any time. Figure 10 shows an
LT1787 high side current sense amplifier monitoring the
current through sense resistor RS. The LT1787 is biased
from the VEE supply to accommodate the common mode
input range of ±10V. The sense resistor is scaled down to
provide a 100mV maximum differential signal to the
current sense amplifier to preserve linearity. The LT1880
amplifier provides gain and level shifting to produce a 0V
to 5V output signal (2.5V DC ±5mV/mA) with up to 1kHz
full-scale bandwidth. An A/D converter could then digitize
this instantaneous current reading to provide digital feed-
back from the circuit.
TheLT1970isjustaseasytouseasastandardoperational
amplifier. Basic amplification of a precision reference
voltage creates a very simple bench DC power supply as
shown in Figure 11. The built-in power stage produces an
adjustable 0V to 25V at 4mA to 100mA of output current.
Voltage and current adjustments are derived from the
LT1634-5 5V reference. The output current capability is
500mA, but this supply is restricted to 100mA for power
dissipation reasons. The worst-case output voltage for
maximum power dissipated in the LT1970 output stage
occurs if the output is shorted to ground or set to a voltage
near zero. Limiting the output current to 100mA sets the
maximum power dissipation to 3W. To allow the output to
1970fb
18
LT1970
W U U
APPLICATIO S I FOR ATIO
U
V
CC
0V TO 1V
12V
VC
SRC
VC
SNK
EN
+IN
V
CC
+
V
ISRC
ISNK
R
S
0.2Ω
TSD
+
OUT
LT1970
SENSE
–
SENSE
R
LOAD
FILTER
V
–
–IN
V
EE
COMMON
R4
LT1787
255k
–
+
V
V
V
S
–12V
S
BIAS
R
R
F
G
–12V
12V
R1
60.4k
20k
–
V
EE
OUT
R2
10k
2.5V
LT1880
–12V
±5mV/mA
+
R3
20k
1kHz FULL CURRENT
BANDWIDTH
–12V
0V TO 5V
A/D
1970 F10
OPTIONAL DIGITAL FEEDBACK
Figure 10. Sensing Output Current
30V DC
R2 40k
R1
2.1k
CURRENT LIMIT
ADJUST
R5
5.49k
R3
10k
R4 10k
LOAD
FAULT
OUTPUT
VOLTAGE
ADJUST
VC
SRC
VC
SNK
EN
+IN
V
CC
+
V
ISRC
R
1Ω
S
ISNK
V
OUT
TSD
+
0V TO 25V
OUT
LT1970
LT1634-5
SENSE
–
4mA TO 100mA
+
C3
10µF
SENSE
FILTER
–
V
–IN
V
EE
GND
COMMON
–5V
LTC1046
C2
10µF
+
+
R
R
G
F
2.55k
10.2k
C1 10µF
1970 F11
Figure 11. Simple Bench Power Supply
1970fb
19
LT1970
W U U
U
APPLICATIO S I FOR ATIO
range all the way to 0V, an LTC1046 charge pump inverter
is used to develop a –5V supply. This produces a negative
rail for the LT1970 which has to sink only the quiescent
current of the amplifier, typically 7mA.
Using a second LT1970, a 0V to ±12V dual tracking power
supply is shown in Figure 12. The midpoint of two 10k
resistors connected between the + and – outputs is held at
0V by the LT1881 dual op amp servo feedback loop. To
R6
18.2k
15V
+
R7
3k
R8
3k
0.1
10µF
+OUT
CURRENT FAULT
LIMIT
THERMAL
VC
SRC
VC
R5
13k
SNK
EN
–IN
V
CC
+
V
ISRC
R
S1
1Ω
ISNK
+OUT
TSD
+
0V TO 12V
4mA TO 150mA
OUT
LT1970
+
SENSE
–
C2
10µF
SENSE
FILTER
–
V
+IN
V
EE
COMMON
18V
R1
R9
10k
1%
5V
C1
1µF
6.19k
REF
–15V
V
OUT
ADJUST
R3
23.2k
R2
10k
R4
10k
15V
+
–
LT1634-5
OPTIONAL SYMMETRY
ADJUST
–
+
CURRENT
R11
10k
1/2 LT1881
LIMIT
100Ω
ADJUST
1/2 LT1881
–15V
R12
10k
GROUND
R13
25.5k
15V
R15
3k
R10
10k
1%
TO TSD PIN
OF +OUT
–OUT
CURRENT
LIMIT
VC
SRC
VC
R14
10.7k
SNK
EN
–IN
V
CC
+
V
ISRC
ISNK
R
S2
1Ω
–OUT
TSD
0V TO –12V
4mA TO 150mA
OUT
+
LT1970
C3
SENSE
–
+
10µF
SENSE
FILTER
–
V
+IN
V
EE
1970 F12
COMMON
10µF
0.1µF
+
–15V
Figure 12. Dual Tracking Bench Power Supply
1970fb
20
LT1970
W U U
APPLICATIO S I FOR ATIO
U
maintain 0V, both outputs must be equal and opposite in
polarity, thus they track each other. If one output reaches
current limit and drops in voltage, the other output follows
to maintain a symmetrical + and – voltage across a
common load. Again, the output current limit is less than
the full capability of the LT1970 due to thermal reasons.
Separate current limit indicators are used on each LT1970
because one output only sources current and the other
only sinks current. Both devices can share the same
thermal shutdown indicator, as the output flags can be
OR’ed together.
the desired speed-set input voltage. Because the LT1970
is unity-gain stable, it can be configured as an integrator
to force whatever voltage across the motor as necessary
to match the feedback speed signal with the set input
signal.
Additionally, the current limit of the amplifier can be
adjusted to control the torque and stall current of the
motor. For reliability, a feedback scheme similar to that
shown in Figure 4 can be used. Assuming that a stalled
rotor will generate a current limit condition, the stall
currentlimitcanbesignificantlyreducedtopreventexces-
sive power dissipation in the motor windings.
Another simple linear power amplifier circuit is shown in
Figure 13. This uses the LT1970 as a linear driver of a DC
motor with speed control. The ability to source and sink
the same amount of output current provides for bidirec-
tional rotation of the motor. Speed control is managed by
sensing the output of a tachometer built on to the motor.
Atypicalfeedbacksignalof3V/1000rpmiscomparedwith
For motor speed control without using a tachometer, the
circuit in Figure 14 shows an approach. Using the enable
feature of the LT1970, the drive to the motor can be
removed periodically. With no drive applied, the spinning
motor presents a back EMF voltage proportional to its
rotational speed. The LT1782 is a tiny rail-to-rail amplifier
OV TO 5V
TORQUE/STALL
CURRENT CONTROL
15V
VC
SRC
VC
SNK
EN
+IN
V
CC
+
V
ISRC
R
S
ISNK
1Ω
TSD
+
OUT
LT1970
SENSE
–
SENSE
12V DC
MOTOR
FILTER
V
–
–IN
V
EE
COMMON
GND
15V
C1
1µF
R1
1.2k
–15V
TACH
FEEDBACK
REVERSE
3V/1000rpm
R4
49.9k
R5
49.9k
1970 F13
R2
10k
FORWARD
R3
1.2k
–15V
Figure 13. Simple Bidirectional DC Motor Speed Controller
1970fb
21
LT1970
W U U
U
APPLICATIO S I FOR ATIO
15V
OV TO 5V
TORQUE/STALL
CURRENT CONTROL
R3
2k
FAULT/STALL
VC
SRC
FWD
R1
10k
5V
STOP
VC
SNK
V
MOTOR SPEED
CONTROL
CC
+IN
+
V
R2
20k
ISRC
0V
REV
R
S
1Ω
ISNK
TSD
+
OUT
LT1970
SENSE
–
SENSE
12V DC
MOTOR
FILTER
V
–
–IN
V
EE
EN
COM
C1
4.7µF
–15V
R14
10k
R4
100k
12V
–
R5
120k
–
+
12V
1/2 LT1638
–12V
100Ω
+
LT1782
–12V
C2
0.01µF
SHDN
R7
10k
R8
20k
R13
10k
R12
10k
+
–
12V
1/2 LT1638
D1
R9
20k
R10
1N4148
82.5k
C3
0.1µF
D2
1N4148
R11
9.09k
1970 F14
–12V
Figure 14. Simple Bidirectional DC Motor Speed Controller Without a Tachometer
compared to the speed-set input voltage, settles the
output to a fixed value. A 0V to 5V signal for the motor
speed input controls both rotational speed and direction.
with a shutdown pin. The amplifier is enabled during this
interval to sample the back EMF voltage across the motor.
Thisvoltageisthenbufferedbyone-halfofanLT1638dual
op amp and used to provide the feedback to the LT1970
integrator. When re-enabled the LT1970 will adjust the
drive to the motor until the speed feedback voltage,
The other half of the LT1638 is used as a simple pulse
oscillator to control the periodic sampling of the motor
back EMF.
1970fb
22
LT1970
U
PACKAGE DESCRIPTIO
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663,
Exposed Pad Variation CA)
6.40 – 6.60*
(.252 – .260)
4.95
(.195)
4.95
(.195)
20 1918 17 16 15 14 1312 11
6.60 ±0.10
2.74
(.108)
4.50 ±0.10
6.40
(.252)
BSC
2.74
(.108)
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
FE20 (CA) TSSOP 0204
0.195 – 0.30
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
1970fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
23
LT1970
W U U
U
APPLICATIO S I FOR ATIO
Figure 15 shows how easy it is to boost the output current
oftheLT1970.This±5Apowerstageusescomplementary
external N- and P-channel MOSFETs to provide the addi-
tional current. The output stage power supply inputs, V+
and V–, are used to provide gate drive as needed. With
higher output currents, the sense resistor RCS, is reduced
in value to maintain the same easy current limit control.
Figure 15 shows some optional resistor dividers between
theoutputconnectionsandthecurrentsenseinputs. They
are required only if the load of this power stage is removed
or at a very low current level. Large power devices with no
load on them can saturate and pull the output voltage very
close to the power supply rails. The current sense ampli-
fiers operate properly with input voltages at least 1V away
from the VCC and VEE supply rails. In boosted current
applications, it may be necessary to attenuate the maxi-
mum output voltage levels by 1V before connecting to the
sense input pins. This only slightly deceases the current
limit thresholds.
This Class B power stage is intended for DC and low
frequency, <1kHz, applications as crossover distortion
becomes evident at higher frequencies.
V
CC
CURRENT LIMIT
CONTROL VOLTAGE
0V TO 5V
15V
R2
100Ω
10µF
0.1µF
IRF9530
V
CC
R1
1k
ENABLE
+IN
VC
SRC
V
C
SNK
R4
+
V
100Ω
OUT
LT1970
+
SENSE
–
R5
100Ω
SENSE
R
CS
COMMON
V
*
*
0.1Ω
–IN
–
5W
V
EE
*
*
R
LOAD
R
F
G
2.2k
2.2k
V
IN
IRF530
R3
100Ω
V
EE
–15V
10µF
0.1µF
*OPTIONAL, SEE TEXT
1970 F15
Figure 15. A = –1 Amplifier with Discrete Power Devices to Boost Output Current to 5A
V
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1010
Fast ±150mA Power Buffer
20MHz Bandwidth, 75V/µs Slew Rate
LT1206
250mA/60MHz Current Feedback Amplifier
1.1A/35MHz Current Feedback Amplifier
Shutdown Mode, Adjustable Supply Current
Stable with C = 10,000pF
LT1210
L
1970fb
LT 0407 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2002
相关型号：
LT1970IFE#TR
LT1970 - 500mA Power Op Amp with Adjustable Precision Current Limit; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C
Linear
LT1970IFE#TRPBF
LT1970 - 500mA Power Op Amp with Adjustable Precision Current Limit; Package: TSSOP; Pins: 20; Temperature Range: -40°C to 85°C
Linear
LT1976BEFE
High Voltage 1.5A, 200kHz Step-Down Switching Regulator with 100μA Quiescent Current
Linear
LT1976BIFE
High Voltage 1.5A, 200kHz Step-Down Switching Regulator with 100μA Quiescent Current
Linear
LT1976BIFE#TR
LT1976/LT1976B - High Voltage 1.5A, 200kHz Step-Down Switching Regulator with 100µA Quiescent Current; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C
Linear
LT1976BIFE#TRPBF
LT1976/LT1976B - High Voltage 1.5A, 200kHz Step-Down Switching Regulator with 100µA Quiescent Current; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C
Linear
LT1976B_15
High Voltage 1.5A, 200kHz Step-Down Switching Regulator with 100A Quiescent Current
Linear
LT1976EFE
High Voltage 1.5A, 200kHz Step-Down Switching Regulator with 100mA Quiescent Current
Linear
LT1976EFE#PBF
LT1976/LT1976B - High Voltage 1.5A, 200kHz Step-Down Switching Regulator with 100µA Quiescent Current; Package: TSSOP; Pins: 16; Temperature Range: -40°C to 85°C
Linear
©2020 ICPDF网 联系我们和版权申明