LT1994IDD#PBF [Linear]
LT1994 - Low Noise, Low Distortion Fully Differential Input/Output Amplifier/Driver; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C;
| 型号： | LT1994IDD#PBF |
| 厂家： | 
Linear |
| 描述： | LT1994 - Low Noise, Low Distortion Fully Differential Input/Output Amplifier/Driver; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C 放大器 光电二极管 |
| 文件： | 总20页 (文件大小：224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT1994
Low Noise, Low Distortion
Fully Differential Input/
Output Amplifier/Driver
FEATURES
DESCRIPTION
TheLT®1994isahighprecision,verylownoise,lowdistor-
tion, fully differential input/output amplifier optimized for
3V,single-supplyoperation.TheLT1994’soutputcommon
mode voltage is independent of the input common mode
voltage, and is adjustable by applying a voltage on the
n
Fully Differential Input and Output
n
Wide Supply Range: 2.375V to 12.6V
n
Rail-to-Rail Output Swing
Low Noise: 3nV/√Hz
n
n
Low Distortion, 2V , 1MHz: –94dBc
P-P
n
n
n
n
n
n
n
n
n
Adjustable Output Common Mode Voltage
V
pin. A separate internal common mode feedback
OCM
Unity-Gain Stable
pathprovidesaccurateoutputphasebalancingandreduced
even-order harmonics. This makes the LT1994 ideal for
level shifting ground referenced signals for driving dif-
ferential input, single-supply ADCs.
Gain-Bandwidth: 70MHz
Slew Rate: 65V/ꢀs
Large Output Current: 85mA
DC Voltage Offset <2mV Max
Open-Loop Gain: 100V/mV
Low Power Shutdown
The LT1994 output can swing rail-to-rail and is capable
of sourcing and sinking up to 85mA. In addition to the
low distortion characteristics, the LT1994 has a low input
referred voltage noise of 3nV/√Hz. This part maintains
its performance for supply voltages as low as 2.375V. It
draws only 13.3mA of supply current and has a hardware
shutdown feature that reduces current consumption to
225μA.
8-Pin MSOP or 3mm × 3mm DFN Package
APPLICATIONS
n
Differential Input A/D Converter Driver
n
Single-Ended to Differential Conversion
n
Differential Amplification with Common Mode
The LT1994 is available in an 8-pin MSOP or 8-pin DFN
package.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Translation
n
Rail-to-Rail Differential Line Driver/Receiver
n
Low Voltage, Low Noise, Differential Signal
Processing
TYPICAL APPLICATION
LT1994 Driving an LTC1403A-1 1MHz
Sine Wave, 8192 Point FFT Plot
A/D Preamplifier: Single-Ended Input to Differential Output
with Common Mode Level Shifting
0
f
f
= 2.8Msps
SAMPLE
IN
–10
–20
= 1.001MHz
499Ω
499Ω
INPUT = 2V
,
3V
P-P
10μF
SINGLE ENDED
SFDR = 93dB
3V
–30
V
P-P
IN
0.1μF
2V
–40
–50
V
SD0
24.9Ω
24.9Ω
DD
+
–60
– +
A
IN
CONV
SCK
–70
V
LT1994
47pF
LTC1403A-1
–
OCM
50.4MHz
–80
0.1μF
+ –
A
IN
–90
V
GND
REF
–100
–110
–120
10μF
1994 TA01
V
= 1.5V
OCM
499Ω
499Ω
0
0.35
0.70
1.05
1.40
FREQUENCY (MHz)
1994 TA01b
1994fb
1
LT1994
ABSOLUTE MAXIMUM RATINGS (Note 1)
+
–
Total Supply Voltage (V to V )..............................12.6V
Specified Temperature Range (Note 5)
Input Voltage (Note 2)............................................... V
LT1994C................................................... 0°C to 70°C
LT1994I................................................ –40°C to 85°C
LT1994H ............................................ –40°C to 125°C
LT1994MP.......................................... –55°C to 125°C
Junction Temperature ........................................... 150°C
Storage Temperature Range................... –65°C to 150°C
S
Input Current (Note 2).......................................... 10mA
Input Current (V , SHDN)................................ 10mA
OCM
V
OCM
, SHDN.............................................................. V
S
Output Short-Circuit Duration (Note 3) ............ Indefinite
Operating Temperature Range (Note 4)
LT1994C............................................... –40°C to 85°C
LT1994I................................................ –40°C to 85°C
LT1994H ............................................ –40°C to 125°C
LT1994MP.......................................... –55°C to 125°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
–
+
IN
1
2
3
4
8
7
6
5
IN
–
+
IN
1
2
3
4
8 IN
V
SHDN
–
OCM
+
V
7 SHDN
OCM
+
–
V
V
V
OUT
6 V
+
–
+
–
5 OUT
OUT
OUT
MS8 PACKAGE
8-LEAD PLASTIC MSOP
DD PACKAGE
8-LEAD (3mm s 3mm) PLASTIC DFN
T
= 150°C, θ = 140°C/W
JA
JMAX
T
= 150°C, θ = 43°C/W
JA
JMAX
–
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO V
ORDER INFORMATION
LEAD FREE FINISH
LT1994CDD#PBF
LT1994IDD#PBF
LT1994HDD#PBF
LT1994MPDD#PBF
LT1994CMS8#PBF
LT1994IMS8#PBF
TAPE AND REEL
PART MARKING*
LBQM
PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
LT1994CDD#TRPBF
LT1994IDD#TRPBF
LT1994HDD#TRPBF
LT1994MPDD#TRPBF
LT1994CMS8#TRPBF
LT1994IMS8#TRPBF
0°C to 70°C
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead (3mm × 3mm) Plastic DFN
8-Lead Plastic MSOP
LBQM
–40°C to 85°C
–40°C to 125°C
–55°C to 125°C
0°C to 70°C
LBQM
LDXQ
LTBQN
LTBQN
8-Lead Plastic MSOP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
1994fb
2
LT1994
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 3V, V– = 0V, VCM = VOCM = VICM = mid-supply, VSHDN = OPEN,
RI = RF = 499Ω, RL = 800Ω to a mid-supply voltage (See Figure 1) unless otherwise noted. VS is defined (V+ – V–). VOUTCM is defined
as (VOUT+ + VOUT–)/2. VICM is defined as (VIN+ + VIN–)/2. VOUTDIFF is defined as (VOUT+ – VOUT–). VINDIFF is defined as (VIN+ – VIN–).
C/I GRADES
TYP
H/MP GRADES
SYMBOL
PARAMETER
CONDITIONS
V = 2.375V, V
MIN
MAX
MIN
TYP
MAX UNITS
l
l
l
l
V
Differential Offset Voltage
(Input Referred)
= V /4
2
2
2
3
2
2
2
3
mV
mV
mV
mV
OSDIFF
S
ICM
ICM
ICM
ICM
S
V = 3V
S
V = 5V
S
V = 5V
S
Differential Offset Voltage Drift
(Input Referred)
V = 2.375V, V
= V /4
3
3
3
3
ꢀV/°C
ꢀV/°C
ꢀV/°C
ꢀV/°C
ΔV /ΔT
OSDIFF
S
S
V = 3V
S
V = 5V
S
V = 5V
S
l
l
l
l
I
Input Bias Current (Note 6)
Input Offset Current (Note 6)
V = 2.375V, V
= V /4
–45
–45
–45
–45
–18
–18
–18
–18
–3
–3
–3
–3
–45
–45
–45
–45
–18
–18
–18
–18
–3
–3
–3
–3
ꢀA
ꢀA
ꢀA
ꢀA
B
S
S
V = 3V
S
V = 5V
S
V = 5V
S
l
l
l
l
I
OS
V = 2.375V, V
= V /4
0.2
0.2
0.2
0.2
2
2
3
4
0.2
0.2
0.2
0.2
2
2
3
4
ꢀA
ꢀA
ꢀA
ꢀA
S
S
V = 3V
S
V = 5V
S
V = 5V
S
R
Input Resistance
Input Capacitance
Common Mode
700
4.5
700
4.5
kΩ
kΩ
IN
Differential Mode
C
Differential
f = 50kHz
2
3
2
3
pF
IN
e
Differential Input Referred Noise
Voltage Density
nV/√Hz
n
i
Input Noise Current Density
f = 50kHz
2.5
15
2.5
15
pA/√Hz
nV/√Hz
n
e
Input Referred Common Mode Output f = 50kHz, V
Noise Voltage Density
Shorted to Ground
OCM
nVOCM
l
l
V
Input Signal Common Mode Range
V = 3V
S
0
–5
1.75
3.75
0
–5
1.75
3.75
V
V
ICMR
S
(Note 7)
V = 5V
l
l
l
l
CMRRI
Input Common Mode Rejection Ratio
55
65
69
45
85
85
55
65
69
45
85
85
dB
dB
dB
dB
V = 3V, ΔV
= 0.75V
= 2V
S
ICM
(Note 8)
(Input Referred) ΔV /ΔV
ICM OSDIFF
CMRRIO
(Note 8)
Output Common Mode Rejection Ratio
(Input Referred) ΔV /ΔV
V = 5V, ΔV
S
OCM
OCM
OSDIFF
PSRR
(Note 9)
Differential Power Supply Rejection
(ΔV /ΔV
V = 3V to 5V
S
105
70
105
70
)
OSDIFF
S
PSRRCM
(Note 9)
Output Common Mode Power Supply
Rejection (ΔV /ΔV
V = 3V to 5V
S
)
OSCM
S
l
l
G
V = 2.5V
1
V/V
%
Common Mode Gain (ΔV
/ΔV
OUTCM
)
OCM
CM
S
Common Mode Gain Error
V = 2.5V
S
–0.15
1
100 • (G – 1)
CM
BAL
Output Balance (ΔV
/ΔV
OUTCM
)
ΔV
= 2V
OUTDIFF
OUTDIFF
l
l
–65
–71
–46
–50
–65
–71
–46
–50
dB
dB
Single-Ended Input
Differential Input
l
l
l
l
V
Common Mode Offset Voltage
(V – V
V = 2.375V, V
= V /4
2.5
2.5
2.5
2.5
25
25
30
40
2.5
2.5
2.5
2.5
25
25
30
40
mV
mV
mV
mV
OSCM
S
ICM
S
)
V = 3V
OUTCM
OCM
S
V = 5V
S
V = 5V
S
1994fb
3
LT1994
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 3V, V– = 0V, VCM = VOCM = VICM = mid-supply, VSHDN = OPEN,
RI = RF = 499Ω, RL = 800Ω to a mid-supply voltage (See Figure 1) unless otherwise noted. VS is defined (V+ – V–). VOUTCM is defined
as (VOUT+ + VOUT–)/2. VICM is defined as (VIN+ + VIN–)/2. VOUTDIFF is defined as (VOUT+ – VOUT–). VINDIFF is defined as (VIN+ – VIN–).
C/I GRADES
TYP
H/MP GRADES
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
MIN
TYP
MAX UNITS
Common Mode Offset Voltage Drift
V = 2.375V, V
= V /4
5
5
5
5
5
5
5
5
ꢀV/°C
ꢀV/°C
ꢀV/°C
ꢀV/°C
ΔV
/ΔT
OSCM
S
ICM
S
V = 3V
S
V = 5V
S
V = 5V
S
–
+
–
+
l
V
Output Signal Common Mode Range
V = 3V, 5V
S
V +
V
V +
V
V
OUTCMR
(Note 7)
(Voltage Range for the V
Pin)
1.1
– 0.8
1.1
– 0.8
OCM
l
l
R
Input Resistance, V
Pin
30
40
60
30
40
60
kΩ
INVOCM
OCM
V
MID
V
OUT
Voltage at the V
Pin
V = 5V
2.45
2.5
2.55
2.45
2.5
2.55
V
OCM
S
l
l
l
Output Voltage, High, Either Output Pin V = 3V, No Load
(Note 10)
70
90
200
140
175
400
70
90
200
140
175
400
mV
mV
mV
S
V = 3V, R = 800Ω
S L
V = 3V, R = 100Ω
S
L
l
l
l
V = 5V, No Load
150
200
900
325
450
2400
150
200
900
325
450
2400
mV
mV
mV
S
V = 5V, R = 800Ω
S
L
V = 5V, R = 100Ω
S
L
l
l
l
Output Voltage, Low, Either Output Pin V = 3V, No Load
30
50
125
70
90
250
30
50
125
70
90
250
mV
mV
mV
S
(Note 10)
V = 3V, R = 800Ω
S L
V = 3V, R = 100Ω
S
L
l
l
l
V = 5V, No Load
80
125
900
180
250
2400
80
125
900
180
250
2400
mV
mV
mV
S
V = 5V, R = 800Ω
S
L
V = 5V, R = 100Ω
S
L
l
l
l
l
I
SC
Output Short-Circuit Current, Either
Output Pin (Note 11)
25
30
40
45
35
40
65
85
10
15
40
45
35
40
65
85
mA
mA
mA
mA
V = 2.375V, R = 10Ω
S
L
V = 3V, R = 10Ω
S
L
V = 5V, R = 10Ω
S
L
V = 5V, V = 0V, R = 10Ω
S
CM
L
+
–
l
l
SR
Slew Rate
50
50
65
65
85
85
50
50
65
65
85
85
V/ꢀS
V/ꢀS
V = 5V, ΔV
= –ΔV
= 1V
OUT
S
OUT
V = 5V, V = 0V,
S
CM
+
–
ΔV
= –ΔV
= 1.8V
OUT
OUT
l
l
GBW
Gain-Bandwidth Product
TEST
V = 3V, T = 25°C
S CM A
58
58
70
70
58
58
70
70
MHz
MHz
S
A
(f
= 1MHz)
V = 5V, V = 0V, T = 25°C
Distortion
V = 3V, R = 800Ω, f = 1MHz,
S
L
IN
+
–
V
– V
= 2V
P-P
OUT
OUT
Differential Input
2nd Harmonic
3rd Harmonic
–99
–96
–99
–96
dBc
dBc
Single-Ended Input
2nd Harmonic
3rd Harmonic
–94
–108
–94
–108
dBc
dBc
t
S
Settling Time
V = 3V, 0.01%, 2V Step
S
120
90
120
90
ns
ns
S
V = 3V, 0.1%, 2V Step
A
Large-Signal Voltage Gain
Supply Voltage Range
Supply Current
V = 3V
100
100
dB
V
VOL
S
l
V
2.375
12.6 2.375
12.6
S
l
l
l
I
V = 3V
13.3
13.9
14.8
18.5
19.5
20.5
13.3
13.9
14.8
20.0
20.5
21.5
mA
mA
mA
S
S
V = 5V
S
V = 5V
S
l
l
l
I
Supply Current in Shutdown
V = 3V
0.225
0.8
0.225
0.8
mA
mA
mA
SHDN
S
V = 5V
0.375 1.75
0.375 1.75
S
V = 5V
0.7
2.5
0.7
2.5
S
1994fb
4
LT1994
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 3V, V– = 0V, VCM = VOCM = VICM = mid-supply, VSHDN = OPEN,
RI = RF = 499Ω, RL = 800Ω to a mid-supply voltage (See Figure 1) unless otherwise noted. VS is defined (V+ – V–). VOUTCM is defined
as (VOUT+ + VOUT–)/2. VICM is defined as (VIN+ + VIN–)/2. VOUTDIFF is defined as (VOUT+ – VOUT–). VINDIFF is defined as (VIN+ – VIN–).
C/I GRADES
TYP
H/MP GRADES
SYMBOL
PARAMETER
CONDITIONS
V = 3V to 5V
MIN
MAX
MIN
TYP
MAX UNITS
+
+
l
l
V
SHDN Input Logic Low
V
V
– 2.1
V
IL
S
– 2.1
+
+
V
SHDN Input Logic High
V = 3V to 5V
S
V
V
V
IH
– 0.6
– 0.6
R
SHDN Pull-Up Resistor
Turn-On Time
V = 2.375V to 5V
40
55
1
75
40
55
1
75
kΩ
ꢀs
ꢀs
SHDN
S
t
t
V
SHDN
V
SHDN
0.5V to 3V
3V to 0.5V
ON
OFF
Turn-Off Time
1
1
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 7: Input Common Mode Range is tested using the Test Circuit of
Figure 1 (R = R ) by applying a single ended 2V , 1kHz signal to V
INP
F
I
P-P
(V
INM
= 0), and measuring the output distortion (THD) at the common
mode Voltage Range limits listed in the Electrical Characteristics table,
and confirming the output THD is better than –40dB. The voltage range for
the output common mode range (Pin 2) is tested using the Test Circuit of
Figure 1 (R = R ) by applying a 0.5V peak, 1kHz signal to the V
Note 2: The inputs are protected by a pair of back-to-back diodes. If the
differential input voltage exceeds 1V, the input current should be limited to
less than 10mA.
F
I
OCM
Pin 2 (with V = V = 0) and measuring the output distortion (THD)
Note 3: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefinitely.
Note 4: The LT1994C/LT1994I are guaranteed functional over the
operating temperature range –40°C to 85°C. The LT1994H is guaranteed
functional over the operating temperature range –40°C to 125°C. The
LT1994MP is guaranteed functional over the operating temperature range
–55°C to 125°C.
Note 5: The LT1994C is guaranteed to meet specified performance from
0°C to 70°C. The LT1994C is designed, characterized, and expected to
meet specified performance from –40°C to 85°C but is not tested or
QA sampled at these temperatures. The LT1994I is guaranteed to meet
specified performance from –40°C to 85°C. The LT1994H is guaranteed
to meet specified performance from –40°C to 125°C. The LT1994MP is
guaranteed to meet specified performance from –55°C to 125°C.
INP
INM
at V
with V
biased 0.5V from the V
pin range limits listed
OUTCM
OCM
OCM
in the Electrical Characteristics Table, and confirming the THD is better
than –40dB.
Note 8: Input CMRR is defined as the ratio of the change in the input
+
–
common mode voltage at the pins IN or IN to the change in differential
input referred voltage offset. Output CMRR is defined as the ratio of the
change in the voltage at the V
referred voltage offset.
pin to the change in differential input
OCM
Note 9: Differential Power Supply Rejection (PSRR) is defined as the ratio
of the change in supply voltage to the change in differential input referred
voltage offset. Common Mode Power Supply Rejection (PSRRCM) is
defined as the ratio of the change in supply voltage to the change in the
common mode offset, V
– V
.
OUTCM
OCM
Note 10: Output swings are measured as differences between the output
and the respective power supply rail.
Note 11: Extended operation with the output shorted may cause junction
temperatures to exceed the 150°C limit and is not recommended.
Note 6: Input bias current is defined as the average of the input currents
–
+
flowing into Pin 1 and Pin 8 (IN and IN ). Input Offset current is defined
as the difference of the input currents flowing into Pin 8 and Pin 1
+
–
(I = I – I ).
OS
B
B
1994fb
5
LT1994
TYPICAL PERFORMANCE CHARACTERISTICS
Differential Input Referred
Voltage Offset vs Temperature
Common Mode Voltage Offset vs
Temperature
Input Bias Current and Input
Offset Current vs Temperature
500
250
0
7.5
5.0
2.5
0
–10
–15
–20
–25
–30
1.0
0.5
0
V
V
V
= 3V
V
V
V
= 3V
S
S
= 1.5V
= 1.5V
= 1.5V
= 1.5V
CM
OCM
CM
OCM
I , V
S
= 5V
B
FOUR TYPICAL UNITS
FOUR TYPICAL UNITS
I
, V = 3V
S
OS
I
OS
, V
=
5V
S
–250
–0.5
–500
–750
I , V = 3V
B
S
–2.5
–1.0
–50
0
25
50
75
100
–25
–50
0
25
50
75
100
–50
0
25
50
75
100
–25
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
1994 G01
1994 G02
1994 G03
Frequency Response vs
Supply Voltage
Frequency Response vs
Load Capacitance
Gain Bandwidth vs Temperature
2
1
2
1
72
71
70
69
68
67
66
R
= R = 499Ω
I
R
= R = 499Ω
F I
F
V
= 2.5V
S
V
= 3V
= 2.5V
V
S
S
V
=
5V
S
V
= 5V
S
V
= 3V
V
S
= 3V
S
0
0
V
= 5V
S
–1
–2
–1
–2
5pF FROM EACH
OUTPUT TO GROUND
25pF FROM EACH
OUTPUT TO GROUND
0.1
1
10
100
0.1
1
10
100
–50
0
25
50
75
100
–25
FREQUENCY (MHz)
FREQUENCY (MHz)
TEMPERATURE (°C)
1994 G05
1994 G06
1994 G04
Differential Power Supply
Rejection vs Frequency
Output Impedance vs Frequency
Output Balance vs Frequency
100
10
1
–30
–40
–50
–60
–70
–80
–90
110
100
90
80
70
60
50
40
30
20
10
0
V
= 3V
I
$V
$V
$V
S
F
OUTCM
S
R
= R = 499Ω
$V
OUTDIFF
OSDIFF
+
V
SUPPLY
–
V
SUPPLY
SINGLE-ENDED INPUT
DIFFERENTIAL INPUT
V
= 3V
V = 3V
S
S
0.1
0.1
1
10
100
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (MHz)
FREQUENCY (Hz)
FREQUENCY (Hz)
1995 G08
1995 G09
1994 G07
1994fb
6
LT1994
TYPICAL PERFORMANCE CHARACTERISTICS
Input Common Mode Rejection vs
Frequency
Common Mode Output Power
Supply Rejection vs Frequency
Input Noise vs Frequency
100
90
80
70
60
50
40
30
60
50
40
30
20
10
0
100
10
1
100
10
1
$V
$V
V
T
= 3V
= 25°C
ICM
S
S
A
V
= 3V
S
–
$V
$V
V
SUPPLY
OSDIFF
OSOCM
V
= p5V
S
+
V
SUPPLY
e
n
i
n
V
= 3V
S
1k
10k
100k
1M
10M
100M
0.1
1
10
100
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (MHz)
FREQUENCY (Hz)
1995 G10
1995 G11
1995 G12
Differential Distortion vs Input
Amplitude (Single-Ended Input)
Differential Distortion vs Input
Common Mode Level
Differential Distortion vs
Frequency
–60
–40
–50
–60
–70
–80
–90
–40
–50
–60
–70
–80
–90
V
f
= 3V
V
V
f
= 3V
V
V
f
= 3V
S
S
S
= 1MHz
= 2V (SINGLE ENDED)
= 2V (SINGLE ENDED)
IN
IN
= 1MHz
P-P
IN
= 1MHz
P-P
R
= R = 499Ω
F
I
IN
F
L
IN
F
L
–70
–80
R
V
= 800Ω
R
R
V
= R = 499Ω
R
R
V
= R = 499Ω
L
I
I
= MID-SUPPLY
= 800Ω
= 800Ω
OCM
= MID-SUPPLY
= MID-SUPPLY
OCM
= MID-SUPPLY
ICM
OCM
V
2ND, V
–
= 1.5V
ICM
3RD
2ND, V = V
CM
–90
2ND
2ND
3RD
–
3RD, V = V
CM
–100
–110
–100
–110
–100
–110
3RD, V
3
= 1.5V
4
ICM
)
1
5
2
0
0.5
1.5
2.0
2.5
1.0
100k
1M
10M
–
+
V
(V
INPUT COMMON MODE DC BIAS, IN OR IN PINS (V)
FREQUENCY (Hz)
IN P-P
1994 G13
1994 G14
1994 G15
Slew Rate vs Temperature
2V Step Response Settling
68
R
= R = 499Ω
I
F
66
64
62
60
V
= 3V
+0.1%
S
ERROR
V
OUT
V
= 5V
S
–0.1%
ERROR
V
= 3V
S
F
R
= R = 499Ω
I
–50
0
25
50
75
100
–25
25ns/DIV
TEMPERATURE (°C)
1994 G17
1994 G16
1994fb
7
LT1994
TYPICAL PERFORMANCE CHARACTERISTICS
Large-Signal Step Response
Small-Signal Step Response
Output with Large Input Overdrive
25pF LOAD
V
= 3V
V
R
= 3V
S
F
S
F
+
OUT
= R = 499Ω
I
R
= R = 499Ω
I
–
V
= V
CM
+
OUT
+
OUT
0pF LOAD
V
= 3V
I
S
F
R
= R = 499Ω
V
= 100mV
,
P-P
IN
SINGLE ENDED
–
OUT
–
OUT
–
OUT
V
IN
= 3V SINGLE ENDED
P-P
V
= 10V SINGLE ENDED
P-P
IN
20ns/DIV
100ns/DIV
2μs/DIV
1994 G18
1994 G19
1994 G20
Supply Current vs Supply Voltage
Supply Current vs SHDN Voltage
Supply Current vs SHDN Voltage
20
15
10
5
16
12
8
16
12
8
+
V
S
= 3V
V
= 3V
SHDN PIN VOLTAGE = V
S
T
= 85°C
A
T
= –40°C
T
= –40°C
T
= 85°C
A
T = 85°C
A
A
A
T
= –40°C
A
T
= 0°C
A
T
T
= 0°C
T
T
= 0°C
A
A
T
= 25°C
A
T
= 70°C
T
= 70°C
A
A
= 25°C
T
= 70°C
= 25°C
A
A
A
4
4
0
0
0
0
5.0
7.5
10.0
12.5
2.5
0
0.5
1.5
2.0
2.5
3.0
1.0
0
0.5
1.5
2.0
2.5
3.0
1.0
SUPPLY VOLTAGE (V)
SHDN PIN VOLTAGE (V)
SHDN PIN VOLTAGE (V)
1994 G21
1994 G23
1994 G23
SHDN Pin Current vs SHDN
Pin Voltage
Shutdown Supply Current vs
Supply Voltage
0
–10
–20
–30
1000
V
= 3V
S
T
= –40°C
A
750
500
250
0
T
= 0°C
A
T
= 25°C
A
T
= 25°C
A
T
= 70°C
A
T
= 85°C
A
T
= 85°C
A
T
= –40°C
A
0
0.5
1.5
2.0
2.5
3.0
0
2.5
7.5
SUPPLY VOLTAGE (V)
10.0
12.5
1.0
5.0
SHDN PIN VOLTAGE (V)
1994 G24
1994 G25
1994fb
8
LT1994
PIN FUNCTIONS
+
–
+
–
IN , IN (Pins 1, 8): Noninverting and Inverting Input
Pins of the Amplifier, Respectively. For best performance,
it is highly recommended that stray capacitance be
kept to an absolute minimum by keeping printed circuit
connections as short as possible, and if necessary, strip-
ping back nearby surrounding ground plane away from
these pins.
V , V (Pins 3, 6): Power Supply Pins. For single-supply
applications (Pin 6 grounded) it is recommended that
high quality 1ꢀF and 0.1μF ceramic bypass capacitors be
placed from the positive supply pin (Pin 3) to the negative
supply pin (Pin 6) with minimal routing. Pin 6 should be
directly tied to a low impedance ground plane. For dual
powersupplies,itisrecommendedthathighquality,0.1ꢀF
ceramic capacitors are used to bypass Pin 3 to ground
and Pin 6 to ground. It is also highly recommended that
high quality 1μF and 0.1μF ceramic bypass capacitors be
placed across the power supply pins (Pins 3 and 6) with
minimal routing.
V
(Pin 2): Output Common Mode Reference Voltage.
OCM
OCM
The V
pin is the midpoint of an internal resistive volt-
age divider between the supplies, developing a (default)
mid-supply voltage potential to maximize output signal
swing. V
has a Thevenin equivalent resistance of
OCM
+
–
approximately 40k and can be overdriven by an external
voltage reference. The voltage on V sets the output
common mode voltage level (which is defined as the av-
erage of the voltages on the OUT and OUT pins). V
should be bypassed with a high quality ceramic bypass
capacitor of at least 0.1ꢀF (unless connected directly to
a low impedance, low noise ground plane) to minimize
common mode noise from being converted to differen-
tial noise by impedance mismatches both externally and
internally to the IC.
OUT , OUT (Pins 4, 5): Output Pins. Each pin can drive
approximately100Ωtogroundwithashort-circuitcurrent
limit of up to 85mA. Each amplifier output is designed
to drive a load capacitance of 25pF. This basically means
the amplifier can drive 25pF from each output to ground
or 12.5pF differentially. Larger capacitive loads should be
decoupled with at least 25Ω resistors from each output.
OCM
+
–
OCM
SHDN (Pin 7): When Pin 7 (SHDN) is floating or when
+
Pin 7 is directly tied to V , the LT1994 is in the normal
operating mode. When Pin 7 is pulled a minimum of 2.1V
+
below V , the LT1994 enters into a low power shutdown
state. Refer to the SHDN pin section under Applications
Information for a description of the LT1994 output imped-
ance in the shutdown state.
1994fb
9
LT1994
APPLICATIONS INFORMATION
Functional Description
+
–
The outputs (OUT and OUT ) of the LT1994 are capable
of swinging rail-to-rail. They can source or sink up to
approximately 85mA of current. Each output is rated to
driveapproximately25pFtoground(12.5pFdifferentially).
Higherloadcapacitancesshouldbedecoupledwithatleast
25Ω of series resistance from each output.
The LT1994 is a small outline, wideband, low noise and
low distortion fully-differential amplifier with accurate
output-phase balancing. The LT1994 is optimized to
drive low voltage, single-supply, differential input ana-
log-to-digital converters (ADCs). The LT1994’s output is
capable of swinging rail-to-rail on supplies as low as 2.5V,
which makes the amplifier ideal for converting ground
Input Pin Protection
The LT1994’s input stage is protected against differential
input voltages that exceed 1V by two pairs of back-to-
back diodes that protect against emitter base breakdown
of the input transistors. In addition, the input pins have
steering diodes to either power supply. If the input pair
is overdriven, the current should be limited to under
10mA to prevent damage to the IC. The LT1994 also has
referenced, single-ended signals into V
referenced
OCM
differential signals in preparation for driving low voltage,
single-supply, differential input ADCs. Unlike traditional
op amps which have a single output, the LT1994 has two
outputs to process signals differentially. This allows for
two times the signal swing in low voltage systems when
comparedtosingle-endedoutputamplifiers.Thebalanced
differentialnatureoftheamplifieralsoprovideseven-order
harmonic distortion cancellation, and less susceptibility
to common mode noise (like power supply noise). The
LT1994 can be used as a single-ended input to differential
output amplifier, or as a differential input to differential
output amplifier.
steering diodes to either power supply on the V
, and
OCM
SHDN pins (Pins 2 and 7) and if exposed to voltages that
exceed either supply, they too should be current limited
to under 10mA.
SHDN Pin
If the SHDN pin (Pin 7) is pulled 2.1V below the positive
supply, an internal current is generated that is used to
power down the LT1994. The pin will have the Thevenin
TheLT1994’soutputcommonmodevoltage,definedasthe
average of the two output voltages, is independent of the
input common mode voltage, and is adjusted by applying
+
equivalent impedance of approximately 55kΩ to V . If
a voltage on the V
pin. If the pin is left open, there is an
OCM
the pin is left unconnected, an internal pull-up resistor of
120k will keep the part in normal active operation. Care
should be taken to control leakage currents at this pin to
under 1ꢀA to prevent leakage currents from inadvertently
puttingtheLT1994intoshutdown.Inshutdown,allbiasing
internalresistivevoltagedivider,whichdevelopsapotential
+
–
halfwaybetweentheV andV pins.TheV
pinwillhave
OCM
an equivalent Thevenin equivalent resistance of 40k, and a
Thevenin equivalent voltage of half supply. Whenever this
pin is not hard tied to a low impedance ground plane, it
is recommended that a high quality ceramic capacitor is
+
currentsourcesareshutoff, andtheoutputpinsOUT and
–
OUT will each appear as open collectors with a nonlinear
used to bypass the V
pin to a low impedance ground
OCM
capacitor in parallel, and steering diodes to either supply.
Becauseofthenonlinearcapacitance,theoutputsstillhave
the ability to sink and source small amounts of transient
current if exposed to significant voltage transients. The
plane (see Layout Considerations in this document). The
LT1994’s internal common mode feedback path forces
accurate output phase balancing to reduce even order
harmonics, and centers each individual output about the
+
–
inputs (IN and IN ) have anti-parallel diodes that can
conduct if voltage transients at the input exceed 1V. The
inputs also have steering diodes to either supply. The
turn-on and turn-off time between the shutdown and
active states are on the order of 1ꢀs but depends on the
circuit configuration.
potential set by the V
pin.
OCM
–
VOUT+ + VOUT
VOUTCM = VOCM
=
2
1994fb
10
LT1994
APPLICATIONS INFORMATION
General Amplifier Applications
Effects of Resistor Pair Mismatch
As levels of integration have increased and, correspond-
ingly, system supply voltages decreased, there has been
a need for ADCs to process signals differentially in order
to maintain good signal-to-noise ratios. These ADCs are
typically supplied from a single-supply voltage that can
be as low as 2.5V and will have an optimal common mode
input range near mid-supply. The LT1994 makes interfac-
ing to these ADCs trivial, by providing both single-ended
to differential conversion as well as common mode level
shifting.Figure1showsageneralsingle-supplyapplication
Figure 2 shows a circuit diagram that takes into consid-
eration that real world resistors will not perfectly match.
Assuming infinite open-loop gain, the differential output
relationship is given by the equation:
RF
R
I
–
VOUTDIFF = VOUT+ – VOUT
≅
•V
INDIFF
+
Δβ
βAVG
Δβ
βAVG
•V
ICM
–
•VOCM,
+
where:
R is the average of R and R , and R is the average
with perfectly matched feedback networks from OUT and
–
OUT . The gain to V
from V
and V is:
INM INP
OUTDIFF
F
F1
F2
I
of R and R .
RF
R
I
I1
I2
+
–
VOUTDIFF = VOUT – VOUT
≈
• VINP – V
(
INM
)
β
is defined as the average feedback factor (or gain)
AVG
from the outputs to their respective inputs:
Note from the above equation that the differential output
+
–
voltage (V
– V
) is completely independent of
⎛
⎜
⎞
OUT
OUT
1
R
R
I1
R +RF1
I1
I2
βAVG = •
+
⎟
⎠
input and output common mode voltages, or the voltage
at the common mode pin. This makes the LT1994 ideally
suited pre-amplification, level shifting, and conversion
of single-ended signals to differential output signals in
preparation for driving differential input ADCs.
2 R +R
⎝
I2
F2
Δβ is defined as the difference in feedback factors:
R
R
I1
I2
Δβ =
–
R +RF2 R +RF1
I2
I1
–
+
R
V
R
V
R
L
I
IN
F
OUT
+
–
+
V
R
I2
V
R
V
R
L
IN
F2
OUT
0.1μF
V
S
R
BAL
V
V
INM
V
INM
3
3
4
1
4
1
–
+
V
–
+
OCM
2
8
V
OCM
2
8
0.1μF
V
LT1994
OUTCM
OCM
0.1μF
V
LT1994
–
OCM
0.1μF
V
–
CM
+
0.1μF
+
5
5
SHDN
6
6
V
7
INP
R
BAL
R
V
7
INP
0.1μF
V
SHDN
V
SHDNB
–
–
–
R
I
R
F
V
OUT
V
R
I1
R
V
R
L
L
F1
OUT
+
+
V
V
IN
1994 F01
IN
1994 F02
Figure 1. Test Circuit
Figure 2. Real-World Application
1994fb
11
LT1994
APPLICATIONS INFORMATION
V
V
is defined as the average of the two input voltages,
For single-ended inputs, because of the signal imbalance
at the input, the input impedance actually increases over
thebalanceddifferentialcase.Theinputimpedancelooking
into either input is:
ICM
INP
and V
(also called the input common mode
INM
voltage):
1
2
V
ICM
= • VINP + V
INM
(
)
R
I
R
INP
= R
=
INM
⎛
⎞
1 ⎡ RF
⎤
⎥
and V
is defined as the difference of the input
1– •
INDIFF
voltages:
⎜
⎝
⎟
⎠
⎢
2 R +RF ⎦
⎣ I
V
= V – V
INP INM
Inputsignalsourceswithnon-zerooutputimpedancescan
alsocausefeedbackimbalancebetweenthepairoffeedback
networks. For the best performance, it is recommended
that the source’s output impedance be compensated for.
If input impedance matching is required by the source,
R1 should be chosen (see Figure 3):
INDIFF
When the feedback ratios mismatch (Δβ), common mode
to differential conversion occurs.
Setting the differential input to zero (V
gree of common mode to differential conversion is given
by the equation:
= 0), the de-
INDIFF
RINM •RS
R1=
VOUTDIFF ꢀ VOUTꢃ – VOUT
z
–
RINM −RS
$B
BAVG
V
ICM – VOCM •
ꢁ
ꢂ
According to Figure 3, the input impedance looking into
thedifferentialamp(R )reflectsthesingle-endedsource
INM
V
INDIFF
ꢀ 0
case, thus:
R
I
Ingeneral,thedegreeoffeedbackpairmismatchisasource
ofcommonmodetodifferentialconversionofbothsignals
and noise. Using 1% resistors or better will provide about
28dB of common mode rejection. Using 0.1% resistors
will provide about 48dB of common mode rejection. A low
impedance ground plane should be used as a reference
R
=
INM
⎛
⎞
1 ⎡ RF
⎤
⎥
1– •
⎜
⎝
⎟
⎠
⎢
2 R +RF ⎦
⎣ I
R2 is chosen to balance R1||R :
S
R1•RS
R2=
for both the input signal source and the V
pin. A direct
OCM
R1+RS
short of V
to this ground plane or bypassing the V
OCM
OCM
with a high quality 0.1μF ceramic capacitor to this ground
plane will further mitigate against common mode signals
from being converted to differential.
R
INM
R
S
R
I
R
F
V
R1
S
Input Impedance and Loading Effects
–
+
+
LT1994
The input impedance looking into the V or V
of Figure 1 depends on whether or not the sources V
input
INM
INP
–
INP
and V
INP
is simply:
are fully differential. For balanced input sources
INM
INM
R
R
I
F
(V = –V ), the input impedance seen at either input
1994 F03
R2 = R || R1
S
R1 CHOSEN SO THAT R1 || R
R2 CHOSEN TO BALANCE R1 || R
= R
S
INM
S
R
INP
= R = R
INM I
Figure 3. Optimal Compensation for Signal-Source Impedance
1994fb
12
LT1994
APPLICATIONS INFORMATION
Input Common Mode Voltage Range
Output Common Mode Voltage Range
The output common mode voltage is defined as the aver-
age of the two outputs:
TheLT1994’sinputcommonmodevoltage(V )isdefined
ICM
+
–
as the average of the two input voltages, V , and V
.
IN
IN
–
+
It extends from V to approximately 1.25V below V . The
–
VOUT+ + VOUT
input common mode range depends on the circuit con-
VOUTCM = VOCM
The V
=
2
figuration (gain), V
and V (refer to Figure 4). For
CM
OCM
fully differential input applications, where V = –V
,
INP
INM
sets this average by an internal common mode
feedbackloopwhichinternallyforcesV
OCM
+
–
the common mode input is approximately:
=–V
. The
OUT
OUT
+
–
output common mode range extends from approximately
V
IN
+ V
2
⎛ R
I
⎞
⎟
IN
–
+
V
ICM
=
≈ VOCM
•
+
1.1V above V to approximately 0.8V below V . The V
⎜
OCM
⎝R + RF ⎠
I
pin sits in the middle of an 80kΩ to 80kΩ voltage divider
⎛ RF
⎝RF + R ⎠
⎞
⎟
that sets the default mid-supply open-circuit potential.
VCM
•
⎜
I
In single-supply applications, where the LT1994 is used
to interface to an ADC, the optimal common mode input
range to the ADC is often determined by the ADC’s refer-
ence. If the ADC makes a reference available for setting
the input common mode voltage, it can be directly tied
With singled-ended inputs, there is an input signal com-
ponent to the input common mode voltage. Applying only
V
(setting V
to zero), the input common voltage is
INP
INM
approximately:
to the V
pin, but must be capable of driving a 40k
OCM
+
–
equivalentresistancethatistiedtoamid-supplypotential.
If an external reference drives the V pin, it should still
V
IN
+ V
2
⎛ R
I
⎞
⎟
IN
V
ICM
=
≈ VOCM
•
+
⎜
OCM
⎝R + RF ⎠
I
be bypassed with a high quality 0.1ꢀF capacitor to a low
impedance ground plane to filter any thermal noise and
to prevent common mode signals on this pin from being
inadvertently converted to differential signals.
⎛ RF
⎝RF + R ⎠
⎞
⎟
V
⎛ RF
⎝RF + R ⎠
⎞
⎟
INP
2
VCM
•
+
•
⎜
⎜
I
I
–
+
R
V
R
V
R
L
I
IN
F
OUT
Noise Considerations
V
S
The LT1994’s input referred voltage noise is on the order
of 3nV/√Hz. Its input referred current noise is on the
order of 2.5pA/√Hz. In addition to the noise generated
by the amplifier, the surrounding feedback resistors also
contribute noise. The output noise generated by both the
amplifier and the feedback components is given by the
equation:
V
INM
3
4
1
2
8
–
+
V
OCM
0.1μF
V
LT1994
OCM
V
–
CM
+
5
SHDN
6
V
7
INP
V
SHDNB
–
2
R
R
V
R
L
I
F
OUT
⎛
⎞
⎡
RF ⎤
R
I ⎦
2
+
eni • 1+
+ 2• I •R
+
V
(
)
IN
n
F
⎜
⎝
⎟
⎠
1994 F04
⎢
⎥
⎣
⎛
eno
=
Figure 4. Circuit for Common Mode Range
2
⎞
⎡RF ⎤
2
2• enRI
•
+ 2•enRF
⎜
⎟
⎠
⎢
⎥
R
⎝
⎣ I ⎦
1994fb
13
LT1994
APPLICATIONS INFORMATION
A plot of this equation and a plot of the noise generated
by the feedback components are shown in Figure 6.
Lower resistor values always result in lower noise at the
penalty of increased distortion due to increased loading of
thefeedbacknetworkontheoutput.Higherresistorvalues
will result in higher output noise, but improved distortion
due to less loading on the output.
The LT1994’s input referred voltage noise contributes the
equivalent noise of a 560Ω resistor. When the feedback
network is comprised of resistors whose values are less
than this, the LT1994’s output noise is voltage noise
dominant (See Figure 6):
Figure 6 shows the noise voltage that will appear differ-
entially between the outputs. The common mode output
noise voltage does not add to this differential noise. For
optimum noise and distortion performance, use a dif-
ferential output configuration.
⎛
⎝
RF ⎞
R ⎠
I
eno ≈ e • 1+
⎜
⎟
ni
Feedback networks consisting of resistors with values
greater than about 10k will result in output noise which
is amplifier current noise dominant.
Power Dissipation Considerations
The LT1994 is housed in either an 8-lead MSOP package
(θ = 140°C/W or an 8-lead DD package (θ = 43°C/W).
JA
JA
eno ≈ 2 •In •RF
TheLT1994combineshighspeedandlargeoutputcurrent
with a small die and small package so there is a need to
be sure the die temperature does not exceed 150°C. In the
2
2
e
nRI2
e
nRF2
R
R
F2
I2
–
8-lead MSOP, LT1994 has its V lead fused to the frame
2
so it is possible to lower the package thermal impedance
i
n–
V /2
S
–
by connecting the V pin to a large ground plane or metal
3
trace. Metal trace and plated through holes can be used to
spread the heat generated by the device to the backside
of the PC board. For example, an 8-lead MSOP on a 3/32"
4
2
1
2
8
e
ncm
–
+
2
V
LT1994
e
no
OCM
–
+
2
5
2
i
FR-4 board with 540mm of 2oz. copper on both sides
n+
6
–
of the PC board tied to the V pin can drop the θ from
JA
7
–V /2
S
140°C/W to 110°C/W (see Table 1).
2
2
2
e
ni
e
nRI1
e
nRF1
R
R
F1
I1
The underside of the DD package has exposed metal
2
(4mm ) from the lead frame where the die is attached.
1994 F05
This provides for the direct transfer of heat from the die
junction to the printed circuit board to help control the
maximumoperatingjunctiontemperature.Thedual-in-line
pin arrangement allows for extended metal beyond the
ends of the package on the topside (component side) of a
circuit board. Table 1 summarizes for the MSOP package,
the thermal resistance from the die junction-to-ambient
that can be obtained using various amounts of topside,
and backside metal (2oz. copper). On multilayer boards,
further reductions can be obtained using additional metal
on inner PCB layers connected through vias beneath the
package.
Figure 5. Noise Analysis
100
10
1
TOTAL
(AMPLIFIER + FEEDBACK NETWORK)
OUTPUT NOISE
FEEDBACK NETWORK
NOISE ALONE
0.1
1
10
R
= R (kΩ)
I
F
1994 F06
Figure 6. LT1994 Output Spot Noise vs Spot Noise Contributed by
Feedback Network Alone
1994fb
14
LT1994
APPLICATIONS INFORMATION
In general, the die temperature can be estimated from
Table 1. LT1994 MSOP Package Thermal Resistivity
the ambient temperature T , and the device power dis-
A
COPPER AREA
COPPER AREA
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
2
2
TOPSIDE (mm )
BACKSIDE (mm )
sipation P :
D
0
0
0
140
135
130
120
110
+
T = T + P • θ
J
A
D
JA
30
The power dissipation in the IC is a function of the supply
voltage, the output voltage, and the load resistance. For
fullydifferentialoutputamplifiersatagivensupplyvoltage
100
100
540
0
100
540
( V ), and a given differential load (R
), the worst-
CC
LOAD
case power dissipation P
occurs at the worst-case
Layout Considerations
D(MAX)
quiescent current (I
= 20.5mA) and when the load
Q(MAX)
BecausetheLT1994isahighspeedamplifier, itissensitive
to both stray capacitance and stray inductance. Compo-
nents connected to the LT1994 should be connected with
as short and direct connections as possible. A low noise,
low impedance ground plane is critical for the highest
performance. In single-supply applications, high quality
surface mount 1ꢀF and 0.1ꢀF ceramic bypass capacitors
with minimum PCB trace should be used directly across
current is given by the expression:
VCC
RLOAD
ILOAD
=
The worst-case power dissipation in the LT1994 at
VCC
RLOAD
ILOAD
=
is:
+
–
the power supplies V to V . In split supply applications,
high quality surface mount 1ꢀF and 0.1ꢀF ceramic bypass
capacitors should be placed across the power supplies
2
PD MAX = 2•VCC • ILOAD + I
– ILOAD •
(
)
Q MAX
(
)
(
)
2
+
–
V to V , and individual high quality surface mount 0.1ꢀF
bypass capacitors should be used from each supply to
ground with direct (short) connections.
VCC
RLOAD
=
+ 2•VCC •IQ(MAX
)
RLOAD
Example: A LT1994 is mounted on a circuit board in a
Any stray parasitic capacitance to ground at the summing
MSOP-8 package (θ = 140°C/W), and is running off of
+
–
JA
junctions, IN and IN should be kept to an absolute mini-
mum even if it means stripping back the ground plane
away from any trace attached to this node. This becomes
especially true when the feedback resistor network uses
5Vsuppliesdrivinganequivalentload(externalloadplus
feedback network) of 75Ω. The worst-case power that
would be dissipated in the device occurs when:
2
resistor values >500Ω in circuits with R = R . Excessive
F
I
VCC
PD(MAX
=
=
+2• VCC •IQ(MAX
)
peaking in the frequency response can be mitigated by
adding small amounts of feedback capacitance around RF
(2pF to 5pF). Always keep in mind the differential nature of
theLT1994,andthatitiscriticalthattheoutputimpedances
seen by both outputs (stray or intended) should be as bal-
anced and symmetric as possible. This will help preserve
the natural balance of the LT1994, which minimizes the
generation of even order harmonics, and preserves the
rejection of common mode signals and noise.
)
RLOAD
5V2
75Ω
+2•5V •17.5MA = 0.54W
The maximum ambient temperature the 8-lead MSOP is
allowed to operate under these conditions is:
T = T
– P • θ = 150°C – (0.54W) •
D JA
A
JMAX
(140°C/W) = 75°C
It is highly recommended that the V
tied to a low impedance ground plane (in split supply
applications) or bypassed to ground with a high quality
pin be either hard
OCM
To operate the device at higher ambient temperature,
–
connect more copper to the V pin to reduce the thermal
resistance of the package as indicated in Table 1.
1994fb
15
LT1994
APPLICATIONS INFORMATION
be comprised of 1% resistors (or better) to enhance the
output common mode rejection. This will also prevent
OCM
mode amplifier path (which cannot be filtered) from being
converted to differential noise, degrading the differential
noise performance.
0.1ꢀF ceramic capacitor in single-supply applications.
This will help prevent thermal noise from the internal
80kΩ-80kΩ voltage divider (25nV/√Hz) and other exter-
nal sources of noise from being converted to differential
noise due to mismatches in the feedback networks. It is
also recommended that the resistive feedback networks
V
input referred common mode noise of the common
SIMPLIFIED SCHEMATIC
+
V
120k
+
V
SHUTDOWN
CIRCUIT
I
I
55k
1
1
SHDN
C
M1
C
M2
–
+
V
V
+
+
V
V
+
V
Q9
Q11
Q12
+
–
+
–
BIAS
BIAS
BIAS
ADJUST
–
+
OUT
OUT
ADJUST
Q10
V
Gm
2B
Gm
2A
–
+
–
+
V
V
V
V
–
–
V
+
V
+
+
–
+
+
+
–
V
OUT
V
V
V
V
I2
R1
4k
80k
80k
I
3
Q7
Q8
V
OCM
R2
4k
Q1
Q2
Q5 Q6
–
D1 D2
D3 D4
IN
IN
–
OUT
V
Q3
Q4
CM
ADJUST
–
+
V
V
I
4A
I
4B
–
+
V
1994 SS01
–
V
1994fb
16
LT1994
TYPICAL APPLICATIONS
Differential 1st Order Lowpass Filter
Example: The specified –3dB frequency is 1MHz Gain = 4
Maximum –3dB frequency (f ) 2MHz
1. Using f = 1000kHz, C11 = 400pF
3dB abs
3dB
Stopband attenuation: –6dB at 2 • f and 14dB at 5 • f
2. Nearest standard 5% value to 400pF is 390pF and C11
= C12 = 390pF
3dB
3dB
C11
3. Using f = 1000kHz, C11 = 390pF and Gain = 4, R21
3dB
= R22 = 412Ω and R11 = R12 = 102Ω (nearest 1%
value)
R11
R21
–
V
IN
+
V
0.1μF
3
Differential 2nd Order Butterworth Lowpass Filter
4
1
2
8
+
–
– +
LT1994
V
V
OUT
OUT
Maximum –3dB frequency (f ) 1MHz
3dB
0.1μF
+
+ –
Stopband attenuation: –12dB at 2 • f and –28dB at 5 • f
3dB
3dB
5
6
7
R21
R22
C12
R12
V
IN
C21
R11
R31
–
V
IN
1994 TA03
+
V
0.1μF
3
4
1
2
8
Component Calculation:
R11 = R12, R21 = R22
+
–
– +
V
V
OUT
OUT
LT1994
C11
R12
0.1μF
+ –
6
5
2MHz
f3dB
7
f3dB ≤2MHz and Gain ≤
R32
R22
+
V
IN
C22
1. Calculate an absolute value for C11 (C11 ) using a
abs
1994 TA04
specified –3dB frequency
4•105
f3dB
Component Calculation:
R11 = R12, R21 = R22, R31 = R32, C21 = C22,
C11abs
=
(C11absin pF and f3dB in kHz)
C11 = 10 • C21, R1 = R11, R2 = R21, R3 = R31,
C2 = C21 and C1 = C11
2. Selectastandard5%capacitorvaluenearesttheabsolute
value for C11
1. Calculate an absolute value for C2 (C2 ) using a
abs
3. Calculate R11 and R21 using the standard 5% C11
specified –3dB frequency
value, f and desired gain
3dB
4•105
f3dB
R11 and R21 equations (C11 in pF and f in kHz)
3dB
C2abs
=
(C2absin pF and f3dB in kHz)(Note 2)
159.2•106
R21=
2. Selectastandard5%capacitorvaluenearesttheabsolute
value for C2 (C1 = 10 • C2)
C11• f3dB
R21
Gain
R11=
1994fb
17
LT1994
TYPICAL APPLICATIONS
3. Calculate R3, R2 and R1 using the standard 5% C2
Example: The specified –3dB frequency is 1MHz Gain = 1
1. Using f = 1000kHz, C2 = 400pF
value, the specified f
gain (Gn)
and the specified passband
3dB
3dB
abs
2. Nearest standard 5% value to 400pF is 390pF and C21
= C22 = 390pF and C11 = 3900pF
1MHz
f3dB
f3dB ≤1MHz and Gain ≤8.8 or Gain ≤
3. Using f
= 1000kHz, C2 = 390pF and Gain = 1, R1
3dB
= 549Ω, R2 = 549Ω and R3 = 15.4Ω (nearest 1%
values). R11 = R21 = 549Ω, R21 = R22 = 549Ω and
R31 = R32 = 15.4Ω.
R1, R2 and R3 equations (C2 in pF and f in kHz)
3dB
1.121– 1.131– 0.127 •Gn •108
(
)
(
)
R3=
(Note 1)
Note 1: The equations for R1, R2, R3 are ideal and do
notaccountforthefinitegainbandwidthproduct(GBW)
of the LT1994 (70MHz). The maximum gain is set by
the C1/C2 ratio (which for convenience is set equal to
ten).
Gn +1 •C2• f
1.266 •1015
(
)
3dB
R2=
R1=
2
R3•C22 • f3dB
R2
Gn
Note 2: The calculated value of a capacitor is chosen
to produce input resistors less than 600Ω. If a higher
valueinputresistanceisrequiredthenmultiplyallresis-
tor values and divide all capacitor values by the same
number.
A Single-Ended to Differential Voltage Conversion with Source Impedance Matching and Level Shifting
R
S
50Ω
374Ω
402Ω
50Ω
+
V
V
0.1μF
IN
V
54.9Ω
3
4
1
2
8
–
+
– +
V
V
OUT
OUT
V
+
–
V
V
+ 0.25V
– 0.25V
V
V
OCM
OUT
V
LT1994
5
V
OCM
OCM
0
0.1μF
OCM
OUT
V
IN
+ –
1
0
t
6
7
t
402Ω
402Ω
1994 TA05
–1
1994fb
18
LT1994
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115
0.38 p 0.10
TYP
5
8
0.675 p0.05
3.5 p0.05
2.15 p0.05 (2 SIDES)
1.65 p0.05
3.00 p0.10
(4 SIDES)
1.65 p 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PACKAGE
OUTLINE
(DD) DFN 1203
4
1
0.25 p 0.05
0.75 p0.05
0.200 REF
0.25 p 0.05
0.50 BSC
0.50
BSC
2.38 p0.05
(2 SIDES)
2.38 p0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
3.00 p 0.102
(.118 p .004)
(NOTE 3)
0.52
(.0205)
REF
8
7 6 5
3.00 p 0.102
(.118 p .004)
(NOTE 4)
4.90 p 0.152
(.193 p .006)
DETAIL “A”
0.254
0.889 p 0.127
(.035 p .005)
(.010)
0o – 6o TYP
GAUGE PLANE
1
2
3
4
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.53 p 0.152
(.021 p .006)
1.10
(.043)
MAX
0.86
(.034)
REF
DETAIL “A”
0.18
(.007)
0.65
(.0256)
BSC
0.42 p 0.038
SEATING
PLANE
(.0165 p .0015)
TYP
0.22 – 0.38
0.1016 p 0.0508
(.009 – .015)
RECOMMENDED SOLDER PAD LAYOUT
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
(.004 p .002)
0.65
(.0256)
BSC
TYP
MSOP (MS8) 0307 REV F
1994fb
19
LT1994
TYPICAL APPLICATION
RFID Receiver Front-End, 1kHz < –3dB BW < 2MHz
(Baseband Gain = 5)
82pF
1μF
140Ω
1k
5V
0.1μF
3
120pF
1
7
2
8
4
5V
LT1994
I
OUT
10pF
270μH*
0.1μF
1μF
5
LT5575
I MIXER
RF AMP
LPF
+
–
I
I
OUT
OUT
6
270μH*
140Ω
1k
RF
82pF
120pF
10pF
5V
82pF
1k
0°/90°
LO BUFFERS
Q MIXER
LO
10pF
1μF
+
–
RF AMP
270μH*
140Ω
LPF
Q
Q
OUT
5V
270μH*
OUT
0.1μF
120pF
3
1
7
2
8
10pF
4
120pF
0.1μF
1μF
5V
LT1994
Q
OUT
5
6
140Ω
1k
82pF
*COILCRAFT 0603HP
1994 TA02
RELATED PARTS
PART NUMBER
LT®1167
DESCRIPTION
Precision, Instrumentation Amp
COMMENTS
Single Gain Set Resistor: G = 1 to 10,000
325MHz, 140V/μs Slew Rate, 3.5nV/√Hz Noise
180MHz, 350V/μs Slew Rate, Shutdown
250V Common Mode, Micropower, Gain = 1, 10
Micropower, Pin Selectable Gain = –13 to 14
Programmable Gain or Fixed Gain (G = 1, 2, 5, 10)
Fixed Gain (G = 2, 4, 10)
LT1806/LT1807
LT1809/LT1810
LT1990
Single/Dual Low Distortion Rail-to-Rail Amp
Single/Dual Low Distortion Rail-to-Rail Amp
High Voltage Gain Selectable Differential Amp
Precision Gain Selectable Differential Amp
Fully Differential Input/Output Amplifiers
Low Distortion and Noise, Differential In/Out
High Speed Gain Selectable Differential Amp
LT1991
LTC1992/LTC1992-x
LT1993-2/-4/-10
LT1995
30MHz, 1000V/μs, Pin Selectable Gain = –7 to 8
Pin Selectable Gain = 9 to 117
LT1996
Precision, 100μA, Gain Selectable Differential Amp
Low Noise, Low Power Fully Differential Amp
600MHz AC Precision Fully Differential Amp
LTC6403
11mA Supply Current
LTC6404-1/LTC6404-2
LTC6404-4
Available H-Grade (–40°C to 125°C)
LT6600-2.5/-5/-10/-15/-20 Differential Amp and Lowpass, Chebyshev Filter
Filter Cutoff = 2.5MHz, 5MHz, 10MHz, 15MHz or 20MHz
1994fb
LT 0309 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
20
●
●
© LINEAR TECHNOLOGY CORPORATION 2005
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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