LT3011IDDTR_技术文档

LT3011

50mA, 3V to 80V Low

Dropout Micropower Linear

Regulator with PWRGD

DESCRIPTION

FEATURES

The LT^®3011 is a high voltage, micropower, low dropout

linearregulator.Thedeviceiscapableofsupplying50mAof

output current with a dropout voltage of 300mV. Designed

for use in battery-powered high voltage systems, the low

quiescent current (46μA operating and 1μA in shutdown)

is well controlled in dropout, making the LT3011 an ideal

choice.

n

Wide Input Voltage Range: 3V to 80V

n

Low Quiescent Current: 46μA

n

Low Dropout Voltage: 300mV

Output Current: 50mA

n

PWRGD Flag with Programmable Delay

n

No Protection Diodes Needed

n

Adjustable Output from 1.24V to 60V

n

1μA Quiescent Current in Shutdown

The LT3011 includes a PWRGD ﬂag to indicate output

regulation. The delay between regulated output level and

ﬂag indication is programmable with a single capacitor.

The LT3011 also has the ability to operate with very small

output capacitors; it is stable with only 1μF on the output.

Smallceramiccapacitorscanbeusedwithouttheaddition

of any series resistance (ESR) as is common with other

regulators. Internal protection circuitry includes reverse-

battery protection, current limiting, thermal limiting, and

reverse current protection.

n

Stable with 1μF Output Capacitor

n

Stable with Ceramic, Tantalum, and Aluminum

Capacitors

Reverse-Battery Protection

n

No Reverse Current Flow from Output to Input

n

Thermal Limiting

n

Thermally Enhanced 12-Lead MSOP and

10-Pin (3mm × 3mm) DFN Packages

APPLICATIONS

The LT3011 features an adjustable output with a 1.24V

reference voltage. The device is available in the thermally

enhanced 12-lead MSOP and the low proﬁle (0.75mm)

10-pin (3mm × 3mm) DFN package, both providing excel-

lent thermal characteristics.

n

Low Current High Voltage Regulators

n

Regulator for Battery-Powered Systems

Telecom Applications

n

Automotive Applications

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

TYPICAL APPLICATION

Dropout Voltage

5V Supply with Shutdown

350

300

V

OUT

IN

OUT

ADJ

5V

50mA

V

LT3011

IN

750k

249k

250

200

150

100

50

1.6M

3V TO

80V

1μF

SHDN

PWRGD

GND

C

T

POWER GOOD

1000pF

3011 TA01

V

OUTPUT

OFF

ON

SHDN

<0.3V

>2.0V

0

10

20

30

40

50

OUTPUT CURRENT (mA)

3011 TA02

3011f

1

LT3011

ABSOLUTE MAXIMUM RATINGS ^{(Note 1)}

Storage Temperature Range................... –65°C to 150°C

Operating Junction Temperature

IN Pin Voltage ......................................................... 80V

OUT Pin Voltage...................................................... 60V

Input-to-Output Differential Voltage........................ 80V

ADJ Pin Voltage ........................................................ 7V

SHDN Pin Voltage ................................................... 80V

(Notes 3, 10, 11)

LT3011E, LT3011I .............................. –40°C to 125°C

LT3011H ............................................ –40°C to 150°C

Lead Temperature (Soldering, 10 sec)

C Pin Voltage.................................................. 7V, –0.5V

T

MSE Package Only............................................ 300°C

PWRGD Pin Voltage....................................... 80V, –0.5V

Output Short-Circuit Duration .......................... Indeﬁnite

PIN CONFIGURATION

TOP VIEW

1

2

3

4

5

6

NC

OUT

ADJ

GND

NC

12 NC

11 IN

10 NC

OUT

ADJ

1

2

3

4

5

10 IN

9

8

7

6

NC

11

13

GND

SHDN

NC

9

8

7

SHDN

NC

PWRGD

C

PWRGD

C

T

MSE PACKAGE

12-LEAD PLASTIC MSOP

DD PACKAGE

10-LEAD (3mm s 3mm) PLASTIC DFN

T

= 150°C, θ = 40°C/W, θ = 16°C/W

JA JC

JMAX

T

= 150°C, θ = 43°C/W, θ = 16°C/W

JA JC

JMAX

EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB

EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH

LT3011EDD#PBF

LT3011IDD#PBF

LT3011EMSE#PBF

LT3011HMSE#PBF

LT3011IMSE#PBF

LEAD BASED FINISH

LT3011EDD

TAPE AND REEL

PART MARKING*

LDKQ

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LT3011EDD#TRPBF

LT3011IDD#TRPBF

LT3011EMSE#TRPBF

LT3011HMSE#TRPBF

LT3011IMSE#TRPBF

TAPE AND REEL

–40°C to 125°C

–40°C to 150°C

–40°C to 125°C

TEMPERATURE RANGE

–40°C to 125°C

–40°C to 150°C

–40°C to 125°C

10-Lead (3mm × 3mm) Plastic DFN

12-Lead Plastic MSOP

LDKQ

3011

12-Lead Plastic MSOP

3011

12-Lead Plastic MSOP

PART MARKING*

LDKQ

PACKAGE DESCRIPTION

LT3011EDD#TR

10-Lead (3mm × 3mm) Plastic DFN

12-Lead Plastic MSOP

LT3011IDD

LT3011IDD#TR

LDKQ

LT3011EMSE

LT3011EMSE#TR

LT3011HMSE#TR

LT3011IMSE#TR

3011

LT3011HMSE

3011

12-Lead Plastic MSOP

LT3011IMSE

3011

12-Lead Plastic MSOP

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

3011f

2

LT3011

(LT3011E, LT3011I)

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁcations which apply over the –40°C to 125°C operating temperature range, otherwise speciﬁcations are T_J= 25°C.

PARAMETER

CONDITIONS

= 50mA

MIN

TYP

MAX

UNITS

l

Minimum Input Voltage

ADJ Pin Voltage (Notes 2, 3)

I

2.8

4

V

LOAD

V

= 3V, I

IN

= 1mA

1.228

1.215

1.24

1.252

1.265

V

IN

LOAD

l

4V < V < 80V, 1mA < I

< 50mA

LOAD

Line Regulation (Note 2)

Load Regulation (Note 2)

1

6

12

mV

ΔV = 3V to 80V, I

IN

= 1mA

LOAD

15

25

mV

V

= 4V, ΔI

= 1mA to 50mA

IN

LOAD

l

Dropout Voltage

I

= 1mA

100

200

300

150

190

mV

LOAD

V

= V

(Notes 4, 5)

OUT(NOMINAL)

IN

I

= 10mA

260

350

mV

LOAD

I

= 50mA

370

550

mV

LOAD

l

GND Pin Current

I

= 0mA

= 1mA

= 10mA

= 50mA

46

105

410

1.9

90

200

700

3.3

μA

LOAD

V

= V

OUT(NOMINAL)

IN

(Notes 4, 6)

μA

mA

Output Voltage Noise

ADJ Pin Bias Current

Shutdown Threshold

C

= 10μF, I

= 50mA, BW = 10Hz to 100kHz, V

= 1.24V

100

30

μV

RMS

OUT

LOAD

OUT

(Note 7 )

100

2

nA

l

V

OUT

V

OUT

= Off to On

= On to Off

1.3

1.1

V

0.3

85

SHDN Pin Current (Note 8)

V

SHDN

V

SHDN

= 0V

= 6V

0.5

0.1

2

0.5

μA

Quiescent Current in Shutdown

PWRGD Trip Point

V

IN

= 6V, V

= 0V

1

90

5

μA

%

SHDN

l

% of Nominal Output Voltage, Output Rising

% of Nominal Output Voltage

94

PWRGD Trip Point Hysteresis

PWRGD Output Low Voltage

1.1

140

3

%

l

I

= 50μA

250

6

mV

μA

V

PWRGD

C Pin Charging Current

T

C Pin Voltage Differential

T

V

– V

CT(PWRGD Low)

1.67

85

CT(PWRGD High)

Ripple Rejection

Current Limit

= 7V (Avg), V

= 0.5V , f

= 120Hz, I

= 50mA

65

60

dB

IN

RIPPLE

P-P RIPPLE

LOAD

V

IN

V

IN

= 7V, V

= 0V

= –0.1V (Note 2)

140

mA

OUT

l

= 4V, ΔV

Input Reverse Leakage Current

Reverse Output Current (Note 9)

V

= –80V, V

= 0V

6

mA

μA

IN

OUT

= 1.24V, V < 1.24V (Note 2)

8

15

OUT

IN

(LT3011H)

ELECTRICAL CHARACTERISTICS

The l denotes the speciﬁcations which apply over the –40°C to 150°C operating temperature range, otherwise speciﬁcations are T_J= 25°C.

PARAMETER

CONDITIONS

= 50mA

MIN

TYP

MAX

UNITS

l

Minimum Input Voltage

ADJ Pin Voltage (Notes 2, 3)

I

2.8

4

V

LOAD

V

= 3V, I

IN

= 1mA

1.228

1.215

1.24

1.252

1.265

V

IN

LOAD

l

4V < V < 80V, 1mA < I

< 50mA

LOAD

Line Regulation (Note 2)

Load Regulation (Note 2)

1

6

12

mV

ΔV = 3V to 80V, I

IN

= 1mA

LOAD

15

25

mV

V

= 4V, ΔI

= 1mA to 50mA

IN

LOAD

l

3011f

3

LT3011

ELECTRICAL CHARACTERISTICS ^(LT3011H)

The l denotes the speciﬁcations which apply over the –40°C to 150°C operating temperature range, otherwise speciﬁcations are at T_J= 25°C.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Dropout Voltage

I

= 1mA

100

150

220

mV

LOAD

l

V

= V

OUT(NOMINAL)

IN

(Notes 4, 5)

I

= 10mA

200

300

260

380

mV

LOAD

I

= 50mA

370

575

mV

LOAD

l

GND Pin Current

I

= 0mA

= 1mA

= 10mA

= 50mA

46

105

410

1.9

125

225

750

3.5

μA

LOAD

V

= V

OUT(NOMINAL)

IN

(Notes 4, 6)

μA

mA

Output Voltage Noise

ADJ Pin Bias Current

Shutdown Threshold

C

= 10μF, I

= 50mA, BW = 10Hz to 100kHz, V

= 1.24V

100

30

μV

RMS

OUT

LOAD

OUT

(Note 7)

100

2

nA

l

V

OUT

V

OUT

= Off to On

= On to Off

1.3

1.1

V

0.3

85

SHDN Pin Current (Note 8)

V

SHDN

V

SHDN

= 0V

= 6V

0.5

0.1

2

0.5

μA

Quiescent Current in Shutdown

PWRGD Trip Point

V

IN

= 6V, V

= 0V

1

90

5

μA

%

SHDN

l

% of Nominal Output Voltage, Output Rising

% of Nominal Output Voltage

95

PWRGD Trip Point Hysteresis

PWRGD Output Low Voltage

1.1

140

3

%

l

I

= 50μA

250

6

mV

μA

V

PWRGD

C Pin Charging Current

T

C Pin Voltage Differential

T

V

– V

CT(PWRGD Low)

1.67

85

CT(PWRGD High)

Ripple Rejection

Current Limit

= 7V (Avg), V

= 0.5V , f

= 120Hz, I

= 50mA

65

60

dB

IN

RIPPLE

P-P RIPPLE

LOAD

V

IN

V

IN

= 7V, V

= 0V

= –0.1V (Note 2)

140

mA

OUT

l

= 4V, ΔV

Input Reverse Leakage Current

Reverse Output Current (Note 9)

V

= –80V, V

= 0V

6

mA

μA

IN

OUT

= 1.24V, V < 1.24V (Note 2)

8

15

OUT

IN

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LT3011 is tested and speciﬁed for these conditions with the

ADJ pin connected to the OUT pin.

Note 3: Operating conditions are limited by maximum junction

temperature. The regulated output voltage speciﬁcation will not apply

for all possible combinations of input voltage and output current. When

operating at maximum input voltage, the output current range must be

limited. When operating at maximum output current, the input voltage

range must be limited.

Note 4: To satisfy requirements for minimum input voltage, the LT3011

is tested and speciﬁed for these conditions with an external resistor

divider (249k bottom, 409k top) for an output voltage of 3.3V. The external

resistor divider will add a 5μA DC load on the output.

dropout region. This is the worst-case GND pin current. The GND pin

current will decrease slightly at higher input voltages.

Note 7: ADJ pin bias current ﬂows into the ADJ pin.

Note 8: SHDN pin current ﬂows out of the SHDN pin.

Note 9: Reverse output current is tested with the IN pin grounded and the

OUT pin forced to the rated output voltage. This current ﬂows into the OUT

pin and out the GND pin.

Note 10: The LT3011 regulators are tested and speciﬁed under pulse

load conditions such that T ≅ T . The LT3011E regulators are 100%

J

A

tested at T = 25°C. Performance of the LT3011E over the full –40°C

A

to 125°C operating junction temperature range is assured by design,

characterization and correlation with statistical process controls. The

LT3011I regulators are guaranteed over the full –40°C to 125°C operating

junction temperature range. The LT3011H is tested to the LT3011H

Electrical Characteristics table at 150°C operating junction temperature.

High junction temperatures degrade operating lifetimes. Operating lifetime

is derated at junction temperatures greater than 125°C.

Note 11: This IC includes overtemperature protection that is intended to protect

the device during momentary overload conditions. Junction temperature will

exceed 125°C (LT3011E/LT3011I) or 150°C (LT3011H) when overtemperature

protection is active. Continuous operation above the speciﬁed maximum

Note 5: Dropout voltage is the minimum input to output voltage differential

needed to maintain regulation at a speciﬁed output current. In dropout, the

output voltage will be equal to (V – V

).

IN

DROPOUT

Note 6: GND pin current is tested with V = V

and a current

IN

OUT(NOMINAL)

source load. This means the device is tested while operating close to its

operating junction temperature may impair device reliability.

3011f

4

LT3011

TYPICAL PERFORMANCE CHARACTERISTICS ^T_J^{= 25°C, unless otherwise noted.}

Dropout Voltage

Guaranteed Dropout Voltage

Dropout Voltage

400

350

300

250

200

150

100

50

400

350

300

250

200

150

100

50

600

500

= TEST POINTS

I

= 50mA

L

T

ꢀ 125oC

J

400

300

T

ꢀ 25oC

J

T

b 125oC

b 25oC

J

I

= 10mA

= 1mA

L

T

J

200

100

0

L

0

10

20

30

50

0

40

0

5

10 15 20 25 30 35 40 45 50

–50 –25

25 50 75 100 125 150

TEMPERATURE (°C)

3011 G03

0

OUTPUT CURRENT (mA)

3011 G02

3011 G01

Quiescent Current

ADJ Pin Voltage

Quiescent Current

80

70

60

50

40

30

20

10

0

1.250

1.248

1.246

1.244

1.242

1.240

1.238

1.236

1.234

1.232

1.230

V

= 6V

= ∞

I

L

= 1mA

T

= 25°C

J

IN

L

= 0

R

=

d

70

60

L

I

L

V

SHDN

= V

IN

V

SHDN

= V

IN

50

40

30

20

10

V

SHDN

= GND

0

2

3

4

5

6

10

–50 –25

0

25 50 75 100 125 150

0

1

7

8

9

–50 –25

25 50 75 100 125 150

TEMPERATURE (°C)

3011 G05

0

TEMPERATURE (°C)

INPUT VOLTAGE (V)

3011 G04

3011 G06

GND Pin Current

GND Pin Current vs I_OUT

SHDN Pin Threshold

1.6

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

V

J

= V

+1V

OUT(NOMINAL)

IN

T

= 25°C

1.4

1.2

R

= 24.8Ω

= 50mA*

L

I

1.0

0.8

0.6

0.4

0.2

R

= 49.6Ω

= 25mA*

L

I

R

I

= 124Ω

= 10mA*

L

R

= 1.24k, I = 1mA*

L

0

–50 –25

0

25 50 75 100 125 150

0

1

2

3

4

5

6

7

8

9

10

0

5

10 15 20 25 30 35 40 45 50

TEMPERATURE (°C)

INPUT VOLTAGE (V)

OUTPUT CURRENT (mA)

3011 G09

3011 G07

3011 G08

T

= 25°C

OUT

J

*FOR V

= 1.24V

3011f

5

LT3011

TYPICAL PERFORMANCE CHARACTERISTICS ^T_J^{= 25°C, unless otherwise noted.}

SHDN Pin Current

ADJ Pin Bias Current

0.6

0.5

0.4

0.3

0.2

0.1

0

0.28

0.24

120

100

80

60

40

20

0

V

= 0V

T

= 25°C

SHDN

J

CURRENT FLOWS

OUT OF SHDN PIN

0.20

0.16

0.12

0.08

0.04

0

–50 –25

0

25 50 75 100 125 150

1

1.5

2

2.5

3

5

0

0.5

3.5

4

4.5

–50 –25

0

25 50 75 100 125 150

TEMPERATURE (°C)

SHDN PIN VOLTAGE (V)

TEMPERATURE (°C)

3011 G11

3011 G12

3011 G10

PWRGD Trip Point

PWRGD Output Low Voltage

C_TCharging Current

4.0

95

94

93

92

91

90

89

88

87

86

85

200

180

160

140

120

100

80

I

= 50μA

PWRGD TRIPPED HIGH

PWRGD

3.5

3.0

OUTPUT

RISING

2.5

2.0

1.5

1.0

0.5

OUTPUT

FALLING

60

40

20

0

–50 –25

0

25 50 75 100 125 150

–50 –25

25 50 75 100 125 150

TEMPERATURE (°C)

3011 G13

–50 –25

25 50 75 100 125 150

0

TEMPERATURE (°C)

3011 G15

3011 G14

C_TComparator Threshold

Current Limit

180

160

140

120

100

80

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

200

180

160

140

120

100

80

V

T

= 0V

V

OUT

J

CT(HIGH)

= 25°C

60

40

V

= 7V

20

V

20

IN

OUT

CT(LOW)

= 0V

0

–50 –25

25 50 75 100 125 150

TEMPERATURE (°C)

3011 G16

0

2

3

4

5

6

10

0

1

7

8

9

–50 –25

25 50 75 100 125 150

TEMPERATURE (°C)

3011 G18

0

INPUT VOLTAGE (V)

3011 G17

3011f

6

LT3011

TYPICAL PERFORMANCE CHARACTERISTICS ^T_J^{= 25°C, unless otherwise noted.}

Reverse Output Current

Input Ripple Rejection

80

160

140

120

100

80

90

88

86

84

82

80

78

76

74

72

70

V

= 0V

= V

V

I

= 7V + 0.5V RIPPLE AT f = 120Hz

P-P

IN

OUT

IN

L

= 1.24V

ADJ

= 50mA

70

60

V

= 1.24V

ADJ PIN CLAMP

(SEE APPLICATIONS

INFORMATION)

OUT

50

40

30

20

10

60

T

= 25°C

IN

J

40

V

= 0V

CURRENT FLOWS

INTO OUTPUT PIN

20

V

OUT

= V

ADJ

0

–50 –25

0

25 50 75 100 125 150

2

3

4

5

6

10

–50 –25

25 50 75 100 125 150

TEMPERATURE (°C)

3011 G21

0

1

7

8

9

0

TEMPERATURE (°C)

OUTPUT VOLTAGE (V)

3011 G19

3011 G20

Input Ripple Rejection

Minimum Input Voltage

Load Regulation

4.0

100

90

80

70

60

50

40

30

20

10

0

–2

I

L

= 50mA

V

I

= 7V + 50mV

RIPPLE

RMS

ΔI = 1mA TO 50mA

L

IN

L

= 50mA, V

= 1.24V

OUT

V

= 1.24V

OUT

3.5

3.0

C

= 10μF

OUT

–4

CERAMIC

2.5

2.0

1.5

1.0

0.5

–6

–8

C

OUT

= 1μF

CERAMIC

–10

0

–12

–50 –25

0

25 50 75 100 125 150

10

100

1k

10k

100k

1M

–50 –25

0

25 50 75 100 125 150

FREQUENCY (Hz)

TEMPERATURE (°C)

3011 G23

3011 G24

3011 G22

Output Noise Spectral Density

Output Noise (10Hz to 100kHz)

Transient Response

10

1

0.3

0.2

0.1

0

V

C

I

= 1.24V

= 1μF

V

C

I

= 1.24V

= 1μF

OUT

= 50mA

L

WORST-CASE NOISE

V

OUT

100μV/DIV

0.1

–0.1

–0.2

50

V

C

= 6V

SET FOR 5V

= 1μF CERAMIC

IN

OUT

IN

0.01

0.001

3011 G26

1ms/DIV

25

= 1μF CERAMIC

LOAD

OUT

ΔI

= 1mA TO 50mA

0

200 300 400 500 600

TIME (μs)

1000

700 800 900

0

100

10

100

1k

10k

100k

FREQUENCY (Hz)

3011 G27

3011 G25

3011f

7

LT3011

PIN FUNCTIONS ^(DFN/MSOP)

OUT (Pin 1/Pin 2): Output. The output supplies power to

the load. A minimum output capacitor of 1μF is required

to prevent oscillations. Larger capacitors will be required

for applications with large transient loads to limit peak

voltage transients. See the Applications Information

section for more information on output capacitance and

reverse output characteristics.

C (Pin 6/Pin 7): Timing Capacitor. The C pin allows the

T T

use of a small capacitor to delay the timing between the

point where the output crosses the PWRGD threshold and

the PWRGD ﬂag changes to a high impedance state. Cur-

rent out of this pin during the charging phase is 3μA. The

voltage difference between the PWRGD low and PWRGD

high states is 1.67V (see the Applications Information

section).

ADJ (Pin 2/Pin 3): Adjust. This is the input to the error

ampliﬁer. This pin is internally clamped to 7V. It has a

bias current of 30nA which ﬂows into the pin (see the

curve labeled ADJ Pin Bias Current vs Temperature in the

Typical Performance Characteristics section). The ADJ

pin voltage is 1.24V referenced to ground, and the output

voltage range is 1.24V to 60V.

SHDN (Pin 8/Pin 9): Shutdown. The SHDN pin is used

to put the LT3011 into a low power shutdown state. The

output will be off when the SHDN pin is pulled low. The

SHDNpincanbedriveneitherby5Vlogicoropen-collector

logic with a pull-up resistor. The pull-up resistor is only

required to supply the pull-up current of the open-collec-

tor gate, normally several microamperes. If unused, the

GND (Pins 3, 11/Pins 4, 13): Ground. The exposed back-

side of the package (Pin 11/Pin 13) is an electrical connec-

tion for GND. As such, to ensure optimum device opera-

tion and thermal performance, the Exposed Pad must be

connected directly to Pin 3/Pin 4 on the PC board.

SHDN pin must be tied to a logic high or V .

IN

IN (Pin 10/Pin 11): Input. Power is supplied to the device

through the IN pin. A bypass capacitor is required on this

pin if the device is more than six inches away from the

main input ﬁlter capacitor. In general, the output imped-

ance of a battery rises with frequency, so it is advisable to

include a bypass capacitor in battery-powered circuits. A

bypass capacitor in the range of 1μF to 10μF is sufﬁcient.

The LT3011 is designed to withstand reverse voltages

on the IN pin with respect to ground and the OUT pin. In

the case of a reverse input voltage, which can occur if a

battery is plugged in backwards, the LT3011 will act as if

there is a diode in series with its input. There will be no

reverse current ﬂow into the LT3011 and no reverse volt-

age will appear at the load. The device will protect both

itself and the load.

NC (Pins 4, 7, 9/Pins 1, 5, 8, 10, 12): No Connection.

These pins have no internal connection. Connecting NC

pins to a copper area for heat dissipation provides a small

improvement in thermal performance.

PWRGD (Pin 5/Pin 6): Power Good. The PWRGD ﬂag is

an open-collector ﬂag to indicate that the output voltage

has increased above 90% of the nominal output voltage.

There is no internal pull-up on this pin; a pull-up resistor

must be used. The PWRGD pin will change state from an

open-collector pull-down to high impedance after both

the output is above 90% of the nominal voltage and the

capacitor on the C pin has charged through a 1.67V dif-

T

Exposed Pad (Pin 11/Pin 13): Ground. The Exposed Pad

must be soldered to the PCB.

ferential. The maximum pull-down current of the PWRGD

pin in the low state is 50μA.

3011f

8

LT3011

APPLICATIONS INFORMATION

The LT3011 is a 50mA high voltage/low dropout regulator

with micropower quiescent current and shutdown. The

deviceiscapableofsupplying50mAatadropoutvoltageof

300mV. Thelowoperatingquiescentcurrent(46μA)drops

to 1μA in shutdown. In addition to low quiescent current,

theLT3011incorporatesseveralprotectionfeatureswhich

make it ideal for use in battery-powered systems. The

device is protected against both reverse input and reverse

output voltages. In battery backup applications where the

output can be held up by a backup battery when the input

is pulled to ground, the LT3011 acts like it has a diode in

series with its output and prevents reverse current ﬂow.

ﬁcations for output voltages greater than 1.24V will be

proportional to the ratio of the desired output voltage to

1.24V; (V /1.24V). For example, load regulation for an

OUT

output current change of 1mA to 50mA is –6mV (typical)

at V

= 1.24V. At V

= 12V, load regulation is:

OUT

12V

1.24V

• – 6mV = – 58mV

Output Capacitance and Transient Response

The LT3011 is designed to be stable with a wide range

of output capacitors. The ESR of the output capacitor

affects stability, most notably with small capacitors. A

minimum output capacitor of 1μF with an ESR of 3Ω or

less is recommended to prevent oscillations. The LT3011

is a micropower device and output transient response

will be a function of output capacitance. Larger values

of output capacitance decrease the peak deviations and

provideimprovedtransientresponseforlargerloadcurrent

changes. Bypass capacitors, used to decouple individual

components powered by the LT3011, will increase the

effective output capacitor value.

Adjustable Operation

TheLT3011hasanoutputvoltagerangeof1.24Vto60V.The

outputvoltageissetbytheratiooftwoexternalresistorsas

showninFigure1.Thedeviceservostheoutputtomaintain

thevoltageattheadjustpinat1.24Vreferencedtoground.

ThecurrentinR1isthenequalto1.24V/R1andthecurrent

in R2 is the current in R1 plus the ADJ pin bias current.

The ADJ pin bias current, 30nA at 25°C, ﬂows through

R2 into the ADJ pin. The output voltage can be calculated

using the formula in Figure 1. The value of R1 should be

less than 250k to minimize errors in the output voltage

caused by the ADJ pin bias current. Note that in shutdown

the output is turned off and the divider current will be zero.

The adjustable device is tested and speciﬁed with the

ADJ pin tied to the OUT pin and a 5μA DC load (unless

otherwise speciﬁed) for an output voltage of 1.24V. Speci-

Extra consideration must be given to the use of ceramic

capacitors. Ceramic capacitors are manufactured with a

variety of dielectrics, each with different behavior across

temperature and applied voltage. The most common

dielectrics used are speciﬁed with EIA temperature char-

acteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and

Y5V dielectrics are good for providing high capacitances

V

OUT

IN

OUT

ADJ

R2

V

= V

1 +

+ (I )(R2)

ADJ

OUT

ADJ

+

R1

LT3011

GND

R2

R1

V

IN

V

I

= 1.24V

= 30nA AT 25oC

OUTPUT RANGE = 1.24V TO 60V

ADJ

3011 F01

Figure 1. Adjustable Operation

3011f

9

LT3011

APPLICATIONS INFORMATION

in a small package, but they tend to have strong voltage PWRGD Flag and Timing Capacitor Delay

andtemperaturecoefﬁcients, asshowninFigures2and3.

The PWRGD ﬂag is used to indicate that the ADJ pin volt-

When used with a 5V regulator, a 16V 10μF Y5V capacitor

age is within 10% of the regulated voltage. The PWRGD

can exhibit an effective value as low as 1μF to 2μF for the

pin is an open-collector output, capable of sinking 50μA

DC bias voltage applied and over the operating tempera-

of current when the ADJ pin voltage is low. There is no

ture range. The X5R and X7R dielectrics result in more

internal pull-up on the PWRGD pin; an external pull-up

stable characteristics and are more suitable for use as the

output capacitor. The X7R type has better stability across

temperature, while the X5R is less expensive and is avail-

able in higher values. Care still must be exercised when

using X5R and X7R capacitors; the X5R and X7R codes

only specify operating temperature range and maximum

capacitancechangeovertemperature.Capacitancechange

due to DC bias with X5R and X7R capacitors is better than

Y5VandZ5Ucapacitors,butcanstillbesigniﬁcantenough

to drop capacitor values below appropriate levels. Capaci-

tor DC bias characteristics tend to improve as component

casesizeincreases, butexpectedcapacitanceatoperating

voltage should be veriﬁed.

resistor must be used. When the ADJ pin rises to within

10% of its ﬁnal reference value, a delay timer is started.

At the end of this delay, programmed by the value of the

capacitor on the C pin, the PWRGD pin switches to a high

T

impedance and is pulled up to a logic level by an external

pull-up resistor.

To calculate the capacitor value on the C pin, use the

T

following formula:

I_CT• t_DELAY

V_CT(HIGH)− V_CT(LOW)

C_TIME

=

Figure 4 shows a block diagram of the PWRGD circuit. At

start-up,thetimingcapacitorisdischargedandthePWRGD

pin will be held low. As the output voltage increases and

the ADJ pin crosses the 90% threshold, the JK ﬂipﬂop is

reset, and the 3μA current source begins to charge the

Voltage and temperature coefﬁcients are not the only

sources of problems. Some ceramic capacitors have a

piezoelectric response. A piezoelectric device generates

voltageacrossitsterminalsduetomechanicalstress,simi-

lar to the way piezoelectric accelerometer or microphone

works. For a ceramic capacitor, the stress can be induced

by vibrations in the system or thermal transients.

timing capacitor. Once the voltage on the C pin reaches

T

the V

threshold (approximately 1.7V at 25°C), the

CT(HIGH)

capacitor voltage is clamped and the PWRGD pin is set to

a high impedance state.

40

20

BOTH CAPACITORS ARE 16V,

1210 CASE SIZE, 10MF

0

X5R

0

–20

X5R

–20

–40

Y5V

–60

Y5V

–80

BOTH CAPACITORS ARE 16V,

1210 CASE SIZE, 10MF

–100

50

TEMPERATURE (oC)

100 125

–50 –25

0

25

75

0

8

12 14

2

4

6

10

16

DC BIAS VOLTAGE (V)

3011 F02

3011 F03

Figure 2. Ceramic Capacitor DC Bias Characteristics

Figure 3. Ceramic Capacitor Temperature Characteristics

3011f

10

LT3011

APPLICATIONS INFORMATION

Duringnormaloperation,aninternalglitchﬁlterwillignore

shorttransients(<15μs).Longertransientsbelowthe90%

threshold will reset the JK ﬂip-ﬂop. This ﬂip-ﬂop ensures

For surface mount devices, heat sinking is accomplished

by using the heat spreading capabilities of the PC board

and its copper traces. Copper board stiffeners and plated

through-holes can also be used to spread the heat gener-

ated by power devices.

that the capacitor on the C pin is quickly discharged all

T

the way to the V

threshold before restarting the

CT(LOW)

time delay. This provides a consistent time delay after the

ADJ pin is within 10% of the regulated voltage before the

PWRGD pin switches to high impedance.

The following table lists thermal resistance for several

different board sizes and copper areas. All measurements

were taken in still air on 3/32" FR-4 board with one ounce

copper.

Thermal Considerations

Table 1. MSOP Measured Thermal Resistance

Thepowerhandlingcapabilityofthedevicewillbelimitedby

themaximumratedjunctiontemperature(125°C,LT3011E/

LT3011I or 150°C, LT3011H). The power dissipated by the

device will be made up of two components:

COPPER AREA

THERMAL RESISTANCE

TOPSIDE

BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)

2500 sq mm 2500 sq mm 2500 sq mm

1000 sq mm 2500 sq mm 2500 sq mm

225 sq mm 2500 sq mm 2500 sq mm

100 sq mm 2500 sq mm 2500 sq mm

52°C/W

54°C/W

58°C/W

64°C/W

1. Output current multiplied by the input/output voltage

differential: I

• (V – V ) and,

OUT

IN OUT

2. GND pin current multiplied by the input voltage:

• V

I

GND

IN

Table 2. DFN Measured Thermal Resistance

COPPER AREA

The GND pin current is found by examining the GND pin

current curves in the Typical Performance Characteristics

section. Power dissipation will be equal to the sum of the

two components listed above.

THERMAL RESISTANCE

TOPSIDE

BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)

2500 sq mm 2500 sq mm 2500 sq mm

1000 sq mm 2500 sq mm 2500 sq mm

225 sq mm 2500 sq mm 2500 sq mm

100 sq mm 2500 sq mm 2500 sq mm

52°C/W

54°C/W

58°C/W

64°C/W

TheLT3011seriesregulatorshaveinternalthermallimiting

designedtoprotectthedeviceduringoverloadconditions.

For continuous normal conditions, the maximum junction

temperature rating of 125°C (LT3011E/ LT3011I) or 150°C

(LT3011H) must not be exceeded. It is important to give

careful consideration to all sources of thermal resistance

fromjunctiontoambient.Additionalheatsourcesmounted

nearby must also be considered.

The thermal resistance junction-to-case (θ ), measured

JC

at the Exposed Pad on the back of the die, is 16°C/W.

Continuous operation at large input/output voltage dif-

ferentials and maximum load current is not practical due

to thermal limitations. Transient operation at high input/

output differentials is possible. The approximate thermal

time-constant for a 2500sq mm 3/32" FR-4 board, with

maximum topside and backside area for one ounce cop-

per, is three seconds. This time-constant will increase as

more thermal mass is added (i.e., vias, larger board and

other components).

I

CT

3μA

C

PWRGD

T

+

–

ADJ

V

CT(HIGH)

– V

BE

(z1.1V)

J

Q

K

V

REF

• 90%

–

+

Foranapplicationwithtransienthighpowerpeaks,average

power dissipation can be used for junction temperature

calculationsaslongasthepulseperiodissigniﬁcantlyless

than the thermal time constant of the device and board.

V

CT(LOW)

z0.1V

3011 F04

Figure 4. PWRGD Circuit Block Diagram

3011f

11

LT3011

APPLICATIONS INFORMATION

Calculating Junction Temperature

Operation at the different power levels is as follows:

Example 1: Given an output voltage of 5V, an input volt-

age range of 24V to 30V, an output current range of 0mA

to 50mA, and a maximum ambient temperature of 50°C,

what will the maximum junction temperature be?

76% operation at P1, 19% for P2, 4% for P3,

and 1% for P4.

P

= 76%(0.23W) + 19%(2.20W) + 4%(0.35W)

EFF

+ 1%(3.42W) = 0.64W

The power dissipated by the device will be equal to:

Withathermalresistanceintherangeof52°C/Wto64°C/W,

this translates to a junction temperature rise above ambi-

ent of 33°C to 41°C.

I

• (V

– V ) + (I

• V

)

OUT(MAX)

IN(MAX)

OUT

GND

IN(MAX)

Where:

I

= 50mA

= 30V

High Temperature Operation

OUT(MAX)

V

CaremustbetakenwhendesigningLT3011applicationsto

operate at high ambient temperatures. The LT3011 works

at elevated temperatures but erratic operation can occur

duetounforeseenvariationsinexternalcomponents.Some

tantalum capacitors are available for high temperature

operation, but ESR is often several ohms; capacitor ESR

above 3Ω is unsuitable for use with the LT3011. Ceramic

capacitor manufacturers (Murata, AVX, TDK and Vishay

Vitramonatthiswriting)nowofferceramiccapacitorsthat

areratedto150°CusinganX8Rdielectric.Deviceinstability

willoccuriftheoutputcapacitorvalueandESRareoutside

design limits at elevated temperature and operating DC

voltage bias (see information on capacitor characteristics

underOutputCapacitanceandTransientResponse).Check

each passive component for absolute value and voltage

ratings over the operating temperature range.

IN(MAX)

I

at (I

= 50mA, V = 30V) = 1mA

GND

OUT IN

So:

P = 50mA • (30V – 5V) + (1mA • 30V) = 1.28W

The thermal resistance will be in the range of 52°C/W to

64°C/W depending on the copper area. So, the junction

temperature rise above ambient will be approximately

equal to:

1.28W • 58°C/W = 74°C

The maximum junction temperature will then be equal to

the maximum junction temperature rise above ambient

plus the maximum ambient temperature or:

T

= 50°C + 74°C = 124°C

JMAX

Example 2: Given an output voltage of 5V, an input voltage

of48Vthatrisesto72Vfor5ms(max)outofevery100ms,

and a 5mA load that steps to 50mA for 50ms out of every

250ms, what is the junction temperature rise above ambi-

ent? Using a 500ms period (well under the time-constant

of the board), power dissipation is as follow:

Leakageincapacitors,orfromsolderﬂuxleftafterinsuf-

ﬁcient board cleaning, adversely affects the low quies-

cent current operation. Consider junction temperature

increase due to power dissipation in both the junction

and nearby components to ensure maximum speciﬁca-

tions are not violated for the LT3011E/LT3011H/LT3011I

or external components.

P1 (48V , 5mA load) = 5mA • (48V – 5V)

IN

+ (200μA • 48V) = 0.23W

Protection Features

P2 (48V , 50mA load) = 50mA • (48V – 5V)

IN

TheLT3011incorporatesseveralprotectionfeatureswhich

make it ideal for use in battery-powered circuits. In ad-

dition to the normal protection features associated with

monolithicregulators,suchascurrentlimitingandthermal

limiting, the device is protected against reverse-input

voltages, and reverse voltages from output-to-input.

+ (1mA • 48V) = 2.20W

P3 (72V , 5mA load) = 5mA (72V – 5V)

IN

+ (200μA • 72V) = 0.35W

P1 (72V , 50mA load) = 50mA (72V – 5V)

IN

+ (1mA • 72V) = 3.42W

3011f

12

LT3011

APPLICATIONS INFORMATION

Current limit protection and thermal overload protection divider is used to provide a regulated 1.5V output from the

areintendedtoprotectthedeviceagainstcurrentoverload

conditions at the output of the device. For normal opera-

tion, the junction temperature should not exceed 125°C

(LT3011E/LT3011I) or 150°C (LT3011H).

1.24V reference when the output is forced to 60V. The top

resistor of the resistor divider must be chosen to limit the

current into the ADJ pin to less than 5mA when the ADJ

pin is at 7V. The 53V difference between the OUT and ADJ

pin is divided by the 5mA maximum current into the ADJ

pin yields a minimum top resistor value of 10.6k.

The input of the device will withstand reverse voltages

of 80V. Current ﬂow into the device will be limited to less

than 6mA (typically less than 100μA) and no negative

voltage will appear at the output. The device will protect

both itself and the load. This provides protection against

batteries which can be plugged in backwards.

In circuits where a backup battery is required, several

different input/output conditions can occur. The output

voltage may be held up while the input is either pulled

to ground, pulled to some intermediate voltage, or is left

open-circuit. Current ﬂow back into the output will follow

the curve shown in Figure 5. The rise in reverse output

current above 7V occurs from the breakdown of the 7V

clampontheADJpin. Witharesistordividerontheregula-

tor output, this current will be reduced depending on the

size of the resistor divider.

The ADJ pin of the adjustable device can be pulled above

or below ground by as much as 7V without damaging the

device.Iftheinputisleftopen-circuitorgrounded,theADJ

pin will act like an open-circuit when pulled below ground,

and like a large resistor (typically 100k) in series with a

diodewhenpulledaboveground.Iftheinputispoweredby

a voltage source, pulling the ADJ pin below the reference

voltage will cause the device to try and force the current

limit out of the output. This will cause the output to go to

an unregulated high voltage. Pulling the ADJ pin above the

reference voltage will turn off all output current.

When the IN pin of the LT3011 is forced below the OUT

pin or the OUT pin is pulled above the IN pin, input cur-

rent will typically drop to less than 2μA. This can happen

if the input of the LT3011 is connected to a discharged

(low voltage) battery and the output is held up by either

a backup battery or a second regulator circuit. The state

of the SHDN pin will have no effect on the reverse output

current when the output is pulled above the input.

In situations where the ADJ pin is connected to a resistor

dividerthatwouldpulltheADJpinaboveits7Vclampvolt-

age if the output is pulled high, the ADJ pin input current

must be limited to less than 5mA. For example, a resistor

160

140

ADJ PIN CLAMP

(SEE ABOVE)

120

100

80

60

40

20

0

T

V

= 25°C

IN

J

= 0V

CURRENT FLOWS

INTO OUTPUT PIN

V

= V

OUT

ADJ

2

3

4

5

6

10

0

1

7

8

9

OUTPUT VOLTAGE (V)

3011 F05

Figure 5. Reverse Output Current

3011f

13

LT3011

TYPICAL APPLICATIONS

5V Buck Converter with Low Current Keep Alive Backup

D2

D1N914

Buck Converter

6

C2

L1^†

Efﬁciency vs Load Current

0.33MF

BOOST

15MH

V

IN

100

90

80

70

60

50

OUT

5V

4

2

5.5V*

V

= 5V

V

SW

OUT

L = 68MH

IN

C3

4.7MF

100V

D1

TO 60V

1A/250mA

V

= 10V

= 42V

IN

10MQ060N

LT1766

CERAMIC

15

14

10

12

SHDN

BIAS

FB

R1

15.4k

C1

+

100MF 10V

SOLID

SYNC

GND

R2

4.99k

TANTALUM

V

C

1, 8, 9, 16 11

C

1nF

0

0.25

0.50

0.75

1.00

1.25

10

1

2

3011 TA03

IN

OUT

LOAD CURRENT (A)

LT3011

*FOR INPUT VOLTAGES BELOW 7.5V,

SOME RESTRICTIONS MAY APPLY

^†INCREASE L1 TO 30MH FOR LOAD

CURRENTS ABOVE 0.6A AND TO

60MH ABOVE 1A.

OPERATING

CURRENT

100k

750k

249k

3011 TA04

8

5

SHDN

ADJ

HIGH

LOW

PWRGD

GND

C

T

3, 11

6

LT3011 PIN NUMBERS ARE FOR

THE DD PACKAGE.

1000pF

LT3011 Automotive Application

IN

OUT

ADJ

NO PROTECTION

DIODE NEEDED!

+

V

IN

LT3011

GND

750k

249k

1MF

12V

(FUTURE 42V)

1MF

LOAD: CLOCK,

SECURITY SYSTEM

ETC

SHDN

OFF

ON

LT3011 Telecom Application

V

IN

OUT

48V

(72V TRANSIENT)

+

–

LT3011

750k

249k

BACKUP

BATTERY

NO PROTECTION

DIODE NEEDED!

1MF

LOAD:

SYSTEM MONITOR

ETC

SHDN

ADJ

GND

3011 TA05

OFF

ON

3011f

14

LT3011

PACKAGE DESCRIPTION

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699)

R = 0.115

TYP

6

0.38

0.10

10

0.675 0.05

3.50 0.05

2.15 0.05 (2 SIDES)

1.65 0.05

3.00 0.10

(4 SIDES)

1.65 0.10

(2 SIDES)

PIN 1

TOP MARK

(SEE NOTE 6)

PACKAGE

OUTLINE

(DD) DFN 1103

5

1

0.25 0.05

0.50 BSC

0.75 0.05

0.200 REF

0.25 0.05

0.50

BSC

2.38 0.10

(2 SIDES)

2.38 0.05

(2 SIDES)

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION

OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS

OF VARIATION ASSIGNMENT

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

MSE Package

12-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1666 Rev B)

BOTTOM VIEW OF

EXPOSED PAD OPTION

2.845 p 0.102

(.112 p .004)

2.845 p 0.102

(.112 p .004)

0.889 p 0.127

(.035 p .005)

1

6

0.35

REF

5.23

(.206)

MIN

1.651 p 0.102

(.065 p .004)

3.20 – 3.45

(.126 – .136)

0.12 REF

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

DETAIL “B”

12

4.039 p 0.102

(.159 p .004)

(NOTE 3)

7

NO MEASUREMENT PURPOSE

0.65

(.0256)

BSC

0.42 p 0.038

(.0165 p .0015)

TYP

0.406 p 0.076

RECOMMENDED SOLDER PAD LAYOUT

(.016 p .003)

12 11 10 9 8 7

REF

DETAIL “A”

0.254

(.010)

3.00 p 0.102

(.118 p .004)

(NOTE 4)

0o – 6o TYP

4.90 p 0.152

(.193 p .006)

GAUGE PLANE

0.53 p 0.152

(.021 p .006)

1

2 3 4 5 6

DETAIL “A”

0.86

(.034)

REF

1.10

(.043)

MAX

0.18

(.007)

SEATING

PLANE

0.22 – 0.38

(.009 – .015)

TYP

0.1016 p 0.0508

(.004 p .002)

MSOP (MSE12) 0608 REV B

0.650

(.0256)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

3011f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

15

LT3011

TYPICAL APPLICATION

Constant Brightness for Indicator LED over Wide Input Voltage Range

RETURN

IN

OUT

LT3011

1MF

OFF

ON

SHDN

GND

ADJ

R

SET

–48V CAN VARY

FROM –4V TO –80V

–48V

3011 TA06

I

= 1.24V/R

SET

LED

RELATED PARTS

PART NUMBER DESCRIPTION

COMMENTS

V : 4.2V to 30V/36V, V

LT1121/

150mA, Micropower, LDO

= 3.75V, V = 0.42V, I = 30μA, I = 16μA,

OUT(MIN) DO Q SD

IN

LT1121HV

Reverse Battery Protection, SOT-223, S8 and Z Packages

LT1676

LT1761

LT1762

LT1763

60V, 440mA (I ), 100kHz, High

V : 7.4V to 60V, V

= 1.24V, I = 3.2mA, I = 2.5μA, S8 Package

Q SD

OUT

IN

OUT(MIN)

Efﬁciency Step-Down DC/DC Converter

100mA, Low Noise Micropower, LDO

V : 1.8V to 20V, V

= 1.22V, V = 0.3V, I = 20μA, I <1μA,

DO Q SD

IN

Low Noise < 20μV

, Stable with 1μF Ceramic Capacitors, ThinSOT^TMPackage

RMS

150mA, Low Noise Micropower, LDO

500mA, Low Noise Micropower, LDO

V : 1.8V to 20V, V

= 1.22V, V = 0.3V, I = 25μA, I <1μA,

, MS8 Package

IN

OUT(MIN) DO Q SD

Low Noise < 20μV

RMS

V : 1.8V to 20V, V

= 1.22V, V = 0.3V, I = 30μA, I <1μA,

DO Q SD

, S8 Package

IN

OUT(MIN)

Low Noise < 20μV

RMS

LT1764/

LT1764A

3A, Low Noise, Fast Transient Response,

LDO

V : 2.7V to 20V, V

= 1.21V, V = 0.34V, I = 1mA, I <1μA,

IN

OUT(MIN) DO Q SD

Low Noise < 40μV

, “A” Version Stable with Ceramic Capacitors,

RMS

DD and TO220-5 Packages

LT1766

LT1776

LT1956

LT1962

60V, 1.2A (I ), 200kHz, High Efﬁciency V : 5.5V to 60V, V

= 1.2V, I = 2.5mA, I = 25μA, TSSOP-16/E Package

Q SD

OUT

IN

OUT(MIN)

Step-Down DC/DC Converter

40V, 550mA (I ), 200kHz, High

V : 7.4V to 40V, V

IN

= 1.24V, I = 3.2mA, I = 30μA, N8 and S8 Packages

Q SD

OUT

Efﬁciency Step-Down DC/DC Converter

60V, 1.2A (I ), 500kHz, High Efﬁciency V : 5.5V to 60V, V

= 1.2V, I = 2.5mA, I = 25μA, TSSOP-16/E Package

Q SD

OUT

IN

Step-Down DC/DC Converter

300mA, Low Noise Micropower, LDO

V : 1.8V to 20V, V

= 1.22V, V = 0.27V, I = 30μA, I <1μA,

DO Q SD

, MS8 Package

IN

Low Noise < 20μV

RMS

LT1963/

LT1963A

1.5A, Low Noise, Fast Transient Response, V : 2.1V to 20V, V

= 1.21V, V = 0.34V, I = 1mA, I <1μA,

IN

OUT(MIN) DO Q SD

LDO

Low Noise < 40μV

, “A” Version Stable with Ceramic Capacitors,

RMS

DD, TO220-5, S0T-223 and S8 Packages

LT1965

1.1A, Low Noise, Low Dropout Linear

Regulator

310mV Dropout Voltage, Low Noise = 40μV

OUT

, V : 1.8V to 20V,

RMS IN

V

: 1.2V to 19.5V, Stable with Ceramic Capacitors, TO-220, DDPak,

MSOP and 3mm × 3mm DFN Packages

280mV Dropout Voltage, Low I = 3μA, V : 1.6V to 20V, ThinSOT and SC-70 Packages

LT3009

20mA, 3μA I Micropower LDO

Q

IN

LT3010/

LT3010H

50mA, 3V to 80V, Low Noise Micropower V : 3V to 8V, V

= 1.275V, V = 0.3V, I = 30μA, I = 1μA,

RMS JMAX

IN

OUT(MIN) DO Q SD

LDO

Low Noise < 100μV

, MS8E Package, H Grade = +140°C T

LT3012/

LT3012H

250mA, 4V to 80V, Low Dropout

Micropower Linear Regulator

V : 4V to 80V, V : 1.24V to 60V, V = 0.4V, I = 40μA, I <1μA,

IN OUT DO Q SD

TSSOP-16E and 4mm × 3mm DFN-12 Packages, H Grade = +140°C T

JMAX

LT3013/

LT3013H

250mA, 4V to 80V, Low Dropout

Micropower Linear Regulator

V : 4V to 80V, V : 1.24V to 60V, V = 0.4V, I = 65μA, I <1μA,

IN OUT DO Q SD

TSSOP-16E and 4mm × 3mm DFN-12 Packages, H Grade = +140°C T

, PWRGD Flag

JMAX

LT3014/HV

20mA, 3V to 80V, Low Dropout

Micropower Linear Regulator

V : 3V to 80V (100V for 2ms, HV Version), V : 1.22V to 60V, V = 0.35V,

IN OUT DO

I = 7μA, I <1μA, ThinSOT and 3mm × 3mm DFN-8 Packages

Q

SD

LT3080/

LT3080-1

1.1A, Parallelable, Low Noise, Low

Dropout Linear Regulator

300mV Dropout Voltage (2-Supply Operation), Low Noise = 40μV

, V : 1.2V to 36V,

RMS IN

V

: 0V to 35.7V, Current-Based Reference with One Resistor V

Set; Directly

OUT

Parallelable (No Op Amp Required), Stable with Ceramic Capacitors, TO-220, SOT-223,

MSOP and 3mm × 3mm DFN Packages; LT3080-1 Features an Integrated Ballast Resistor

ThinSOT is a trademark of Linear Technology Corporation.

3011f

LT 0808 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

16

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT3011IDDTR
厂家：	Linear
描述：	50mA, 3V to 80V Low Dropout Micropower Linear Regulator with PWRGD 50mA时3V至80V低压差微功耗线性稳压器，具有PWRGD 稳压器
文件：	总16页 (文件大小：225K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT3011IDDTR [Linear]

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