LT3023EDD#PBF [Linear]
LT3023 - Dual 100mA, Low Dropout, Low Noise, Micropower Regulator; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C;
| 型号： | LT3023EDD#PBF |
| 厂家： | 
Linear |
| 描述： | LT3023 - Dual 100mA, Low Dropout, Low Noise, Micropower Regulator; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C |
| 文件： | 总24页 (文件大小：277K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3032 Series
Dual 150mA
Positive/Negative Low Noise
Low Dropout Linear Regulator
FEATURES
DESCRIPTION
TheLT®3032isadual, lownoise, positiveandnegativelow
dropout voltage linear regulator. Each regulator delivers
up to 150mA with a typical 300mV dropout voltage. Each
regulator’s quiescent current is low (30μA operating and
<3μAinshutdown)andwell-controlledindropout,making
it an excellent choice for battery-powered circuits.
n
Low Noise: 20μV
(Positive) and
RMS
30μV
(Negative)
RMS
n
n
n
n
n
n
n
n
n
n
n
n
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Low Quiescent Current: 30μA/Channel
Wide Input Voltage Range: 2ꢀ3V to 20V
Output Current: 150mA
Low Shutdown Current: <3μA Total (Typical)
Low Dropout Voltage: 300mV/Channel
Fixed Output Voltages: 5V, 12V, 15V
Adjustable Outputs from 1.22V to 20V
No Protection Diodes Needed
Stable with 2.2μF Output Capacitors
Stable with Ceramic, Tantalum or Aluminum Capacitors
Starts into Reverse Output Voltage
Current Limit and Thermal Limit
Another key feature of the LT3032 is low output noise.
Addinganexternal10nFbypasscapacitortoeachregulator
reducesoutputnoiseto20μV
100kHz bandwidth. The LT3032 is stable with minimum
output capacitors of 2.2μF. The regulators do not require
the addition of ESR as is common with other regulators.
30μV
RMS/
overa10Hzto
RMS
The regulators are offered as adjustable output devices
with an output voltage down to the 1.22V reference volt-
age or in fixed voltages of 5V, 12V and 15V. Internal
protection circuitry includes reverse-output protection,
current limiting and thermal limiting.
Low Profile 14-Lead 4mm × 3mm × 0.75mm
DFN Package
APPLICATIONS
The LT3032 is available in a unique low profile 14-lead
4mm × 3mm × 0.75mm DFN package with exposed back-
side pads for each regulator, allowing optimum thermal
performance.
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Battery-Powered Instruments
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Bipolar Power Supplies
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Low Noise Power Supplies
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
TYPICAL APPLICATION
Dual Polarity Low Noise 150mA Power Supply
10Hz to 100kHz Output Noise
5V OUT AT 150mA
20μV NOISE
INP
OUTP
LT3032-5
RMS
5.4V TO
20V
<0.25V = OFF
>2V = ON
OUTP
10μF
10μF
20μV
30μV
0.01μF
0.01μF
RMS
RMS
10μF
100μV/DIV
BYPP
SHDNP
SHDNN
GND
BYPN
–5.4V TO
–20V
OUTN
100μV/DIV
10μF
–5V OUT AT –150mA
30μV NOISE
INN
OUTN
RMS
3032 TA01
3032 TA02a
1mS/DIV
3032fd
1
LT3032 Series
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
INP Pin Voltage....................................................... 20V
INN Pin Voltage....................................................... 20V
OUTP Pin Voltage.................................................... 20V
OUTN Pin Voltage (Note 3) ..................................... 20V
INP Pin to OUTP Pin Differential Voltage ................ 20V
OUTN Pin to INN Pin Differential Voltage
(Note 3)..........................................................–0.5V, 20V
ADJP Pin Voltage...................................................... 7V
ADJN Pin Voltage
OUTP
1
2
3
4
5
6
7
14 INP
†
NC /ADJP
BYPP
GND
15
GND
13 NC
12 SHDNP
11 BYPN
10 SHDNN
GND
16
INN
INN
9
8
INN
††
OUTN
ADJN/NC
DE14MA PACKAGE
14-LEAD (4mm × 3mm) PLASTIC DFN
T
JMAX
= 125°C, θ = 30°C/W TO 43°C/W*, θ = 10°C/W*
JA JC
(with Respect to INN Pin, Note 3) ..................–0.5V, 20V
BYPP Pin Voltage................................................... 0.5V
BYPN Pin Voltage
(with Respect to INN Pin)........................................ 20V
SHDNP Pin Voltage................................................. 20V
SHDNN Pin Voltage
*SEE APPLICATIONS INFORMATION FOR MORE DETAIL
PIN 2: NC FOR LT3032-5/LT3032-12/LT3032-15, ADJP FOR LT3032
†
††
PIN 8: NC FOR LT3032-5/LT3032-12/LT3032-15, ADJN FOR LT3032
EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PINS 4, 5 ON PCB
EXPOSED PAD (PIN 16) IS INN, MUST BE SOLDERED TO PINS 6, 9 ON PCB
(with Respect to INN Pin, Note 3) ..................–0.5V, 35V
SHDNN Pin Voltage
(with Respect to GND Pin) ..............................–20V, 15V
Output Short-Circuit Duration.......................... Indefinite
Operating Junction Temperature Range (Note 2)
E, I Grades......................................... –40°C to 125°C
MP-Grade .......................................... –55°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
3032
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
LT3032EDE#PBF
LT3032EDE#TRPBF
LT3032IDE#TRPBF
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
LT3032IDE#PBF
3032
LT3032MPDE#PBF
LT3032EDE-5#PBF
LT3032IDE-5#PBF
LT3032MPDE-5#PBF
LT3032EDE-12#PBF
LT3032IDE-12#PBF
LT3032MPDE-12#PBF
LT3032EDE-15#PBF
LT3032IDE-15#PBF
LT3032MPDE-15#PBF
LT3032MPDE#TRPBF
LT3032EDE-5#TRPBF
LT3032IDE-5#TRPBF
LT3032MPDE-5#TRPBF
LT3032EDE-12#TRPBF
LT3032IDE-12#TRPBF
3032
30325
30325
30325
30322
30322
LT3032MPDE-12#TRPBF 30322
LT3032EDE-15#TRPBF
LT3032IDE-15#TRPBF
03215
03215
LT3032MPDE-15#TRPBF 03215
3032fd
2
LT3032 Series
ORDER INFORMATION
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
3032
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
–40°C to 125°C
–40°C to 125°C
–55°C to 125°C
LT3032EDE
LT3032EDE#TR
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
14-Lead (4mm × 3mm) Plastic DFN
LT3032IDE
LT3032IDE#TR
3032
LT3032MPDE
LT3032EDE-5
LT3032IDE-5
LT3032MPDE#TR
LT3032EDE-5#TR
LT3032IDE-5#TR
LT3032MPDE-5#TR
LT3032EDE-12#TR
LT3032IDE-12#TR
LT3032MPDE-12#TR
LT3032EDE-15#TR
LT3032IDE-15#TR
LT3032MPDE-15#TR
3032
30325
30325
30325
30322
30322
30322
03215
03215
03215
LT3032MPDE-5
LT3032EDE-12
LT3032IDE-12
LT3032MPDE-12
LT3032EDE-15
LT3032IDE-15
LT3032MPDE-15
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°Cꢀ
PARAMETER
CONDITIONS
MIN
TYP
1.8
MAX
UNITS
l
l
Minimum INP Operating Voltage
Minimum INN Operating Voltage
LT3032 I
LT3032 I
= 150mA
2.3
V
V
LOAD
LOAD
= –150mA
–2.3
–1.6
Regulated Output Voltage
(Notes 4, 10)
LT3032-5
LT3032-5
LT3032-12
LT3032-12
LT3032-15
LT3032-15
LT3032
V
= 5.5V, I
INP
= 1mA
4.925
4.850
5.00
5.00
5.075
5.150
V
V
INP
LOAD
l
l
l
l
l
l
l
l
6V ≤ V ≤ 20V, 1mA ≤ I
≤ 150mA
LOAD
V
= –5.5V, I
INN
= –1mA
–5.075
–5.150
–5.00
–5.00
–4.925
–4.850
V
V
INN
LOAD
–6V ≥ V ≥ –20V, –1mA ≥ I
≥ –150mA
LOAD
V
= 12.5V, I
INP
= 1mA
11.82
11.64
12.00
12.00
12.18
12.36
V
V
INP
LOAD
13V ≤ V ≤ 20V, 1mA ≤ I
≤ 150mA
LOAD
V
= –12.5V, I
= –1mA
–12.18 –12.00 –11.82
–12.36 –12.00 –11.64
V
V
INN
LOAD
–13V ≥ V ≥ –20V, –1mA ≥ I
≥ 150mA
INN
LOAD
V
= 15.5V, I
INP
= 1mA
14.775
14.550
15.00
15.00
15.225
15.450
V
V
INP
LOAD
16V ≤ V ≤ 20V, 1mA ≤ I
≤ 150mA
LOAD
V
= –15.5V, I
= –1mA
–15.225 –15.00 –14.775
–15.450 –15.00 –14.550
V
V
INN
LOAD
–16V ≥ V ≥ –20V, –1mA ≥ I
≥ 150mA
INN
LOAD
ADJP Pin Voltage
(Notes 4, 5)
V
= 2V, I
= 1mA
1.202
1.184
1.22
1.22
1.238
1.256
V
V
INP
LOAD
2.3V ≤ V ≤ 20V, 1mA ≤ I
≤ 150mA
INP
LOAD
ADJN Pin Voltage
(Notes 4, 5, 10)
LT3032
V
= –2V, I
= –1mA
–1.238
–1.256
–1.22
–1.22
–1.202
–1.184
V
V
INN
LOAD
–2.3V ≤ V ≤ –20V, –1mA ≤ I
≤ –150mA
INN
LOAD
l
l
Line Regulation (Note 5)
LT3032-5 OUTP
OUTN
ΔV = 5.5V to 20V, I
INN
= 1mA
LOAD
1
15
6
50
mV
mV
INP
LOAD
ΔV = –5.5V to –20V, I
= –1mA
l
l
LT3032-12 OUTP
OUTN
ΔV = 12.5V to 20V, I
INN
= 1mA
LOAD
1.5
13
15
75
mV
mV
INP
LOAD
ΔV = –12.5V to –20V, I
= –1mA
l
l
LT3032-15 OUTP
OUTN
ΔV = 15.5V to 20V, I
INN
= 1mA
LOAD
2
10
20
75
mV
mV
INP
LOAD
ΔV = –15.5V to 20V, I
= –1mA
l
l
LT3032
ADJP
ADJN
ΔV = 2V to 20V, I
INN
= 1mA
LOAD
1
1
6
12
mV
mV
INP
LOAD
ΔV = –2V to –20V, I
= –1mA
3032fd
3
LT3032 Series
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°Cꢀ
PARAMETER
CONDITIONS
LT3032-5 OUTP
MIN
TYP
–9
MAX
UNITS
mV
Load Regulation (Notes 5, 13)
V
V
V
V
V
V
= 6V, ΔI
= 1mA to 150mA
INP
INN
INP
INN
INP
INN
LOAD
LT3032-5 OUTN
LT3032-12 OUTP
LT3032-12 OUTN
LT3032-15 OUTP
LT3032-15 OUTN
= –6V, ΔI
= 13V, ΔI
= –1mA to –150mA
= 1mA to 150mA
15
mV
LOAD
20
mV
LOAD
= –13V, ΔI
= –1mA to –150mA
20
mV
LOAD
= 16V, ΔI
= 1mA to 150mA
25
mV
LOAD
= –16V, ΔI
= –1mA to –150mA
27
mV
LOAD
LT3032
ADJP
V
INP
V
INP
= 2.3V, ΔI
= 2.3V, ΔI
= 1mA to 150mA
= 1mA to 150mA
–1.5
–7
–15
mV
mV
LOAD
LOAD
l
LT3032
ADJN
V
V
= –2.3V, ΔI
= –2.3V, ΔI
= –1mA to –150mA
= –1mA to –150mA
1.5
7
mV
mV
INN
INN
LOAD
LOAD
l
l
l
15
Dropout Voltage
I
I
I
I
I
I
I
I
= 1mA
0.09
0.15
0.21
0.27
0.10
0.15
0.21
0.30
0.20
0.27
V
V
V
V
V
V
V
V
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
V
= V
OUTP(NOMINAL)
INP
= 10mA
= 50mA
(Notes 6, 7)
= 150mA
= –1mA
l
l
Dropout Voltage
0.20
0.27
V
= V
OUTN(NOMINAL)
INN
= –10mA
= –50mA
= –150mA
(Notes 6, 7)
l
l
l
l
l
l
l
GND Pin Current
I
I
I
I
I
I
I
= 0mA (LT3032, LT3032-5)
–25
–50
–70
–80
–350
–1.3
–4
–65
–120
–120
180
–500
–1.8
–7
μA
μA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
V
= V
, V = 0V
OUTP(NOMINAL) INN
= 0mA (LT3032-12, LT3032-15)
= 1mA (LT3032, LT3032-5)
= 1mA (LT3032-12, LT3032-15)
= 10mA
INP
(Notes 6, 8, 9)
μA
μA
μA
mA
mA
= 50mA
= 150mA
l
l
l
l
l
l
l
GND Pin Current
I
I
I
I
I
I
I
= 0mA (LT3032, LT3032-5)
= 0mA (LT3032-12, LT3032-15)
= –1mA (LT3032, LT3032-5)
= –1mA (LT3032-12, LT3032-15)
= –10mA
30
50
70
130
180
180
600
1.5
5
μA
μA
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
V
= V
, V = 0V
INN
OUTN(NOMINAL) INP
(Notes 6, 8, 9, 10)
85
μA
90
μA
μA
mA
mA
300
0.75
2
= –50mA
= –150mA
ADJP Pin Bias Current
ADJN Pin Bias Current
Shutdown Threshold
LT3032
LT3032
(Notes 5, 9)
(Notes 5, 9)
30
100
–100
2
nA
nA
–30
l
l
l
l
l
l
SHDNP
SHDNP
SHDNN
SHDNN
SHDNN
SHDNN
V
OUTP
V
OUTP
V
OUTN
V
OUTN
V
OUTN
V
OUTN
= Off to On
0.7
0.6
1.4
–1.9
1.4
–1.9
V
V
V
V
V
V
= On to Off
0.25
= Off to On (Positive)
= Off to On (Negative)
= On to Off (Positive)
= On to Off (Negative)
2
–2.8
0.25
–0.25
SHDNP Pin Current (Note 9)
V
V
= 0V
–1
–1
1
4
μA
μA
SHDNP
SHDNP
= 20V
1
SHDNN Pin Current
(Note 9)
V
V
V
= 0V
= 15V
= -15V
1
15
–9
μA
μA
μA
SHDNN
SHDNN
SHDNN
6
–3
l
l
l
Quiescent Current in Shutdown
V
V
V
= 6V, V
= 0V, V = 0V
0.1
–3
10
8
–10
20
μA
μA
μA
INP
INN
INN
SHDNP
INN
= –6V, V
= 0V, V = 0V (LT3032, LT3032-5)
SHDNN
INP
–1V, V
= V
= 0V, V = 0V
OUT(NOMINAL)
SHDNN INP
(LT3032-12/ LT3032-15)
3032fd
4
LT3032 Series
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°Cꢀ
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Output Voltage Noise (10Hz to 100kHz)
C
OUTP
C
OUTN
= 10μF, C
= 10μF, C
0.01μF, I
0.01μF, I
= 150mA
= –150mA
20
30
μV
RMS
μV
RMS
BYPP
BYPN
LOAD
LOAD
Ripple Rejection
V
V
to V
= 1.5V (Average), I = 100mA
LOAD
50
46
68
54
dB
dB
INP
INN
OUTP
OUTN
V
= 0.5V
f
= 120Hz
to V
= –1.5V (Average), I
= –100mA
RIPPLE
P-P, RIPPLE
LOAD
Current Limit (Note 12)
V
V
V
V
= 7V, V
= 0V
OUTN
OUTP(NOMINAL)
OUTP(NOMINAL)
400
350
mA
mA
mA
mA
INP
INN
INP
INN
OUTP
= –7V, V
= 0V
l
l
= 2.3Vor V
= –2.3Vor V
+ 1V, ΔV
= –0.1V
OUTN
170
170
OUTP
– 1V, ΔV
= 0.1V
l
l
INP Reverse Leakage Current
INN Reverse Leakage Current
V
INP
V
INN
= –20V, V
= 0V
–1
1
mA
mA
OUTP
= 20V, V
, V
, V
= Open Circuit
OUTN ADJN SHDNN
Reverse Output Current
(Notes 5, 11)
LT3032-5
LT3032-12
LT3032-15
LT3032
V
V
V
V
= 5V, V < 5V
10
25
25
5
20
50
50
10
μA
μA
μA
μA
OUTP
OUTP
OUTP
OUTP
INP
= 12V, V < 12V
INP
= 15V, V < 15V
INP
= V
= 1.22V, V < 1.22V
INP
ADJP
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
For lower output voltages, dropout voltage is limited by the minimum
input voltage specification under some output voltage/load conditions;
see curves for Minimum INN Voltage and Minimum INP Voltage in Typical
Performance Characteristics. LTC is unable to guarantee Maximum
Dropout Voltage specifications at 50mA and 150mA due to production
test limitations with Kelvin-Sensing the package pins. Please consult the
Typical Performance Characteristics for curves of Dropout Voltage as a
function of Output Load Current and Temperature.
Note 2: The LT3032 is tested and specified under pulse load conditions
such that T ≅ T . The LT3032E is 100% tested at T = 25°C. Performance
J
A
A
of the LT3032E over the full –40°C to 125°C operating junction
temperature range is assured by design, characterization, and correlation
with statistical process controls. The LT3032I regulators are guaranteed
over the full –40°C to 125°C operating junction temperature range.
Note 8: GND pin current is tested with V = V
or V
=
INP
OUTP(NOMINAL)
INN
V
and a current source load. This means the device is tested
OUTN(NOMINAL)
while operating in its dropout region. This is the worst-case GND pin
current. GND pin current decreases slightly at higher input voltages.
Note 9: Positive current flow is into the pin. Negative current flow is out of
Note 3: Parasitic diodes exist internally between the INN pin and the OUTN,
ADJN, and SHDNN pins. These pins cannot be pulled more than 0.5V
below the INN pin during fault conditions, and must remain at a voltage
more positive than the INN pin during operation.
the pin.
Note 4: Operating conditions are limited by maximum junction
Note 10: For input-to-output differential voltages from INN to OUTN
greater than –7V, a –50μA load is needed to maintain regulation.
Note 11: Reverse output current is tested with the INP pin grounded and
the OUTP pin forced to the nominal output voltage. This current flows into
the OUTP pin and out the GND pin.
temperature. Specifications do not apply for all possible combinations of
input voltages and output currents. When operating at maximum input
voltages, the output current ranges must be limited. When operating at
maximum output currents, the input voltage ranges must be limited.
Note 5: The LT3032 is tested and specified for these conditions with the
ADJP pin tied to the OUTP pin and the ADJN pin tied to the OUTN pin.
Note 12: Positive side current limit is tested at V = 2.3V or
INP
V
+ 1V (whichever is more positive). Negative side current
OUTP(NOMINAL)
Note 6: To satisfy requirements for minimum input voltage, the LT3032 is
tested and specified for these conditions with an external resistor divider
(two 250k resistors) from OUTP/OUTN to the corresponding ADJP/ADJN
pin to give an output voltage of 2.44V. The external resistor divider adds a
5μA DC load on the output. The LT3032-12/LT3032-15 have higher internal
resistor divider current, resulting in higher GND pin current at light/no load.
Note 7: Dropout voltage is the minimum input-to-output voltage
differential needed to maintain regulation at a specified output current. In
dropout, output voltage equals:
limit is tested at V = –2.3V or V
negative).
Note 13: LTC is unable to guarantee load regulation specifications on
fixed voltage versions of the LT3032 due to production test limitations
with Kelvin-Sensing the package pins. Please consult the Typical
Performance Characteristics for curves of Load Regulation as a function of
Temperature.
– 1V (whichever is more
INN
OUTN(NOMINAL)
V
– V
DROPOUT
INP/INN
3032fd
5
LT3032 Series
TYPICAL PERFORMANCE CHARACTERISTICS
INP-to-OUTP
Typical Dropout Voltage
INN-to-OUTN
Typical Dropout Voltage
INP-to-OUTP
Dropout Voltage
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
T
T
= 125°C
= 25°C
J
J
I
= 150mA
L
T
= 125°C
J
I
= 50mA
= 10mA
= 1mA
L
T
= 25°C
I
L
J
I
L
0
–50
0
0
0
–40
–80
–120
–160
0
25
50
75
125
40
120
–25
100
0
20
60 80 100
140 160
TEMPERATURE (°C)
LOAD CURRENT (mA)
LOAD CURRENT (mA)
3032 G02
3032 G03
3032 G01
INN-to-OUTN
Dropout Voltage
INP Quiescent Current
INN Quiescent Current
500
450
400
350
300
250
200
150
100
50
70
60
50
40
30
20
10
0
–60
–50
–40
–30
–20
–10
I
I
= 0 (FIXED VOLTAGES)
= –5μA (ADJUSTABLE)
I
I
= 0 (FIXED VOLTAGES)
= 5μA (ADJUSTABLE)
L
L
L
L
V
= V = V
INP
+1V
OUTP(NOMINAL)
SHDNP
(12V, 15V)
V
= V = V
INN
–1V
OUTN(NOMINAL)
SHDNN
I
= 150mA
= 50mA
(12V, 15V)
L
V
= V = 6V
INP
SHDNP
(5V, ADJ)
V
= V
= –6V
INN
SHDNN
(5V, ADJ)
I
L
I
= 10mA
= 1mA
L
I
L
V
= 0V, V
50
= –6V
INN
SHDNN
V
= 0V, V = 6V
INP
SHDNP
0
–50
0
–25
0
25
50
75
125
0
25
50
75 100 125
–50
100
–50 –25
0
25
75 100 125
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3032 G04
3032 G05
3032 G06
LT3032-5 OUTP Output Voltage
LT3032-5 OUTN Output Voltage
LT3032-12 OUTP Output Voltage
12.24
12.18
12.12
12.06
12.00
11.94
11.88
11.82
11.76
5.100
5.075
5.050
5.025
5.000
4.975
4.950
4.925
4.900
–5.100
–5.075
–5.050
–5.025
–5.000
–4.975
–4.950
–4.925
–4.900
I
L
= –1mA
I
= 1mA
L
I = 1mA
L
–25
0
25
50
75
125
–25
0
25
50
75
125
–25
0
50
75 100 125
–50
100
–50
100
–50
25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3032 G58
3032 G52
3032 G53
3032fd
6
LT3032 Series
TYPICAL PERFORMANCE CHARACTERISTICS
LT3032-12 OUTN Output Voltage
LT3032-15 OUTP Output Voltage
LT3032-15 OUTN Output Voltage
–12.24
–12.18
–12.12
–12.06
–12.00
–11.94
–11.88
–11.82
–11.76
15.300
15.225
15.150
15.075
15.000
14.925
14.850
14.775
14.700
–15.300
–15.225
–15.150
–15.075
–15.000
–14.925
–14.850
–14.775
–14.700
I
= –1mA
I
= 1mA
I = –1mA
L
L
L
–25
0
25
50
75
125
–25
0
25
50
75
125
–25
0
25
50
75
125
–50
100
–50
100
–50
100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3032 G59
3032 G60
3032 G61
LT3032 ADJP Pin Voltage
LT3032 ADJN Pin Voltage
LT3032-5 INP Quiescent Current
–1.240
–1.235
–1.230
–1.225
–1.220
–1.215
–1.210
–1.205
–1.200
400
350
300
250
200
150
100
50
1.240
1.235
1.230
1.225
1.220
1.215
1.210
1.205
1.200
I
L
= –1mA
T
= 25°C
= ∞
J
L
I
= 1mA
L
R
V
= V
INP
SHDNP
V
= 0V
SHDNP
0
–25
0
25
50
75
125
–50 –25
0
25
50
75 100 125
–50
100
0
2
4
6
8
10 12 14 16 18 20
TEMPERATURE (°C)
TEMPERATURE (°C)
INP VOLTAGE (V)
3032 G08
3032 G07
3032 G54
LT3032-5 INN Quiescent Current
LT3032-12 INP Quiescent Current
LT3032-12 INN Quiescent Current
400
350
300
250
200
150
100
50
–80
–70
–60
–50
–40
–30
–20
–10
0
–60
–50
–40
–30
–20
–10
–0
T
= 25°C
= ∞
T
= 25°C
= ∞
T
= 25°C
R = ∞
L
J
L
J
L
J
R
R
V
= V
INN
SHDNN
V
= V
SHDNN INN
V
= V
INP
SHDNP
V
= 0V
SHDNN
V
= 0V
SHDNN
V
= 0V
SHDNP
0
0
–2 –4 –6 –8 –10 –12 –14 –16 –18 –20
0
2
4
6
8
10 12 14 16 18 20
0
–2 –4 –6 –8 –10 –12 –14 –16 –18 –20
INN VOLTAGE (V)
INP VOLTAGE (V)
INP VOLTAGE (V)
3032 G55
3032 G62
3032 G63
3032fd
7
LT3032 Series
TYPICAL PERFORMANCE CHARACTERISTICS
LT3032-15 INP Quiescent Current
LT3032-15 INN Quiescent Current
LT3032 INP Quiescent Current
400
350
300
250
200
150
100
50
–80
–70
–60
–50
–40
–30
–20
–10
0
30
25
20
15
10
5
T
= 25°C
= ∞
T
= 25°C
R = ∞
L
J
L
J
R
V
= V
INP
SHDNP
V
= V
INP
SHDNP
T
= 25°C
= 250k
J
L
V
V
= V
INN
SHDNN
R
= 0V
SHDNN
V
= 0V
SHDNP
V
= 0V
SHDNP
0
0
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
0
–2 –4 –6 –8 –10 –12 –14 –16 –18 –20
INP VOLTAGE (V)
INP VOLTAGE (V)
INN VOLTAGE (V)
3032 G09
3032 G64
3032 G65
LT3032-5
Positive Side GND Pin Current
LT3032-5
Negative Side GND Pin Current
LT3032 INN Quiescent Current
–40
–35
–30
–25
–20
–15
–10
–5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
= 25°C
SHDNN
T
= 25°C
= V
J
J
INP
T
= 25°C
= 250k
J
L
V
= V
V
INN
= –5V
SHDNP
R
*FOR V
*FOR V
= 5V
OUTN
OUTP
I
= –5μA
L
R
L
= 33.3Ω
V
= V
INN
L
SHDNN
I
= 150mA*
R
L
= 33.3Ω
L
I
= 150mA*
R
L
= 50Ω
= –100mA*
L
I
R
= 50Ω
= 100mA*
L
R
L
= 100Ω
L
I
L
I
= –50mA*
R
= 100Ω
L
= 50mA*
R = 500Ω
L
I = –10mA*
L
V
= 0V
SHDNN
I
L
–0
0
–2 –4 –6 –8 –10 –12 –14 –16 –18 –20
0
–1 –2 –3 –4 –5 –6 –7 –8 –9 –10
4
0
1
2
3
5
6
7
8
9
10
INN VOLTAGE (V)
INN VOLTAGE (V)
INP VOLTAGE (V)
3032 G10
3032 G57
3032 G56
LT3032-12
Positive Side GND Pin Current
LT3032-12
Negative Side GND Pin Current
LT3032-15
Positive Side GND Pin Current
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
= 25°C
SHDNP
T = 25°C
J
T
= 25°C
SHDNP
J
J
R
= 100Ω
L
L
V
= V
V
= V
SHDNN INN
V
= V
INP
INP
*I = 150mA
*FOR V
= 12V
*FOR V
= –12V
OUTN
*FOR V
= 15V
OUTP
OUTP
R
= 80Ω
L
L
*I = 150mA
R
= 80Ω
L
L
*I = –150mA
R = 150Ω
L
*I = 100mA
R
= 120Ω
*I = 100mA
L
L
L
R
= 120Ω
L
*I = –100mA
L
R
= 240Ω
L
R
= 240Ω
*I = 50mA
L
*I = –50mA
L
L
R
= 300Ω
L
*I = 50mA
L
R
= 1.2k, *I = –10mA
L
L
0
2
4
6
8
10 12 14 16 18 20
0
–2 –4 –6 –8 –10 –12 –14 –16 –18 –20
2
4
6
10 12 14 16 18 20
0
8
INP VOLTAGE (V)
INN VOLTAGE (V)
INP VOLTAGE (V)
3032 G66
3032 G67
3032 G68
3032fd
8
LT3032 Series
TYPICAL PERFORMANCE CHARACTERISTICS
LT3032-15
Negative Side GND Pin Current
LT3032
LT3032
Negative Side GND Pin Current
Positive Side GND Pin Current
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
= 25°C; V
= V
;
INN
T
= 25°C
SHDNN
J
SHDNN
J
T
= 25°C
J
*FOR V
= –1.22V
V
= V
OUTN
INN
V
= V
INP
SHDNP
*FOR V
= –15V
OUTN
*FOR V
= 1.22V
OUTP
R
L
= 8.07Ω
= –150mA*
R
= 100Ω
L
I
*I = –150mA
L
L
R
L
= 8.07Ω
L
I
= 150mA*
R
L
= 12.2Ω
= –100mA*
L
I
R
= 150Ω
R
= 12.2Ω
L
L
L
*I = –100mA
I
= 100mA*
L
R
= 24.4Ω
L
R
L
= 24.4Ω
I
= –50mA*
L
L
I
= 50mA*
R
L
= 122Ω
= –10mA*
L
R
= 300Ω, *I = 50mA
L
L
I
R
= 1.5k, *I = –10mA
L
L
0
–1 –2 –3 –4 –5 –6 –7 –8 –9 –10
0
–2 –4 –6 –8 –10 –12 –14 –16 –18 –20
4
0
1
2
3
5
6
7
8
9
10
INN VOLTAGE (V)
INN VOLTAGE (V)
INP VOLTAGE (V)
3032 G12
3032 G69
3032 G11
Positive Side GND Pin Current
vs ILOAD
Negative Side GND Pin Current
vs ILOAD
SHDNP Pin Threshold
–4.0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= V
– 1V
OUTN(NOMINAL)
V
= V
+ 1V
INN
I
L
= 1mA
INP
OUTP(NOMINAL)
T
= 25°C
J
ON
T
= –50°C
J
T
= 25°C
J
OFF
T
= 125°C
J
0
–20 –40 –60 –80 –100 –120 –140 –160
40
120
–50
0
25
50
75
125
0
20
60 80 100
140 160
–25
100
NEGATIVE LOAD CURRENT (mA)
TEMPERATURE (°C)
POSITIVE LOAD CURRENT (mA)
3032 G14
3032 G13
3032 G15
SHDNN Pin Thresholds
SHDNP Pin Input Current
SHDNP Pin Input Current
2.5
2.0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
= 20V
SHDNP
ON
1.5
1.0
0.5
0
OFF
ON
–0.5
–1.0
–1.5
–2.0
–2.5
–25
0
25
50
75
125
–50 –25
0
25
50
75 100 125
–50
100
4
0
1
2
3
5
6
7
8
9
10
TEMPERATURE (°C)
TEMPERATURE (°C)
SHDNP PIN VOLTAGE (V)
3032 G16
3032 G18
3032 G17
3032fd
9
LT3032 Series
TYPICAL PERFORMANCE CHARACTERISTICS
SHDNN Pin Input Current
SHDNN Pin Input Current
ADJP Pin Bias Current
10
8
12
9
140
120
100
80
V
= –15V
INN
T
= 25°C
J
POSITIVE CURRENT
FLOWS INTO THE PIN
POSITIVE CURRENT
FLOWS INTO THE PIN
6
6
4
V
V
= 15V
SHDNN
SHDNN
2
3
0
0
60
–2
–4
–6
–8
–10
= –15V
–3
–6
–9
40
20
0
–50 –25
0
25
TEMPERATURE (°C)
50
75 100 125
–50
0
25
50
75 100 125
–10 –8 –6 –4 –2
0
2
4
6
8
10
–25
TEMPERATURE (°C)
SHDNN PIN VOLTAGE (V)
3032 G19
3032 G20
3032 G21
ADJN Pin Bias Current
Positive Side Current Limit
Positive Side Current Limit
–70
–60
–50
–40
–30
–20
–10
0
500
450
400
350
300
250
200
150
100
50
500
450
400
350
300
250
200
150
100
50
V
= 0V
V
= 7V
= 0V
OUTP
INP
OUTP
V
0
0
–50 –25
0
25
50
75 100 125
0
2
3
4
5
6
7
50
TEMPERATURE (°C)
125
1
–50
0
25
75 100
–25
TEMPERATURE (°C)
INP-TO-OUTP DIFFERENTIAL VOLTAGE (V)
3032 G22
3032 G23
3032 G24
Negative Side Current Limit
Negative Side Current Limit
Reverse OUTP Pin Current
–600
–500
–400
–300
–200
–100
0
–600
–500
–400
–300
–200
–100
0
100
90
80
70
60
50
40
30
20
10
0
T
= 25°C, V = 0V
INP
J
ΔV
OUTN
= 100mV
V
V
= –7V
INN
OUTN
CURRENT FLOWS
INTO OUTP PIN
= 0V
LT3032
V
= V
(LT3032)
OUTP
ADJP
LT3032-5
LT3032-12
LT3032-15
0
–4
–8
–12
–16
–20
–50 –25
0
25
50
75 100 125
8
0
2
4
6
10 12 14 16 18 20
INN-TO-OUTN DIFFERENTIAL VOLTAGE (V)
TEMPERATURE (°C)
OUTP PIN VOLTAGE (V)
3032 G25
3032 G26
3032 G27
3032fd
10
LT3032 Series
TYPICAL PERFORMANCE CHARACTERISTICS
Reverse OUTP Pin Current
INP-to-OUTP Ripple Rejection
INP-to-OUTP Ripple Rejection
45
40
35
30
25
20
15
10
5
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
V
V
V
V
V
= 0V
C
= 0.01μF
INP
BYPP
= V
=1.22V (LT3032)
OUTP
OUTP
OUTP
OUTP
ADJP
= 5V (LT3032-5)
= 12V (LT3032-12)
= 15V (LT3032-15)
C
= 1000pF
BYPP
C
= 100pF
BYPP
C
C
= 10μF
= 2.2μF
OUTP
(LT3032-12/LT3032-15)
I
= 150mA
L
I = 150mA
L
(LT3032-5)
OUTP
V
= V
+
INP
OUTP(NOMINAL)
V
= V
+
INP
OUTP(NOMINAL)
1.5V + 50mV
C
RIPPLE
RMS
1.5V + 50mV
RIPPLE
RMS
= 0
BYPP
C
= 10μF
(LT3032)
OUTP
0
10
100
1k
10k
100k
1M
10
100
1k
10k
100k
1M
–50
0
25
50
75 100 125
–25
FREQUENCY (Hz)
FREQUENCY (Hz)
TEMPERATURE (°C)
3032 G29
3032 G30
3032 G28
INN-to-OUTN Ripple Rejection
INP-to-OUTP Ripple Rejection
INN-to-OUTN Ripple Rejection
80
70
60
50
40
30
20
10
0
68
66
64
62
60
58
56
54
52
60
58
56
54
52
50
48
46
44
I
= –150mA
L
V
= V
P-P
= –150mA
– 1.5V +
OUTN(NOMINAL)
INN
V
= V
– 1.5V +
INN
OUTN(NOMINAL)
0.5V RIPPLE AT f = 120Hz
50mV
RIPPLE
RMS
I
L
C
= 0
BYPN
C
= 10μF
OUTN
V
= V
+
INP
OUTP(NOMINAL)
1.5V + 0.5V RIPPLE
P-P
AT f = 120Hz
I
= 150mA
C
= 1μF
L
OUTN
10k
10
100
1k
100k
1M
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
FREQUENCY (Hz)
TEMPERATURE (°C)
TEMPERATURE (°C)
3032 G31
3032 G33
3032 G32
LT3032 Minimum INP Pin Voltage
LT3032 Minimum INN Pin Voltage
Positive Load Regulation
0
–10
–20
–30
–40
–50
–60
–70
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
LT3032
LT3032-5
V
= 1.22V
OUTP
I
= 150mA
L
LT3032-12
I
I
= –150mA
= –1mA
L
L
I
= 1mA
L
LT3032-15
NOTE: THE SHDNN PIN THRESHOLD
MUST BE MET TO ENSURE
DEVICE OPERATION
V
= V
+1V
50
INP
OUTP(NOMINAL)
ΔI = 1mA TO 150mA
L
–50 –25
0
25
75 100 125
–50 –25
0
25
50
75 100 125
–50
0
25
50
75 100 125
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3032 G36
3032 G35
3032 G34
3032fd
11
LT3032 Series
TYPICAL PERFORMANCE CHARACTERISTICS
Negative Load Regulation
OUTP Noise Spectral Density
OUTN Noise Spectral Density
10
1
10
1
60
50
40
30
20
10
0
C
I
= 10μF
V
I
= V
– 1V
OUTN(NOMINAL)
OUTP
L
INN
L
= 150mA
= –1mA TO –150mA
C
= 1000pF
C
C
BYPP
= 0.01μF
BYPN
= 100pF
BYPN
C
= 1000pF
BYPP
C
= 100pF
C
= 0
BYPP
BYPN
LT3032-12
LT3032-15
0.1
LT3032-5
0.1
0.01
C
= 0.01μF
= 10μF
BYPN
OUTN
C
I
V
V
= –5V
= V
OUTN
OUTN
LT3032
75 100 125
V
V
= 5V
ADJP
OUTP
OUTP
= –150mA
L
ADJN
= V
0.01
–50 –25
0
25
50
10
100
1k
FREQUENCY (Hz)
10k
100k
10
100
1k
FREQUENCY (Hz)
10k
100k
TEMPERATURE (°C)
3032 G39
3032 G37
3032 G38
OUTP RMS Noise
vs Bypass Capacitor
OUTP RMS Noise
vs Load Current (10Hz to 100kHz)
OUTN RMS Noise
vs Bypass Capacitor
350
300
250
200
150
100
50
350
300
250
200
150
100
50
250
200
150
100
50
LT3032-15
C
L
= 10μF
OUTN
C
I
= 10μF
OUTP
L
LT3032-12
LT3032-5
LT3032
LT3032-15
LT3032-12
I
= –150mA
= 150mA
LT3032-15
LT3032-12
f = 10Hz TO 100kHz
f = 10Hz TO 100kHz
LT3032-15
C
BYPP
BYPP
= 10μF
OUTP
C
C
= 0
= 0.01μF
LT3032-12
LT3032-5
LT3032
LT3032-5
LT3032
LT3032-5
LT3032
0
0
0
10
100
1k
10k
0.01
0.1
1
10
LOAD CURRENT (mA)
100
1k
10
100
1k
10k
C
(pF)
C
(pF)
BYPN
BYPP
3032 G42
3032 G40
3032 G41
OUTN RMS Noise
vs Load Current (10Hz to 100kHz)
OUTP 10Hz to 100kHz Output Noise
CBYPP = 0
OUTP 10Hz to 100kHz Output Noise
CBYPP = 0ꢀ01μF
140
120
100
80
C
= 10μF
OUTN
C
= 0
= 0.01μF
BYPN
BYPN
C
LT3032-15
LT3032-15
LT3032-12
LT3032-5
LT3032
LT3032-12
V
V
OUTP
100μV/DIV
OUTP
100μV/DIV
60
LT3032-5
40
LT3032
3032 G44
3032 G45
20
C
L
V
= 10μF
1ms/DIV
C
= 10μF
OUTP
1ms/DIV
OUTP
I
= 150mA
I = 150mA
L
0
= 5V
V
= 5V
OUTP
OUTP
–0.01
–0.1
–1
–10
–100
–1k
LOAD CURRENT (mA)
3032 G43
3032fd
12
LT3032 Series
TYPICAL PERFORMANCE CHARACTERISTICS
OUTN, 10Hz to 100kHz
Output Noise, CBYPN = 0
OUTP Transient Response
CBYPP = 0
OUTN, 10Hz to 100kHz Output
Noise, CBYPN = 0ꢀ01μF
0.3
0.2
0.1
0
V
V
C
C
= 5V
OUTP
INP
INP
= 6V
= 10μF
= 10μF
OUTP
V
OUTN
–0.1
–0.2
–0.3
150
100
50
V
OUTN
100μV/DIV
200μV/DIV
3032 G46
3032 G47
C
= 10μF
= –150mA
= –5V
1ms/DIV
OUTN
LOAD
C
= 10μF
= –150mA
= –5V
1ms/DIV
OUTN
LOAD
I
I
V
0
OUTN
V
OUTN
800
TIME (μs)
0
400
1200
1600
2000
3032 G48
OUTP Transient Response
CBYPP = 0ꢀ01μF
OUTN Transient Response
CBYPN = 0
OUTN Transient Response
CBYPN = 0ꢀ01μF
0.06
0.04
0.02
0
V
= –5V
V
OUTN
= –5V
V
= 5V
OUTN
OUTP
0.2
0.1
0.04
0.02
0
V
C
C
= –6V
V
C
C
= –6V
V
C
C
= 6V
INN
INN
OUTN
INN
INN
OUTN
INP
INP
OUTP
= 10μF
= 10μF
= 10μF
= 10μF
= 10μF
= 10μF
0
–0.02
–0.04
–0.06
0
–0.1
–0.2
0
–0.02
–0.04
–50
–100
–150
150
100
50
–50
–100
–150
0
80
TIME (μs)
0
40
120
160
200
0
100 200 300 400 500 600 700 800 900 1k
0
50 100 150 200 250 300 350 400 450 500
TIME (μs)
TIME (μs)
3032 G49
3032 G50
3032 G51
3032fd
13
LT3032 Series
PIN FUNCTIONS
OUTP(Pin1):PositiveOutput.Thisoutputsuppliespower
to the positive side load. A minimum output capacitor
of 2.2μF is required to prevent oscillations. Larger out-
put capacitors are required for applications with large
transient loads to limit peak voltage transients. See the
Applications Information section for more information
on output capacitance, bypass capacitance, and reverse
output characteristics.
a battery rises with frequency, so it is advisable to include
a bypass capacitor in battery-powered circuits. A bypass
capacitor in the range of 1μF to 10μF is sufficient.
OUTN(Pin7):NegativeOutput.Thisoutputsuppliespower
to the negative side load. A minimum output capacitor
of 1μF is required to prevent oscillations. Larger output
capacitors are required for applications with large tran-
sient loads to limit peak voltage transients. A parasitic
diode exists between OUTN and INN; OUTN can not be
pulled more negative than INN during normal operation,
or more than 0.5V below INN during a fault condition. See
theApplicationsInformationsectionformoreinformation
on output capacitance and bypass capacitors.
ADJP (Pin 2, Adjustable Part Only): Positive Adjust. This
is the input to the positive side error amplifier. This pin
is internally clamped to 7V. It has a typical bias current
of 30nA which flows into the pin (see curve of ADJP Pin
Bias Current vs Temperature in the Typical Performance
Characteristics).TheADJPpinvoltageis1.22Vreferenced
to ground and the output voltage range is 1.22V to 20V.
ADJN(Pin8, AdjustablePartOnly):NegativeAdjust. This
is the input to the negative side error amplifier. The ADJN
pin has a typical bias current of 30nA that flows out of the
pin. The ADJN pin voltage is –1.22V referenced to ground,
andtheoutputvoltagerangeis–1.22Vto–20V. Aparasitic
diode exists between ADJN and INN. The ADJN pin cannot
bepulledmorenegativethanINNduringnormaloperation,
or more than 0.5V below INN during a fault condition.
BYPP (Pin 3): Positive Bypass. The BYPP pin is used to
bypassthereferenceofthepositivesideregulatortoachieve
low noise performance. The BYPP pin is clamped internally
to 0.6V (one V ). A small capacitor from OUTP to this pin
BE
will bypass the reference to lower the output voltage noise.
A maximum value of 0.01μF is used for reducing output
voltage noise to a typical 20μV
over the 10Hz to 100kHz
RMS
SHDNN(Pin10):NegativeShutdown.TheSHDNNpinputs
the negative side into a low power shutdown state. The
SHDNN pin is referenced to ground for regulator control,
allowing the negative side to be driven by either positive
or negative logic. The negative output will be off if the
SHDNN pin is within 0.8V(typical) of ground. Pulling the
SHDNNpinmorethan–1.9Vor+1.4V(typical)willturnthe
negative output on. The SHDNN pin can be driven by 5V
logic or open-collector logic with a pull-up resistor. The
pull-up resistor is required to supply the pull-up current of
theopen-collectordevice,normallyseveralmicroamperes,
and the SHDNN pin current, typically 3μA out of the pin
(for negative logic) or 6μA into the pin (for positive logic).
If unused, the SHDNN pin must be connected to INN. The
negativeoutputwillbeshutdowniftheSHDNNpinisopen
circuit. A parasitic diode exists between SHDNN and INN,
the SHDNN pin cannot be pulled more negative than INN
during normal operation, or more than 0.5V below INN
during a fault condition.
bandwidth. If not used, this pin must be left unconnected.
GND (Pins 4, 5, Exposed Pad Pin 15): Ground. One of
the DFN’s exposed backside pads (Pin 15) is an electrical
connection to ground. To ensure proper electrical and
thermal performance, solder Pin 15 to the PCB’s ground
and tie directly to Pins 4 and 5. Connect the bottom of
the positive and negative output voltage setting resistor
dividers directly to Pins 4 and 5 for optimum load regula-
tion performance.
INN (Pin 6, 9, Exposed Pad Pin 16): Negative Input. The
DFN package’s second exposed backside pad (Pin 16) is
an electrical connection to INN. To ensure proper electri-
cal and thermal performance, solder Pin 16 to the PCB’s
negative input supply and tie directly to Pins 6 and 9.
Power is supplied to the negative side of the LT3032
through the INN pins. A bypass capacitor is required on
this pin if it is more than six inches away from the main
input filter capacitor. In general, the output impedance of
3032fd
14
LT3032 Series
PIN FUNCTIONS
BYPN (Pin 11): Negative Bypass. The BYPN pin is used
to bypass the reference of the negative side regulator to
achieve low noise performance. A small capacitor from
OUTN to this pin will bypass the reference to lower the
output voltage noise. A maximum value of 0.01μF is used
The positive output will be shut down if the SHDNP pin
is open circuit. The SHDNP pin can be tied directly to the
SHDNN pin and both pins driven directly by positive logic
for a single point control of both outputs.
NC (Pin 13/Pins 2, 8 for Fixed Voltage Devices): No
Connect. The No Connect pin has no connection to inter-
nal circuitry and may be tied to INP, GND, INN, SHDNP,
SHDNN, OUTP, OUTN, floated, or tied to any other point.
for reducing output voltage noise to a typical 30μV
RMS
over the 10Hz to 100kHz bandwidth. If not used, this pin
must be left unconnected.
SHDNP(Pin12):PositiveShutdown. TheSHDNPpinputs
the positive side into a low power shutdown state. The
positive output will be off when the SHDNP pin is pulled
below 0.6V(typical). The SHDNP pin can be driven by 5V
logic or open-collector logic with a pull-up resistor. The
pull-up resistor is required to supply the pull-up current
of the open-collector device, normally several microam-
peres, and the SHDNP pin current, typically 1μA into the
pin. If unused, the SHDNP pin must be connected to INP.
INP (Pin 14): Positive Input. Power is supplied to the
positive side of the LT3032 through the INP pin. A bypass
capacitorisrequiredonthispinifitismorethansixinches
away from the main input filter capacitor. In general, the
output impedance of a battery rises with frequency, so
it is advisable to include a bypass capacitor in battery-
powered circuits. A bypass capacitor in the range of 1μF
to 10μF is sufficient.
3032fd
15
LT3032 Series
APPLICATIONS INFORMATION
TheLT3032isadual150mApositiveandnegativelownoise
low dropout linear regulator with micropower quiescent
current and shutdown. It supplies 150mA at a dropout
of 300mV. Output voltage noise can be lowered on the
V
OUTP
LT3032
OUTP
R2P
R1P
⎛
⎝
⎞
(
R2P
)
V
V
= 1.22 V 1+
+
I
(
)
⎜
⎟
⎠
OUTP
ADJP
+
+
R2P
R1P
R1N
R2N
= 1.22 V
ADJP
ADJP
I
= 30nA at 25°C
ADJP
OUTPUT RANGE = 1.22 V TO 20 V
positive side to 20μV
and to 30μV
on the negative
RMS
RMS
GND
side over the 10Hz to 100kHz bandwidth with the addition
of 0.01μF reference bypass capacitors. Additionally, the
reference bypass capacitors improve transient response,
lowering the settling time for transient load conditions.
Quiescent current is 25μA for the positive side and –30μA
for the negative side (45μA each for the LT3032-12/
LT3032-15), typically dropping to less than 3μA total in
shutdown. In addition to the low quiescent current, the
LT3032 incorporates several protection features which
make it ideal for use in battery-powered systems. If the
load is common mode between the two outputs, it does
not matter which output starts first; either output can be
pulled to the opposing side of ground and the regulator
will still start and operate.
R2N
R1N
⎛
⎞
(
ADJN
)
V
V
= –1.22 V 1+
+
I
(
R2N
)
⎜
⎟
⎠
OUTN
⎝
= –1.22 V
ADJN
ADJN
OUTN
I
= –30nA at 25°C
ADJN
OUTPUT RANGE = –1.22 V TO – 20 V
V
OUTN
3032 F01
Figure 1ꢀ Setting Output Voltages
The LT3032 is tested and specified with the ADJP/ADJN
pin tied to the respective OUTP/OUTN pin and a 5μA DC
load (unless otherwise specified) for an output voltage
of 1.22V. Specifications for output voltages greater than
this will be proportional to 1.22V; (V / 1.22V). For
OUT
example, load regulation for an output current change
Setting Output Voltage
of 1mA to 150mA is –2mV typical at V
= –1.22V. At
OUTN
V
= –12V, load regulation is:
OUTN
The adjustable LT3032 has output voltage ranges of 1.22V
to 20V for the positive side and –1.22V to –20V for the
negative side. The output voltages are set by the ratio of
two external resistor dividers as shown in Figure 1. The
LT3032 servos the outputs to maintain the voltages at the
ADJP and ADJN pins to 1.22V and –1.22V, respectively.
The current in the bottom resistor of each divider (R1P
or R1N) is equal to 1.22V/R1 and the current in the top
resistor (R2P or R2N) is equal to the current in the bottom
resistor plus the respective ADJP/ADJN pin bias current.
The bias current for ADJP and ADJN is 30nA at 25°C,
flowing into the pin for ADJP and flowing out of the pin
for ADJN. The output voltages can then be calculated us-
ing the formulas shown in Figure 1. The value of R1P or
R1N should be less than 250k to minimize errors in the
resultant output voltage caused by the ADJP/ADJN pin
bias current. Note that in shutdown the respective output
is turned off and the divider current will be zero. Curves
of ADJP Pin Voltage, ADJN Pin Voltage, ADJP Pin Bias
Current, and ADJN Pin Bias Current (all vs Temperature)
appear in the Typical Performance Characteristics.
(–12V/–1.22V)•(–2mV) = –19.6mV
Bypass Capacitors and Low Noise Performance
The LT3032 provides reasonable noise performance
without reference bypass capacitors from OUTP/OUTN
to the corresponding BYPP/BYPN pin. Using the LT3032
with the addition of reference bypass capacitors lowers
output voltage noise. Good quality low leakage capacitors
are recommended. These capacitors bypass the internal
referencesforthepositiveandnegativesidesoftheLT3032,
providing low frequency noise poles. The noise poles
provided by the bypass capacitors decrease the output
voltage noise to as low as 20μV
for the positive side
RMS
and 30μV
for the negative side with the use of 0.01μF
RMS
bypass capacitors.
The BYPP pin and BYPN pin are high impedance nodes
and leakage into or out of these pins affects the reference
voltage. The BYPP pin operates at approximately 74mV at
3032fd
16
LT3032 Series
APPLICATIONS INFORMATION
25°C during normal operation where the BYPN pin oper-
ates at approximately –60mV. DC leakages on the order
of 1μA into or out of these pins can throw off the internal
reference by 20% or more.
Give extra consideration to the use of ceramic capacitors.
Ceramic capacitors are manufactured with a variety of di-
electrics, each with different behavior across temperature
and applied voltage. The most common dielectrics used
are specified with EIA temperature characteristic codes of
Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are
good for providing high capacitances in a small package,
but they tend to have strong voltage and temperature
coefficients as shown in Figures 3 and 4. When used with
a 5V regulator, a 16V 10ꢀF Y5V capacitor can exhibit an
effective value as low as 1ꢀF to 2ꢀF for the DC bias voltage
appliedandovertheoperatingtemperaturerange.TheX5R
and X7R dielectrics result in more stable characteristics
and are more suitable for use as the output capacitor.
The X7R type has better stability across temperature,
while the X5R is less expensive and is available in higher
values. Care still must be exercised when using X5R and
X7R capacitors. The X5R and X7R codes only specify
operating temperature range and maximum capacitance
change over temperature. Capacitance change due to DC
bias with X5R and X7R capacitors is better than Y5V and
Z5U capacitors, but can still be significant enough to drop
capacitor values below appropriate levels. Capacitor DC
bias characteristics tend to improve as component case
size increases, but expected capacitance at operating
voltage should be verified in situ for a given application.
Output Capacitance and Transient Response
The LT3032 requires output capacitors for stability. It
is designed to be stable with most low ESR capacitors
(typically ceramic, tantalum or low ESR electrolytic). A
minimum output capacitor of 2.2ꢀF with an ESR of 3Ω
or less is recommended to prevent oscillations on each
output. The LT3032 is a micropower device and output
transient response is a function of output capacitance.
Larger values of output capacitance decrease peak de-
viations and provide improved transient response for
largerloadcurrentchanges.Additionalcapacitors,usedto
decouple individual components powered by the LT3032,
increase the effective output capacitor value. When using
bypass capacitors (for low noise operation), larger values
of output capacitors are needed. For 100pF of bypass ca-
pacitance, 3.3μF of output capacitance is recommended.
With a 330pF bypass capacitor or larger, a 4.7μF output
capacitor is recommended. The shaded region of Figure 2
defines the range over which the LT3032 is stable. The
minimum ESR needed is defined by the amount of bypass
capacitance used, while the maximum ESR is 3ꢁ. These
requirements are applicable to both the positive and nega-
tive linear regulator.
Voltage and temperature coefficients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress. In
a ceramic capacitor, the stress can be induced by vibra-
tions in the system or thermal transients. Tapping on the
ceramicbypasscapacitorwithapencilgeneratedthenoise
shown in Figure 5. Similar vibration induced behavior can
masquerade as increased output voltage noise.
4.0
3.5
3.0
STABLE REGION
2.5
2.0
1.5
1.0
0.5
0
C
= 0
BYP
C
= 100pF
BYP
C
= 330pF
BYP
C
≥ 3300pF
BYP
1
3
6
9 10
8
2
4
5
7
OUTPUT CAPACITANCE (μF)
1762 F02
Figure 2ꢀ Stability
3032fd
17
LT3032 Series
APPLICATIONS INFORMATION
20
Stability and Input Capacitance
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
0
Low ESR, ceramic input bypass capacitors are acceptable
forapplicationswithoutlonginputleads.However,applica-
tions connecting a power supply to an LT3032’s circuit’s
INP/INN and GND pins with long input wires combined
withlowESR,ceramicinputcapacitorsarepronetovoltage
spikes, reliability concerns and application-specific board
oscillations. The input wire inductance found in many
battery-poweredapplications, combinedwiththelowESR
ceramic input capacitor, forms a high-Q LC resonant tank
circuit. In some instances this resonant frequency beats
against the output current dependent LDO bandwidth and
interferes with proper operation. Simple circuit modifica-
tions/solutions are then required. This behavior is not
indicative of LT3032 instability, but is a common ceramic
input bypass capacitor application issue.
X5R
–20
–40
–60
Y5V
–80
–100
0
8
12 14
2
4
6
10
16
DC BIAS VOLTAGE (V)
3032 F03
Figure 3ꢀ Ceramic Capacitor DC Bias Characteristics
40
20
The self-inductance, or isolated inductance, of a wire is
directly proportional to its length. Wire diameter is not a
major factor on its self-inductance. For example, the self-
inductance of a 2-AWG isolated wire (diameter = 0.26”) is
about half the self-inductance of a 30-AWG wire (diameter
= 0.01”). One foot of 30-AWG wire has about 465nH of
self-inductance.
X5R
0
–20
–40
Y5V
–60
–80
BOTH CAPACITORS ARE 16V,
1210 CASE SIZE, 10μF
One of two ways reduces a wire’s self-inductance. One
method divides the current flowing towards the LT3032
between two parallel conductors. In this case, the farther
apart the wires are from each other, the more the self-
inductanceisreduced;uptoa50%reductionwhenplaced
a few inches apart. Splitting the wires basically connects
two equal inductors in parallel, but placing them in close
proximity gives the wires mutual inductance adding to
the self-inductance. The second and most effective way
to reduce overall inductance is to place both forward and
return current conductors (the input and GND wires) in
verycloseproximity.Two30-AWGwiresseparatedbyonly
0.02”, used as forward– and return– current conductors,
reduce the overall self-inductance to approximately one-
fifth that of a single isolated wire.
–100
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
3032 F04
Figure 4ꢀ Ceramic Capacitor Temperature Characteristics
3032 F05
OUTPUT SET TO 5V
Figure 5ꢀ Noise Resulting From Tapping on a Ceramic Capacitor
3032fd
18
LT3032 Series
APPLICATIONS INFORMATION
The LT3032 is a surface mount device and heat sinking is
accomplished by using the heat spreading capabilities of
the PC board and its copper traces. Copper board stiffen-
ers and plated through-holes can also be used to spread
the heat generated by power devices.
If wiring modifications are not permissible for the applica-
tions,includingseriesresistancebetweenthepowersupply
and the input of the LT3032 also stabilizes the application.
As little as 0.1ꢁ to 0.5ꢁ, often less, is effective in damp-
ing the LC resonance. If the added impedance between
the power supply and the input is unacceptable, adding
ESR to the input capacitor also provides the necessary
damping of the LC resonance. However, the required ESR
is generally higher than the series impedance required.
Note that the exposed pads (Pins 15 and 16) are elect-
ricallyconnectedtoground(GND)andthenegativeinput
(INN) respectivelyꢀ
The following table lists thermal resistance as a function
of copper area on a fixed board size. All measurements
were taken in still air on a 4-layer FR-4 board with 1oz
solid internal planes and 2oz external trace planes with a
total finished board thickness of 1.6mm.
Thermal Considerations
The power handling capability of the device is limited by
the maximum rated junction temperature (125°C). The
power dissipated by the device is made up of the follow-
ing components:
Table 3ꢀ DE Package, 14-Lead DFN
COPPER AREA
1. Output current of each side multiplied by the respective
THERMAL RESISTANCE
TOPSIDE*
BACKSIDE
BOARD AREA (JUNCTION-TO-AMBIENT)
input/output voltage differential: (I )(V to V ),
OUT
IN
OUT
2
2
2
2500mm
2500mm
2500mm
2500mm
2500mm
2500mm
32°C/W
33°C/W
38°C/W
43°C/W
and
2. GND pin current for each side multiplied by its input
voltage: (I )(V )
2
2
2
2
2
1000mm
2500mm
2
2
225mm
2500mm
GND
IN
2
2
100mm
2500mm
The GND pin current of each side is found by examining
the GND Pin Current curves in the Typical Performance
Characteristics. Total power dissipation equals the sum
for both channels of the components listed above.
*Device is mounted on topside
For further information on thermal resistance and using
thermal information, refer to JEDEC standard JESD51,
notably JESD51-12.
The LT3032 has internal thermal limiting designed to pro-
tect each side of the regulator during overload conditions.
For continuous normal conditions, the maximum junction
temperature rating of 125°C must not be exceeded. It is
important to give careful consideration to all sources of
thermal resistance from junction to ambient. Additional
heat sources mounted nearby must also be considered.
PCB layers, copper weight, board layout and thermal vias
affect the resultant thermal resistance. This table provides
thermal resistance numbers for best-case 4-layer boards
with 1oz internal and 2oz external copper. Modern, mul-
tilayer PCBs may not be able to achieve quite the same
level performance as found in this table.
3032fd
19
LT3032 Series
APPLICATIONS INFORMATION
Calculating Junction Temperature
Protection Features
Example: Given a positive output voltage of 3.3V, a posi-
tive input voltage of 4V to 6V, output current range from
10mAto150mA,negativeoutputvoltageof–3.3V,negative
input voltage of –5V to –6V, a negative output current of
–100mA, and a maximum ambient temperature of 50°C,
what will the maximum junction temperature be for a
The LT3032 incorporates several protection features that
make it ideal for use in battery-powered circuits. In ad-
dition to the normal protection features associated with
monolithicregulators,suchascurrentlimitingandthermal
limiting, the LT3032 is protected against reverse input
voltages and reverse output voltages on both channels.
2
2
2500mm board with topside copper of 1000mm ?
Current limit protection and thermal overload protection
protect the device against current overload conditions at
the outputs of the part. For normal operation, the junction
temperature should not be allowed to exceed 125°C.
The power in each side equals:
P
= (V
– V )(I
)+(V
•I
)
SIDE
IN(MAX)
OUT OUT(MAX)
IN(MAX) GND
where,
The positive input of the LT3032 withstands 20V reverse
voltage. The negative input also withstands reverse volt-
age, but the negative input may not be more than 0.5V
I
= 150mA
= 6V
OUTP(MAX)
V
(one V ) higher than the OUTN and SHDNN pins. This
INP(MAX)
BE
provides protection against batteries that are plugged in
backwards.
I
I
at (I
= 150mA, V = 6V) = 3.7mA
OUTP INP
GND
OUTN(MAX)
= –100mA
= –6V
The outputs of the LT3032 can be pulled to opposing volt-
ageswithoutdamagingthepart.Theoutputsmaybepulled
to the opposing polarity with a load that is common mode
between the two and one regulator starts before the other;
inthiscondition,itdoesnotmatterwhichregulatorstarted
first. Both sides are capable of having the output pulled to
the opposing polarity and both will still start and operate.
V
I
INN(MAX)
at (I
= –100mA, V = –6V) = –1.5mA
INN
GND
OUTN
The total power equals:
P
= P
+ P
TOTAL
POSITIVE NEGATIVE
If an input is left open circuit or grounded, the corre-
sponding output can be pulled to its opposing polarity by
as much as 20V. The output will act like an open circuit;
no current will flow into or out of the pin. If the input is
powered by a voltage source, the output will source the
short-circuit current and will protect itself by thermal
limiting. In this case, grounding the respective SHDNP/
SHDNN pin will turn off that side of the LT3032 and stop
the output from sourcing current.
So,
P
= 150mA(6V – 3.3V) + 3.7mA(6V) = 0.43W
POSITIVE
P
= –100mA(–6V+3.3V)–1.5mA(–6V) =
NEGATIVE
0.28W
P
= 0.43W + 0.28W = 0.71W
TOTAL
Junction Temperature equals:
T = T + P • θ (using tables)
J
A
TOTAL
JA
The ADJP pin can be pulled above or below ground by
7V without damage to the device. If the input is left open
circuit or grounded, the ADJP pin acts like an open circuit
whenpulledbelowgroundandlikealargeresistor(typically
100k) in series with a diode when pulled above ground.
T = 50°C + 0.71W • 33°C/W = 73.4°C
J
In this case, the junction temperature is below the maxi-
mum rating, ensuring reliable operation.
3032fd
20
LT3032 Series
APPLICATIONS INFORMATION
In situations where the ADJP pin is connected to a resistor
divider that would pull the ADJP pin above its 7V clamp
voltage if the output is pulled high, the ADJP pin input
current must be limited to less than 5mA. For example, a
resistor divider is used to provide a 1.5V output from the
1.22V reference and the output is forced to 20V. The top
resistor of the divider must be chosen to limit the current
into the ADJP pin to less than 5mA when the ADJP pin is
at7V. The13VdifferencebetweenOUTPandADJPdivided
by the 5mA maximum current into the ADJP pin yields a
minimum top resistor value of 2.6k.
Like many IC power regulators, the negative side of the
LT3032hassafeoperatingarea(SOA)protection. Thesafe
operating area protection activates when the differential
voltage between INN and OUTN is greater than -7V. The
SOA protection decreases current limit as a function of
the voltage differential between INN and OUTN and keeps
the power transistor inside a safe operating region for all
values of forward input-to-output voltage. The protection
is designed to provide some output current at all values
of INN to OUTN differential voltage up to the Absolute
Maximum Rating. A 50μA load is required to maintain
regulation for INN to OUTN differential voltages greater
than –7V. When in shutdown, protection circuitry remains
activeandwillcausetheoutputtoriseslightlyatzeroload.
A small pre-load is needed for zero output, if desired (see
graph of Quiescent Current vs Input Voltage in Typical
Performance Characteristics).
In circuits where a backup battery is required on the posi-
tive output, several different input/output conditions can
occur. The output voltage may be held up while the input
is either pulled to ground, pulled to some intermediate
voltage or is left open circuit. Current flow back into OUTP
follows the curve shown in Figure 6.
When power to the negative side is first turned on, as the
inputvoltagerises,OUTNfollowsINN,allowingtheregula-
tor to start into very heavy loads. During start-up, as the
INN voltage is rising, the differential voltage between INN
and OUTN is small, allowing the negative side to supply
large output currents. With a high INN voltage, a problem
can occur wherein removal of an output short will not al-
low the output voltage to fully recover. Other regulators,
such as the LT1175, LT1964, and LT3080 also exhibit this
phenomenon, so it is not unique to the LT3032.
100
T
= 25°C, V = 0V
INP
J
CURRENT FLOWS
INTO OUTP PIN
90
80
70
60
50
40
30
20
10
0
LT3032
V
= V
(LT3032)
OUTP
ADJP
LT3032-5
LT3032-12
LT3032-15
8
0
2
4
6
10 12 14 16 18 20
TheproblemoccurswithaheavyoutputloadwhentheINN
voltageishighandtheOUTNvoltageislow. Commonsitu-
ations are immediately after the removal of a short-circuit
or when the SHDNN pin is pulled high after the INN pin
has already been turned on. The load line for such a load
may intersect the output current curve at two points. If
this happens, there are two stable operating points for the
negative side of the LT3032. With this double intersection,
the INN supply may need to be cycled down to zero and
brought up again to make OUTN recover.
OUTP PIN VOLTAGE (V)
3032 F06
Figure 6ꢀ Reverse Output Current
If the INP pin is forced below the OUTP pin or the OUTP
pin is pulled above the INP pin, input current typically
drops to less than 2μA. This can happen if the device is
connected to a discharged (low voltage) battery and the
output is held up by a backup battery or a second regula-
tor circuit. The state of the SHDNP pin has no effect on
the reverse output current if OUTP is pulled above INP.
3032fd
21
LT3032 Series
PACKAGE DESCRIPTION
Please refer to http://wwwꢀlinearꢀcom/designtools/packaging/ for the most recent package drawingsꢀ
DE14MA Package
14-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1731 Rev A)
1.78 p0.05
0.70 p0.05
0.10 TYP
0.51 TYP
3.50 p0.05
1.65 p 0.05
2.10 p0.05
1.65 p 0.05
1.07
p0.05
PACKAGE
OUTLINE
0.25 p 0.05
0.50 BSC
3.00 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.115
TYP
8
4.00 p0.10
(2 SIDES)
1.78 p0.10
14
R = 0.05
TYP
1.07
p0.10
0.10 TYP
0.51 TYP
3.00 p0.10
1.65 p 0.10
0.40 p 0.10
1.65 p 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PIN 1 NOTCH
R = 0.20 OR
0.25 s 45o
CHAMFER
7
1
0.25 p 0.05
0.75 p0.05
0.200 REF
0.50 BSC
(DE14MA) DFN 0507 REV A
3.00 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3032fd
22
LT3032 Series
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
08/10 Updated all applicable sections to add fixed voltage 5V option.
1-7, 9-14
B
01/11 Swapped OUTN and INN pins in Absolute Maximum Ratings.
Revised values in SHDNN and SHDNP descriptions in Pin Functions.
Revised quiescent current for the positive side up to 25μA in Applications Information.
09/11 Updated to add 12V and 15V options
2
12, 13
14
C
D
1-12, 21
03/12 Added MP-Grade to Order Information and Absolute Maximum Ratings
2, 3
3032fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LT3032 Series
TYPICAL APPLICATION
5V to 15V Tracking Supply
5V TO 15V
AT 150mA
10μF
5.5V TO
20V
INP
OUTP
LT3032
0.01μF
536k
BYPP
OFF ON
SHDNP
SHDNN
ADJP
GND
95.3k
250k
ADJN
BYPN
0.01μF
536k
10μF
–5V TO –15V
AT –150mA
–5.5V TO
–20V
OUTN
3032 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1175
800mA Negative Low Dropout
Micropower Regulator
V : –4.5V to -20V, I = 45ꢀA, 0.5V Dropout Voltage, S8, DD-Pak, TO-220 and SOT-223
IN
Q
Packages
LT1761
LT1762
LTC1844
100mA, Low Noise LDO
300mV Dropout Voltage, Low Noise: 20μV
, V = 1.8V to 20V, ThinSOT package
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Dual 100mA, Low Noise, Micropower LDO V : 1.8V to 20V, V
= 1.22V, VDO = 0.30V, I = 40ꢀA, ISD < 1ꢀA; DFN and MS10E
Q
IN
OUT(MIN)
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LT3024
LT3027
LT3028
LT3029
Dual 100mA/500mA, Low Noise,
Micropower LDO
V : 1.8V to 20V, V
= 1.22V, VDO = 0.30V, I = 60ꢀA, ISD < 1ꢀA; DFN and
Q
IN
OUT(MIN)
TSSOP-16E Packages
Dual 100mA, Low Noise, Micropower
LDO with Independent Inputs
V : 1.8V to 20V, V
= 1.22V, VDO = 0.30V, I = 50ꢀA, ISD < 1ꢀA; DFN and MS10E
Q
IN
OUT(MIN)
Packages
Dual 100mA/500mA, Low Noise,
Micropower LDO with Independent Inputs TSSOP-16E Packages
V : 1.8V to 20V, V
= 1.22V, VDO = 0.32V, I = 60ꢀA, ISD < 1ꢀA; DFN and
IN
OUT(MIN)
Q
Dual 500mA/500mA, Low Dropout, Low
Noise, Micropower Linear Regulator
Low Noise: 20ꢀV
(10Hz to 100kHz), Low Quiescent Current: 55ꢀA per Channel Wide
RMS
Input Voltage Range: 1.8V to 20V (Common or Independent Input Supply) Adjustable
Output: 1.215V Reference, Very Low Quiescent Current in Shutdown: <1ꢀA per Channel
Stable with 3.3ꢀF Minimum Output Capacitor, Thermally Enhanced 16-Lead MSOP and
16-Lead (4mm × 3mm) DFN Packages
LT3082
200mA, Parallelable, Single Resistor, Low Wide Input Voltage Range: 1.2V to 40V Low Value Input/Output Capacitors Required:
Dropout Linear Regulator 0.22ꢀF, Single Resistor Sets Output Voltage Initial Set Pin Current Accuracy: 1%, Low
Output Noise: 40ꢀV (10Hz to 100kHz) Reverse-Battery Protection, Reverse-Current
RMS
Protection 8-Lead SOT-23, 3-Lead SOT-223 and 8-Lead 3mm × 3mm DFN Packages
3032fd
LT 0312 REV D • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
© LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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