LT3472EDD#PBF_技术文档

LT3472

Boost and Inverting

DC/DC Converter

for CCD Bias

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FEATURES

DESCRIPTIO

The LT^®3472 dual channel switching regulator generates

positive and negative outputs for biasing CCD imagers.

The device delivers up to –8V at 50mA and 15V at 20mA

from a lithium-ion cell, providing bias for many popular

CCD imagers. Switching at 1.1MHz, the LT3472 uses tiny,

low profile capacitors and inductors and generates low

noise outputs that are easy to filter. Schottky diodes are

internal and the output voltages are set with one resistor

per channel, reducing external component count. The

entire solution is less than 1mm profile and occupies just

50mm².

■

Generates 15V at 20mA, –8V at 50mA

from a Li-Ion Cell

■

Internal Schottky Diodes

■

V_INRange: 2.2V to 16V

Output Voltages Up to ±34V

Capacitor-Programmable Soft-Start

■

Sequencing: Positive Output Reaches 88% of Final

Value Before Negative Output Begins

■

Requires Only One Resistor to Set Output Voltage

■

Constant Switching Frequency Ensures Low

Noise Outputs

■

Available in a 10-Lead (3mm × 3mm) DFN Package

Internal sequencing circuitry disables the negative chan-

nel until the positive channel has reached 88% of its final

value, ensuring that the sum of the two outputs is always

positive. Separate soft-start capacitors for each output

allow the ramp of each output to be independently

controlled.

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APPLICATIO S

■

CCD Bias

■

TFT LCD Bias

■

OLED Bias

■

± Rail Generation for Op Amps

The LT3472 is available in a low profile (0.75mm) 10-pin

3mm × 3mm DFN package.

, LTC and LT are registered trademarks of Linear Technology Corporation.

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TYPICAL APPLICATIO

Li-Ion CCD Bias Supply

V

IN

Conversion Efficiency

3V TO 4.2V

2.2µF

85

1µF

22µH

47µH

80

75

70

65

60

55

50

45

40

POS CHANNEL

NEG CHANNEL

SWP

V

SWN

DN

IN

V

POS

15V

V

POS

20mA

550k

47µH

LT3472

GND

FBP

4.7pF

V

320k

10pF

NEG

–8V

FBN

50mA

SHDN

SSP

SSN

100nF

2.2µF

0

40

50

10

20

30

LOAD CURRENT (mA)

3472 TA01b

3472 TA01a

3472f

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LT3472

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ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

TOP VIEW

ORDER PART

NUMBER

V_IN, SHDN Voltage................................................... 16V

SWP, SWN, V_POSVoltage ....................................... 36V

DN Voltage ............................................................ –36V

FBP, FBN, SSP, SSN Voltage ................................... 10V

Maximum Junction Temperature .......................... 125°C

Operating Temperature Range

SWP

1

2

3

4

5

10

9

V

POS

V

SSP

FBP

SSN

FBN

IN

LT3472EDD

11

SHDN

SWN

DN

8

7

6

DFN PART

MARKING

DD PACKAGE

10-LEAD (3mm × 3mm) PLASTIC DFN

Extended Commercial......................... –40°C to 85°C

Storage Temperature Range ................. –65°C to 125°C

T_JMAX= 125°C, θ_JA= 43°C/W, θ_JC= 3°C/W

EXPOSED PAD IS GND (PIN 11)

MUST BE SOLDERED TO PCB

LBGC

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 3V, SHDN = 3V unless otherwise noted.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Minimum Operation Voltage

Maximum Operation Voltage

Supply Current

2.2

V

16

1

SHDN = 3V, Not Switching

SHDN = 0V

2.8

0.1

mA

µA

SHDN Voltage High

●

0.8

V

SHDN Voltage Low

0.3

SHDN Pin Bias Current

SHDN = 3V

35

1.25

0

µA

Positive Feedback Voltage

Negative Feedback Voltage

Positive Feedback Voltage Line Regulation

Negative Feedback Voltage Line Regulation

FBP Current

●

1.2

–5

1.3

5

V

mV

%/V

mV/V

µA

0.01

0.008

25

FBP = V

FBN = V

●

24.5

1.02

0.9

25.3

1.18

1.4

FBP

FBN Current

25

µA

FBN

FBP to Start Negative Channel

Switching Frequency

1.1

V

1.1

MHz

%

Maximum Duty Cycle (Both Channels)

Positive Channel Switch Current Limit

Negative Channel Switch Current Limit

●

88

92

250

300

350

400

245

400

0.01

700

750

mA

mV

µA

Positive Channel Switch V

I

= 200mA

= 5V

CESAT

SWP

SWN

Negative Channel Switch V

CESAT

Switch Leakage Current (Both Channels)

Schottky DP Forward Drop

V

5

950

1000

4

SW

I

= 150mA

mV

µA

DP

DN

Schottky DN Forward Drop

Schottky Leakage Current (Both Channels)

V = 36V

R

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: The LT3472E is guaranteed to meet specified performance from

0°C to 70°C. Specifications over the –40°C to 85°C operating range are

assured by design, characterization and correlation with statistical process

controls.

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LT3472

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TYPICAL PERFOR A CE CHARACTERISTICS

Minimum FBP Voltage to Enable

Inverter

Quiescent Current

FBP Voltage

3.1

3.0

2.9

2.8

2.7

2.6

2.5

1.13

1.12

1.11

1.10

1.09

1.08

1.07

1.06

1.05

1.30

1.28

1.26

1.24

1.22

1.20

50

0

TEMPERATURE (°C)

50

0

TEMPERATURE (°C)

50

0

TEMPERATURE (°C)

–50

100

–50

100

–50

100

3472 G01

3472 G02

3472 G03

FBN Bias Current

FBN Voltage

FBP Bias Current

10

5

26.0

25.5

25.0

24.5

24.0

26.0

25.5

25.0

24.5

24.0

0

–5

–10

50

0

TEMPERATURE (°C)

50

0

TEMPERATURE (°C)

50

0

TEMPERATURE (°C)

–50

100

–50

100

–50

100

3472 G04

3472 G05

3472 G06

SHDN Pin Bias Current

Positive Channel Switch V_CESAT

350

300

250

200

150

100

50

300

250

200

150

100

50

90°C

25°C

–45°C

0

50

100

150

200

250

300

0

5

10

SHDN VOLTAGE (V)

15

20

SWITCH CURRENT (mA)

3472 G07

3472 G08

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LT3472

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TYPICAL PERFOR A CE CHARACTERISTICS

Negative Channel Schottky

I-V Characteristic

Positive Channel Schottky

I-V Characteristic

Negative Channel Switch V_CESAT

600

500

400

300

200

100

0

400

350

300

250

200

150

100

50

350

300

250

200

150

100

50

25°C

90°C

25°C

90°C

–45°C

0

0.2

0.4

0.8

0

100

150

200

250

0.2

0.4

0.8

1.0

0

1.0

50

0

0.6

SWITCH CURRENT (mA)

SCHOTTKY FORWARD DROP (V)

3472 G10

3472 G09

3472 G11

3472f

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LT3472

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PI FU CTIO S

SWP (Pin 1): Switch Pin for Positive (Boost) Channel.

SSN (Pin 7): Soft Start-Up Pin for Inverter. Connect a cap

here for soft start-up. Leave open for quick start-up. This

pin is connected to 1.25V with a 50k resistor internally.

Connect boost inductor here.

V_IN(Pin 2): Input Supply Pin. Must be locally bypassed

with a X5R or X7R type ceramic capacitor.

FBP (Pin 8): Feedback Pin for Boost. Connect boost

feedback resistor R1 from this Pin to V_O1. Choose R1

accordingto V_O1=1.25•(1+R1/50k).Pinvoltage=1.25V

when regulated.

SHDN(Pin3):ShutdownPin. Connectto0.8Vorhigherto

enable device, 0.3V or less to disable device.

SWN (Pin 4): Switch Pin for Negative (Inverter) Channel.

Connect inverter input inductor and flying capacitor here.

SSP (Pin 9): Soft Start-Up Pin for Boost. Connect a cap

here for soft start-up. Leave open for quick start-up. This

pin is connected to 1.25V with a 50k resistor internally.

DN (Pin 5): Anode of Internal Schottky for Inverter.

Connect inverter output inductor and flying capacitor

here.

V

_POS(Pin10):OutputPinforBoost. Connectboostoutput

capacitor here.

FBN (Pin 6): Feedback Pin for Inverter. Connect feedback

resistor R2 from this pin to V_O2. Choose R2 according to

V_O2= 1.25 • R2/50k. Pin voltage = 0V when regulated.

GND (Exposed Pad) (Pin 11): GND Pin. Tie directly to

ground plane through multiple vias under the package for

optimum thermal performance.

W

BLOCK DIAGRA

SWP

1

COMPARATOR

DP

8

–

+

FBP

10

V

POS

X1

R

DRIVER 1

A1

–

+

50k

Q1

A2

Q

S

–

+

V

2

IN

∑

V

REF

1.25V

RAMP

GENERATOR

11

3

GND

50k

1.2MHz

OSCILLATOR

SHDN

COMPARATOR

6

7

FBN

SSN

+

–

DRIVER 2

X2

R

4

SWN

A3

–

S

Q2

A4

Q

+

–

+

50k

1.25V

50k

∑

DN

RAMP

GENERATOR

5

DN

SSP

9

3472 BD

Figure 1. LT3472 Block Diagram

3472f

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LT3472

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APPLICATIO S I FOR ATIO

Operation

Inductor Selection

The LT3472 uses a constant frequency, current mode

control scheme to provide excellent line and load regula-

tion. Operation can be best understood by referring to the

block diagram in Figure 1. At the start of each oscillator

cycle, the SR latch X1 is set, which turns on the power

switch Q1. A voltage proportional to the switch current is

added to a stabilizing ramp and the resulting sum is fed

into the positive terminal of the PWM comparator A2.

When this voltage exceeds the level at the negative input

of A2, the SR latch X1 is reset turning off the power switch

Q1. The level at the negative input of A2 is set by the error

amplifier A1, and is simply an amplified version of the

difference between the feedback voltage and the reference

voltage of 1.25V. In this manner, the error amplifier sets

the correct peak current level to keep the output in regu-

lation. If the error amplifier’s output increases, more

current is delivered to the output; if it decreases, less

current is delivered. The second channel is an inverting

converter. The basic operation is the same as the positive

channel. The SR latch X2 is also set at the start of each

oscillator cycle. The power switch Q2 is turned on at the

same time as Q1. The turn off of Q2 is determined by its

own feedback loop, which consists of error amplifier A3

and PWM comparator A4. The reference voltage of this

negative channel is ground.

A 22µH inductor is recommended for LT3472 step-up

channel. The inverter channel can use a 22µH or 47µH

inductor. 47µH inductors will provide slightly more cur-

rent. Small size and high efficiency are the major concerns

for most LT3472 applications. Inductors with low core

losses and small DCR (copper wire resistance) at 1.1MHz

are good choices for LT3472 applications. Some induc-

tors in this category with small size are listed in

Table 1. The efficiency comparison of different inductors

is shown in Figure 3.

85

INVERTER LOAD = 20mA

LQH32CN220

80

TOKO 1067FB-220M

75

LQH2MCN220

70

65

60

0

10

15

20

O1

25

30

5

LOAD CURRENT I (mA)

3473 F02a

3472 F02a

85

80

75

70

65

60

BOOST LOAD = 20mA

LQH32CN220

Switching waveforms with typical load conditions are

shown in Figure 2.

TOKO 1067FB-220M

LQH2MCN220

V

SWP

20V/DIV

I

L1

100mA/DIV

V

SWN

20V/DIV

I

SWN

100mA/DIV

0

10

15

20

25

30

5

3472 FO4

LOAD CURRENT I (mA)

V

= 3.6V

500ns/DIV

O2

IN

= 15V, 20mA

POS

NEG

3473 F02a

3472 F02b

= –7.5V, 30mA

Figure 3. Efficiency Comparison of Different Inductors

Figure 2. Switching Waveforms

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LT3472

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APPLICATIO S I FOR ATIO

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Table 1. Recommended Inductors

1A. The selection of inductor and capacitor value should

ensure the peak of the inrush current to be below 1A. The

peak inrush current can be calculated as follows:

Part No.

Inductance DCR

Current

Manufacturer

(µH)

(Ω) Rating (mA)

LQH32CN220

LQH32CN470

LQH2MCN220

LQH2MCN470

22

47

22

47

0.71

1.3

2.1

5.1

250

170

185

120

Murata

(814) 237-1431

www.murata.com

⎡

⎤

V – 0.6

L•ω

α

ω

⎛ ⎞

IN

I_P=

•EXP – •arctan

•

⎜ ⎟

⎢

⎥

⎝ ⎠

α

ω

⎣

⎦

D1067FB-220M

22

2.0

4.0

270

160

350

TOKO

(408) 432-8281

www.tokoam.com

⎡

⎤

ω

⎛ ⎞

SIN arctan•

⎜ ⎟

⎢

⎥

⎝ ⎠

α

⎣

⎦

ELJPC220KF

Panasonic

(714) 373-7334

www.panasonic.com

r + 1.5

2•L

1

L•C

α =

ω =

CDRH3D16-220

0.53

Sumida

(847) 956-0666

www.sumida.com

r

–

2

4 •L

LB2012B220M

LEM2520-220

22

1.7

5.5

75

125

Taiyo Yuden

(408) 573-4150

www.t-yuden.com

where L is the inductance, r is the resistance of the

inductor and C is the output capacitance. For low DCR

inductors, which is usually the case for this application,

the peak inrush current can be simplified as follows:

Capacitor Selection

The small size of ceramic capacitors makes them suitable

for LT3472 applications. X5R and X57 types of ceramic

capacitors are recommended because they retain their

capacitance over wider voltage and temperature ranges

than other types such as Y5V or Z5U. A 2.2µF input

capacitor and a 2.2µF output capacitor are sufficient for

most LT3472 applications.

⎛

⎞

V – 0.6

L • ω

α π

IN

I_P=

•EXP –

•

⎜

⎟

ω 2

⎝

⎠

Table 3 gives inrush peak currents for some component

selections. Note that inrush current is not a concern if the

input voltage rises slowly.

Table 3. Inrush Peak Current

Table 2. Recommended Ceramic Capacitor Manufacturers

V

(V)

r (Ω)

0.5

L (µH)

22

C (µF)

2.2

1

I (A)

IN

P

Manufacturer

Taiyo Yuden

Murata

Phone

URL

5

0.89

0.59

0.46

0.32

0.46

(408) 573-4150

(814) 237-1431

(408) 986-0424

www.t-yuden.com

www.murata.com

www.kemet.com

3.6

0.7

22

2.1

22

Kemet

1.3

47

0.7

22

1

Inrush Current

The LT3472 uses internal Schottky diodes. When supply

voltage is abruptly applied to V_INpin, for the positive

channel, the voltage difference between V_INand V_POS

generates inrush current flowing from input through the

inductor L_Pand the internal Schottky diode D_Pto charge

the output capacitor C_OP. For the inverter channel, there is

a similar inrush current flowing from input through the

inductor L_N1path, charging the capacitor C_NF, and return-

ing through the internal Schottky diode D_N. The maximum

current the Schottky diodes in the LT3472 can sustain is

External Diode Selection

As stated previously the LT3472 has internal Schottky

diodes. The Schottky diode D_Pis sufficient for most step-

up applications. However, for high current inverter appli-

cations, a properly selected external Schottky diode in

parallel with D_Ncan improve efficiency. For external diode

selection, both forward voltage drop and diode capaci-

tance need to be considered. Schottky diodes rated for

higher current usually have lower forward voltage drop

3472f

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LT3472

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APPLICATIO S I FOR ATIO

andlargercapacitance,whichcancausesignificantswitch-

ing losses at 1.1MHz switching frequency. Some recom-

mended Schottky diodes are listed in Table 4.

In order to maintain accuracy, high precision resistors are

preferred (1% is recommended).

Soft-Start

Table 4. Recommended Schottky Diodes

The LT3472 has independent soft-start control for each

channel. As shown in Figure 1, the SSP and SSN pins have

an internal resistor of 50k pulling up to 1.25V, respec-

tively. By connecting a capacitor from the SSP or SSN pin

to ground, the ramp of each output can be programmed

individually. If SSP or SSN is open or pull higher than

1.25V, thecorrespondingoutputwillrampupquickly. The

waveforms with and without soft-start for the Boost

channel are shown in Figure 4.

Forward

Current

(mA)

Forward

Voltage

Drop (V)

Diode

Capacitance

(pF)

Part No.

Manufacturer

CMDSH-3

100 0.58 @100mA 7 @ 10V Central Semiconductor

CMDSH2-3 200 0.49 @ 200mA 15 @ 10V (631) 435-1110

www.centralsemi.com

Setting the Output Voltages

The LT3472 has an accurate feedback resistor of 50k for

each channel. Only one resistor is needed to set the output

voltage for each channel. The output voltage can be set

according to the following formulas:

Thewaveformswithandwithoutsoft-startforthenegative

channel are shown in Figure 5.

Start Sequencing

The LT3472 has internal sequencing circuitry that inhibits

thenegativechannelfromoperatinguntilfeedbackvoltage

of the step-up channel reaches about 1.1V, ensuring that

R1

50k

⎛

⎞

⎟

⎠

V_POS= 1.25• 1+

⎜

⎝

⎛

R2

50k

⎞

⎟

⎠

V_NEG= –1.25•

⎜

⎝

V

SSP

2V/DIV

1V/DIV

V

POS

5V/DIV

I

IN

200mA/DIV

100mA/DIV

3472 FO4a

3472 FO4b

1ms/DIV

100µs/DIV

Figure 4a. V_SSP, V_POS, I_INwith 100nF on SSP

Figure 4b. V_SSP, V_POS, I_INwith SSP Open

V

SSN

2V/DIV

1V/DIV

V

NEG

V

NEG

5V/DIV

I

IN

200mA/DIV

100mA/DIV

3472 FO5a

3472 FO5b

500µs/DIV

100µs/DIV

Figure 5a. V_SSN, V_NEG, I_INwith 100nF on SSN

Figure 5b. V_SSN, V_NEG, I_INwith SSN Open

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LT3472

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APPLICATIO S I FOR ATIO

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the sum of the two outputs is always positive. The se-

quencing is shown in Figure 6.

ence (EMI) problems, proper layout of the high frequency

switchingpathisessential. ThevoltagesignalsoftheSWP

andSWNpinshaveriseandfalltimesofafewns.Minimize

the length and area of all traces connected to the SWP and

SWN pins and always use a ground plane under the

switching regulator to minimize interplane coupling. Rec-

ommended component placement is shown in Figure 7.

Board Layout Consideration

As with all switching regulators, careful attention must be

paid to the PCB board layout and component placement.

Tomaximizeefficiency, switchriseandfalltimesaremade

as short as possible. To prevent electromagnetic interfer-

V

POS

C

OP

5V/DIV

C

L

IN

L

P

C

FBP

R

FBP

C

SSP

V

NEG

5V/DIV

N1

V

SHDN

C

5V/DIV

SSN

3472 FO6

100µs/DIV

R

C

FBN

C

NF

L

N2

Figure 6. Start-Up Sequencing

C

ON

3472 F06

Figure 7. Recommended Component Placement

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LT3472

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TYPICAL APPLICATIO S

V

IN

3V TO 4.2V

C

IN

2.2µF

C

NF

L

P

N1

47µH

1µF

22µH

SWP

V

SWN

DN

V

IN

POS

15V

V

POS

R

FBP

550k

20mA

L

N2

LT3472

GND

FBP

47µH

R

C

, 4.7pF

FBP

FBN

V

320k

NEG

–8V

FBN

50mA

C

FBN

10pF

SHDN

SSP

SSN

C

OP

2.2µF

SSP

100nF

SSN

100nF

ON

2.2µF

3472 TA02

C

: TAIYO YUDEN JMK107BJ225

IN

: TAIYO YUDEN EMK316BJ225

OP

NF

ON

: TAIYO YUDEN EMK212BJ105

: TAIYO YUDEN LMK212BJ225

L : MURATA LQH32CN220

P

L

, L : MURATA LQH32CN470

N1 N2

V_POSLoad Step Response

V_NEGLoad Step Response

15mA

25mA

I

POS

–20mA

–30mA

I

NEG

V

POS

NEG

20mV/DIV

10mV/DIV

3472 TA04

3472 TA05

20µs/DIV

50µs/DIV

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LT3472

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PACKAGE DESCRIPTIO

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699)

R = 0.115

TYP

6

0.38 ± 0.10

10

0.675 ±0.05

3.50 ±0.05

2.15 ±0.05 (2 SIDES)

1.65 ±0.05

3.00 ±0.10

(4 SIDES)

1.65 ± 0.10

(2 SIDES)

PIN 1

TOP MARK

(SEE NOTE 6)

PACKAGE

OUTLINE

(DD10) DFN 1103

5

1

0.25 ± 0.05

0.50 BSC

0.75 ±0.05

0.200 REF

0.25 ± 0.05

0.50

BSC

2.38 ±0.10

(2 SIDES)

2.38 ±0.05

(2 SIDES)

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).

CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

3472f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

11

LT3472

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TYPICAL APPLICATIO

V

IN

3V TO 4.2V

2.2µF

1µF

22µH

47µH

SWP

V

SWN

DN

IN

V

POS

15V

20mA

V

POS

550k

47µH

LT3472

GND

FBP

4.7pF

V

320k

10pF

NEG

–8V

FBN

50mA

SHDN

SSP

SSN

100nF

2.2µF

3472 TA03

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LT1611

550mA (I ), 1.4MHz, High Efficiency Micropower

Inverting DC/DC Converter

V : 1.1V to 10V, V

ThinSOT Package

= –34V, I = 3mA, I <1µA,

OUT(MAX) Q SD

SW

IN

LT1615/LT1615-1

LT1617/LT1617-1

LT1930/LT1930A

LT1931/LT1931A

LT1944/LT1944-1

LT1945(Dual)

300mA/80mA (I ), High Efficiency

Step-Up DC/DC Converter

V : 1V to 15V, V

ThinSOT Package

= 34V, I = 20µA, I <1µA,

SW

IN

OUT(MAX) Q SD

350mA/100mA (I ), High Efficiency Micropower

V : 1.2V to 15V, V

= –34V, I = 20µA, I <1µA,

Q SD

SW

IN

OUT(MAX)

Inverting DC/DC Converter

ThinSOT Package

1A (I ), 1.2MHz/2.2MHz, High Efficiency

V : 2.6V to 16V, V

= 34V, I = 4.2mA/5.5mA, I <1µA,

Q SD

SW

IN

Step-Up DC/DC Converter

ThinSOT Package

1A (I ), 1.2MHz/2.2MHz, High Efficiency Micropower

V : 2.6V to 16V, V

= –34V, I = 5.8mA, I <1µA,

Q SD

SW

IN

Inverting DC/DC Converter

ThinSOT Package

Dual Output, 350mA/100mA (I ), Constant

V : 1.2V to 15V, V

= 34V, I = 20µA, I <1µA,

Q SD

SW

IN

Off-Time, High Efficiency Step-Up DC/DC Converter

MS10 Package

Dual Output, Boost/Inverter, 350mA (I ), Constant

Off-Time, High Efficiency Step-Up DC/DC Converter

V : 1.2V to 15V, V

= ±34V, I = 40µA, I <1µA,

Q SD

SW

IN

MS10 Package

LT1946/LT1946A

LT3461/LT3461A

LT3462/LT3462A

LT3463/LT3463A

1.5A (I ), 1.2MHz/2.7MHz, High Efficiency

Step-Up DC/DC Converter

V : 2.45V to 16V, V

MS8 Package

= 34V, I = 3.2mA, I <1µA,

SW

IN

OUT(MAX) Q SD

0.3A (I ), Inverting 1.3MHz/3MHz High Efficiency

V : 2.5V to 16V, V

ThinSOT Package

= 38V, I = 2.8mA, I <1µA,

Q SD

SW

IN

OUT(MAX)

Step-Up DC/DC Converter with Integrated Schottky Diodes

300mA (I ), Inverting 1.2MHz/2.7MHz DC/DC Converter

V : 2.5V to 16V, V

= –38V, I = 2.9mA, I <10µA,

Q SD

SW

IN

with Integrated Schottky Diodes

ThinSOT Package

Dual Output, Boost/Inverter, 250mA (I ), Constant

V : 2.3V to 15V, V

IN

= 40V, I = 40µA, I <1µA,

Q SD

SW

Off-Time, High Efficiency Step-Up DC/DC Converter

with Integrated Schottkys

DFN Package

LT3464

85mA (I ), High Efficiency Step-Up DC/DC Converter

with Integrated Schottky and PNP Disconnect

V : 2.3V to 10V, V

ThinSOT Package

= 34V, I = 25µA, I <1µA,

Q SD

SW

IN

OUT(MAX)

LT3467/LT3467A

1.1A, 1.3MHz/2.1MHz Step-Up DC/DC Converter with

Integrated Soft-Start in ThinSOT

V : 2.4V to 16V, V

ThinSOT Package

= 40V, I = 1mA, I <1µA,

Q SD

IN

OUT(MAX)

3472f

LT/TP 0804 1K • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

12

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LT3472EDD#PBF
厂家：	Linear
描述：	LT3472 - Boost and Inverting DC/DC Converter for CCD Bias; Package: DFN; Pins: 10; Temperature Range: -40°C to 85°C 转换器 CD
文件：	总12页 (文件大小：223K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LT3472EDD#PBF [Linear]

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