LT3751IUFD#TRPBF [Linear]
LT3751 - High Voltage Capacitor Charger Controller with Regulation; Package: QFN; Pins: 20; Temperature Range: -40°C to 85°C;
| 型号： | LT3751IUFD#TRPBF |
| 厂家： | 
Linear |
| 描述： | LT3751 - High Voltage Capacitor Charger Controller with Regulation; Package: QFN; Pins: 20; Temperature Range: -40°C to 85°C |
| 文件： | 总34页 (文件大小：629K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3751
High Voltage Capacitor
Charger Controller with Regulation
FEATURES
DESCRIPTION
The LT®3751 is a high input voltage capable flyback con-
n
Charges Any Size Capacitor
n
Low Noise Output in Voltage Regulation Mode
Stable Operation Under a No-Load Condition
Integrated 2A MOSFET Gate Driver with Rail-to-Rail
troller designed to rapidly charge a large capacitor to a
user-adjustable high target voltage set by the transformer
turns ratio and three external resistors. Optionally, a feed-
back pin can be used to provide a low noise high voltage
regulated output.
n
n
Operation for V ≤ 8V
CC
n
Selectable 5.6V or 10.5V Internal Gate Drive
Voltage Clamp
The LT3751 has an integrated rail-to-rail MOSFET gate
driver that allows for efficient operation down to 4.75V.
A low 106mV differential current sense threshold volt-
age accurately limits the peak switch current. Added pro-
tection is provided via user-selectable overvoltage and
undervoltage lockouts for both V and V
application can charge a 1000µF capacitor to 500V in less
than one second.
n
n
n
n
n
User-Selectable Over/Undervoltage Detect
Easily Adjustable Output Voltage
Primary or Secondary Side Output Voltage Sense
Wide Input V Voltage Range (5V to 24V)
CC
Available in 20-Pin QFN 4mm × 5mm and 20-Lead
. A typical
TRANS
CC
TSSOP Packages
APPLICATIONS
The CHARGE pin is used to initiate a new charge cycle
and provides ON/OFF control. The DONE pin indicates
when the capacitor has reached its programmed value and
the part has stopped charging. The FAULT pin indicates
when the LT3751 has shut down due to either VCC or
n
High Voltage Regulated Supply
n
High Voltage Capacitor Charger
n
Professional Photoflash Systems
n
Emergency Strobe
V
voltage exceeding the user-programmed supply
n
TRANS
tolerances.
Security/Inventory Control Systems
n
Detonators
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents including 6518733 and 6636021.
TYPICAL APPLICATION
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
Load Regulation and Efficiency
T1
D1
1:10
V
500V
TRANS
24V
5ꢍꢍ
ꢕꢖꢗ
ꢕꢖꢘ
ꢕꢖꢕ
ꢕꢖꢙ
ꢕꢖꢍ
ꢖꢍ
ꢗꢕ
7ꢗ
7ꢙ
ꢘꢘ
ꢘꢍ
0 TO 150mA
+
10µF
×2
330µF
•
40.2k
TRANS
×2
+
100µF
•
RV
CHARGE
CLAMP
18.2k
0.47µF
OFF ON
RDCM
40.2k
RV
OUT
V
CC
24V
V
CC
LT3751
10µF
HVGATE
LVGATE
CSP
TO
DONE
FAULT
V
CC
MICRO
374k
475k
374k
475k
UVLO1
OVLO1
UVLO2
6mΩ
V
TRANS
CSN
FB
715k
ꢁꢅꢉꢎꢅꢉ ꢏꢁꢀꢉꢂꢐꢇ
ꢇꢑꢑꢒꢄꢒꢇꢈꢄꢓ
V
CC
OVLO2
GND
1.74k
10nF
RBG
ꢍ
5ꢍ
1ꢍꢍ
15ꢍ
732Ω
ꢀꢁꢂꢃ ꢄꢅꢆꢆꢇꢈꢉ ꢊꢋꢂꢌ
3751 ꢉꢂꢍ1ꢚ
3751 TA01a
3751fd
1
For more information www.linear.com/LT3751
LT3751
(Note 1)
ABSOLUTE MAXIMUM RATINGS
Current into RV
Pin ........................................ 10mA
V , CHARGE, CLAMP..............................................24V
OUT
CC
Current into RDCM Pin......................................... 10mA
Current into UVLO1 Pin.......................................... 1mA
Current into UVLO2 Pin.......................................... 1mA
Current into OVLO1 Pin.......................................... 1mA
Current into OVLO2 Pin.......................................... 1mA
Maximum Junction Temperature .......................... 125°C
Operating Temperature Range (Note 2).. –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
DONE, FAULT ............................................................24V
LVGATE (Note 8).......................................................24V
V
CC
– LVGATE .............................................................8V
HVGATE ................................................................Note 9
RBG, CSP, CSN ...........................................................2V
FB ..............................................................................5V
Current into DONE Pin ........................................... 1mA
Current into FAULT Pin........................................... 1mA
Current into RV
Pin....................................... 1mA
TRANS
PIN CONFIGURATION
ꢄꢅꢆ ꢇꢈꢉꢊ
ꢍꢏꢂ ꢔꢎꢁꢕ
ꢖꢔ
ꢍꢖꢃꢗꢌ
1
ꢇ
3
ꢐ
5
ꢑ
7
ꢒ
ꢓ
ꢇꢈ ꢖꢋꢄꢚ
1ꢓ ꢗꢄ
ꢘꢔꢊꢏ1
ꢏꢔꢊꢏ1
ꢘꢔꢊꢏꢇ
ꢏꢔꢊꢏꢇ
FAULT
ꢀꢁ 1ꢂ 1ꢃ 17
1ꢒ ꢖꢔ
17 ꢗꢄ
ꢏꢘꢍ
ꢅꢇꢘꢅ1
ꢋꢇꢘꢅꢀ
ꢅꢇꢘꢅꢀ
FAULT
1
ꢀ
3
ꢕ
5
ꢛ
1ꢛ ꢝꢇ
15 ꢓꢏ
ꢅꢋꢄ
1ꢑ ꢖꢛꢆ
1ꢕ ꢝꢞꢑ
ꢇ1
ꢀ1
15 ꢙꢔꢆꢃꢍꢁ
1ꢐ ꢊꢔꢆꢃꢍꢁ
13 ꢜꢇꢑꢎꢄꢉ
1ꢀ ꢘꢇꢑꢎꢄꢉ
DONE
DONE
ꢏꢜꢎꢝꢑꢉ
11 ꢇ
ꢏꢏ
ꢄꢙꢃꢖꢆꢁ
ꢄꢊꢃꢚꢂ
13
ꢔ
ꢄꢄ
1ꢇ ꢄꢌꢂ
11 ꢄꢌꢗ
7
ꢃ
ꢂ 1ꢁ
ꢀꢛ 1ꢈ
ꢀꢁ ꢂꢃꢄꢅꢃꢆꢁ
ꢇꢈꢉꢊꢁꢃꢋ ꢂꢊꢃꢌꢍꢎꢄ ꢍꢌꢌꢏꢂ
ꢋꢌꢍ ꢆꢎꢏꢐꢎꢑꢉ
ꢀꢁꢒꢆꢈꢓ ꢔꢕꢖꢖ × 5ꢖꢖꢗ ꢆꢘꢎꢙꢄꢈꢏ ꢚꢌꢓ
T
= 125°C, θ = 38°C/W
JA
JMAX
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
T
= 125°C, θ = 43°C/W
JA
JMAX
EXPOSED PAD (PIN 21) IS GND, MUST BE TIED TO PCB
http://www.linear.com/product/LT3751#orderinfo
ORDER INFORMATION
LEAD FREE FINISH
LT3751EFE#PBF
LT3751IFE#PBF
LT3751EUFD#PBF
LT3751IUFD#PBF
LEAD BASED FINISH
LT3751EFE
TAPE AND REEL
LT3751EFE#TRPBF
LT3751IFE#TRPBF
LT3751EUFD#TRPBF
LT3751IUFD#TRPBF
TAPE AND REEL
LT3751EFE#TR
PART MARKING*
LT3751FE
LT3751FE
3751
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
TEMPERATURE RANGE
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
20-Lead Plastic TSSOP
20-Lead Plastic TSSOP
20-Pin (4mm × 5mm) Plastic QFN
20-Pin (4mm × 5mm) Plastic QFN
PACKAGE DESCRIPTION
3751
PART MARKING*
LT3751FE
LT3751FE
3751
20-Lead Plastic TSSOP
LT3751IFE
LT3751IFE#TR
20-Lead Plastic TSSOP
LT3751EUFD
LT3751EUFD#TR
LT3751IUFD#TR
20-Pin (4mm × 5mm) Plastic QFN
20-Pin (4mm × 5mm) Plastic QFN
LT3751IUFD
3751
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
3751fd
2
For more information www.linear.com/LT3751
LT3751
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = CHARGE = 5V, CLAMP = 0V, unless otherwise noted. Individual
25kΩ resistors tied from 5V VTRANS supply to RVTRANS, RVOUT, RDCM, unless otherwise noted. (Note 2)
PARAMETER
Voltage
CONDITIONS
MIN
4.75
4.75
TYP
MAX
24
UNITS
l
l
V
V
V
CC
RV
Voltage
(Note 3)
65
TRANS
V
Quiescent Current
Not Switching, CHARGE = 5V
Not Switching, CHARGE = 0.3V
5.5
0
8
1
mA
µA
CC
RV
RV
, R
Quiescent Current
(Note 4)
TRANS DCM
Not Switching, CHARGE = 5V
Not Switching, CHARGE = 0.3V
l
l
35
42
40
0
45
1
µA
µA
Quiescent Current
(Note 4)
Not Switching, CHARGE = 5V
Not Switching, CHARGE = 0.3V
OUT
47
0
52
1
µA
µA
UVLO1, UVLO2, OVLO1, OVLO2 Clamp Voltage Measured at 1mA into Pin, CHARGE = 0V
55
60
V
V
RV
, RV , R
Clamp Voltage
Measured at 1mA into Pin, CHARGE = 0V
TRANS
OUT DCM
CHARGE Pin Current
CHARGE = 24V
CHARGE = 5V
CHARGE = 0V
425
60
µA
µA
µA
1
l
l
CHARGE Minimum Enable Voltage
CHARGE Maximum Disable Voltage
Minimum CHARGE Pin Low Time
One-Shot Clock Period
1.5
V
V
I
≤ 1µA
0.3
VCC
20
38
μs
μs
V
l
l
32
44
1.005
40
V
V
Comparator Trip Voltage
Comparator Overdrive
Measured at RBG Pin
2µs Pulse Width,
RV
R
0.955
0.98
20
OUT
OUT
mV
, RV
TRANS
= 25kΩ
OUT
= 0.83kΩ
BG
DCM Comparator Trip Voltage
Measured as V
(Note 5)
– V
, R
= 25kΩ, V = 4.75V
350
600
900
mV
DRAIN
TRANS DCM
CC
Current Limit Comparator Trip Voltage
FB Pin = 0V
FB Pin = 1.3V
l
l
100
7
106
11
112
15
mV
mV
FB Pin Bias Current
Current Sourced from FB Pin, Measured at FB Pin Voltage
(Note 6)
64
1.22
1.16
55
1.34
60
5
300
1.25
1.2
nA
V
l
FB Pin Voltage
1.19
1.12
FB Pin Charge Mode Threshold
FB Pin Charge Mode Hysteresis
FB Pin Overvoltage Mode Threshold
FB Pin Overvoltage Hysteresis
DONE Output Signal High
DONE Output Signal Low
DONE Leakage Current
FAULT Output Signal High
FAULT Output Signal Low
FAULT Leakage Current
UVLO1 Pin Current
V
(Note 7)
mV
V
1.29
1.38
mV
V
100kΩ to 5V
100kΩ to 5V
40
5
200
200
mV
nA
V
DONE = 5V
100kΩ to 5V
5
100kΩ to 5V
40
5
200
200
mV
nA
μA
μA
μA
μA
FAULT = 5V
l
l
l
l
UVLO1 Pin Voltage = 1.24V
UVLO2 Pin Voltage = 1.24V
OVLO1 Pin Voltage = 1.24V
OVLO2 Pin Voltage = 1.24V
48.5
48.5
48.5
48.5
50
50
50
50
51.5
51.5
51.5
51.5
UVLO2 Pin Current
OVLO1 Pin Current
OVLO2 Pin Current
3751fd
3
For more information www.linear.com/LT3751
LT3751
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = CHARGE = 5V, CLAMP = 0V, unless otherwise noted. Individual
25kΩ resistors tied from 5V VTRANS supply to RVTRANS, RVOUT, RDCM, unless otherwise noted. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
1.225
1.225
1.225
1.225
0.7
MAX
1.255
1.255
1.255
1.255
UNITS
l
l
l
l
UVLO1 Threshold
UVLO2 Threshold
OVLO1 Threshold
OVLO2 Threshold
Gate Minimum High Time
Gate Peak Pull-Up Current
Measured from Pin to GND
Measured from Pin to GND
Measured from Pin to GND
Measured from Pin to GND
1.195
1.195
1.195
1.195
V
V
V
V
μs
V
V
= 5V, LVGATE Active
= 12V, LVGATE Inactive
2.0
1.5
A
A
CC
CC
Gate Peak Pull-Down Current
Gate Rise Time
V
V
= 5V, LVGATE Active
1.2
1.5
A
A
CC
CC
= 12V, LVGATE Inactive
10% → 90%, C
V
V
= 3.3nF (Note 8)
GATE
= 5V, LVGATE Active
40
55
ns
ns
CC
CC
= 12V, LVGATE Inactive
Gate Fall Time
90% → 10%, C
= 3.3nF (Note 8)
GATE
V
V
= 5V, LVGATE Active
30
30
ns
ns
CC
CC
= 12V, LVGATE Inactive
Gate High Voltage
(Note 8):
V
V
V
V
= 5V, LVGATE Active
4.98
10
5
5
V
V
V
V
CC
CC
CC
CC
= 12V, LVGATE Inactive
= 12V, LVGATE Inactive, CLAMP Pin = 5V
= 24V, LVGATE Inactive
10.5
5.6
11.5
6.5
11.5
10
10.5
Gate Turn-Off Propagation Delay
C
= 3.3nF
180
ns
GATE
25mV Overdrive Applied to CSP Pin
Gate Voltage Overshoot
CLAMP Pin Threshold
500
1.6
mV
V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3751E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design
characterization and correlation with statistical process controls. The
LT3751I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 5: Refer to Block Diagram for V
and V
definitions.
TRANS
DRAIN
Note 6: Low noise regulation of the output voltage requires a resistive
voltage divider from output voltage to FB pin. FB pin should not be
grounded in this configuration. Refer to the Typical Application diagram for
proper FB pin configuration.
Note 7: The feedback pin has built-in hysteresis that defines the boundary
between charge-only mode and low noise regulation mode.
Note 8: LVGATE should be used in parallel with HVGATE when V is less
than or equal to 8V (LVGATE active). When not in use, LVGATE should be
CC
tied to V (LVGATE inactive).
CC
Note 3: A 60V internal clamp is connected to RV
, RDCM, RV
,
TRANS
OUT
Note 9: Do not apply a positive or negative voltage or current source to
HVGATE, otherwise permanent damage may occur.
UVLO1, UVLO2, OVLO1 and OVLO2. Resistors should be used such that
the pin currents do not exceed the Absolute Maximum Ratings.
Note 4: Currents will increase as pin voltages are taken higher than the
internal clamp voltage.
3751fd
4
For more information www.linear.com/LT3751
LT3751
TYPICAL PERFORMANCE CHARACTERISTICS
VCC Pin Current
VTRANS Supply Current
CHARGE Pin Current
7
ꢑ
5
ꢒ
3
ꢓ
1
ꢌ
15ꢌ
1ꢒ5
1ꢒꢌ
135
13ꢌ
1ꢓ5
1ꢓꢌ
115
11ꢌ
ꢑ5ꢌ
ꢑꢌꢌ
35ꢌ
3ꢌꢌ
ꢒ5ꢌ
ꢒꢌꢌ
15ꢌ
1ꢌꢌ
5ꢌ
ꢍꢃ
ꢃ
ꢗ ꢍꢃ ꢗ ꢍ
ꢚ ꢓ5ꢛ
ꢆꢍꢇꢂꢎ
ꢏꢏ
ꢄꢐꢆ ꢘꢏꢙ
ꢗ ꢏꢜꢇꢍꢈꢉ ꢚ 5ꢃ
ꢁ
ꢚ ꢁ
ꢝ ꢁ
ꢝ ꢁ
ꢃꢆꢍꢇꢂꢎ ꢍꢃꢆꢍꢇꢂꢎ ꢍꢃꢄꢐꢆ ꢍꢘꢏꢙ
ꢕꢒꢌꢖꢏ
ꢓ5ꢖꢏ
ꢕꢑꢌꢖꢍ
ꢒ5ꢖꢍ
1ꢒ5ꢖꢍ
ꢕꢒꢌꢖꢍ
ꢓ5ꢖꢍ
1ꢓ5ꢖꢏ
1ꢓ5ꢖꢍ
ꢌ
ꢌ
ꢒ
ꢔ
1ꢓ
1ꢑ
ꢓꢌ
ꢓꢒ
ꢌ
1ꢌ
ꢓꢌ
3ꢌ
ꢒꢌ
5ꢌ
ꢔꢌ
ꢌ
ꢑ
ꢔ
1ꢒ
1ꢓ
ꢒꢌ
ꢒꢑ
ꢀꢁꢂ ꢃꢄꢅꢆꢇꢈꢉ ꢊꢃꢋ
ꢀꢁꢂ ꢃꢄꢅꢆꢇꢈꢉ ꢊꢃꢋ
ꢀꢁꢂ ꢃꢄꢅꢆꢇꢈꢉ ꢊꢃꢋ
3751 ꢈꢌ1
3751 ꢈꢌꢓ
3751 ꢈꢌ3
CHARGE Pin Minimum
Enable Voltage
CHARGE Pin Maximum
Disable Voltage
DONE, FAULT Pin Voltage Low
1ꢒ3
1ꢒꢓ
1ꢒ1
1ꢒꢂ
ꢂꢒꢕ
ꢂꢒꢔ
ꢂꢒ7
ꢂꢒꢖ
1ꢒꢓ
1ꢒ1
1ꢒꢂ
ꢂꢒꢔ
ꢂꢒꢖ
ꢂꢒ7
ꢂꢒꢕ
ꢂꢒ5
ꢁꢂꢂ
35ꢂ
3ꢂꢂ
ꢑ5ꢂ
ꢑꢂꢂ
15ꢂ
1ꢂꢂ
5ꢂ
ꢌ
ꢃꢃ
ꢌ
ꢃꢃ
ꢌ
ꢃꢃ
ꢚ 5ꢌ
ꢚ 1ꢓꢌ
ꢚ ꢓꢁꢌ
1ꢏꢋ ꢙꢄꢅꢚ
1ꢂꢂꢛꢋ ꢙꢄꢅꢚ
1ꢂꢛꢋ ꢙꢄꢅꢚ
ꢌ
ꢃꢃ
ꢌ
ꢃꢃ
ꢌ
ꢃꢃ
ꢚ 5ꢌ
ꢚ 1ꢓꢌ
ꢚ ꢓꢁꢌ
ꢂ
ꢀꢁꢂ ꢀꢓꢂ
ꢂ
ꢓꢂ ꢁꢂ ꢖꢂ ꢔꢂ 1ꢂꢂ 1ꢓꢂ
ꢀꢁꢂ ꢀꢓꢂ
ꢂ
ꢓꢂ ꢁꢂ ꢕꢂ ꢖꢂ 1ꢂꢂ 1ꢓꢂ
ꢀꢁꢂ ꢀꢑꢂ
ꢂ
ꢑꢂ ꢁꢂ ꢒꢂ ꢓꢂ 1ꢂꢂ 1ꢑꢂ
ꢏꢈꢗꢉꢈꢆꢅꢏꢘꢆꢈ ꢐꢙꢃꢑ
ꢏꢈꢗꢉꢈꢆꢅꢏꢘꢆꢈ ꢐꢙꢃꢑ
ꢊꢍꢔꢃꢍꢕꢋꢊꢖꢕꢍ ꢎꢗꢘꢐ
3751 ꢇꢂꢁ
3751 ꢇꢂ5
3751 ꢌꢂꢒ
VOUT Comparator Trip Voltage
UVLO1 Trip Voltage
UVLO1 Trip Current
30.8
30.4
30.0
29.6
29.2
28.8
28.4
1ꢐꢑ3ꢒ
1ꢐꢑ3ꢁ
1ꢐꢑ3ꢑ
1ꢐꢑ3ꢂ
1ꢐꢑꢑꢓ
1ꢐꢑꢑꢒ
1ꢐꢑꢑꢁ
5ꢂꢒ5
5ꢂꢒꢁ
5ꢂꢒ3
5ꢂꢒꢔ
5ꢂꢒ1
5ꢂꢒꢂ
ꢁꢓꢒꢓ
ꢁꢓꢒꢕ
ꢁꢓꢒ7
RV
BG
, RV
= 25.5k (R
= 1%)
TRANS
OUT
TOL
R
= 833Ω
ꢄ
ꢊꢊ
ꢄ
ꢊꢊ
ꢄ
ꢊꢊ
ꢚ 5ꢄ
ꢚ 1ꢔꢄ
ꢚ ꢔꢁꢄ
ꢄ
ꢗꢗ
ꢄ
ꢗꢗ
ꢄ
ꢗꢗ
ꢘ 5ꢄ
ꢘ 1ꢑꢄ
ꢘ ꢑꢁꢄ
V
= 5V
= 12V
= 24V
TRANS
V
V
V
= 48V
= 72V
TRANS
TRANS
TRANS
TRANS
V
–40 –20
0
20 40 60 80 100 120
TEMPERATURE (°C)
ꢀꢁꢂ ꢀꢑꢂ
ꢂ
ꢑꢂ ꢁꢂ ꢒꢂ ꢓꢂ 1ꢂꢂ 1ꢑꢂ
ꢀꢁꢂ ꢀꢔꢂ
ꢂ
ꢔꢂ ꢁꢂ ꢖꢂ ꢕꢂ 1ꢂꢂ 1ꢔꢂ
ꢊꢍꢔꢇꢍꢕꢋꢊꢃꢕꢍ ꢎꢖꢗꢏ
ꢍꢌꢘꢇꢌꢋꢐꢍꢃꢋꢌ ꢎꢙꢊꢑ
3751 G07
3751 ꢌꢂꢓ
3751 ꢗꢂꢓ
3751fd
5
For more information www.linear.com/LT3751
LT3751
TYPICAL PERFORMANCE CHARACTERISTICS
Current Comparator Trip Voltage
(Charge Mode)
Current Comparator Minimum
Trip Voltage (Regulation Mode)
FB Pin Voltage
1ꢑꢒꢒ3
1ꢑꢒꢒꢒ
1ꢑꢒꢒ1
1ꢑꢒꢒꢂ
1ꢑꢒ1ꢓ
1ꢂꢎꢏꢂ
1ꢂꢐꢏ5
1ꢂꢐꢏꢂ
1ꢂ7ꢏ5
1ꢂ7ꢏꢂ
13ꢎꢂ
1ꢏꢎꢑ
1ꢏꢎꢐ
1ꢏꢎꢁ
1ꢏꢎꢏ
1ꢏꢎꢂ
11ꢎꢑ
11ꢎꢐ
11ꢎꢁ
11ꢎꢏ
11ꢎꢂ
ꢃ
ꢄꢅ
ꢙ ꢃ
ꢀ ꢃ
ꢃ
ꢘ ꢃ
ꢀ ꢃ
ꢗꢙꢓ ꢗꢙꢚ
ꢘꢚꢔ
ꢘꢚꢛ
ꢄꢅ
ꢛꢜ ꢘ 1ꢎ3ꢃ
ꢈ
ꢚꢚ
ꢈ
ꢚꢚ
ꢈ
ꢚꢚ
ꢛ 5ꢈ
ꢛ 1ꢒꢈ
ꢛ ꢒꢁꢈ
ꢃ
ꢘꢘ
ꢃ
ꢘꢘ
ꢃ
ꢘꢘ
ꢙ 5ꢃ
ꢙ 1ꢒꢃ
ꢙ ꢒꢁꢃ
ꢃ
ꢗꢗ
ꢃ
ꢗꢗ
ꢃ
ꢗꢗ
ꢘ 5ꢃ
ꢘ 1ꢏꢃ
ꢘ ꢏꢁꢃ
ꢀꢁꢂ ꢀꢒꢂ
ꢂ
ꢒꢂ ꢁꢂ ꢔꢂ ꢕꢂ 1ꢂꢂ 1ꢒꢂ
ꢀꢁꢂ ꢀꢒꢂ
ꢂ
ꢒꢂ ꢁꢂ ꢑꢂ ꢐꢂ 1ꢂꢂ 1ꢒꢂ
ꢀꢁꢂ ꢀꢏꢂ
ꢂ
ꢏꢂ ꢁꢂ ꢐꢂ ꢑꢂ 1ꢂꢂ 1ꢏꢂ
ꢄꢊꢒꢓꢊꢔꢈꢄꢕꢔꢊ ꢋꢖꢗꢍ
ꢋꢎꢖꢅꢎꢗꢌꢋꢘꢗꢎ ꢏꢙꢚꢐ
ꢄꢊꢓꢔꢊꢕꢈꢄꢖꢕꢊ ꢋꢗꢘꢍ
3751 ꢍ1ꢒ
3751 ꢉ1ꢂ
3751 ꢉ11
FB Pin Regulation
Mode Threshold
FB Pin Regulation
Mode Hysteresis
FB Pin Bias Current
ꢎꢂ
5ꢏ
5ꢎ
5ꢁ
5ꢐ
5ꢂ
1ꢂꢂ
ꢒꢂ
ꢓꢂ
7ꢂ
ꢔꢂ
5ꢂ
ꢁꢂ
1ꢑ1ꢒꢓ
1ꢑ1ꢒꢁ
1ꢑ1ꢒꢂ
1ꢑ15ꢒ
1ꢑ15ꢔ
ꢌ
ꢗꢗ
ꢌ
ꢗꢗ
ꢌ
ꢗꢗ
ꢘ 5ꢌ
ꢘ 1ꢐꢌ
ꢘ ꢐꢁꢌ
ꢗꢈꢐꢃꢅꢆꢈꢉ ꢐꢍ ꢙꢚ ꢊꢋꢌ ꢛꢄꢜꢍꢐꢕꢈ
ꢛ
ꢇꢇ
ꢝ 1ꢖꢛ
ꢈ
ꢙꢙ
ꢈ
ꢙꢙ
ꢈ
ꢙꢙ
ꢚ 5ꢈ
ꢚ 1ꢔꢈ
ꢚ ꢔꢁꢈ
ꢀꢁꢂ ꢀꢐꢂ
ꢂ
ꢐꢂ ꢁꢂ ꢎꢂ ꢏꢂ 1ꢂꢂ 1ꢐꢂ
ꢀꢁꢂ ꢀꢖꢂ
ꢂ
ꢖꢂ ꢁꢂ ꢔꢂ ꢓꢂ 1ꢂꢂ 1ꢖꢂ
ꢀꢁꢂ ꢀꢔꢂ
ꢂ
ꢔꢂ ꢁꢂ ꢒꢂ ꢓꢂ 1ꢂꢂ 1ꢔꢂ
ꢆꢇꢒꢓꢇꢈꢔꢆꢕꢈꢇ ꢊꢖꢗꢍ
ꢍꢈꢗꢊꢈꢆꢐꢍꢅꢆꢈ ꢎꢘꢇꢑ
ꢋꢎꢕꢅꢎꢖꢌꢋꢗꢖꢎ ꢏꢘꢙꢐ
3751 ꢑ15
3751 ꢕ13
3751 ꢍ1ꢁ
FB Pin Overvoltage Mode
Threshold Voltage
FB Pin Overvoltage
Mode Hysteresis
CLAMP Pin Threshold
1ꢑ35ꢒ
1ꢑ35ꢁ
1ꢑ35ꢓ
1ꢑ35ꢂ
1ꢑ3ꢁꢔ
1ꢑ3ꢁꢒ
1ꢑ3ꢁꢁ
1ꢑꢒ
1ꢑꢓ
1ꢑ7
1ꢑꢔ
1ꢑ5
1ꢑꢁ
ꢎ1ꢏꢂ
ꢎꢂꢏꢎ
ꢎꢂꢏꢐ
5ꢑꢏꢒ
5ꢑꢏꢁ
5ꢑꢏꢂ
ꢈ
ꢙꢙ
ꢈ
ꢙꢙ
ꢈ
ꢙꢙ
ꢚ 5ꢈ
ꢚ 1ꢓꢈ
ꢚ ꢓꢁꢈ
ꢊ
ꢃꢃ
ꢊ
ꢃꢃ
ꢙ 1ꢕꢊ
ꢙ ꢕꢁꢊ
ꢌ
ꢙꢙ
ꢌ
ꢙꢙ
ꢌ
ꢙꢙ
ꢚ 5ꢌ
ꢚ 1ꢐꢌ
ꢚ ꢐꢁꢌ
ꢀꢁꢂ ꢀꢓꢂ
ꢂ
ꢓꢂ ꢁꢂ ꢒꢂ ꢔꢂ 1ꢂꢂ 1ꢓꢂ
ꢀꢁꢂ
1ꢕꢂ
ꢂ
ꢁꢂ
ꢓꢂ
ꢀꢁꢂ ꢀꢐꢂ
ꢂ
ꢐꢂ ꢁꢂ ꢎꢂ ꢒꢂ 1ꢂꢂ 1ꢐꢂ
ꢋꢎꢕꢅꢎꢖꢌꢋꢗꢖꢎ ꢏꢘꢙꢐ
ꢌꢎꢆꢇꢎꢖꢅꢌꢗꢖꢎ ꢏꢘꢃꢐ
ꢆꢇꢔꢕꢇꢈꢖꢆꢗꢈꢇ ꢊꢘꢙꢍ
3751 ꢍ1ꢒ
3751 ꢍ1ꢓ
3751 ꢓ17
3751fd
6
For more information www.linear.com/LT3751
LT3751
TYPICAL PERFORMANCE CHARACTERISTICS
DCM Trip Voltage (VDRAIN – VTRANS),
RVTRANS = RDCM = 25kΩ
HVGATE Pin Clamp Voltage
HVGATE Pin Clamp Voltage
11ꢐꢂ
1ꢂꢐꢑ
1ꢂꢐꢒ
1ꢂꢐ7
1ꢂꢐꢓ
1ꢂꢐ5
1ꢂꢐꢁ
5ꢐ7ꢂ
5ꢐꢑ5
5ꢐꢑꢂ
5ꢐ55
5ꢐ5ꢂ
ꢂꢒꢓꢁ
ꢂꢒꢓꢔ
ꢂꢒꢓꢂ
ꢂꢒ5ꢕ
ꢂꢒ5ꢓ
ꢂꢒ5ꢁ
ꢄ
ꢚ ꢔꢁꢄ
ꢊ
ꢊ
ꢊ
ꢊ
ꢚ 5ꢊ
ꢄ
ꢙ 1ꢓꢄ
ꢙꢙ
ꢆꢇꢍꢘꢙ
ꢆꢇꢍꢘꢙ
ꢆꢇꢍꢘꢙ
ꢆꢇꢍꢘꢙ
ꢘꢘ
ꢙꢍꢆꢕꢉ ꢚ ꢂꢄ
ꢚ 1ꢔꢊ
ꢚ ꢔꢁꢊ
ꢚ ꢁꢕꢊ
ꢘꢍꢆꢔꢉ ꢙ 1ꢓꢄ
ꢀꢁꢂ ꢀꢔꢂ
ꢂ
ꢔꢂ ꢁꢂ ꢓꢂ ꢒꢂ 1ꢂꢂ 1ꢔꢂ
ꢀꢁꢂ ꢀꢓꢂ
ꢂ
ꢓꢂ ꢁꢂ ꢑꢂ ꢒꢂ 1ꢂꢂ 1ꢓꢂ
ꢀꢁꢂ
ꢂ
ꢁꢂ
ꢕꢂ
1ꢔꢂ
ꢇꢈꢕꢉꢈꢖꢆꢇꢗꢖꢈ ꢎꢘꢙꢏ
ꢇꢈꢔꢉꢈꢕꢆꢇꢖꢕꢈ ꢎꢗꢘꢏ
ꢆꢏꢅꢉꢏꢇꢍꢆꢖꢇꢏ ꢐꢗꢄꢑ
3751 ꢅ1ꢑ
3751 ꢅꢓꢂ
3751 ꢎꢔ1
PIN FUNCTIONS
(TSSOP/QFN)
RV
(Pin 1/Pin 19): Transformer Supply Sense Pin.
UVLO2 (Pin 4/Pin 2): VCC Undervoltage Lockout Pin.
Senses when V drops below:
TRANS
Connect a resistor between the RVTRANS pin and the
CC
V
supply. Refer to Table 2 for proper sizing of the
RTVRTARNASNS resistor. The minimum operation voltage for
TRANS
V
= 1.225+ 50µA • R
UVLO2
UVLO2
V
is 4.75V.
and trips the FAULT latch low, disabling switching. After
rises above V , toggling the CHARGE pin reac-
UVLO1 (Pin 2/Pin 20): V
Undervoltage Lockout Pin.
TRANS
drops below:
V
CC
UVLO2
Senses when V
TRANS
tivates switching.
OVLO2 (Pin 5/Pin 3): VCC Overvoltage Lockout Pin.
Senses when V rises above:
V
= 1.225+ 50µA • R
UVLO1
UVLO1
CC
and trips the FAULT latch low, disabling switching. After
VTRANS rises above VUVLO1, toggling the CHARGE pin
reactivates switching.
V
= 1.225+ 50µA • R
OVLO2
OVLO2
and trips the FAULT latch low, disabling switching. After
drops below V , toggling the CHARGE pin reac-
OVLO1 (Pin 3/Pin 1): V
Overvoltage Lockout Pin.
TRANS
rises above:
V
CC
OVLO2
Senses when V
TRANS
tivates switching.
V
= 1.225+ 50µA • R
OVLO1
FAULT (Pin 6/Pin 4): Open Collector Indication Pin. When
either VTRANS or VCC exceeds the user-selected voltage
range, or an internal UVLO condition occurs, a transistor
turns on. The part will stop switching. This pin needs a
proper pull-up resistor or current source.
OVLO1
and trips the FAULT latch low, disabling switching. After
drops below V , toggling the CHARGE pin
V
TRANS
OVLO1
reactivates switching.
3751fd
7
For more information www.linear.com/LT3751
LT3751
PIN FUNCTIONS
DONE (Pin 7/ Pin 5): Open Collector Indication Pin. When
the target output voltage (charge mode) is reached or the
FAULT pin goes low, a transistor turns on. This pin needs
a proper pull-up resistor or current source.
LVGATE (Pin 14/Pin 12): Low Voltage Gate Pin. Connect
the NMOS gate terminal to this pin when operating V
CC
below 8V. The internal gate driver will drive the voltage to
the V rail. When operating V higher than 8V, tie this
CC
CC
pin directly to V .
CC
CHARGE (Pin 8/Pin 6): Charge Pin. Initiates a new charge
cycle (charge mode) or enables the part (regulation mode)
when driven higher than 1.5V. Bring this pin below 0.3V
to discontinue charging and put the part into shutdown.
Turn-on ramp rates should be between 10ns to 10ms.
CHARGE pin should not be directly ramped with V or
LT3751 may not properly initialize.
HVGATE (Pin 15/Pin 13): High Voltage Gate Pin. Connect
NMOS gate terminal to this pin for all V operating volt-
CC
ages. Internal gate driver will drive the voltage to within
V
CC
– 2V during each switch cycle.
CC
RBG (Pin 16/Pin 14): Bias Generation Pin. Generates
a bias current set by 0.98V/R . Select R to achieve
BG
BG
TRANS
CLAMP (Pin 9/Pin 7): Internal Clamp Voltage Selection
desired resistance for R
, RV , and RV
.
DCM
OUT
Pin. Tie this pin to V to activate the internal 5.6V gate
CC
NC (Pins 17, 19/Pins 15, 18): No Connection.
driver clamp. Tie this pin to ground to activate the internal
RVOUT (Pin 18/Pin 16): Output Voltage Sense Pin.
Develops a current proportional to the output capacitor
voltage. Connect a resistor between this pin and the drain
of NMOS such that:
10.5V gate driver clamp.
FB (Pin 10/Pin 8): Feedback Regulation Pin. Use this pin
to achieve low noise voltage regulation. FB is internally
regulated to 1.22V when a resistive divider is tied from
this pin to the output. FB pin should not float. Tie FB pin
to either a resistor divider or ground.
⎛
⎜
⎝
⎞
⎟
⎠
RV
OUT
V
= 0.98 • N •
− V
DIODE
OUT
R
BG
CSN (Pin 11/Pin 9): Negative Current Sense Pin. Senses
when RV
is set equal to RV
, otherwise:
OUT
TRANS
external NMOS source current. Connect to local R
SENSE
⎡
⎤
⎥
⎦
⎛
⎜
⎝
⎞
⎟
⎠
RV
OUT
RV
OUT
ground connection for proper Kelvin sensing. The current
V
= N • 0.98 •
+ V
− 1
⎢
⎣
OUT
TRANS
limit is set by 106mV/R
.
R
RV
TRANS
SENSE
BG
CSP (Pin 12/Pin 10): Positive Current Sense Pin. Senses
NMOS source current. Connect the NMOS source terminal
and the current sense resistor to this pin. The current
− V
DIODE
where V
= forward voltage drop of diode D1 (refer
DIODE
to the Block Diagram).
limit is fixed at 106mV/R
in charge mode. The cur-
SENSE
rent limit can be reduced to a minimum 11mV/R
regulation mode.
in
RDCM (Pin 20/Pin 17): Discontinuous Mode Sense Pin.
Senses when the external NMOS drain is equal to 20µA •
SENSE
R
DCM
+ V
and initiates the next switch cycle. Place
TRANS
V
(Pin 13/Pin 11): Input Supply Pin. Must be locally
CC
a resistor equal to 0.45 times the resistor on the RV
pin between this pin and V
TRANS
bypassed with high grade (X5R or better) ceramic capaci-
.
DRAIN
tor. The minimum operating voltage for V is 4.75V.
CC
GND (Pin 21/Pin 21): Ground. Tie directly to local ground
plane.
3751fd
8
For more information www.linear.com/LT3751
LT3751
BLOCK DIAGRAM
T1
1:10
•
D1
V
V
OUT
450V
TRANS
12V
+
47µF
×2
RV
TRANS
40.2k
10µF
+
C
OUT
•
RV
TRANS
V
OUT
COMPARATOR
–
+
CHARGE
0.98V
60V
REFERENCE
OFF ON
OTLO
START-UP
RV
OUT
RV
OUT
ONE-SHOT
40.2k
V
CC
V
CC
12V
MASTER
LATCH
DIFF. AMP
COMPARATOR
WITH
INTERNAL
60V CLAMPS
60V
100k
DONE
DCM
COMPARATOR
10µF
R
DCM
S
R
Q
RDCM
60V
–
+
18.2k
ꢀ
ENABLE
GATE
DRIVER
DCM
ONE-SHOT
100k
1.22V
REFERENCE
FAULT
V
DRAIN
S
ꢀ
R
Q
FAULT
LATCH
V
CC
26kHz ONE-SHOT
CLOCK
HVGATE
GATE DRIVE
CIRCUITRY
M1
S
R
Q
ꢀ
INTERNAL
UVLO
3.8V
+
–
SWITCH
LATCH
CLAMP
LVGATE
V
CC
V
CC
R
UVLO1
191k
UVLO1
OVLO1
UVLO2
OVLO2
V
V
RESET
TRANS
–
+
CC
AUXILIARY
CLK
55V
COUNT
+
COUNTER
162mV
R
OVLO1
240k
– +–
+
–
26kHz
ONE-SHOT
CLOCK
55V
MAIN
CSP
CSN
+
R
SENSE
12mΩ
106mV
UVLO/OVLO
R
UVLO2
191k
COMPARATORS
– +–
V
–
+
CC
TIMING AND PEAK
CURRENT CONTROL
55V
55V
11mV TO 106mV
MODULATION
TO CHARGE
ONE-SHOT
26kHz
ONE-SHOT
CLOCK
ERROR
AMP
1.22V
REFERENCE
+
–
R
OVLO2
240k
A1
+
–
R
FBH
3.65M
FB
DIE
TEMP
TO V
OUT
COMPARATOR
160ºC
MODE
CONTROL
1.22V
REFERENCE
R
FBL
10k
10nF
GND
RBG
3751 BD
R
BG
1.33k
3751fd
9
For more information www.linear.com/LT3751
LT3751
OPERATION
The LT3751 can be used as either a fast, efficient high
voltage capacitor charger controller or as a high voltage,
low noise voltage regulator. The FB pin voltage determines
one of the three primary modes: charge mode, low noise
regulation, or no-load operation (see Figure 1).
ꢍ
ꢋꢌꢂꢍ
ꢀ
ꢆ ꢀ
ꢌꢂꢍ
ꢁꢂꢃꢄꢅ
ꢇꢅꢈꢉꢄꢊ
ꢍ
ꢋ
ꢌꢒ
ꢀꢁ ꢂꢃꢄ
ꢅꢆꢇꢈꢉꢊꢋ
ꢍ
ꢋꢅꢐꢑ
ꢄꢆꢍꢇꢆꢉꢎ
ꢆꢂꢋꢏꢉꢈꢃꢆꢄ
ꢀ
ꢉꢎꢁ
ꢏ ꢀ
ꢋ
ꢇꢍꢉꢇꢐ
ꢅꢐꢑ
ꢍ
1ꢔ3ꢕꢅ
ꢌꢒ
ꢄ
ꢏꢋꢊꢐꢇꢉꢈꢃꢆꢄ
1ꢔ1ꢖꢅ
ꢑꢒꢉꢏꢊꢋ
ꢓꢆꢎꢋ
ꢀ
ꢌꢂꢍ
ꢀ
ꢆ ꢀ
ꢁꢂꢃꢄꢅ
ꢇꢅꢈꢉꢄꢊ
ꢌꢔꢌꢅ
3751 ꢀꢌ1
Figure 1. FB Pin Modes
CHARGE MODE
ꢆꢈꢀ
ꢉꢎꢁ
ꢏ ꢀ
ꢄ
ꢊ
ꢇꢍꢉꢇꢐ
When the FB pin voltage is below 1.16V, the LT3751 acts
as a rapid capacitor charger. The charging operation has
four basic states for charge mode steady-state operation
(see Figure 2).
ꢀ
ꢅꢐꢑ
ꢀ
ꢉꢎꢁ
ꢏ ꢀ
ꢇꢍꢉꢇꢐ
1. Start-Up
The first switching cycle is initiated approximately 2µs
after the CHARGE pin is raised high. During this phase,
the start-up one-shot enables the master latch turning
on the external NMOS and beginning the first switching
cycle. After start-up, the master latch will remain in the
switching-enable state until the target output voltage is
reached or a fault condition occurs.
ꢆꢄ ꢈꢀ
ꢆ ꢀ
ꢊ
ꢇꢅꢈꢉꢄꢊ
ꢁꢂꢃꢄꢅ
ꢀ
ꢉꢎꢁ
ꢏ ꢀ
ꢄ
ꢇꢍꢉꢇꢐ
ꢀ
ꢏ
ꢁꢂꢃꢄꢅ
ꢀ
ꢇꢂꢃꢍꢄ
ꢀ
ꢁꢂꢃꢄꢅ
The LT3751 utilizes circuitry to protect against trans-
former primary current entering a runaway condition and
remains in start-up mode until the DCM comparator has
enough headroom. Refer to the Start-Up Protection sec-
tion for more detail.
ꢀ
ꢀ
ꢇꢅꢈꢉꢄꢊ
ꢇꢅꢈꢉꢄꢊ
3751 ꢓꢔꢕ
1ꢖ
ꢕꢖ
3ꢖ
ꢌꢂꢍꢗꢃꢂꢘꢙꢅꢍꢇꢐ
ꢑꢚꢃꢂꢛꢍꢄꢛ
ꢅꢐꢑꢉꢄꢇꢃꢂꢘ
ꢐꢄꢐꢂꢛꢘ ꢁꢂꢃꢄꢅꢓꢐꢂ
ꢃꢄꢇ ꢉꢎꢁꢌꢎꢁ
ꢇꢍꢅꢑꢉꢄꢁꢍꢄꢎꢉꢎꢅ
ꢗꢉꢇꢐ
ꢇꢐꢁꢐꢑꢁꢍꢉꢄ
ꢇꢐꢁꢐꢑꢁꢍꢉꢄ
2. Primary-Side Charging
Figure 2. Idealized Charging Waveforms
When the NMOS switch latch is set, and depending on the
use of LVGATE, the gate driver rapidly charges the gate
pin to V – 2V in high voltage applications or directly to
CC
V
in low voltage applications (refer to the Application
CC
3751fd
10
For more information www.linear.com/LT3751
LT3751
OPERATION
Information section for proper use of LVGATE). With the
gate driver output high, the external NMOS turns on,
comparator sets the NMOS switch latch and a new switch
cycle begins. Steps 2-4 continue until the target output
voltage is reached.
forcing V
– V
across the primary winding.
TRANS
DS(ON)
Consequently, current in the primary coil rises linearly at
a rate (V – V )/L . The input voltage is mir-
Start-Up Protection
TRANS
DS(ON) PRI
rored on the secondary winding –N • (V
– V
)
TRANS
DS(ON)
The LT3751 at start-up, when the output voltage is very
low (or shorted), usually does not have enough V
node voltage to trip the DCM comparator. The part in start-
up mode uses the internal 26kHz clock and an auxiliary
current comparator. Figure 3 shows a simplified block
diagram of the start-up circuitry.
which reverse-biases the diode and prevents current flow
in the secondary winding. Thus, energy is stored in the
core of the transformer.
DRAIN
3. Secondary Energy Transfer
When current limit is reached, the current limit compara-
tor resets the NMOS switch latch and the device enters the
third phase of operation, secondary energy transfer. The
energy stored in the transformer core forward-biases the
diode and current flows into the output capacitor. During
this time, the output voltage (neglecting the diode drop)
is reflected back to the primary coil. If the target output
voltage is reached, the VOUT comparator resets the master
latch and the DONE pin goes low. Otherwise, the device
enters the next phase of operation.
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈꢇꢄꢁꢉ
ꢇꢌꢊꢁꢋꢃꢋꢌꢍ
ꢊꢅꢁꢁꢋꢌꢍ
ꢊꢂꢃꢎꢄꢁꢄꢍꢂꢁ
ꢊꢂꢅꢌꢍꢋꢁ 1
ꢖ
ꢀꢁꢂꢃ ꢒꢊꢃ
ꢁꢋꢔꢋꢍ
ꢊꢂꢃꢎꢄꢁꢄꢍꢂꢁ
ꢀꢁꢂꢃ ꢊꢈꢐ
ꢔꢘꢇꢍꢊꢙ
ꢈꢄꢍꢊꢙ
ꢗ
ꢇꢌꢊꢁꢋꢃꢋꢌꢍ
ꢊꢂꢅꢌꢍꢋꢁ ꢕ
ꢁꢋꢔꢋꢍ
ꢀꢁꢂꢃ ꢑꢄꢍꢋ
ꢒꢁꢇꢓꢋꢁ ꢂꢌ
3751 ꢀꢏ3
Figure 3. Start-Up Protection Circuitry
Toggling the CHARGE pin always generates a start-up
one-shot to turn on the external switch, initiating the
charging process. After the start-up one-shot, the LT3751
waits for either the DCM comparator to generate a one-
shot or the output of the start-up protection circuitry
going high, which ever comes first. If the switch drain
4. Discontinuous Mode Detection
During secondary energy transfer to the output capacitor,
(V
+ V
)/N will appear across the primary wind-
OUT
DIODE
ing. A transformer with no energy cannot support a DC
voltage, so the voltage across the primary will decay to
zero. In other words, the drain of the NMOS will ring
node, V
, is below the DCM comparator threshold
DRAIN
down from V
the drain voltage falls to V
+ (V
+ V
)/N to V
. When
TRANS
OUT
DIODE
+ 20µA • R
TRANS
(see Entering Normal Boundary Mode), the DCM compar-
ator will never fire and the start-up circuitry is dominant.
, the DCM
TRANS
DCM
ꢐ
ꢐ
ꢁꢋ1
ꢐ
ꢁꢋꢔ
ꢐ
ꢈꢃꢂꢕꢗ
ꢐ
ꢍꢅꢁ
ꢈꢉꢊ
1ꢄꢀꢋꢍꢁ
ꢛ
ꢀꢁꢂꢃꢁꢄꢅꢆ
ꢇꢈꢉꢊ ꢁꢋꢃꢌꢀꢋꢍꢎꢈ ꢏ ꢐ
ꢒꢍꢅꢗꢈꢂꢃꢚꢄꢊꢍꢈꢌ
ꢇꢈꢉꢊ ꢁꢋꢃꢌꢀꢋꢍꢎꢈ ꢏ ꢐ
ꢒꢌꢎꢍꢓ ꢐ
ꢁꢋꢔ
ꢇꢓꢂꢕꢁ ꢖꢍꢃ ꢁꢕꢊꢌꢄꢍꢅꢁꢑ
ꢑ
ꢑ
ꢁꢋꢔ
ꢁꢋ1
3751 ꢖꢘꢙ
Figure 4. DCM Comparator Thresholds
3751fd
11
For more information www.linear.com/LT3751
LT3751
OPERATION
At very low output voltages, the boundary-mode switch-
ing cycle period increases significantly such that the
energy stored in the transformer core is not depleted
before the next clock cycle. In this situation, the clock
may initiate another switching cycle before the secondary
winding current reaches zero and cause the LT3751 to
enter continuous-mode conduction. Normally, this is not
a problem; however, if the secondary energy transfer time
is much longer than the CLK period, significant primary
current overshoot can occur. This is due to the non-zero
starting point of the primary current when the switch
turns on and the finite speed of the current comparator.
and indicates that the energy in the secondary winding
has depleted. For this to happen, VDRAIN must exceed
V
+ ΔV
prior to its negative edge; otherwise,
TRANS
DRAIN
the DCM comparator will not generate a one-shot to initi-
ate the next switching cycle. The part would remain stuck
in this state indefinitely; however, the LT3751 uses the
start-up protection circuitry to jumpstart switching if the
DCM comparator does not generate a one-shot after a
maximum time-out of 500µs.
Figure 4 shows a typical V
node waveform with a
DRAIN
test circuit voltage clamp applied to the output. VTH1 is the
start-up threshold and is set internally by forcing I
to 40μA. Once the first DCM one-shot is initiateOdF,FtShEeT
mode latch is set to boundary-mode. The mode latch then
sets the clock count to maximum (500µs) and lowers the
The LT3751 startup circuitry adds an auxiliary current
comparator with a trip level 50% higher than the nomi-
nal trip level. Every time the auxiliary current comparator
trips, the required clock count between switching cycles is
incremented by one. This allows more time for secondary
energy transfer.
DCM comparator threshold to V (I
= 20μA). This
TH2
provides needed hysteresis betweenOsFFtaSrEtT-up mode and
boundary-mode operation.
Counter 1 in Figure 3 is set to its maximum count when
the first DCM comparator one-shot is generated. If no
DCM one-shot is initiated in normal boundary-mode oper-
ation during a maximum count of approximately 500µs,
the LT3751 re-enters start-up mode and the count is
returned to zero.
LOW NOISE REGULATION
Low noise voltage regulation can be achieved by adding
a resistive divider from the output node to the LT3751 FB
pin. At start-up (FB pin below 1.16V), the LT3751 enters
the charge mode to rapidly charge the output capacitor.
Once the FB pin is within the threshold range of 1.16V
to 1.34V, the part enters into low noise regulation. The
switching methodology in regulation mimics that used
in the capacitor charging mode, but with the addition of
peak current and duty cycle control techniques. Figure 5
shows the steady state operation for both regulation tech-
niques. Figure 6 shows how both techniques are com-
bined to provide stable, low noise operation over a wide
load and supply range.
Note that Counter 1 is initialized to zero at start-up.
Thus, the output of the startup circuitry will go high after
one clock cycle. Counter 2 is reset when the gate driver
goes high. This repeats until either the auxiliary cur-
rent comparator increments the required clock count or
until V
is high enough to sustain normal operation
DRAIN
described in steps 2 through 4 in the previous section.
Entering Normal Boundary Mode
The LT3751 has two DCM comparator thresholds that
are dependent on what mode the part is in, either start-
up mode or normal boundary-mode, and the state of the
mode latch. For boundary-mode switching, the LT3751
requires the DCM sense voltage (VDRAIN) to exceed
During heavy load conditions, the LT3751 sets the peak
primary current to its maximum value, 106mV/R
SENSE
and sets the maximum duty cycle to approximately 95%.
This allows for maximum power delivery. At very light
loads, the opposite occurs, and the LT3751 reduces the
peak primary current to approximately one tenth its maxi-
mum value while modulating the duty cycle below 10%.
The LT3751 controls moderate loads with a combination
of peak current mode control and duty cycle control.
V
by the ΔDCM comparator threshold, ΔV
:
TRANS
DRAIN
ΔV
= (40µA + I ) • R – 40µA • RV
OFFSET DCM TRANS
DRAIN
where IOFFSET is mode dependent. The DCM one-shot sig-
nal is negative edge triggered by the switch node, V
,
DRAIN
3751fd
12
For more information www.linear.com/LT3751
LT3751
OPERATION
CHARGE MODE
LIGHT LOAD OPERATION
26kHz
ONE-SHOT
CLK
26kHz
ONE-SHOT
CLK
...
...
...
...
SWITCH
ENABLE
MAXIMUM
PEAK CURRENT
NO BLANKING
SWITCH
ENABLE
DUTY CYCLE
CONTROL
DUTY CYCLE
CONTROL
FORCED
BLANKING
I
I
PRI
PRI
...
...
t
t
t
≈ 38µs
PER
NO-LOAD OPERATION
HEAVY LOAD OPERATION
26kHz
ONE-SHOT
CLK
26kHz
ONE-SHOT
CLK
...
...
...
...
110%
OUT, NOM
V
SWITCH
ENABLE
PEAK CURRENT
CONTROL
V
OUT
FORCED
BLANKING
105%
OUT, NOM
V
...
1/10TH I
I
PK
PRI
...
I
PRI
t
t
t
≈ 38µs
PER
3751 F05
Figure 5. Modes of Operation (Steady State)
ꢄ
ꢑ
ꢒ ꢊꢓꢇꢐ ꢋꢐꢋꢃꢍ ꢑ
ꢒ
ꢃꢄꢎ
ꢄ
ꢎꢉꢔ
ꢖ5ꢗ
ꢘꢈꢙꢃꢈꢉꢊ
ꢈꢚꢍꢌꢉꢇꢄꢈꢘ
1ꢕ1ꢁ
ꢎꢉꢔ
1ꢁꢗ
ꢁ
ꢄ
ꢃꢈꢉꢊ
ꢋꢓꢌꢌꢍꢘꢇ
ꢋꢆꢉꢌꢅꢍ
ꢎꢈꢊꢍ
3751 ꢀꢁꢂ
ꢃꢄꢅꢆꢇ ꢃꢈꢉꢊ
ꢎꢈꢊꢍꢌꢉꢇꢍ
ꢃꢈꢉꢊ
ꢆꢍꢉꢏꢐ ꢃꢈꢉꢊ
Figure 6. Regulation Technique
3751fd
13
For more information www.linear.com/LT3751
LT3751
OPERATION
Periodic Refresh
Light Load Operation
When the LT3751 enters regulation, the internal circuitry
deactivates switching when the internal one-shot clock
is high. The clock operates at a 1/20th duty cycle with a
minimum blank time of 1.5µs. This reset pulse is timed to
drastically reduce switching frequency content within the
audio spectrum and is active during all loading conditions.
Each reset pulse guarantees at least one energy cycle. A
minimum load is required to prevent the LT3751 from
entering no-load operation.
The LT3751 uses duty cycle control to drastically reduce
audible noise in both the transformer (mechanical) and
the ceramic capacitors (piezoelectric effects). Internal
control circuitry forces a one-shot condition at a periodic
rate greater than 20kHz and out of the audio spectrum.
The regulation loop then determines the number of pulses
that are required to maintain the correct output voltage.
Figure 5 shows the use of duty-cycle control.
No-Load Operation
Heavy Load Operation
The LT3751 can remain in low noise regulation at very low
loading conditions. Below a certain load current threshold
(Light Load Operation), the output voltage would continue
to increase and a runaway condition could occur. This is
due to the periodic one-shot forced by the periodic refresh
circuitry. By design, the LT3751 has built-in overvoltage
protection associated with the FB pin.
The LT3751 enters peak current mode control at higher
output load conditions. The control loop maximizes the
number of switch cycles between each reset pulse. Since
the control scheme operates in boundary mode, the reso-
nant boundary-mode period changes with varying peak
primary current:
⎡
⎤
1
N
When the FB pin voltage exceeds 1.34V ( 20mV), the
LT3751 enters no-load operation. No-load operation does
not reset with the one-shot clock. Instead, the pulse train
is completely load-dependent. These bursts are asynchro-
nous and can contain long periods of inactivity. This allows
regulation at a no-load condition but with the increase of
audible noise and voltage ripple. Note that when operating
with no-load, the output voltage will increase 10% above
the nominal output voltage.
Period = I • L
•
PRI
+
⎢
⎥
PK
V
V
OUT
⎣
⎦
TRANS
and the power output is proportional to the peak primary
current:
1/ 2 •I
PK
P
=
OUT
⎡
⎢
⎤
1
N
+
⎥
V
V
OUT
⎣
⎦
TRANS
Noise becomes an issue at very low load currents. The
LT3751 remedies this problem by setting the lower peak
current limit to one tenth the maximum level and begins
to employ duty-cycle control.
3751fd
14
For more information www.linear.com/LT3751
LT3751
APPLICATIONS INFORMATION
1ꢑꢑ
ꢖꢑ
ꢕꢑ
7ꢑ
ꢔꢑ
5ꢑ
ꢓꢑ
3ꢑ
ꢒꢑ
1ꢑ
ꢑ
The LT3751 charger controller can be optimized for either
capacitor charging only or low noise regulation applica-
tions. Several equations are provided to aid in the design
process.
P = 20 WATTS
P = 50 WATTS
P = 100 WATTS
Safety Warning
Large capacitors charged to high voltage can deliver a
lethal amount of energy if handled improperly. It is partic-
ularly important to observe appropriate safety measures
when designing the LT3751 into applications. First, cre-
ate a discharge circuit that allows the designer to safely
discharge the output capacitor. Second, adequately space
high voltage nodes from adjacent traces to satisfy printed
circuit board voltage breakdown requirements.
1
1ꢑ
ꢀꢁꢂꢃ ꢀꢄꢅꢆꢂꢄꢇ ꢈꢉꢄꢄꢁꢊꢋ ꢌꢂꢍ
1ꢑꢑ
3751 ꢐꢑ7
Figure 7. Maximum Power Output
Selecting Transformer Turns Ratio
Selecting Operating Mode
The transformer ratio, N, should be selected based on
the input and output voltages. Smaller N values equate
to faster charge times and larger available output power.
Tie the FB pin to GND to operate the LT3751 as a capacitor
charger. In this mode, the LT3751 charges the output at
peak primary current in boundary mode operation. This
constitutes maximum power delivery and yields the fast-
est charge times. Power delivery is halted once the output
reaches the desired output voltage set by the RV
RBG pins.
Note that drastically reducing N below the V /V
OUT TRANS
ratio will increase the flyback voltage on the drain of the
NMOS and increase the current through the output diode.
and
OUT
The ratio, N, should not be drastically increased either,
2
due to the increased capacitance, N • C , reflected to
SEC
the primary. A good choice is to select N equal to V
/
OUT
Tie a resistor divider from the FB pin to V
and GND
OUT
V
.
TRANS
to operate the LT3751 as a low noise voltage regulator
(refer to Low Noise regulation section for proper design
procedures). The LT3751 operates as a voltage regulator
using both peak current and duty cycle modulation to
vary output current during different loading conditions.
V
OUT
N ≤
V
TRANS
Choosing Capacitor Charger I
PK
When operating the LT3751 as capacitor charger, choose
Selecting Component Parameters
IPK based on the required capacitor charge time, tCHARGE
,
Most designs start with the initial selection of VTRANS
,
and the initial design inputs.
VOUT, COUT, and either charge time, tCHARGE, (capacitor
charger) or POUT,MAX (regulator). These design inputs
are then used to select the transformer ratio, N, the peak
2 • N • V
+ V
• C
• V
OUT OUT
(
)
(
TRANS
OUT
I
=
PK
Efficiency • V
• t
− t
d
CHARGE
)
TRANS
primary current, IPK, and the primary inductance, LPRI
Figure 7 can be used as a rough guide for maximum
power output for a given V and I .
.
The converter efficiency varies over the output voltage
range. The I equation is based on the average efficiency
PK
TRANS
PK
over the entire charging period. Several factors can cause
the charge time to increase. Efficiency is the most domi-
nant factor and is mainly affected by the transformer
winding resistance, core losses, leakage inductance, and
transistor R . Most applications have overall efficiencies
above 70%.DS
3751fd
15
For more information www.linear.com/LT3751
LT3751
APPLICATIONS INFORMATION
Transformer Design
The total propagation delay, t , is the second most domi-
d
nant factor that affects efficiency and is the summation of
gate driver on-off propagation delays and the discharge
time associated with the secondary winding capacitance.
There are two effective methods to reduce the total propa-
gation delay. First, reduce the total capacitance on the
secondary winding, most notably the diode capacitance.
Second, reduce the total required NMOS gate charge.
Figure 8 shows the effect of large secondary capacitance.
The transformer’s primary inductance, LPRI, is determined
by the desired V
and previously calculated N and I
OUT
PK
parameters. Use the following equation to select L
:
PRI
3µs • V
OUT
L
=
PRI
I
• N
PK
The previous equation guarantees that the VOUT com-
parator has enough time to sense the flyback waveform
The energy stored in the secondary winding capacitance
and trip the DONE pin latch. Operating V
significantly
OUT
2
is ½ • C • V
. This energy is reflected to the primary
SEC
when the diodOeUsTtops forward conduction. If the reflected
capacitance is greater than the total NMOS drain capaci-
tance, the drain of the NMOS power switch goes negative
and its intrinsic body diode conducts. It takes some time
for this energy to be dissipated and thus adds to the total
propagation delay.
higher than that used to calculate L could result in a
PRI
runaway condition and overcharge the output capacitor.
The L equation is adequate for most regulator applica-
tions.PNRIote that if both IPK and N are increased signifi-
cantly for a given V
and V , the maximum I will
TRANS
OUT PK
not be reached within the refresh clock period. This will
result in a lower than expected maximum output power.
To prevent this from occurring, maintain the condition in
the following equation.
ꢀ
ꢁꢂꢃꢄꢅ
38µs
L
<
PRI
ꢄ
⎡
⎤
ꢉꢊꢋ
1
N
I
•
+
⎢
⎥
ꢅꢍ ꢉꢊꢋꢎ
ꢋꢃꢌꢃꢋꢄꢏꢃꢅꢋꢊ
PK
V
V
OUT
⎣
⎦
TRANS
ꢄ
ꢌꢂꢄ
The upper constraint on L can be reduced by increas-
PRI
ꢉꢊꢋꢎ ꢁꢄꢉꢋꢐꢃꢂꢑꢊ
ing V
and starting the design process over. The best
ꢒ
regulTaRtiAoNnS occurs when operating the boundary-mode
frequency above 100kHz (refer to Operation section for
boundary-mode definition).
3751 ꢆꢇꢈ
Figure 8. Effect of Secondary Winding Capacitance
Choosing Regulator Maximum I
Figure 9 defines the maximum boundary-mode switching
frequency when operating at a desired output power level
PK
The I parameter in regulation mode is calculated based
PK
and is normalized to L /P
(μH/Watt). The relation-
PRI OUT
on the desired maximum output power instead of charge
time like that in a capacitor charger application.
ship of output power, boundary-mode frequency, I , and
PK
primary inductance can be used as a guide throughout
⎛
⎜
⎝
⎞
⎟
⎠
P
1
N
OUT(AVG)
the design process.
I
= 2 •
•
+
PK
Efficiency
V
V
OUT
TRANS
Note that the LT3751 regulation scheme varies the peak
current based on the output load current. The maximum
I
is only reached during charge mode or during heavy
PK
load conditions where output power is maximized.
3751fd
16
For more information www.linear.com/LT3751
LT3751
APPLICATIONS INFORMATION
Table 1. Recommended Transformers
MANUFACTURER
PART NUMBER
SIZE L × W × H (mm)
MAXIMUM I (A)
L
(µH)
PRI
TURNS RATIO (PRI:SEC)
PRI
Coilcraft
www.coilcraft.com
DA2033-AL
DA2034-AL
GA3459-BL
GA3460-BL
HA4060-AL
HA3994-AL
17.4 × 24.1 × 10.2
20.6 × 30 × 11.3
32.65 × 26.75 × 14
32.65 × 26.75 × 14
34.29 × 26.75 × 14
34.29 × 28.75 × 14
5
10
20
50
2
10
1:10
1:10
10
5
1:10
2.5
300
7.5
1:10
1:3
5
2:1:3:3*
Würth Elektronik/Midcom
www.we-online.com
750032051
750032052
750310349
750310355
28.7 × 22 × 11.4
28.7 × 22 × 11.4
36.5 × 42 × 23
36.5 × 42 × 23
5
10
10
5
1:10
1:10
1:10
1:10
10
20
50
2.5
Sumida
www.sumida.com
C8117
23 × 18.6 × 10.8
32.2 × 27 × 14
32.5 × 26.5 × 13.5
32.5 × 26.5 × 13.5
5
10
10
5
1:10
1:10
1:10
1:10
C8119
10
20
50
PS07-299
PS07-300
2.5
TDK
www.tdk.com
DCT15EFD-U44S003
DCT20EFD-U32S003
DCT25EFD-U27S005
22.5 × 16.5 × 8.5
30 × 22 × 12
27.5 × 33 × 15.5
5
10
20
10
10
5
1:10
1:10
1:10
*Transformer has three secondaries where the ratio is designated as PRI:SEC1:SEC2:SEC3
RV
, RV
and R
Selection
TRANS
OUT
DCM
1ꢔꢖꢔꢔꢔ
1ꢖꢔꢔꢔ
ꢔꢖ1ꢔꢔ
ꢔꢖꢔ1ꢔ
ꢔꢖꢔꢔ1
f
f
f
ꢘ 5ꢔꢙꢒꢚ
ꢘ 1ꢔꢔꢙꢒꢚ
ꢘ ꢛꢔꢔꢙꢒꢚ
ꢆꢂꢗ
ꢆꢂꢗ
ꢆꢂꢗ
RVTRANS sets the common-mode reference voltage for
both the DCM comparator and V comparator. Select
OUT
RV
from Table 2 based on the transformer supply
volTtaRgAeNSrange, VTRANS, and the maximum trip voltage,
ΔV
(V
-V
).
DRAIN DRAIN TRANS
The RV
pin is connected to an internal 40µA current
TRANS
source. Pin current increases as the pin voltage is taken
higher than the internal 60V Zener clamp. The LT3751 can
operate from V
greater than the 60V internal Zener
TRANS
1
1ꢔ
ꢀꢁꢂꢃ ꢀꢄꢅꢆꢂꢄꢇ ꢈꢉꢄꢄꢁꢊꢋ ꢌꢂꢍ
1ꢔꢔ
clamps by limiting the RVTRANS pin current to 250µA.
3751 ꢓꢔꢕ
Operating V above 200V requires the use of resis-
TRANS
Figure 9. Maximum Switching Frequency
tor dividers. Two applications are presented that operate
Table 2. Suggested RVTRANS, RVOUT, and RDCM Values
V
Range
∆V
RANGE
RV
RV
R
DCM
TRANS
DRAIN
TRANS
OUT
(V)
(V)
(kΩ)
5.11
25.5
40.2
80.6
(kΩ)
5.11
25.5
40.2
80.6
(kΩ)
2.32
11.5
18.2
36.5
4.75 to 55
4.75 to 60
8 to 80
0 to 5
2.5 to 50
5 to 80
8 to 160
V
− 55V
V
− 55V
TRANS
TRANS
80 to 200
>200
2mA • RV
0.86 • RV
TRANS
OUT
0.25
0.25
Resistor Divider Dependent
Use Resistor Divider
Use Resistor Divider
Use Resistor Divider
3751fd
17
For more information www.linear.com/LT3751
LT3751
APPLICATIONS INFORMATION
with VTRANS between 100V and 400V (refer to Typical
Applications section). Consult applications engineering
RV
from Table 2 meets this criterion. Use the following
OUT
equation to size R (V
≤ 80V):
BG TRANS
for applications with V
operating above 400V.
TRANS
⎛
⎞
RV
OUT
⎜
⎟
R
= 0.98 •N •
BG
RV
is required for capacitor charger applications but
OUT
⎜
⎟
V
+ V
DIODE
⎝
⎠
OUT,TRIP
may be removed for regulator applications. Note that the
comparator can be used as secondary protection
V
OUT
Tie R pin to ground when not using the V
compara-
OUT
for regulator applications. If the V
comparator is used
BG
OUT
tor. Consult applications engineering for calculating R
for protection, design V
15% to 20% higher than
OUT
BG
OUT,TRIP
when operating V
above 80V.
the regulation voltage. Tie the RV
pin to ground when
TRANS
RV
resistor is removed.
OUT
NMOS Switch Selection
R
needs to be properly sized in relation to RV
.
DCM
TRANS
Choose an external NMOS power switch with minimal
gate charge and on-resistance that satisfies current limit
and voltage break-down requirements. The gate is nomi-
nally driven to V – 2V during each charge cycle. Ensure
that this does nCoCt exceed the maximum gate to source
voltage rating of the NMOS but enhances the channel
enough to minimize the on-resistance.
Improper selection of R
can lead to undesired switch-
ing operation at low ouDtpCuMt voltages. Use Table 2 to size
R
.
DCM
Parasitic capacitance on RVTRANS, RVOUT, and RDCM
should be minimized. Capacitances on these nodes slow
down the response times of the VOUT and DCM com-
parators. Keep the distance between the resistor and
pin short. It is recommended to remove all ground and
power planes underneath these pins and their respective
components (refer to the recommended board layout at
the end of this section).
Similarly, the maximum drain-source voltage rating of
the NMOS must exceed V
+ V /N or the magni-
TRANS
OUT
tude of the leakage inductance spike, whichever is greater.
The maximum instantaneous drain current rating must
exceed selected current limit. Because the switching
period decreases with output voltage, the average current
though the NMOS is greatest when the output is nearly
charged and is given by:
R
BG
Selection
R
sets the trip current (0.98/R ) and is directly related
BG
to the selection of RV . The bBeGst accuracy is achieved
with a trip current beOtwUTeen 100µA and 2mA. Choosing
I
• V
PK
OUT(PK)
I
=
AVG,M
2(V
+N • V
)
OUT(PK)
TRANS
See Table 3 for recommended external NMOS transistors.
Table 3. Recommended NMOS Transistors
MANUFACTURER
PART NUMBER
I (A)
D
V
(V)
R
(mΩ)
Q
G(TOT)
(nC)
PACKAGE
DS(MAX)
DS(ON)
Fairchild Semiconductor
www.fairchildsemi.com
FDS2582
4.1
21
150
200
200
200
800
66
11
27
55
16
19
SO-8
2
FQB19N20L
FQP34N20L
FQD12N20L
FQB4N80
140
75
D PAK
31
TO-220
DPAK
12
3.9
280
3600
2
D PAK
On Semiconductor
www.onsemi.com
MTD6N15T4G
NTD12N10T4G
NTB30N20T4G
NTB52N10T4G
6
150
100
200
100
300
165
81
15
14
75
72
DPAK
DPAK
12
30
52
2
D PAK
2
30
D PAK
Vishay
www.vishay.com
Si7820DN
2.6
3.4
33
200
150
200
240
135
60
12.1
20
53
1212-8
1212-8
TO-220
Si7818DN
SUP33N20-60P
3751fd
18
For more information www.linear.com/LT3751
LT3751
APPLICATIONS INFORMATION
Table 4. Recommended Output Diodes
MANUFACTURER
PART NUMBER
I
(A)
V
RRM
(V)
T (ns)
RR
PACKAGE
F(AV)
Central Semiconductor
www.centralsemi.com
CMR1U-10M
CMSH2-60M
CMSH5-40
1
2
5
1000
60
40
100
SMA
SMA
SMC
Fairchild Semiconductor
www.fairchildsemi.com
ES3J
ES1G
ES1J
3
1
1
600
400
600
35
35
35
SMC
SMA
SMA
On Semiconductor
www.onsemi.com
MURS360
MURA260
MURA160
3
2
1
600
600
600
75
75
75
SMC
SMA
SMA
Vishay
www.vishay.com
USB260
US1G
2
1
1
5
600
400
1000
600
30
50
75
30
SMB
SMA
SMA
US1M
2
GURB5H60
D PAK
Gate Driver Operation
The average diode current is also a function of the output
voltage.
The LT3751 gate driver has an internal, selectable 10.5V
or 5.6V clamp with up to 2A current capability (using
LVGATE). For 10.5V operation, tie CLAMP pin to ground,
I
• V
PK
TRANS
I
=
AVG
2 • (V
+N • V
)
OUT
TRANS
and for 5.6V operation, tie the CLAMP pin to the V pin.
CC
The highest average diode current occurs at low output
voltages and decreases as the output voltage increases.
Reverse recovery time, reverse bias leakage and junction
capacitance should also be considered. All affect the over-
all charging efficiency. Excessive diode reverse recovery
times can cause appreciable discharging of the output
capacitor, thereby increasing charge time. Choose a diode
with a reverse recovery time of less than 100ns. Diode
leakage current under high reverse bias bleeds the output
capacitor of charge and increases charge time. Choose a
diode that has minimal reverse bias leakage current. Diode
junction capacitance is reflected back to the primary, and
energy is lost during the NMOS intrinsic diode conduction.
Choose a diode with minimal junction capacitance. Table 4
recommends several output diodes for various output
voltages that have adequate reverse recovery times.
Choose a clamp voltage that does not exceed the NMOS
manufacturer’s maximum VGS ratings. The 5.6V clamp
can also be used to reduce LT3751 power dissipation
and increase efficiency when using logic-level FETs. The
typical gate driver overshoot voltage is 0.5V above the
clamp voltage.
The LT3751’s gate driver also incorporates a PMOS pull-
up device via the LVGATE pin. The PMOS pull-up driver
should only be used for V applications of 8V or below.
CC
Operating LVGATE with V above 8V will cause perma-
CC
nent damage to the part. LVGATE is active when tied to
HVGATE and allows rail-to-rail gate driver operation. This
is especially useful for low VCC applications, allowing bet-
ter NMOS drive capability. It also provides the fastest rise
times, given the larger 2A current capability verses 1.5A
when using only HVGATE.
Setting Current Limit
Output Diode Selection
Placing a sense resistor from the positive sense pin, CSP,
to the negative sense pin, CSN, sets the maximum peak
switch current. The maximum current limit is nominally
106mV/RSENSE. The power rating of the current sense
resistor must exceed:
The output diode(s) are selected based on the maximum
repetitive reverse voltage (VRRM) and the average for-
ward current (IF(AV)). The output diode’s VRRM should
exceed VOUT + N • VTRANS. The output diode’s IF(AV)
should exceed I /2N, the average short-circuit current.
PK
2
⎛
⎞
V
I
• R
SENSE
3
OUT(PK)
PK
⎜
⎟
P
≥
RSENSE
⎜
⎟
V
+N • V
OUT(PK) TRANS
⎝
⎠
3751fd
19
For more information www.linear.com/LT3751
LT3751
APPLICATIONS INFORMATION
Additionally, there is approximately a 180ns propaga-
tion delay from the time that peak current limit is
detected to when the gate transitions to the low state.
Under/Overvoltage Lockout
The LT3751 provides user-programmable under and
overvoltage lockouts for both V and V
equations in the Pin Functions section for proper selection
of resistor values. When under/overvoltage lockout com-
parators are tripped, the master latch is disabled, power
delivery is halted, and the FAULT pin goes low.
. Use the
TRANS
CC
This delay increases the peak current limit by (V
)
TRANS
(180ns)/L
.
PRI
Sense resistor inductance (L ) is another source of
RSENSE
current limit error. LRSENSE creates an input offset voltage
(V ) to the current comparator and causes the current
OS
Adequate supply bulk capacitors should be used to reduce
power supply voltage ripple that could cause false tripping
during normal switching operation. Additional filtering
may be required due to the high input impedance of the
under/overvoltage lockout pins to prevent false tripping.
Individual capacitors ranging from 100pF to 1nF may be
placed between each of the UVLO1, UVLO2, OVLO1 and
OVLO2 pins and ground. Disable the undervoltage lock-
outs by directly connecting the UVLO1 and UVLO2 pins
to VCC. Disable the overvoltage lockouts by directly con-
necting the OVLO1 and OVLO2 pins to ground.
comparator to trip early. V can be calculated as:
OS
⎛
⎜
⎝
⎞
⎟
⎠
L
RSENSE
V
= V
•
OS
TRANS
L
PRIMARY
The change in current limit becomes VOS/RSENSE. The
error is more significant for applications using large di/
dt ratios in the transformer primary. It is recommended to
use very low inductance (< 2nH) sense resistors. Several
resistors can be placed in parallel to help reduce the
inductance.
The LT3751 provides internal Zener clamping diodes to
Care should also be taken in placement of the sense lines.
The negative return line, CSN, must be a dedicated trace
to the low side resistor terminal. Haphazardly routing the
CSN connection to the ground plane can cause inaccurate
current limit and can also cause an undesirable discon-
tinuous charging profile.
protect itself in shutdown when V
is operated above
55V. Supply voltages should onlTyRbAeNSapplied to UVLO1,
UVLO2, OVLO1 and OVLO2 with series resistance such
that the Absolute Maximum pin currents are not exceeded.
Pin current can be calculated using:
V
− 55V
APPLIED
I
=
DONE and FAULT Pin Design
PIN
R
SERIES
Both the DONE and FAULT pins require proper pull-up
resistors or current sources. Limit pin current to 1mA
into either of these pins. 100kΩ pull-up resistors are rec-
ommended for most applications. Both the DONE and
FAULT pins are latched in the low output state. Resetting
either latch requires the CHARGE pin to be toggled. A fault
condition will also cause the DONE pin to go low. A third,
non-latching condition occurs during startup when the
CHARGE pin is driven high. During this start-up condi-
tion, both the DONE and FAULT pins will go low for several
micro seconds. This indicates the internal rails are still
ramping to their proper levels. External RC filters may be
added to both indication pins to remove start-up indica-
tion. Time constants for the RC filter should be between
5µs to 20µs.
Note that in shutdown, RV
, RV , R
, UVLO1,
TRANS
OUT DCM
UVLO2, OVLO1 and OVLO2 currents increase significantly
when operating V above the Zener clamp voltages
TRANS
and are inversely proportional to the external series pin
resistances.
NMOS Snubber Design
The transformer leakage inductance causes a parasitic
voltage spike on the drain of the power NMOS switch dur-
ing the turn-off transition. Transformer leakage inductance
effects become more apparent at high peak primary cur-
rents. The worst-case magnitude of the voltage spike is
determined by the energy stored in the leakage inductance
and the total capacitance on the V
node.
DRAIN
3751fd
20
For more information www.linear.com/LT3751
LT3751
APPLICATIONS INFORMATION
LOW NOISE REGULATION
2
L
•I
LEAK PK
V
=
The LT3751 has the option to provide a low noise regu-
lated output voltage when using a resistive voltage divider
from the output node to the FB pin. Refer to the Selecting
Component Parameters section to design the transformer,
NMOS power switch, output diode, and sense resistor.
Use the following equations to select the feedback resis-
tor values based on the power dissipation and desired
output voltage:
D,LEAK
C
VDRAIN
Two problems can arise from large VD,LEAK. First, the
magnitude of the spike may require an NMOS with an
unnecessarily high V
which equates to a larger
DRAIN
(BR)DSS
R
. Secondly, the V
node will ring—possibly
DS(ON)
below ground—causing false tripping of the DCM com-
parator or damage to the NMOS switch (see Figure 11).
Both issues can be remedied using a snubber. If leakage
inductance causes issues, it is recommended to use a RC
snubber in parallel with the primary winding, as shown
in Figure 10. Size C
leakage spike voltage, known leakage inductance, and an
RC time constant less than 1µs. Otherwise, the leakage
2
V
− 1.22
(
)
OUT
R
R
=
=
; Top Feedback Resistor
FBH
P
D
and R
based on the desired
⎛
⎜
⎝
⎞
⎟
⎠
SNUB
SNUB
1.22
− 1.22
• R ; Bottom Feedback Resistor
FBH
FBL
V
OUT
R , depending on output voltage and type used, may
FBH
voltage spike can cause false tripping of the V
parator and stop charging prematurely.
com-
OUT
require several smaller values placed in series. This will
reduce the risk of arcing and damage to the feedback
resistors. Consult the manufacturer’s rated voltage speci-
fication for safe operation of the feedback resistors.
Figure 11 shows the effect of the RC snubber resulting in
a lower voltage spike and faster settling time.
The LT3751 has a minimum periodic refresh frequency
limit of 23kHz. This drastically reduces switching fre-
quency components in the audio spectrum. The LT3751
can operate with no-load, but the regulation scheme
switches to no-load operation and audible noise and
output voltage ripple increase. This can be avoided by
operating with a minimum load current.
ꢍ
ꢁ
ꢂꢃꢄ
ꢃ
ꢅꢆꢇꢈ
ꢍ
ꢉ
ꢅꢆꢇꢈ
ꢁ
ꢁꢊꢋꢌ
ꢉ
ꢎꢏꢃꢋꢄꢆ
Minimum Load Current
3751 ꢀ11
Periodic refresh circuitry requires an average minimum
load current to avoid entering no-load operation. Usually,
the feedback resistors should be adequate to provide this
minimum load current.
Figure 10. RC Snubber Circuit
ꢁ
ꢄꢅꢆꢇꢈ
ꢉꢊꢇꢋꢌꢒꢎꢋ
ꢍꢈꢎꢏꢏꢐꢅꢑ
2
L
•I • 23kHz
PRI PK
I
≥
LOAD(MIN)
ꢀꢁ
100 • V
OUT
ꢈꢔꢒꢍ ꢄꢇꢒꢄꢐ
ꢕꢒꢈꢄꢎꢕꢋꢍ
ꢁ
ꢄꢅꢆꢇꢈ
I
is the peak primary current at maximum power deliv-
ꢉꢊꢇꢋꢌ
PK
ꢍꢈꢎꢏꢏꢐꢅꢑ
ery. The LT3751 will enter no-load operation if the mini-
mum load current is not met. No-load operation will pre-
vent the application from entering a runaway condition;
however, the output voltage will increase 10% over the
nominal regulated voltage.
ꢀꢁ
ꢇ
ꢓꢅꢇ
3751 ꢂ1ꢃ
Figure 11. Effects of RC Snubber
3751fd
21
For more information www.linear.com/LT3751
LT3751
APPLICATIONS INFORMATION
Large Signal Stability
Small Signal Stability
The LT3751’s error amplifier is internally compensated to
increase its operating range but requires the converter’s
output node to be the dominant pole. Small signal stability
constraints become more prevalent during heavy load-
ing conditions where the dominant output pole moves
to higher frequency and closer to the internal feedback
poles and zeros. The feedback loop requires the output
pole frequency to remain below 200Hz to guarantee small
signal stability. This allows smaller RLOAD values than the
large signal constraint. Thus, small signal issues should
not arise if the large signal constraint is met.
Large signal stability can be an issue when audible noise
is a concern. Figure 12 shows that the problem originates
from the one-shot clock and the output voltage ripple.
The load must be constrained such that the output volt-
age ripple does not exceed the regulation range of the
error amplifier within one clock period (approximately
6mV referred to the FB pin).
The output capacitance should be increased if oscillations
occur or audible noise is present. Use Figure 13 to deter-
mine the maximum load for a given output capacitance to
maintain low audible noise operation. A small capacitor
can also be added from the FB pin to ground to lower the
ripple injected into FB pin.
Board Layout
The high voltage operation of the LT3751 demands care-
ful attention to the board layout, observing the following
points:
ꢏꢁꢔꢕ
ꢕꢓꢁꢁꢒ
ꢀ
ꢁꢂꢃ
1. Minimize the area of the high voltage end of the sec-
ondary winding.
ꢑ
ꢒꢓꢑ
2. Provide sufficient spacing for all high voltage nodes
(NMOS drain, VOUT and secondary winding of the
transformer) in order to meet the breakdown voltage
requirements.
ꢅꢆꢇꢈꢉ
ꢁꢊꢋꢌꢍꢈꢁꢃ
ꢎꢏꢐ
3751 ꢄ13
3. Keep the electrical path formed by CVTRANS, the primary
of T1, and the drain of the NMOS as short as possible.
Increasing the length of this path effectively increases
the leakage inductance of T1, potentially resulting in an
overvoltage condition on the drain of the NMOS.
Figure 12. Voltage Ripple Stability Constraint
3ꢉ
ꢑ5
ꢑꢉ
15
1ꢉ
5
ꢓ
ꢓ
ꢓ
ꢔ 15ꢉꢓ
ꢔ 3ꢉꢉꢓ
ꢔ ꢕꢉꢉꢓ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
4. Reduce the total node capacitance on the RV
and
OUT
R
pins by removing any ground or power planes
DCM
underneath the RDCM and RVOUT pads and traces.
Parasitic capacitance can cause unwanted behavior
on these pins.
5. Thermal vias should be added underneath the Exposed
Pad, Pin 21, to enhance the LT3751’s thermal perfor-
mance. These vias should go directly to a large area of
ground plane.
ꢉ
ꢉ
5ꢉ
1ꢉꢉ
15ꢉ
ꢑꢉꢉ
ꢀꢁꢂꢃꢁꢂ ꢃꢀꢄꢅꢆ ꢇꢄꢈ
3751 ꢐ1ꢒ
6. Isolated applications require galvanic separation of the
output-side ground and primary-side ground. Adequate
spacing between both ground planes is needed to meet
voltage safety requirements.
Figure 13. COUT(MIN) vs Output Power
3751fd
22
For more information www.linear.com/LT3751
LT3751
APPLICATIONS INFORMATION
ꢛ
ꢈ ꢌ ꢄ ꢊ ꢇ ꢎ ꢆ ꢅ
ꢉ ꢅ ꢒ ꢖ ꢆ ꢅ
ꢛ
3751fd
23
For more information www.linear.com/LT3751
LT3751
APPLICATIONS INFORMATION
ꢘ
ꢉ ꢍ ꢅ ꢋ ꢈ ꢏ ꢇ ꢆ
ꢘ
ꢊ ꢆ ꢙ ꢓ ꢇ ꢆ
3751fd
24
For more information www.linear.com/LT3751
LT3751
TYPICAL APPLICATIONS
42A Capacitor Charger
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
T1**
1:10
D1 D2***
V
V
* M1, M2 REQUIRES PROPER
OUT
500V
TRANS
12V TO 24V
+
HEATSINK/THERMAL DISSIPATION
C2
R6
C3
TO MEET MANUFACTURER’S SPECIFICATIONS
10µF
•
40.2k
1000µF
×3
+
C4
1200µF
** THERMAL DISSIPATION OF T1 WILL LIMIT
THE CHARGE/DISCHARGE DUTY CYCLE OF C4
RV
CHARGE
CLAMP
TRANS
•
R7, 18.2k
R8, 40.2k
OFF ON
RDCM
***D2 MAY BE OMITTED FOR OUTPUT
VOLTAGE OPERATION BELOW 300V
V
CC
V
LT3751
CC
4.7nF
Y-RATED
12V TO 24V
RV
C1
10µF
OUT
R10, 100k
DONE
R11, 100k
R1, 191k
HVGATE
LVGATE
CSP
M1, M2*
V
FAULT
UVLO1
OVLO1
UVLO2
CC
C1: 25V X5R OR X7R CERAMIC CAPACITOR
C2: 25V X5R OR X7R CERAMIC CAPACITOR
R5
2.5mΩ
C3: 25V ELECTROLYTIC
V
TRANS
R2, 475k
R3, 191k
C4: HITACHI FX22L122Y 1200µF, 550V ELECTROLYTIC
OR: CORNELL DUBILIER DCMC192T550CE2B 1900µF, 550V ELECTROLYTIC
D1, D2: VISHAY GURB5H60 600V, 5A ULTRAFAST RECTIFIER
M1, M2: 2 PARALLEL VISHAY SUP33N20-60P 200V, 33A NMOS
R1 THRU R4, R6 THRU R11: USE 1% 0805 RESISTORS
R5: USE 2 PARALLEL 5mΩ IRC LR SERIES 2512 RESISTORS
T1: COILCRAFT GA3460-BL 50A SURACE MOUNT TRANSFORMER
CSN
FB
V
CC
R4, 475k
OVLO2
GND RBG
3751 TA02
R9
787Ω
FOR ANY V
VOLTAGE BETWEEN
OUT
50V AND 500V SELECT R9 ACCORDING TO:
⎛
⎞
40.2kΩ
+ V
R9 = 0.98 • N • ⎜
⎟
⎜
⎟
V
⎝
⎠
OUT
DIODE
Efficiency
Output Capacitor Charge Times
Charging Waveform
ꢒ5
ꢒꢋ
75
7ꢋ
ꢓ5
1ꢍꢎꢎ
ꢕꢎꢎ
ꢖꢎꢎ
ꢎ
ꢙ
ꢙ
ꢙ
ꢙ
ꢙ
ꢙ
ꢙ
ꢙ
ꢚ 5ꢎꢎꢙꢛ ꢙ
ꢚ 5ꢎꢎꢙꢛ ꢙ
ꢚ 3ꢎꢎꢙꢛ ꢙ
ꢚ 3ꢎꢎꢙꢛ ꢙ
ꢚ 1ꢎꢎꢙꢛ
ꢚ ꢍꢖꢙ
ꢚ 1ꢍꢙ
ꢚ ꢍꢖꢙ
ꢚ 1ꢍꢙ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢂꢐꢅꢇꢜ
ꢂꢐꢅꢇꢜ
ꢂꢐꢅꢇꢜ
ꢂꢐꢅꢇꢜ
ꢆ
ꢆ
ꢌ 5ꢀꢀꢆ
ꢇꢍꢈꢎꢏ
ꢑꢐ ꢌ 1ꢉꢀꢀꢒꢓ
ꢊꢋꢇ
ꢌ ꢉꢐꢆ
ꢀꢁꢂ
ꢚ ꢍꢖꢙ
ꢂꢐꢅꢇꢜ
ꢚ 1ꢎꢎꢙꢛ
ꢀꢁꢂ
ꢚ 1ꢍꢙ
ꢂꢐꢅꢇꢜ
ꢆ
ꢊꢋꢇ
1ꢀꢀꢆꢃꢄꢅꢆ
ꢈꢆꢔꢍꢈꢕꢔ
ꢅꢎꢖꢋꢇ
ꢑꢋꢍꢍꢔꢎꢇ
5ꢈꢃꢄꢅꢆ
ꢄ
ꢄ
ꢙ 1ꢕꢄ
ꢙ ꢕꢔꢄ
ꢂꢗꢆꢏꢘ
ꢂꢗꢆꢏꢘ
3751 ꢇꢈꢀꢉd
5ꢋ
15ꢋ
ꢕ5ꢋ
35ꢋ
ꢔ5ꢋ
ꢍꢎꢎ
ꢖꢎꢎ
ꢘꢎꢎ
ꢕꢎꢎ
1ꢎꢎꢎ
1ꢍꢎꢎ
1ꢀꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢂꢆꢇꢈ ꢉꢄꢊ
ꢀꢁꢂꢃꢁꢂ ꢄꢅꢃꢅꢄꢆꢂꢅꢇꢄꢈ ꢉꢊꢋꢌ
3751 ꢂꢆꢋꢕꢖ
3751 ꢂꢅꢎꢍꢗ
3751fd
25
For more information www.linear.com/LT3751
LT3751
TYPICAL APPLICATIONS
High Voltage Regulator
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
T1*
D1
1:10
V
V
OUT
TRANS
100V TO 500V
5V TO 24V
+
C2
C3
C5
0.47µF
R6
•
5× 2.2µF
680µF
40.2k
* M1 AND T1 REQUIRE PROPER
+
C4***
100µF
HEATSINK/THERMAL DISSIPATION
•
TO MEET MANUFACTURER’S SPECIFICATIONS
RV
TRANS
R7, 18.2k
R8, 40.2k
OFF ON
CHARGE
CLAMP
RDCM
** DEPENDING ON DESIRED OUTPUT VOLTAGES,
R10 MUST BE SPLIT INTO MULTIPLE RESISTORS,
TO MEET MANUFACTURER’S VOLTAGE SPECIFICATION.
LT3751
V
CC
V
RV
OUT
CC
5V TO 24V
C1
10µF
***C4 MUST BE SIZED TO MEET LARGE SIGNAL
STABILITY CRITERIA DESCRIBED IN THE
APPLICATIONS INFORMATION SECTION
DONE
TO
MICRO
HVGATE
LVGATE
CSP
M1*
V
FAULT
UVLO1
OVLO1
UVLO2
OVLO2
CC
R1, 69.8k
R5
6mΩ
C1: 25V X5R OR X7R CERAMIC
C2: 25V X5R OR X7R CERAMIC
C3: 25V ELECTROLYTIC
C5: TDK CKG57NX7R2J474M
D1: VISHAY US1M 1000V
M1: FAIRCHILD FQP34N20L
R1 THRU R4, R6 THRU R9, R11: USE 1% 0805
R5: IRC LR SERIES 2512 RESISTORS
R10: USE 200V 1206 RESISTOR(S)
T1: COILCRAFT GA3459-AL
V
TRANS
R2, 475k
R3, 69.8k
CSN
FB
R10**
R11
V
CC
R4, 475k
C6
10nF
GND RBG
3751 TA04
R9
Suggested Component Values
Steady-State Operation with
1.1mA Load Current
I
(mA)
= 5V,
I
(mA)
OUT(MAX)
OUT(MAX)
V
AT V
AT V = 24V,
TRANS
R9
R11
R10
OUT
TRANS
ꢆ
ꢍꢎꢇ
(V)
100
200
300
400
5% V
DEFLECTION 5% V
DEFLECTION
(kΩ)
(kΩ)
(kΩ)
OUT
OUT
ꢈꢏ ꢏꢍꢎꢌꢐꢑꢄ
ꢒꢆꢃꢄꢅꢆ
180
110
75
270
315
245
200
170
3.32
0.383
0.768
1.13
30.9
124
274
499
715
1.65
ꢆ
ꢄꢊꢈꢅꢋ
5ꢀꢆꢃꢄꢅꢆ
1.10
ꢅ
ꢌꢊꢅ
55
0.825
Tie to GND
1.54
1ꢀꢈꢃꢄꢅꢆ
†
500
40
1.74
3751 ꢇꢈꢀ3ꢉ
1ꢀꢁꢂꢃꢄꢅꢆ
†
Transformer primary inductance limits V
comparator operation to V
= 400V
. RV
MAX OUT
OUT
OUT
and R should be tied to ground when operating V
above 400V.
BG
OUT
Steady-State Operation with
100mA Load Current
Efficiency (VOUT = 500V)
Load Regulation (VOUT = 500V)
ꢏꢈ
515
51ꢈ
5ꢈ5
5ꢈꢈ
ꢏꢐ5
ꢆ
ꢕ
ꢘ ꢒꢙꢕ
ꢍꢎꢇ
ꢓꢖꢃꢌꢗ
ꢏꢍꢎꢌꢐꢑꢄ
ꢒꢆꢃꢄꢅꢆ
ꢐ5
ꢐꢈ
75
7ꢈ
ꢑ5
ꢑꢈ
ꢕ
ꢘ 1ꢒꢕ
ꢓꢖꢃꢌꢗ
ꢆ
ꢄꢊꢈꢅꢋ
5ꢀꢆꢃꢄꢅꢆ
ꢌ
ꢕ ꢑꢏꢌ
ꢊꢒꢃꢓꢔ
ꢅ
ꢌꢊꢅ
1ꢀꢈꢃꢄꢅꢆ
ꢕ
ꢘ 5ꢕ
ꢓꢖꢃꢌꢗ
ꢌ
ꢕ 1ꢑꢌ
ꢊꢒꢃꢓꢔ
3751 ꢇꢈꢀ3ꢉ
1ꢀꢁꢂꢃꢄꢅꢆ
ꢌ
ꢕ 5ꢌ
ꢀ
ꢊꢒꢃꢓꢔ
ꢈ
5ꢈ
1ꢈꢈ
ꢅꢆꢃꢇ
15ꢈ
ꢒꢈꢈ
ꢈ
5ꢈ
1ꢈꢈ
ꢅꢆꢃꢇ
15ꢈ
ꢑꢈꢈ
ꢀ
ꢁꢂꢃꢄ
ꢁꢂꢃꢄ
3751 ꢓꢃꢈ3ꢔ
3751 ꢊꢃꢈ3d
3751fd
26
For more information www.linear.com/LT3751
LT3751
TYPICAL APPLICATIONS
1.6A High Input Voltage, Isolated Capacitor Charger
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
T1*
1:3
V
F1, 1A
D1 D2
TRANS
V
* T1 REQUIRES PROPER THERMAL MANAGEMENT
TO ACHIEVE DESIRED OUTPUT POWER LEVELS
OUT
100V TO
400VDC
50V TO 500V
+
R6
C2
2.2µF
×5
C3
•
+
625k
47µF
C4
220µF
** M1 REQUIRES PROPER HEAT SINK/THERMAL
DISSIPATION TO MEET MANUFACTURER’S
SPECIFICATIONS
R7, 96.2k
•
R8
RV
417k
TRANS
C5
0.47µF
FOR ANY OUTPUT VOLTAGE BETWEEN 50V
TO 500V, SET R12 GIVEN BY:
OFF ON
RDCM
CHARGE
CLAMP
R9
67.3k
LT3751
0.98
R10
208k
V
CC
R12 =
V
CC
V
4.7nF
Y-RATED
10V TO 24V
OUT,TRIP
C1
10µF
+ 40µA • 2
RV
OUT
TO
MICRO
DONE
3 • R10
R11
32.1k
R5
20Ω
C1: 25V X5R OR X7R CERAMIC
FAULT
UVLO1
OVLO1
UVLO2
OVLO2
C2: 630V X5R OR X7R CERAMIC
C3: 450V ILLINOIS CAP 476CKE450MQW
C4: 50V TO 500V ELECTROLYTIC
C5: TDK CKG57NX7R2J474M
R1, 1.5M
HVGATE
LVGATE
FB
M1**
R13
V
CC
V
TRANS
R2, 9M
D1, D2: VISHAY US1M 1000V
R3, 154k
CSP
F1: BUSSMANN PCB-1-R
M1: FAIRCHILD FQB4N80
V
CC
68mΩ
R4, 475k
R1, R2: 2 X 1206 RESISTORS IN SERIES, 1%
R3 THRU R5, R9, R12: 0805 RESISTORS, 1%
R6, R10: 3 X 1206 RESISTORS IN SERIES, 0.1%
R7, R11: 0805 RESISTORS, 0.1%
R8: 3 X 1206 RESISTORS IN SERIES, 1%
R13: IRC LR SERIES 1206 RESISTOR, 1%
T1: COILCRAFT HA4060-AL
CSN
GND RBG
3751 TA04a
R12
Output Trip Voltage
and Charge Time
(VOUT = 500V, COUT = 220µF)
Efficiency
Charging Waveform
53ꢍ
5ꢐꢍ
1ꢍꢍꢍ
ꢓ5ꢍ
1ꢋꢋ
ꢓ5
ꢆ
ꢆ
ꢆ
ꢌ 5ꢀꢀꢆ
ꢌ 3ꢀꢀꢆ
ꢌ 1ꢐꢆ
ꢊꢋꢇ
ꢇꢍꢈꢎꢏ
ꢊꢋꢇ
ꢄ
ꢍꢏ
ꢘ 1ꢋꢋꢄ
ꢓꢋ
ꢄ
ꢄ
ꢘ ꢔ5ꢋꢄ
ꢘ ꢕꢋꢋꢄ
ꢍꢏ
ꢍꢏ
ꢅ
ꢆꢃꢄꢎꢄꢏꢀꢂ
ꢒ5
ꢒꢋ
75
7ꢋ
51ꢍ
7ꢍꢍ
ꢆ
ꢊꢋꢇ
1ꢀꢀꢆꢃꢄꢅꢆ
ꢈꢆꢑꢍꢈꢒꢑ
ꢅꢎꢓꢋꢇ
ꢔꢋꢍꢍꢑꢎꢇ
ꢐꢀꢀꢁꢈꢃꢄꢅꢆ
ꢕꢖꢈꢏꢉꢊ ꢄꢀꢗꢊ
5ꢍꢍ
ꢑꢒꢍ
55ꢍ
ꢑꢍꢍ
ꢔꢕꢈꢍꢒꢑ
1ꢀꢆꢃꢄꢅꢆ
ꢖ5
3751 ꢇꢈꢀꢉd
3ꢍꢍ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢑꢍꢍ
ꢔ5ꢋ
35ꢋ
ꢕ5ꢋ
1ꢍꢍ
ꢐꢍꢍ
5ꢋ
15ꢋ
1ꢀꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢂꢆꢇꢈ ꢉꢄꢊ
3751 ꢄꢈꢍꢑꢔ
3751 ꢂꢆꢋꢕꢗ
3751fd
27
For more information www.linear.com/LT3751
LT3751
TYPICAL APPLICATIONS
High Input Voltage, High Output Voltage Regulator
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
V
T1*
1:3
OUT
V
F1, 1A
D1 D2
TRANS
100V TO 500V
100V TO
400VDC
* T1 REQUIRES PROPER THERMAL MANAGEMENT
TO ACHIEVE DESIRED OUTPUT POWER LEVELS
+
C2
2.2µF
×5
C3
R6, 625k
R7, 97.6k
+
•
47µF
C4
** M1 REQUIRES PROPER HEAT SINK/THERMAL
DISSIPATION TO MEET MANUFACTURER’S
SPECIFICATIONS
100µF
•
RV
TRANS
R8, 417k
C5
OFF ON
CHARGE
CLAMP
RDCM
0.47µF
***DEPENDING ON DESIRED OUTPUT VOLTAGE,
R10 MUST BE SPLIT INTO MULTIPLE RESISTORS
TO MEET MANUFACTURER’S VOLTAGE SPECIFICATION
R9
67.3k
V
CC
LT3751
10V TO
V
RV
OUT
CC
24V
C1
10µF
DONE
R5, 20Ω
TO
MICRO
C1: 25V X5R OR X7R CERAMIC
HVGATE
LVGATE
CSP
M1**
R12
C2: 630V X5R OR X7R CERAMIC
C3: 450V ILLINOIS CAP 476CKE450MQW
C4: 50V TO 500V ELECTROLYTIC
C5: TDK CKG57NX7R2J474M
V
FAULT
UVLO1
OVLO1
UVLO2
OVLO2
CC
R1, 1.5M
V
TRANS
68mΩ
C6: 6.3V X5R OR X7R CERAMIC
D1, D2: VISHAY US1M 1000V
F1: BUSSMANN PCB-1-R
M1: FAIRCHILD FQB4N80
R2, 9M
CSN
FB
R10***
R11
R3, 154k
V
CC
R4, 475k
R1, R2: 2 X 1206 RESISTORS IN SERIES, 1%
R3 THRU R5, R7, R9, R11: 0805 RESISTORS, 1%
R6, R8: 3 X 1206 RESISTORS IN SERIES, 1%
R10: 1206 RESISTOR(S), 1%
C6
10nF
GND RBG
3751 TA05a
R12: IRC LR SERIES 1206 RESISTOR, 1%
T1: COILCRAFT HA4060-AL
Suggested Component Values
I
(mA)
I
(mA)
OUT(MAX)
TRANS
OUT
OUT(MAX)
V
AT V
= 100V,
AT V = 400V,
TRANS
R10
R11
OUT
(V)
100
200
300
400
500
1% V
DEFLECTION 1% V
DEFLECTION
OUT
(kΩ)
(kΩ)
0.383
0.768
1.13
55
110
95
130
150
175
130
140
30.9
124
274
499
715
80
1.54
65
1.74
Steady-State Operation with
50mA Load Current
Efficiency
Line Regulation
ꢔꢌ
ꢓꢌ
7ꢌ
ꢒꢌ
5ꢌ
ꢍꢌ
3ꢎꢐ
3ꢎ7
3ꢎꢏ
3ꢎ5
ꢆ
ꢆ
ꢊ ꢋꢀꢀꢆ
ꢅꢉ
ꢌꢍꢇ
ꢗ
ꢗ
ꢘ 1ꢌꢌꢗ
ꢘ ꢕ5ꢌꢗ
ꢏꢇ
ꢏꢇ
ꢊ ꢎꢀꢀꢆ
ꢀ
ꢀ
ꢔ 1ꢍꢕꢈ
ꢆꢃꢄ
ꢆꢃꢄ
ꢆ
ꢄꢏꢈꢅꢉ
1ꢀꢀꢆꢃꢄꢅꢆ
ꢀ
ꢔ ꢑ5ꢕꢈ
ꢆꢃꢄ
ꢗ
ꢘ ꢍꢌꢌꢗ
ꢏꢇ
ꢔ 5ꢍꢕꢈ
ꢅ
ꢐꢏꢅ
ꢋꢈꢃꢄꢅꢆ
3751 ꢇꢈꢀ5d
ꢌ
5ꢌ
ꢀꢁꢂꢃꢁꢂ ꢄꢁꢅꢅꢆꢇꢂ ꢈꢉꢊꢋ
75
1ꢍꢍ
3ꢍꢍ
ꢑꢍꢍ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢓꢍꢍ
ꢕ5
1ꢀꢁꢂꢃꢄꢅꢆ
3751 ꢂꢊꢌ5ꢖ
3751 ꢄꢈꢍ5ꢒ
3751fd
28
For more information www.linear.com/LT3751
LT3751
TYPICAL APPLICATIONS
Isolated 282V Voltage Regulator
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
D2
R2, 10Ω
ISOLATION BOUNDARY
T1
•
•
Npb
V
TRANS
D5
V
F1, 2A
TRANS
V
OUT
100V TO
200VDC
282V
+
C4
1µF
×2
R1
49.9k
C3
R3
225mA
•
+
22µF
210k
C6
0.1µF
C7
400µF
Np
Ns
M1
D3
×2
R4
RV
CHARGE
CLAMP
105k
TRANS
OFF ON
RDCM
C1
100pF
R5
210k
R16
249k
D4
LT3751
V
RV
OUT
CC
Nsb
R15
5.11Ω
C1, C8: 16V COG CERAMIC
C2
U2
D1
DONE
HVGATE
LVGATE
CSP
M2
TO
•
R17
221k
D6
C2: 16V X5R OR X74 CERAMIC
C3: 350V ELECTROLYTIC
1µF
MICRO
C5
0.01µF
V
COMP
IN
C8
FAULT
UVLO1
OVLO1
UVLO2
OVLO2
V
CC
C4: 250V X5R OR X7R CERAMIC
22nF
R9, 2.7M
C5, C6, C11, C12: 630V X5R OR X7R CERAMIC
C7: 350V ELECTROLYTIC
C9
3.3µF
LT4430
R19
3.16k
V
TRANS
R10, 4.3M
R11, 84.5k
C9, C10: 25V X5R OR X7R CERAMIC
F1: 250V, 2A FUSE
R1: 2010 RESISTOR, 1%
R6
40mΩ
GND
FB
C10
0.47µF
R18
1k
CSN
FB
R2, R3, R6, R16, R17: 1206 RESISTORS, 1%
R4, R5: TWO 1206 RESISTORS IN SERIES, 1%
R7 THRU R12, R15 THRU R20: 0805 RESISTORS, 1%
D1: 12V ZENER
V
CC
R12, 442k
OC
D7
U1
V
CC
R7
475Ω
OPTO
GND RBG
R20
274Ω
D2: VISHAY MURS140
R8 3751 TA06a
2.49k
D3: VISHAY P6KE200A
D4: VISHAY MURS160
D5: STMICROELECTRONICS STTH112A
D6: VISHAY BAT54
T1: TDK SRW24LQ
D7: NXP SEMICONDUCTORS BAS516
M1: VISHAY IRF830
(Np:Ns:Npb:Nsb = 1:2:0.08:0.08)
U1: NEC PS2801-1
4.7nF
Y RATED
M2: STMICROELECTRONICS STB11NM60FD U2: LINEAR TECHNOLOGY LT4430
Steady-State Operation with
7.1mA Load Current
Load Regulation
Efficiency
1ꢀꢀ
ꢊ5
ꢊꢀ
ꢋ5
ꢋꢀ
75
7ꢀ
ꢈꢊ5ꢈ
ꢈꢊꢑ5
ꢈ
ꢏ3ꢘ ꢕꢓꢍꢒꢓꢍ
ꢌꢋꢘ ꢕꢓꢍꢒꢓꢍ
ꢑ5ꢘ ꢕꢓꢍꢒꢓꢍ
ꢇ
ꢅꢌꢉꢆꢏ
1ꢁꢁꢇꢄꢅꢆꢇ
ꢆ
ꢋꢌꢆꢍꢉꢌꢎ
ꢀꢉꢄꢅꢆꢇ
3751 ꢈꢉꢁꢊd
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢉꢈꢊꢑ5
ꢉꢈꢊ5ꢈ
Steady-State Operation with
225mA Load Current
1ꢀꢀ
1ꢑꢀ
1ꢌꢀ
1ꢏꢀ
1ꢋꢀ
ꢑꢀꢀ
ꢈ
5ꢈ
1ꢈꢈ
15ꢈ
ꢄꢅꢆꢇ
ꢑꢈꢈ
ꢑ5ꢈ
ꢃꢅꢒꢓꢍ ꢔꢕꢖꢍꢎꢗꢁ ꢇꢔꢉ
ꢀ
ꢁꢂꢃ
3751 ꢍꢎꢀꢏꢐ
3751 ꢃꢆꢈꢒꢓ
ꢇ
ꢅꢍꢉꢆꢐ
1ꢁꢁꢇꢄꢅꢆꢇ
ꢆ
ꢌꢍꢆꢎꢉꢍꢏ
ꢀꢉꢄꢅꢆꢇ
3751 ꢈꢉꢁꢊꢋ
ꢀꢁꢂꢃꢄꢅꢆꢇ
3751fd
29
For more information www.linear.com/LT3751
LT3751
TYPICAL APPLICATIONS
Wide Input Voltage Range, 15 Watt, Triple Output Voltage Regulator
T1
2:1:3:3
(P1:S1:S2:S3)
D1
V
V
OUT3
IN
5V TO 24V
+15V
+
+
C2
1000µF
×2
R5
C3
10µF
C7
R12
C4
•
25.5k
10µF
4.99k
470µF
S3
S2
S1
RV
CHARGE
CLAMP
TRANS
OFF ON
D2
R6
V
OUT2
11.5k
–15V
V
RDCM
C5
470µF
C8
10µF
CC
R13
4.99k
C1
10µF
+
+
P1
R7
25.5k
LT3751
R1, 100k
•
•
•
RV
DONE
OUT
D3
R2, 100k
R3, 66.5k
R4, 464k
V
M1
OUT1
FAULT
UVLO1
OVLO1
+5V
C6
100µF
×2
C9
100µF
HVGATE
LVGATE
CSP
C1, C3: 25V X5R OR X7R CERAMIC
V
CC
C2: 25V SANYO 25ME1000AX
C4, C5: 35V SANYO 35ME470AX
R11
25mΩ
C6: 10V KEMET T520D107M010ASE055
C7, C8: 16V CERAMIC, TDK C4532X7R1E106M
C9: 6.3V CERAMIC, TDK C4532X5R0J107M
D1, D2: CENTRAL SEMI CMSH2-60M
D3: CENTRAL SEM1 CMSH5-40
R9
309Ω
CSN
FB
UVLO2
OVLO2
GND RBG
R10
100Ω
M1: FAIRCHILD FQD12N20L
R8
2.21k
R1 THRU R10, R12, R13: 0805 RESISTOR, 1%
R11: 1206 RESISTOR, 1%
T1: COILCRAFT HA3994-AL, 2:1:3:3 (P1:S1:S2:S3)
3751 TA07a
Maximum Output Conditions
I
*
OUT(MAX) (mA)
V
P
OUT(MAX)
CC
(V)
(W)
V
OUT1
V
V
OUT3
OUT2
5
6.5
10
13
750
300
300
300
300
300
300
12
24
1750
2500
*All other output currents set to 0mA
Cross Regulation
(IVOUT1 = 100mA)
Cross Regulation
(IVOUT1 = 500mA)
Efficiency
(IVOUT1 = 500mA)
ꢆꢐ
ꢆꢍ
ꢆꢆ
ꢆꢎ
1ꢏ
1ꢐ
1ꢍ
ꢖꢌ
ꢓ5
ꢓꢌ
75
7ꢌ
ꢕ5
ꢕꢌ
ꢆꢐ
1ꢍ
1ꢎ
1ꢏ
ꢂ
ꢗ ꢆꢔꢂ
ꢁꢐ
ꢂ
ꢁꢒ
ꢓ 5ꢂ
ꢂ
ꢗ 1ꢆꢂ
ꢁꢐ
ꢂ
ꢁꢒ
ꢓ ꢆꢏꢂ
ꢂ
ꢁꢒ
ꢓ ꢆꢍꢂ
ꢂ
ꢁꢒ
ꢓ 5ꢂ
ꢂ
ꢁꢒ
ꢓ 1ꢆꢂ
ꢂ
ꢁꢒ
ꢓ 1ꢆꢂ
ꢂ
ꢁꢐ
ꢗ 5ꢂ
1
1ꢎ
1ꢎꢎ
1ꢎꢎꢎ
ꢌ
ꢆꢌꢌ
ꢀꢁ
ꢔꢌꢌ
ꢇ ꢁ
ꢕꢌꢌ
ꢓꢌꢌ
1
1ꢐ
1ꢐꢐ
1ꢐꢐꢐ
ꢀꢁ
ꢇ ꢁ
ꢈꢈ ꢉꢊꢋꢌ
ꢈꢉꢊꢋ
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ꢇ ꢁ
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3751fd
30
For more information www.linear.com/LT3751
LT3751
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT3751#packaging for the most recent package drawings.
FE Package
20-Lead Plastic TSSOP (4.4mm)
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Exposed Pad Variation CB
DETAIL A
6.40 – 6.60*
3.86
(.152)
(.252 – .260)
0.60
(.024)
REF
3.86
(.152)
20 1918 17 16 15 14 1312 11
0.28
(.011)
REF
6.60 ±0.10
DETAIL A IS THE PART OF
THE LEAD FRAME FEATURE
FOR REFERENCE ONLY
2.74
(.108)
DETAIL A
4.50 ±0.10
6.40
(.252)
BSC
2.74
(.108)
SEE NOTE 4
NO MEASUREMENT PURPOSE
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
0.195 – 0.30
FE20 (CB) TSSOP REV L 0117
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
3751fd
31
For more information www.linear.com/LT3751
LT3751
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT3751#packaging for the most recent package drawings.
UFD Package
20-Pin Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1711 Rev B)
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3751fd
32
For more information www.linear.com/LT3751
LT3751
REVISION HISTORY (Revision history begins at Rev B)
REV
DATE
DESCRIPTION
PAGE NUMBER
B
5/10
Updated FAULT (Pin 6/Pin 4) description in Pin Functions
Updated DONE (Pin 7/Pin 5) description in Pin Functions
Updated Block Diagram
7
8
9
Revised Applications Information section
Revised Typical Applications illustration
Revised Applications Information section
Corrected Schematic R8 value from 3.40k to 2.21k
Updated FE package drawing
17, 18
30
20
30
31
2
C
D
6/12
12/17 Revised Absolute Maximum storage temperature range upper limit from 125°C to 150°C.
3751fd
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
33
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
For more information www.linear.com/LT3751
LT3751
TYPICAL APPLICATION
300V Regulated Power Supply
T1
D1
1:10
V
V
TRANS
24V
OUT
300V
+
C2
C3
R6
40.2k
0mA TO 270mA
•
2.2µF
+
680µF
C4
20µF
×5
•
RV
CHARGE
TRANS
R7
18.2k
OFF ON
RDCM
RV
CLAMP
OUT
V
CC
V
CC
24V
C1
10µF
R8*
274k
M1
R5
HVGATE
LVGATE
CSP
DONE
FAULT
TO
V
CC
MICRO
R1
432k
UVLO1
OVLO1
UVLO2
OVLO2
* DEPENDING ON DESIRED OUTPUT
VOLTAGE, R8 MUST BE SPLIT
INTO MULTIPLE RESISTORS TO
MEET MANUFACTURER’S VOLTAGE
SPECIFICATION.
6mΩ
V
R2
TRANS
LT3751
475k
CSN
FB
R3
432k
C5
10nF
V
CC
R4
475k
R9
1.13k
GND RBG
3751 TA08
C1: 25V X5R OR X7R CERAMIC CAPACITOR
C2: 25V X5R OR X7R CERAMIC CAPACITOR
C3: 25V ELECTROLYTIC
C4: 330V RUBYCON PHOTOFLASH CAPACITOR
D1: VISHAY US1M 1000V
M1: FAIRCHILD FQP34N20L
R1 THROUGH R4: USE 1% 0805 RESISTORS
R5: IRC LR SERIES 2512 RESISTOR
T1: SUMIDA PS07-299, 20A TRANSFORMER
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
V : 2.75V to 5.5V, Charges Two Supercapacitors in Series to 4.8V or 5.3V
LTC3225
150mA Supercapacitor Charger
IN
LT3420/LT3420-1
1.4A/1A, Photoflash Capacitor Charger
with Automatic Top-Off
Charges 220µF to 320V in 3.7 Seconds from 5V, V : 2.2V to 16V, I < 1µA,
IN SD
10-Lead MS Package
LT3468/LT3468-1/
LT3468-2
1.4A, 1A, 0.7A, Photoflash Capacitor Charger V : 2.5V to 16V, Charge Time: 4.6 Seconds for LT3468 (0V to 320V, 100µF,
IN
V
= 3.6V), I < 1µA, ThinSOT Package
SD
IN
LT3484-0/LT3484-1/ 1.4A, 0.7A, 1A Photoflash Capacitor Charger
LT3484-2
V : 1.8V to 16V, Charge Time: 4.6 Seconds for LT3484-0 (0V to 320V, 100µF,
IN
IN
V
= 3.6V), I < 1µA, 2mm × 3mm 6-Lead DFN Package
SD
LT3485-0/LT3485-1/ 1.4A, 0.7A, 1A, 2A Photoflash Capacitor
V : 1.8V to 10V, Charge Time: 3.7 Seconds for LT3485-0 (0V to 320V, 100µF,
IN
V = 3.6V), I < 1µA, 3mm × 3mm 10-Lead DFN Package
IN SD
LT3485-2/LT3485-3
Charger with Output Voltage Monitor and
Integrated IGBT
LT3585-0/LT3585-1/ 1.2A, 0.55A, 0.85A, 1.7A Photoflash
V : 1.5V to 16V, Charge Time: 3.3 Seconds for LT3585-3 (0V to 320V, 100µF,
IN
V = 3.6V), I < 1µA, 3mm × 2mm DFN-10 Package
IN SD
LT3585-2/LT3585-3
Capacitor Charger with Adjustable Input
Current and IGBT Drivers
LT3750
Capacitor Charger Controller
V : 3V to 24V, Charge Time: 300ms for (0V to 300V, 100µF) MSOP-10 Package
IN
3751fd
LT 1217 REV D • PRINTED IN USA
www.linear.com/LT3751
34
ANALOG DEVICES, INC. 2017
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