LT5512EUF#TR [Linear]
LT5512 - 1kHz-3GHz High Signal Level Active Mixer; Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C;型号: | LT5512EUF#TR |
厂家: | Linear |
描述: | LT5512 - 1kHz-3GHz High Signal Level Active Mixer; Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C 电信 电信集成电路 |
文件: | 总12页 (文件大小:259K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Final Electrical Specifications
LT5512
DC-3GHz High Signal Level
Down-Converting Mixer
July 2002
U
DESCRIPTIO
FEATURES
The LT®5512 is a broadband mixer IC optimized for high
linearity downconverter applications including cable and
wireless infrastructure. The IC includes a differential LO
buffer amplifier driving a double-balanced mixer. An inte-
grated RF buffer amplifier improves LO-RF isolation and
eliminates the need for precision external bias resistors.
■
Broadband RF, LO and IF Operation
High Input IP3: +20dBm at 950MHz
■
+17dBm at 1900MHz
■
Typical Conversion Gain: 1dB at 1900MHz
■
SSB Noise Figure: 14dB at 1900MHz
■
Integrated LO Buffer: Insensitive to LO Drive Level
Single-Ended or Differential LO Signal
High LO-RF Isolation
Enable Function
4.5V to 5.25V Supply Voltage Range
4mm × 4mm QFN Package
■
The LT5512 is a high-linearity alternative to passive diode
mixers. Unlike passive mixers, which have conversion
loss and require high LO drive levels, the LT5512 delivers
conversion gain and requires significantly lower LO drive
levels.
■
■
■
■
U
APPLICATIO S
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Cellular/PCS/UMTS Infrastructure
■
CATV Downlink Infrastructure
■
High Linearity Mixer Applications
U
TYPICAL APPLICATIO
5V
Output IF Power and Output IM3 vs
RF Input Power (Two Input Tones)
1850MHz
TO
1910MHz
1850MHz
TO
1910MHz
EN
+
V
V
CC2
CC1
1:2
IF
VGA
10
0
170MHz
(TYP)
RF
LNA
+
IF
IF
A/D
IF
OUT
–10
–20
–30
–40
–50
–60
–70
–80
–
–
RF
IM3
+
–
LO
LO
T
= 25°C
A
LO
P
= –10dBm
= 1730MHz
= 1899.9MHz
f
f
f
LO
RF1
RF2
LO
INPUT
= 1900.1MHz
5512 F01a
–10dBm
–21 –18 –15 –12 –9 –6 –3
0
3
6
RF INPUT POWER (dBm/TONE)
5512 F01b
Figure 1. High Signal-Level Downmixer for Wireless Infastructure
5512i
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
1
LT5512
W W U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
ORDER PART
TOP VIEW
Supply Voltage ....................................................... 5.5V
Enable Voltage ............................... –0.3V to VCC + 0.3V
LO+ to LO– Differential Voltage ............................ ±1.5V
................................................... (+6dBm equivalent)
RF+ to RF– Differential Voltage ............................. ±0.7V
..................................................(+10dBm equivalent)
Operating Temperature Range .................–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
NUMBER
16 15 14 13
LT5512EUF
NC
+
1
2
3
4
12 GND
+
RF
11 IF
–
–
RF
NC
IF
10
9
GND
5
6
7
8
PART MARKING
5512
UF PACKAGE
16-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 37°C/W
EXPOSED PAD IS GROUND
(MUST BE SOLDERED TO
PRINTED CIRCUIT BOARD)
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
2
2
RF Input Frequency Range
Requires Appropriate Matching
Requires Appropriate Matching
Requires Appropriate Matching
DC to 3000
DC to 3000
DC to 2000
LO Input Frequency Range
IF Output Frequency Range
MHz
2
MHz
1900MHz Downmixer Application: (Test Circuit Shown in Figure 2) VCC = 5VDC, EN = High, TA = 25°C, RF input = 1900MHz at –10dBm,
LO input = 1730MHz at –10dBm, IF output measured at 170MHz, unless otherwise noted. (Notes 2, 3)
LO Input Power
–15 to –5
dBm
dB
Conversion Gain
–1
1
17
Input 3rd Order Intercept
LO to RF Leakage
2-Tone, –10dBm/Tone, ∆f = 200kHz
dBm
dBm
dBm
dB
–53
–46
50
LO to IF Leakage
RF to LO Isolation
Output 1dB Compression
LO Input Common Mode Voltage
Single-Sideband Noise Figure
6.2
2
dBm
Internally Biased
V
DC
14
dB
5512i
2
LT5512
1230MHz Cable Infrastructure Downmixer Application: (Test Circuit Shown
ELECTRICAL CHARACTERISTICS
in Figure 3) VCC = 5VDC, EN = High, TA = 25°C, RF input = 1230MHz at –10dBm, LO input swept from 1500MHz to 2100MHz,
PLO = –10dBm, IF output measured from 270MHz to 870MHz, unless otherwise noted.
PARAMETER
CONDITIONS
= 1800MHz, f = 570MHz
MIN
TYP
2.8
MAX
UNITS
dB
Conversion Gain
f
LO
IF
Input 3rd Order Intercept
2-Tone RF Input, –10dBm/Tone, ∆f = 1MHz,
17.9
dBm
f
= 1800MHz, f = 570MHz
LO
IF
LO to RF Leakage
–56
–40
51
dBm
dBm
dB
LO to IF Leakage
RF to LO Isolation
2 • RF – LO Output Spur
Single-Sideband Noise Figure
f
f
= 570MHz, P = –18dBm, f = 1800MHz
–60
13.3
dBc
dB
IF
RF
LO
= 1800MHz, f = 570MHz
LO
IF
DC ELECTRICAL CHARACTERISTICS
(Test Circuit Shown in Figure 2) VCC = 5VDC, EN = High, TA = 25°C
(Note 3), unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Enable (EN) Low = Off, High = On
Turn On Time
3
µs
µs
µA
Turn Off Time
13
50
Input Current
V
= 5V
ENABLE DC
Enable = High (On)
Enable = Low (Off)
3
V
DC
V
DC
0.3
Power Supply Requirements (V
Supply Voltage
)
CC
4.50
5.25
74
V
DC
Supply Current
57
mA
Shutdown Current
EN = Low
100
µA
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: External components on the final test circuit are optimized for
Note 3: Specifications over the –40°C to 85°C temperature range are
assured by design, characterization and correlation with statistical process
controls.
operation at f = 1900MHz, f = 1730MHz and f = 170MHz (Figure 2).
RF
LO
IF
U W
(Test Circuit Shown in Figure 2)
TYPICAL PERFOR A CE CHARACTERISTICS
Shutdown Current vs Supply Voltage
Supply Current vs Supply Voltage
59
100
10
1
58
T
A
= 85°C
57
56
55
54
53
52
51
50
49
T
A
= 85°C
T
= 25°C
A
T
A
= 25°C
T
A
= –40°C
T
= –40°C
A
0.1
4.5
4.75
5.0
5.25
5.5
4.5
5.0
5.25
5.5
4.75
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
5512 G02
5512 G01
5512i
3
LT5512
U W
TYPICAL PERFOR A CE CHARACTERISTICS
(1900MHz Downmixer Application)
VCC = 5VDC, EN = High, TA = 25°C, 1900MHz RF input matching, RF input = 1900MHz at –10dBm, LO input = 1730MHz at –10dBm, IF
output measured at 170MHz, unless otherwise noted. (Test circuit shown in Figure 2).
Conv Gain and IIP3 vs Temperature
RF = 1900MHz, IF = 170MHz
Conv Gain, IIP3 and SSB NF vs
RF Frequency (Low-Side LO)
Conv Gain, IIP3 and SSB NF vs
RF Frequency (High-Side LO)
18
16
14
12
10
8
20
18
16
14
12
10
8
18
16
14
12
10
8
IIP3
IIP3
IIP3
LOW-SIDE LO
SSB NF
SSB NF
HIGH-SIDE LO
f
= 170MHz
= 25°C
IF
A
T
f
= 170MHz
= 25°C
IF
A
T
6
6
6
CONV GAIN
4
4
4
CONV GAIN
1900
HIGH-SIDE LO
LOW-SIDE LO
2
CONV GAIN
1900
2
2
0
0
0
1700
1800
2000
2100
–50
–25
0
25
50
75
100
1700
2000
2100
1800
RF FREQUENCY (MHz)
TEMPERATURE (°C)
RF FREQUENCY (MHz)
5512 • G04
5512 • G05
5512 • G03
LO-IF and LO-RF Leakage vs
LO Input Power
Conv Gain and IIP3 vs
LO Input Power
SSB Noise Figure vs
LO Input Power
20
18
16
14
12
10
8
16.0
15.5
15.0
14.5
14.0
13.5
13.0
12.5
12.0
–20
–25
–30
–35
–40
–45
–50
–55
–60
f
f
= 1900MHz
= 170MHz
= 25°C
f
= 1730MHz
= 25°C
RF
IF
A
LO
A
T
A
= 25°C
T
T
T
= –40°C
A
IIP3
T
= 85°C
A
HIGH-SIDE LO
LO-IF
LOW-SIDE LO
6
CONV GAIN
T
= 85°C
A
T
A
= 25°C
4
LO-RF
T
= –40°C
A
2
0
–18 –16 –14 –12 –10 –8 –6 –4 –2
–18 –16 –14 –12 –10 –8 –6 –4 –2
–18 –16 –14 –12 –10 –8 –6 –4 –2
LO INPUT POWER (dBm)
LO INPUT POWER (dBm)
LO INPUT POWER (dBm)
5512 • G06
5512 • G07
5512 • G08
RF, LO and IF Port Return Loss
vs Frequency
Conv Gain and IIP3 vs
Supply Voltage
Output IF Power and Output IM3 vs
RF Input Power (Two Input Tones)
18
16
14
12
10
8
10
0
0
T
A
= –40°C
T
A
= 25°C
T
A
= –40°C
–5
–10
–15
–20
–25
–30
P
OUT
–10
–20
–30
–40
–50
–60
–70
–80
–90
T
= 85°C
A
T
A
= 85°C
LO
IIP3
T
A
= 85°C
T
= 25°C
A
IF
6
T
A
= –40°C
CONV GAIN
IM3
RF
4
T
= 25°C
A
T
A
= 85°C
T
= –40°C
A
T
A
= 25°C
2
T
= 25°C
A
0
4.5
4.75
5.0
5.25
5.5
0
1000 1500 2000 2500 3000
FREQUENCY (MHz)
–21
–9
–3
0
500
–18 –15 –12
–6
3
RF INPUT POWER (dBm/TONE)
SUPPLY VOLTAGE (V)
5512 • G09
5512 G11
5512 G10
5512i
4
LT5512
U W
TYPICAL PERFOR A CE CHARACTERISTICS
(1230MHz Cable Infrastructure Downmixer
Application) VCC = 5VDC, EN = High, TA = 25°C, RF input = 1230MHz at –10dBm, LO input swept from = 1500MHz to 2100MHz,
LO = –10dBm, IF output measured from 270MHz to 870MHz, unless otherwise noted. (Test circuit shown in Figure 3.)
P
Conv Gain, IIP3 and SSB NF
vs IF Output Frequency
IF Output Power and 2RF-LO Spur
vs RF Input Power
LO Leakage vs LO Frequency
20
18
16
14
12
10
8
10
0
–10
–20
–30
–40
–50
–60
–70
T
= 85°C
IIP3
A
T
= –40°C
A
T
= 25°C
A
P
OUT
T
= 85°C
A
–10
–20
–30
–40
–50
–60
–70
–80
–90
T
= –40°C
A
T
= 25°C
A
SSB NF
LO-IF
T
= 25°C
A
T
= –40°C
A
2RF-LO
T = 85°C
A
6
CONV GAIN
T
= 25°C
A
LO-RF
T
= –40°C
A
4
f
f
= 1800MHz
LO
IF
2
T
= 25°C
A
T
= 85°C
= 570MHz
A
0
270
370
470
570
670
770
870
1500
1700 1800 1900 2000 2100
LO FREQUENCY (MHz)
0
1600
–21
–9
–3
–18 –15 –12
–6
RF INPUT POWER (dBm)
IF OUTPUT FREQUENCY (MHz)
5512 G12
5512 G13
5512 G14
Conv Gain, IIP3 and SSB NF
vs LO Input Power
RF, LO and IF Port Return Losses
vs Frequency
Conv Gain and IIP3 vs
Temperature
20
18
16
14
12
10
8
20
18
16
14
12
10
8
0
–5
T
A
= 85°C
5.5V
DC
T
A
= 25°C
4.5V
IIP3
IIP3
DC
T
= –40°C
IF
A
RF
LO
–10
–15
–20
–25
–30
5V
DC
SSB NF
T
= 25°C
A
f
f
= 1800MHz
f
f
= 1800MHz
LO
= 570MHz
IF
LO
IF
= 570MHz
CONV GAIN
6
6
T
= 25°C
A
T
A
= 85°C
CONV GAIN
T
= –40°C
4
A
4
4.5, 5.0 AND 5.5V
DC
2
2
–20
–15
–10
–5
0
0
1000
1500
2000
2500
–50 –35 –20 –5 10 25 40 55 70 85
500
LO INPUT POWER (dBm)
FREQUENCY (MHz)
TEMPERATURE (°C)
5512 G15
5512 G17
5512 G16
5512i
5
LT5512
U
U
U
PI FU CTIO S
NC (Pins 1, 4, 8, 13, 16): Not connected internally. These
pinsshouldbegroundedonthecircuitboardforimproved
LO to RF and LO to IF isolation.
RF+, RF– (Pins 2, 3): Differential Inputs for the RF Signal.
These pins must be driven with a differential signal. Each
pin must be connected to a DC ground capable of sinking
15mA (30mA total). This DC bias return can be accom-
plished through the center-tap of a balun, or with shunt
inductors. An impedance transformation is required to
match the RF input to 50Ω (or 75Ω).
externally connected to the other VCC pins, and decoupled
with 100pF and 0.01µF capacitors.
GND (Pins 9 and 12): Ground. These pins are internally
connected to the backside ground for better isolation.
They should be connected to RF ground on the circuit
board, although they are not intended to replace the
primary grounding through the backside contact of the
package.
IF–, IF+ (Pins 10, 11): Differential Outputs for the IF
Signal. An impedance transformation may be required to
match the outputs. These pins must be connected to VCC
through impedance matching inductors, RF chokes or a
transformer center-tap.
LO–, LO+ (Pins 14, 15): Differential Inputs for the Local
Oscillator Signal. They can also be driven single-ended by
connecting one to an RF ground through a DC blocking
capacitor. These pins are internally biased to 2V; thus, DC
blocking capacitors are required. An impedance transfor-
mation is required to match the LO input to 50Ω (or 75Ω).
EN (Pin 5): Enable Pin. When the input voltage is higher
than 3V, the mixer circuits supplied through Pins 6, 7, 10,
and 11 are enabled. When the input voltage is less than
0.3V, all circuits are disabled. Typical enable pin input
current is 50µA for EN = 5V and 0µA when EN = 0V.
V
CC1 (Pin 6): Power Supply Pin for the LO Buffer Circuits.
Typical current consumption is 22mA. This pin should be
externally connected to the other VCC pins, and decoupled
with 100pF and 0.01µF capacitors.
VCC2 (Pin 7): Power Supply Pin for the Bias Circuits.
Typical current consumption is 4mA. This pin should be
GROUND (Backside Contact): Circuit Ground Return for
the Entire IC. This must be soldered to the printed circuit
board ground plane.
W
BLOCK DIAGRA
BACKSIDE
GROUND
17
LINEAR
GND
+
12
DOUBLE-BALANCED
MIXER
AMPLIFIER
+
2
3
RF
15mA
11 IF
15mA
–
IF
10
9
–
+
RF
GND
HIGH-SPEED
LO BUFFER
LO 15
–
BIAS
14
LO
5
EN
6
7
V
CC1
V
CC2
5512 BD
5512i
6
LT5512
TEST CIRCUITS
C6
C7
LO
IN
RF
GND
1500MHz
TO
ER = 4.4
0.018"
0.062"
2300MHz
L3
DC
0.018"
GND
16
15 14
13
NC
+
–
NC LO LO
1
2
3
4
12
11
10
9
RF
IN
NC
T1
T2
GND
TL1
C4
1700MHz
TO
IF
OUT
170MHz
1
5
4
1
2
3
6
L1
+
+
IF
RF
RF
2100MHz
LT5512
C8
–
–
IF
3
C5
4
L2
TL2
NC
GND
EN
V
V
NC
CC1 CC2
5
6
7
8
EN
R1
V
CC
C3
C1
C2
GND
5512 F02
REF DES
VALUE
SIZE
0402
0402
0603
0402
0402
PART NUMBER
REF DES
L1, L2
L3
VALUE
47nH
5.6nH
10
SIZE
PART NUMBER
C1, C5, C6, C7 100pF
Murata GRP1555C1H101J
Murata GRP155R71C103K
0402
0402
0402
Coilcraft 0402CS-47NX
Toko LL1005-FH5N6
C2
C3
C4
C8
0.01µF
1.0µF
1.5pF
6.8pF
Taiyo Yuden LMK107F105ZA
Murata GRP1555C1H1R5C
Murata GRP1555C1H6R8D
R1
T1
2:1
Murata LDB211G9010C-001
Mini-Circuits TC8-1
T2
8:1
TL1, TL2
Z = 72Ω
O
θ = 8.1°
(W = 0.4mm, L = 2mm)
Figure 2. Test Schematic for 1900MHz Downconverter (PCS/UMTS Applications)
C6
C7
LO
IN
1500MHz
TO
2100MHz
L3
16
15 14
13
NC
+
–
NC LO LO
T2
1
2
3
4
12
11
10
9
C9
IF
OUT
L1
L2
NC
T1
GND
6
4
TL1
C4
1
270MHz
TO
RF
IN
1230MHz
2
1
6
+
+
C5
IF
RF
RF
2
870MHz
3
4
LT5512
–
–
C10
IF
3
5
TL2
NC
GND
N/C
EN
V
V
NC
CC1 CC2
5
6
7
8
EN
R1
V
CC
C3
C1
C2
GND
5512 F03
REF DES
C1, C5, C6,
C7, C9, C10
C2
VALUE
SIZE
PART NUMBER
REF DES
L1, L2
L3
VALUE
12nH
8.2nH
10
SIZE
PART NUMBER
0402
0402
0402
Toko LL1005-FH12N
Toko LL1005-FH8N2
100pF
0.01µF
1.0µF
0402
0402
0603
0402
Murata GRP1555C1H101J
Murata GRP155R71C103K
Taiyo Yuden LMK107F105ZA
Murata GRP1555C1H2R7C
R1
C3
T1
1:1
Murata LDB311G2705C-428
M/A-COM ETC1.6-4-2-3
(W = 0.4mm, L = 2.0mm)
C4
2.7pF
T2
4:1
TL1, TL2
Z = 72Ω
O
θ = 5.4°
Figure 3. Test Schematic for 1230MHz Downconverter (Cable Infrastructure Downlink Transmitter Applications)
5512i
7
LT5512
W U U
U
APPLICATIO S I FOR ATIO
The LT5512 consists of a double-balanced mixer, RF differential input impedance up to the desired value for the
buffer amplifier, high-speed limiting LO buffer, and bias/ balun input. The following example shows how to design
enable circuits. The RF, LO and IF ports are differential. All the low-pass impedance transformation network for the
threeportscanbematchedfromDCto3GHz, althoughthe RF input.
IC has been optimized for downconverter applications
FromTable1,thedifferentialinputimpedanceat1900MHz
where the RF and LO input signals are high frequency and
is 20.6 + j22.8. As shown in Figure 5, the 22.8Ω reactance
the IF output frequency ranges from DC up to 2GHz. Low
side or high side LO injection can be used.
is split, with one half on each side of the 20.6Ω load
resistor. The matching network will consist of additional
inductance in series with the internal inductance and a
RF Input Port
capacitor in parallel with the desired 100Ω source imped-
The RF input buffer has been designed to simplify imped-
ance matching while improving LO-RF isolation and noise
figure.AsimplifiedschematicisshowninFigure4withthe
associated external impedance matching elements for a
1.9GHz application. Each RF input requires a low resis-
tance DC return to ground capable of sinking 15mA. This
can be accomplished with the center-tap of a balun as
shown in Figure 4, or bias chokes connected from Pins 2
and 3 to ground.
ance. The capacitance (C4) and inductance are calculated
as follows.
n = RS/RL = 100/20.6 = 4.85
Q = √n – 1 = 1.963
XC = RS/Q = 100/1.963 = 50.9Ω
C4 = 1/(ωXc) = 1.6pF (use 1.5pF)
XL = (RL • Q) = (20.6 • 1.963) = 40.4Ω
XEXT = XL – XINT = 40.4 – 22.8 = 17.6Ω
LEXT = (XEXT/ω) = 1.47nH
V
BIAS
The external inductance is split in half (0.74nH), with each
halfconnectedbetweenthepinandtheshuntcapacitor, as
shown in Figure 5. The inductance is implemented with
short (2mm) high-impedance printed transmission lines,
which yield a compact board layout. Finally, the 2:1balun
transforms the 100Ω differential impedance down to a
50Ω single-ended input for the RF signal.
V
CC
15mA
15mA
2
3
TL1
= 72Ω
θ = 8.1° AT 1.9GHz
TL2
C4
1.5pF
Z
Z = 72Ω
O
O
θ = 8.1° AT 1.9GHz
Table 1. RF Input Differential Impedance
100Ω
Frequency
(MHz)
10
Differential Input
Impedance
18.2 + j0.14
18.0 + j0.26
18.1 + j2.8
Differential S11
Mag
2
3
4
1
Angle
179.6
178.6
172.6
166.3
150.8
124.3
116.9
109.2
101.7
5
T1
1:2
0.467
0.470
0.471
0.473
0.479
0.503
0.512
0.522
0.530
44
LDB211G9010C-001
RF
IN
5512 F04
50Ω
240
Figure 4. RF Input with External
Matching for a 1.9GHz Application
450
18.1 + j5.2
950
18.7 + j11.3
20.6 + j22.8
21.4 + j26.5
22.5 + j30.5
24.1 + j34.7
1900
2150
2450
2700
Table 1 lists the differential input impedance and differen-
tial reflection coefficient between Pins 2 and 3 for several
common RF frequencies. As shown in Figures 4 and 5,
low-pass impedance matching is used to transform the
5512i
8
LT5512
W U U
APPLICATIO S I FOR ATIO
U
Table 2. LO Input Differential Impedance
1/2 X
1/2 X
EXT
INT
Frequency
(MHz)
750
Differential Input
Impedance
263 – j172
213 – j178
175 – j173
146 – j164
125 – j153
108 – j142
95 – j131
Differential S11
2
3
j11.4
RS
RL
Mag
0.766
0.760
0.752
0.743
0.733
0.722
0.709
0.695
0.68
Angle
–10.2
–13.4
–16.6
–19.8
–22.8
–25.8
–28.9
–31.8
–34.6
C4
100Ω
1/2 X
1/2 X
20.6Ω
EXT
INT
j11.4
1000
1250
1500
1750
2000
2250
2500
2750
5512 F05
Figure 5. 1.9GHz RF Input Matching
It is also possible to eliminate the RF balun and drive the
RF inputs differentially. In this case, inductors from Pins
2 and 3 to ground would be required to bias the input
stage. Thevalueoftheinductorsshouldbehighenoughto
avoid reducing the input impedance at the frequency of
interest.
86 – j122
78 – j113
Single-ended LO drive can be used if a differential LO
source is not available, or the added expense of a LO balun
is undesirable. In this case, one LO input is AC-coupled to
ground through a 100pf DC blocking capacitor as shown
in Figure 7. The other input is matched to 50Ω using a
series inductor and a second DC blocking capacitor. The
LT5512ischaracterizedandproductiontestedwithsingle-
ended LO drive.
LO Input Port
The LO buffer amplifier consists of high-speed limiting
differentialamplifiers,designedtodrivethemixerquadfor
high linearity. The LO+ and LO– pins are designed for
differential or single-ended drive. An external balun is
optional. Both LO pins are internally biased to 2VDC.
The LO input has been designed for simple impedance
matching for frequencies up to 3GHz. A simplified sche-
matic is shown in Figure 6 with the associated external
impedance matching. The matching technique is similar
to that described earlier for the RF port, except the match
is not nearly as critical. Table 2 lists the differential input
impedance and differential reflection coefficient between
the LO+ and LO– pins (Pin 15 to Pin 14). As shown, the real
part of the series impedance is close to 100Ω. Series
inductors (L3, L4) are used to tune out the capacitive
portion of the differential impedance.
2V
+
LO
15
L3
LO
IN
50Ω
C6
100pF
V
C7
100pF
CC
14
LO
–
5512 F07
Figure 7. Single-Ended LO Input Matching
The differential port impedance listed in Table 2 can be
usedtocomputethevalueoftheseriesmatchinginductor,
L3. Alternatively, Figure 8 shows measured LO input
return loss for various values of L3.
T3
1:2
LDB211G9010C-001
+
LO
15
2V
1
4
L3
C11
LO
IN
50Ω
V
CC
2
3
L4
5
14
LO
–
5512 F06
Figure 6. LO Input with External Matching Elements
5512i
9
LT5512
W U U
U
APPLICATIO S I FOR ATIO
0
An alternative matching network for a broadband CATV IF
(270MHz to 870MHz) is shown in Figure 3. Here, a low-
pass impedance transformer consisting of the internal
capacitance, with L1 and L2, transforms the 371Ω output
resistance at 870MHz to 200Ω. A 4:1 balun then com-
pletes the match down to 50Ω. Supply voltage is applied
through the center-tap of the transformer.
–5
–10
4.7nH
5.6nH
6.8nH
–15
–20
–25
–30
8.2nH
Table 3. IF Output Differential Impedance (Parallel Equivalent)
Frequency
(MHz)
10
Differential Output
Impedance
Differential S11
10nH
2000
Mag
Angle
0
0
3000 3500
4000
500 1000 1500
2500
FREQUENCY (MHz)
396 || – j10k
394 || – j5445
393 || – j2112
392 || – j1507
387 || – j798
377 || – j478
371 || – j416
363 || – j359
363 || – j295
346 || – j244
317 || – j192
0.766
0.775
0.774
0.773
0.772
0.768
0.766
0.762
0.764
0.756
0.743
1573 F08
70
–1.1
–2.8
–3.9
–7.3
–12.2
–14.0
–16.2
–19.6
–23.6
–29.9
Figure 8. Single-Ended LO Port Return Loss
vs Frequency for Various Values of L3
170
240
450
IF Output Port
750
The IF outputs, IF+ and IF–, are internally connected to the
collectors of the mixer switching transistors as shown in
Figure 9. These differential outputs should be combined
externally through an RF balun or 180° hybrid to achieve
optimum performance. Both pins must be biased at the
supply voltage, which can be applied through matching
inductors (see Figure 2), or through the center-tap of an
output transformer (see Figure 3). These pins are pro-
tected with ESD diodes; the diodes allow peak AC signal
swing up to 1.3V above VCC.
860
1000
1250
1500
1900
11
+
IF
L1
TO
As shown in Table 3, the IF output differential impedance
is approximately 390Ω in parallel with 0.44pF. A simple
band-pass IF matching network suitable for wireless ap-
plications is shown in Figure 9. Here, L1, L2 and C8 set the
desired IF output frequency. The 390Ω differential output
can then be applied directly to a differential filter, or an 8:1
balun for impedance transformation down to 50Ω. To
achieve maximum linearity, C8 should be located as close
as possible to the IF+/IF– pins. Even small amounts of
inductance in series with C8 (such as through a via) can
significantly degrade IIP3. For high IF frequencies, the
value of C8 should be reduced by the value of internal
capacitance(seeTable 3).Thismatchingnetworkissimple
and offers good selectivity for narrow band IF applica-
tions.
DIFFERENTIAL
FILTER OR
BALUN
V
400Ω
C8
CC
L2
–
IF
10
5512 F09
Figure 9. IF Output Equivalent Circuit
with Band-Pass Matching Elements
5512i
10
LT5512
U
PACKAGE DESCRIPTIO
UF16 Package
16-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1692)
0.72 ±0.05
4.35 ± 0.05
2.90 ± 0.05
2.15 ± 0.05
(4 SIDES)
PACKAGE OUTLINE
0.30 ±0.05
0.65 BCS
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
0.75 ± 0.05
R = 0.115
TYP
0.55 ± 0.20
4.00 ± 0.10
(4 SIDES)
15
16
PIN 1
1
2
2.15 ± 0.10
(4-SIDES)
(UF) QFN 0102
0.30 ± 0.05
0.65 BSC
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC)
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
4. EXPOSED PAD SHALL BE SOLDER PLATED
5512i
11
LT5512
W U U
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APPLICATIO S I FOR ATIO
5512 F10b
5512 F10a
Figure 10. 1900MHz Evaluation Board Layout
5512 F11
Figure 11. 1230MHz Cable Infrastructure Evaluation Board Layout
(Wide Output Range Down-Converting Mixer for Downlink Transmitter)
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT5500
LT5502
1.8GHz to 2.7GHz Receiver-Front End
1.8V to 5.25V Supply, Dual-Gain LNA, Mixer, LO Buffer
400MHz Quadrature IF Demodulator with RSSI
1.8V to 5.25V Supply, 70MHz to 400MHz IF,
84dB Limiting Gain, 90db RSSI Range
LT5503
1.2GHz to 2.7GHz Direct IQ Modulator
and Upconverting Mixer
1.8V to 5.25V Supply, Four-Step RF Power Control,
120MHz Modulation Bandwidth
LT5504
LTC5505
LTC5507
LT5511
800MHz to 2.7GHz RF Measuring Receiver
RF Power Detectors with >40dB Dynamic Range
100kHz to 1000MHz RF Power Detector
High Signal Level Upconverting Mixer
80dB Dynamic Range, Temperature Compensated, 2.7V to 5.5V Supply
300MHz to 3GHz, Temperature Compensated, 2.7V to 6V Supply
Temperature Compensated, 2.7V to 6V Supply
RF Output to 3GHz, 17dBm IIP3, Integrated LO Buffer
5512i
LT/TP 0702 1.5K • PRINTED IN USA
12 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2002
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