LT5524EFE [Linear]
Low Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain; 低失真IF与数字控制增益放大器/ ADC驱动器
| 型号： | LT5524EFE |
| 厂家： | 
Linear |
| 描述： | Low Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain |
| 文件： | 总16页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT5524
Low Distortion IF
Amplifier/ADC Driver with
Digitally Controlled Gain
U
FEATURES
DESCRIPTIO
TheLT®5524isaprogrammablegainamplifier(PGA)with
bandwidth extending from low frequency (LF) to 540MHz.
It consists of a digitally controlled variable attenuator,
followed by a high linearity amplifier. Four parallel digital
inputs control the gain over a 22.5dB range with 1.5dB
step resolution. An on-chip power supply regulator/filter
helps isolate the amplifier signal path from external noise
sources.
■
Output IP3 at 100MHz: 40dBm
■
Maximum Output Power: 16dBm
■
Bandwidth: LF to 540MHz
■
Propagation Delay: 0.8ns
■
Maximum Gain: 27dB
■
Gain Control Range: 22.5dB
■
Gain Control Step: 1.5dB
■
Gain Control Settling Time: 500ns
■
Noise Figure: 8.6dB at 100MHz (Max Gain)
The LT5524’s open-loop architecture offers stable opera-
tion for any practical load conditions, including peaking-
free AC response when driving capacitive loads, and
excellent reverse isolation.
■
Output Noise Floor: –138dBm/Hz (Max Gain)
■
Reverse Isolation: –92dB
■
Single Supply: 4.75V to 5.25V
■
Shutdown Mode
■
■
■
The LT5524 may be operated broadband, where the out-
put differential RC time constant sets the bandwidth, or it
may be used as a narrowband driver with the appropriate
output filter.
Enable/Disable Time: 1µs
Differential I/O Interface
20-Lead TSSOP Package
U
, LTC and LT are registered trademarks of Linear Technology Corporation.
Patents Pending.
APPLICATIO S
■
High Linearity ADC Driver
■
IF Sampling Receivers
■
VGA IF Power Amplifier
■
50Ω Driver
■
Instrumentation Applications
U
TYPICAL APPLICATIO
Output IP3 vs Frequency, ROUT = 200Ω
54
51
48
5V
CHOKE
0.1µF
CHOKE
0.1µF
45
MAX GAIN
IF
AMP
RF
INPUT
IF
BPF
100Ω
LT5524
ADC
42
5524 TA01
39
LO
0.1µF
0.1µF
1.5dB
ATTENUATION
STEP
GAIN CONTROL
36
33
30
4 LINES
100
FREQUENCY (MHz)
0
50
150
200
5524 TA02
5524f
1
LT5524
W W
U W
U
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ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Notes 1, 2)
TOP VIEW
Power Supply Voltage (VCC1, VCC2) .......................... 6V
Output DC Voltage (OUT+, OUT–) ............................. 7V
Control Input Voltage (EN, PGAx) ............. –0.5V to VCC
Signal Input Voltage (IN+, IN–) ................... –0.5V to 3V
Operating Ambient Temperature Range.. – 40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
EN
1
2
3
4
5
6
7
8
9
20 NC
19
V
V
CC1
CC2
LT5524EFE
GND
GND
18 GND
17 GND
+
–
IN
16 OUT
15 OUT
21
–
+
IN
GND
GND
14 GND
13 GND
12 PGA3
11 PGA2
PGA0
PGA1 10
FE PACKAGE
20-LEAD PLASTIC TSSOP
TJMAX = 150°C, θJA = 38°C/W
EXPOSED PAD (PIN 21) IS GND
MUST BE SOLDERED TO PCB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
W W
U
U
PROGRA ABLE GAI SETTI GS
ATTENUATION STEP
POWER GAIN
27.0dB
25.5dB
24.0dB
22.5dB
21.0dB
19.5dB
18.0dB
16.5dB
15.0dB
13.5dB
12.0dB
10.5dB
9.0dB
RELATIVE TO MAX GAIN
0dB
PGA0
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
PGA1
High
High
Low
Low
High
High
Low
Low
High
High
Low
Low
High
High
Low
Low
PGA2
High
High
High
High
Low
Low
Low
Low
High
High
High
High
Low
Low
Low
Low
PGA3
High
High
High
High
High
High
High
High
Low
Low
Low
Low
Low
Low
Low
Low
*
1
2
–1.5dB
3
–3.0dB
4
–4.5dB
5
–6.0dB
6
–7.5dB
7
–9.0dB
8
–10.5dB
–12.0dB
–13.5dB
–15.0dB
–16.5dB
–18.0dB
–19.5dB
–21.0dB
–22.5dB
9
10
11
12
13
14
15
16
7.5dB
6.0dB
4.5dB (Note 3)
*R
OUT
= 200Ω
5524f
2
LT5524
DC ELECTRICAL CHARACTERISTICS
VCC = 5V, VCCO = 5V, EN = 3V, TA = 25°C, unless otherwise noted.
(Note 7) (Test circuits shown in Figures 9 and 10)
SYMBOL PARAMETER
Normal Operating Conditions
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
Supply Voltage (Pins 2, 19)
(Note 4)
4.75
3
5
5
5.25
5.5
V
V
CC
+
–
+
–
OUT , OUT Output Pin DC Common Mode Voltage OUT , OUT Connected to V
via
OSUP
CCO
Choke Inductors or Resistors (Note 5)
Shutdown DC Characteristics, EN = 0.6V
+
–
V
IN , IN Bias Voltage
Max Gain (Note 6)
1.15
1.3
44
1.5
20
V
µA
µA
µA
µA
IN(BIAS)
IL(PGA)
IH(PGA)
OUT
I
I
I
I
PGAO, PGA1, PGA2, PGA3 Input Current
V
V
= 0.6V
= 5V
IN
IN
PGAO, PGA1, PGA2, PGA3 Input Current
20
+
–
OUT , OUT Current
Supply Current
All Gain Settings
20
V
All Gain Settings (Note 4)
100
CC
CC
Enable and PGA Inputs DC Characteristics
V
V
EN and PGAx Input Low Voltage
EN and PGAx Input High Voltage
PGAO, PGA1, PGA2, PGA3 Input Current
PGAO, PGA1, PGA2, PGA3 Input Current
EN Input Current
x = 0, 1, 2, 3
x = 0, 1, 2, 3
0.6
V
V
IL
3
IH
I
I
I
I
V
V
V
= 0.6V
20
30
20
µA
µA
µA
IL(PGA)
IH(PGA)
IL(EN)
IH(EN)
IN
IN
IN
= 3V and 5V
= 0.6V
15
4
EN Input Current
V
V
= 3V
= 5V
18
38
µA
µA
IN
IN
100
DC Characteristics, EN = 3V
+
–
V
IN , IN Bias Voltage
Max Gain (Note 6)
All Gain Settings (DC)
Max Gain
1.34
17
1.48
122
0.15
20
1.65
V
Ω
IN(BIAS)
R
Input Differential Resistance
IN
g
Amplifier Transconductance
S
m
+
–
I
I
I
OUT , OUT Quiescent Current
Output Current Mismatch
All Gain Settings, V
= 5V
–
24
mA
µA
OUT
OUT
+
All Gain Settings, IN , IN Open
100
OUT(OFFSET)
CC
V
+ V
Supply Current
Max Gain (Note 4)
Min Gain (Note 4)
34
36
40
43
mA
mA
CC1
CC2
I
Total Supply Current
I
+ 2 • I (Max Gain)
OUT
75
91
mA
CC(TOTAL)
CC
5524f
3
LT5524
AC ELECTRICAL CHARACTERISTICS
VCC = 5V, VCCO = 5V, EN = 3V, TA = 25°C, ROUT = 200Ω. Maximum gain
specifications are with respect to differential inputs and differential outputs, unless otherwise noted.
(Note 7) (Test circuits shown in Figures 9 and 10)
SYMBOL PARAMETER
Dynamic Performance
CONDITIONS
MIN
TYP
MAX
UNITS
BW
Large-Signal –3dB Bandwidth
All Gain Settings (Note 8), R
= 100Ω
LF to 540
MHz
V
OUT
+
–
V
Output Voltage Clipping Levels
Each OUT , OUT with Respect to Ground
(Note 11)
2
8
OUT(CLIP)
OUT(MAX)
m
P
Clipping Limited Maximum Sinusoidal
Output Power
All Gain Settings, Single Tone,
16
dBm
f
= 100MHz (Note 10)
IN
g
Amplifier Transconductance
Reverse Isolation
Max Gain, f = 100MHz
0.15
–92
S
IN
S12
f
= 100MHz (Note 9)
dB
IN
Distortion and Noise
OIP3
Output Third Order Intercept Point for
PGA0 = High (PGA1, PGA2, PGA3 Any State)
P
= 4dBm (Each Tone), 200kHz Tone Spacing,
OUT
= 100MHz
f
+40
dBm
IN
Output Third Order Intercept Point for
PGA0 = Low (PGA1, PGA2, PGA3 Any State)
P
= 4dBm (Each Tone), 200kHz Tone Spacing,
OUT
= 100MHz
f
+36
–76
–72
dBm
dBc
dBc
IN
HD2
HD3
Second Harmonic Distortion
Third Harmonic Distortion
P
P
= 5dBm (Single Tone), f = 50MHz
IN
OUT
OUT
= 5dBm (Single Tone), f = 50MHz
IN
N
FLOOR
Output Noise Floor
(PGAO, PGA2, PGA3 Any State)
PGA1 = High, f = 100MHz
–138
–140
dBm/Hz
dBm/Hz
IN
PGA1 = Low, f = 100MHz
IN
NF
Noise Figure
Max Gain Setting, f = 100MHz
8.6
500
600
dB
ns
ns
IN
PGA Settling Time
Enable/Disable Time
Output Settles within 10% of Final Value
Output Settles within 10% of Final Value
Amplifier Power Gain and Gain Step
G
G
G
Maximum Gain
Minimum Gain
Gain Step Size
f
f
f
f
= 20MHz and 200MHz
= 20MHz and 200MHz
= 20MHz and 200MHz
= 20MHz and 200MHz
27
4.5
dB
dB
dB
dB
MAX
MIN
IN
IN
IN
IN
0.8
1.5
2.2
STEP
Gain Step Accuracy
±0.2
Amplifier I/O Impedance (Parallel Values, Specified Differentially)
R
Input Resistance
Input Capacitance
Output Resistance
Output Capacitance
f
f
f
f
= 100MHz
= 100MHz
= 100MHz
= 100MHz
122
2
Ω
pF
IN
IN
IN
IN
IN
IN
C
R
O
5
kΩ
pF
C
1.7
O
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
matching is assumed. P is the available input power. P
is the power
OUT
IN
into the external load, R , as seen by the LT5524 differential outputs. All
OUT
dBm figures are with respect to 50Ω.
Note 2: All voltage values are with respect to ground.
Note 3: Default state for open PGA inputs.
Note 8: High frequency operation is limited by the RC time constants at
the input and output ports. The low frequency (LF) roll-off is set by I/O
interface choice.
Note 9: Limited by package and board isolation.
Note 10: See “Clipping Free Operation” in the Applications Information
Note 4: V
and V
(Pins 2 and 19) are internally connected.
CC2
CC1
Note 5: External V
is adjusted such that V
output pin common
OSUP
CCO
mode voltage is as specified when resistors are used. For choke inductors
or transformer, V = V = 5V typ.
OSUP
CCO
section. Refer to Figure 7.
Note 6: Internally generated common mode input bias voltage requires
capacitive or transformer coupling to the signal source.
Note 7: Specifications over the –40°C to 85°C operating temperature
range are assured by design, characterization and correlation with
statistical process controls. Gain always refers to power gain. Input
+
–
Note 11: Although the instantaneous AC voltage on the OUT or OUT pins
may in some situations safely exceed 8V (with respect to ground), in no
case should the DC voltage on these pins be allowed to exceed the
ABSMAX tested limit of 7V.
5524f
4
LT5524
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TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C, VCC = 5V, VCCO = 5V, EN = 3V, control
input levels VIL = 0.6V, VIH = 3V unless otherwise noted. (Test circuit shown in Figure 9)
Frequency Response for All Gain
Steps, ROUT = 200Ω
Gain Error vs Attenuation Step at
25MHz, ROUT = 200Ω
Gain Error vs Attenuation Step at
100MHz, ROUT = 200Ω
30
27
24
21
18
15
12
9
0.8
0.6
0.8
0.6
25°C
–40°C
85°C
25°C
–40°C
85°C
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–0.2
–0.4
–0.6
–0.8
6
3
0
12
6
ATTENUATION STEP (dB)
12
6
ATTENUATION STEP (dB)
0
3
9
15
18
21
0
3
9
15
18
21
10
100
1000
FREQUENCY (MHz)
5524 G01
5524 G02
5524 G03
Minimum Gain vs VCC at 120MHz,
ROUT = 200Ω
Maximum Gain vs VCC at
120MHz, ROUT = 200Ω
POUT vs PIN at 50MHz, Max Gain
25
20
15
10
5
27.6
27.4
27.2
27.0
26.8
26.6
26.4
26.2
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
–40°C
–40°C
25°C
25°C
85°C
R
= 200Ω
OUT
85°C
0
–5
–16 –13
(dBm)
–31 –28 –25 –22 –19
–10 –7
4.7
4.9
5.1
(V)
5.5
4.5
5.3
4.7
4.9
5.1
5.5
4.5
5.3
P
IN
V
V
CC
(V)
CC
5524 G06
5524 G05
5524 G04
OIP3 vs Frequency at Pin = –23dBm,
Max Gain and 1.5dB Attenuation
Step, ROUT = 200Ω
Harmonic Distortion vs POUT at
50MHz, Max Gain, ROUT = 200Ω
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
54
51
48
45
42
39
36
33
30
MAX GAIN
HD3
HD2
1.5dB
ATTENUATION
STEP
HD5
6
HD4
12
–100
100
0
50
150
200
15
–6
0
3
9
–3
P
OUT
(dBm)
FREQUENCY (MHz)
5524 G07
5524 G08
5524f
5
LT5524
TYPICAL PERFOR A CE CHARACTERISTICS Two tones, 200kHz spacing, TA = 25°C, EN = 3V,
U W
VCC = 5V, VCCO = 5V, control input levels VIL = 0.6V, VIH = 3V unless otherwise noted. (Test circuit shown in Figure 10)
NF vs Attenuation Step at
Freq = 100MHz
Output Noise Floor vs Attenuation
Noise Figure vs Frequency
Step, Freq = 100MHz, ROUT = 200Ω
30
27
24
21
18
15
12
9
–136
–137
–138
–139
–140
–141
–142
10.0
9.5
9.0
8.5
8.0
7.5
7.0
1.5dB ATTENUATION STEP
(PGA0 = LOW)
PGA1 = HIGH
PGA1 = LOW
MAX GAIN
3dB ATTENUATION STEP
(PGA1 = LOW)
6
3
0
250 300
0
50 100 150 200
350 400
0
3
6
9
12
15
18
21
0
6
9
12 15 18 21
3
FREQUENCY (MHz)
ATTENUATION STEP (dB)
ATTENUATION STEP (dB)
5524 G09
5524 G10
5524 G11
Pulse Response vs Output Level at
Max Gain. Indicated Voltage Levels
are into 50Ω External Load
Single-Ended Output Current
vs Attenuation Step
VIN(BIAS) vs Attenuation Step
1.60
1.55
1.50
1.45
1.40
21.0
20.5
20.0
19.5
19.0
C
= 0.82pF
OUT
–40°C
85°C
25°C
25°C
85°C
–40°C
0
6
9
12 15 18 21
3
0
6
9
12 15 18 21
3
2ns/DIV
5524 G12
ATTENUATION STEP (dB)
ATTENUATION STEP (dB)
5524 G14
5524 G13
ICC Shutdown Current vs VCC
EN = 0.6V
,
Total ICC vs Attenuation Step
80
78
75
73
70
68
65
70
60
85°C
25°C
85°C
25°C
50
40
30
20
10
–40°C
–40°C
0
0
6
9
12 15 18 21
4.7
4.9
5.1
5.5
3
4.5
5.3
ATTENUATION STEP (dB)
INPUT V (V)
CC
5524 G15
5524 G16
5524f
6
LT5524
U
U
U
PI FU CTIO S
EN (Pin 1): Enable Pin for Amplifier. When the input
voltage is higher than 3V, the amplifier is turned on. When
the input voltage is less than or equal to 0.6V, the amplifier
is turned off. This pin is internally pulled to ground if not
connected.
PGA2(Pin11):AmplifierPGAControlInputPinforthe6dB
Attenuation Step (see Programmable Gain table). Input is
highwhentheinputvoltageisgreaterthan3V. Inputislow
when the input voltage is less than or equal to 0.6V. This
pin is internally pulled to ground if not connected.
VCC1(Pin2):PowerSupply.Thispinisinternallyconnected
toVCC2 (Pin19).Decouplingcapacitors(1000pFand0.1µF
for example) may be required in some applications.
PGA3 (Pin 12): Amplifier PGA Control Input Pin for 12dB
Attenuation Step (see Programmable Gain table). Input is
highwhentheinputvoltageisgreaterthan3V. Inputislow
when the input voltage is less than or equal to 0.6V. This
pin is internally pulled to ground if not connected.
OUT+ (Pin 15): Positive Amplifier Output. A transformer
with center tap tied to VCC or a choke inductor is recom-
mended to source the DC quiescent current.
GND (Pins 3, 4, 7, 8, 13, 14, 17, 18): Ground.
IN+ (Pin 5): Positive Signal Input Pin with Internal DC
Bias.
IN– (Pin 6): Negative Signal Input Pin with Internal DC
Bias.
OUT– (Pin 16): Negative Amplifier Output. A transformer
with center tap tied to VCC or a choke inductor is recom-
mended to source the DC quiescent current.
PGA0(Pin9):AmplifierPGAControlInputPinforthe1.5dB
Attenuation Step (see Programmable Gain table). Input is
highwhentheinputvoltageisgreaterthan3V. Inputislow
when the input voltage is less than or equal to 0.6V. This
pin is internally pulled to ground if not connected.
VCC2 (Pin 19): Power Supply. This pin is internally con-
nected to VCC1 (Pin 2).
NC (Pin 20): Not Connected.
PGA1(Pin10):AmplifierPGAControlInputPinforthe3dB
Attenuation Step (see Programmable Gain table). Input is
highwhentheinputvoltageisgreaterthan3V. Inputislow
when the input voltage is less than or equal to 0.6V. This
pin is internally pulled to ground if not connected.
Exposed Pad (Pin 21): Ground. This pin must be soldered
to the printed circuit board ground plane for good heat
transfer.
W
BLOCK DIAGRA
LT5524
+
–
OUT
ATTENUATOR
IN
16
5
6
R
IN
AMPLIFIER
–
100Ω
+
IN
OUT
15
VOLTAGE REGULATOR
AND BIAS
GAIN CONTROL
LOGIC
ENABLE
CONTROL
GND (3, 4, 7, 8
13, 14, 17, 18)
V
CC1
V
CC2
PGA3 PGA2 PGA1 PGA0
12 11 10
NC
20
EN
21
2
19
9
1
5524 F01
Figure 1. Functional Block Diagram
5524f
7
LT5524
W U U
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APPLICATIO S I FOR ATIO
Circuit Operation
where:
The LT5524 is a high linearity amplifier with high imped-
ance output (Figure 1). It consists of the following
sections:
gm is the LT5524 transconductance = 0.15S.
RIN is the LT5524 differential input impedance ≅ 122Ω.
Input impedance matching is assumed.
• An input variable attenuator “gain-control” block with
ROUT is the external differential output impedance as
seen by the LT5524’s differential outputs. ROUT should
bedistinguishedfromtheactualloadimpedance,RLOAD,
which will typically be coupled to the LT5524 output by
an impedance transformation network.
122Ω input impedance
• A differential transconductance amplifier, with enable
input
• An internal bias block with internal voltage regulator
• A gain control logic block
The power gain as a function of ROUT is plotted in Figure 2.
The ideal relationship is linear. The curved line indicates
the roll-off due to the finite (noninfinite) output resistance
of the LT5524.
The LT5524 amplifier provides amplification with very low
distortion using a linearized open-loop architecture. In
contrast with high linearity amplifiers employing negative
feedback, the LT5524 offers:
45
40
35
30
25
20
15
10
• Stable operation for any practical load
• A capacitive output reactance (not inductive) that pro-
vides peaking free AC response to capacitive loads
• Exceptional reverse isolation of –100dB at 50MHz and
–78dB at 300MHz (package and board leakage limited)
TheLT5524isatransconductanceamplifieranditsopera-
tion can be understood conceptually as consisting of two
steps: First, the input signal voltage is converted to an
output current. The intermodulation distortion (in dBc) of
the LT5524 output current is determined by the input
signal level, and is almost independent of the output load
conditions. Thus, the LT5524’s input IP3 is also nearly
independent of the output load.
IDEAL
5
0
WITH R
O
20
100
1000 2000
R
(Ω)
OUT
5524 F02
Figure 2. Power Gain as a Function of ROUT
The actual available output power (as well as power gain
andOIP3)willbereducedbylossesintheoutputinterface,
consisting of:
Next, the external output load (ROUT) converts the output
current to output voltage (or power). The LT5524’s volt-
age and power gain both increase with increasing ROUT
.
• The insertion loss of the output impedance transforma-
tion network (for example the transformer insertion
loss in Figure 6)
Accordingly, the output power and output IP3 also in-
crease with increasing ROUT. The actual output linearity
performance in the application will thus be set by the
choice of output load, as well as by the output network.
• About –3dB loss if a matching resistor (RMATCH in
Figure 6) is used to provide output load impedance
back-matching (for example when driving transmis-
sion lines)
Maximum Gain Calculation
The maximum power gain (with the 0dB attenuation step)
is:
GPWR(dB) = 10 • log(gm2 • RIN • ROUT
)
5524f
8
LT5524
W U U
APPLICATIO S I FOR ATIO
Input Interface
U
V
OSUP
C3
C1
R1
51Ω
R2
51Ω
R
LOAD
50Ω
For the lowest noise and highest linearity, the LT5524
should be driven with a differential input signal. Single-
ended drive will severely degrade linearity and noise
performance.
LT5524
+
–
IN
–
R
IN
R
R
OUT
LOAD
C2
122Ω
50Ω
IN
+
LT5524 F05
Example input matching networks are shown in Figures 3
and 4.
Figure 5. Output Impedance-Matched
and Capacitively Coupled to a Differential Load
Input matching network design criteria are:
Note: In Figure 5, (choke) inductors may be placed in
parallel with or used to replace resistors R1 and R2, thus
eliminating the DC voltage drop across these resistors.
• DC block the LT5524 internal bias voltage (see Input
Bias Voltage section for DC coupling information)
• MatchthesourceimpedancetotheLT5524,RIN ≅122Ω
V
OSUP
C1
• Provide well balanced differential input drive (capacitor
C2 in Figure 4)
R
MATCH
255Ω
R
LOAD
50Ω
T2
4:1
LT5524
+
–
(OPTIONAL)
IN
IN
–
•
•
•
• Minimize insertion loss to avoid degrading the noise
figure (NF)
R
IN
R
OUT
122Ω
+
LT5524 F06
R1
C1
LT5524
+
–
50Ω
IN
IN
Figure 6. Output Impedance-Matched and
Transformer-Coupled to a Single-Ended Load
–
R
IN
R2
50Ω
V
C2
SRC
122Ω
+
LT5524 F03
Output network design criteria are:
• Provide DC isolation between the LT5524 DC output
voltage and RLOAD
• ProvideapathfortheoutputDCcurrentfromtheoutput
voltage source VOSUP
Figure 3. Input Capacitively-Coupled to a Differential Source
.
R
T1
1:2
SRC
LT5524
+
–
50Ω
.
IN
IN
–
•
•
•
R
IN
V
SRC
• Provide an impedance transformation, if required, be-
tween the load impedance, RLOAD, and the optimum
122Ω
+
LT5524 F04
C2
0.33µF
ROUT loading.
• Set the bandwidth of the output network.
Figure 4. Input Transformer-Coupled to a Single-Ended Source
• Optional: Provide board output impedance matching
using resistor RMATCH (when driving a transmission
line).
Output Interface
The output interface network provides an impedance
transformationbetweentheactualloadimpedance,RLOAD
andtheLT5524outputloading, ROUT, chosentomaximize
powerorlinearity,ortominimizeoutputnoise,orforsome
other criteria as explained in the following sections.
,
• Use high linearity passive parts to avoid introducing
noninearity.
Note that there is a noise penalty of up to 6dB when using
power delivered by only one output in Figure 5.
Two examples of output matching networks are shown in
Figures 5 and 6 (as implemented in the LT5524 demo
boards).
5524f
9
LT5524
W U U
U
APPLICATIO S I FOR ATIO
25
Clipping Free Operation
V
CC
= V
CCO
= 5V
The LT5524 is a class A amplifier. To avoid signal distor-
tion, the user must ensure that the LT5524 outputs do not
enterintocurrentorvoltagelimiting.Thefollowingdiscus-
sion applies to maximum gain operation.
CURRENT
LIMIT
VOLTAGE
LIMIT
20
15
10
5
Toavoidcurrentclipping, theoutputsignalcurrentshould
not exceed the DC quiescent current, IOUT = 20mA (typi-
cal). Correspondingly, the maximum input voltage,
VIN(MAX), is IOUT/gm = 133mV (peak). In power terms,
0
20
100
1000 2000
P
IN(MAX) = –11.5dBm (assuming RIN = 122Ω).
R
(Ω)
OUT
5524 F07
To avoid output voltage clipping (due to LT5524 output
stage saturation or breakdown), the single-ended output
voltage swing should stay within the specified limits; i.e.,
2V ≤ VOUT ≤ 8V. For a DC output bias of 5V, the maximum
single ended swing will be 3Vpeak and the maximum
differential swing will be 6Vpeak. The simultaneous onset
Figure 7. Maximum Output Power as a Function of ROUT
shutdown mode. These inputs are typically coupled by
means of a capacitor or a transformer to a signal source,
and impedance matching is assumed. In shutdown mode,
the internal bias can handle up to 1µA leakage on the input
coupling capacitors. This reduces the turn-on delay due to
the input coupling RC time constant when exiting shut-
down mode.
of both current and voltage limiting occurs when ROUT
=
=
6Vpeak/20mA = 300Ω (typ) for a maximum POUT
17.8dBm. This calculation applies for a sinusoidal signal.
For nonsinusoidal signals, use the appropriate crest fac-
tor to calculate the actual maximum power that avoids
output clipping.
If DC coupling to the input is required, the external
common mode bias should track the LT5524’s internal
common mode level. The DC current from the LT5524
inputsshouldnotexceedIIN(SINK) =–200µAandIIN(SOURCE)
= 400µA.
Although the instantaneous AC voltage on the OUT+ or
OUT– pins may in some situations safely exceed 8V (with
respect to ground), in no case should the DC voltage on
these pins be allowed to exceed the ABSMAX tested limit
of 7V.
Stability Considerations
The LT5524’s open-loop architecture allows it to drive any
practical load. Note that LT5524 gain is proportional to the
load impedance, and may exceed the reverse isolation at
frequencies above 1GHz if the LT5524’s outputs are left
unloaded,withinstabilityastheundesirableconsequence.
Insuchcases, placingaresistivedifferentialload(e.g., 4k)
or a small capacitor at the LT5524 outputs can be used to
limit the maximum gain.
For nonoptimal ROUT values, the maximum available out-
putpowerwillbelowerandcanbecalculated(considering
current limiting for ROUT < 300Ω, and voltage limiting for
ROUT > 300Ω). The result of this calculation is shown in
Figure 7.
The LT5524 input should not be overdriven (PIN
>
–11.5dBm at maximum gain). The consequences of over-
drive are reduced bandwidth and, when the frequency is
greater than 50MHz, reduced output power. At reduced
gainsettings, themaximumPIN isincreasedbyanamount
equal to the gain reduction.
The LT5524 has about 20GHz gain-bandwidth product.
Hence, attention must be paid to the printed circuit board
layout to avoid output pin to input pin signal coupling (the
evaluation board layout is a good example). Due to the
LT5524’s internal power supply regulator, external supply
decouplingcapacitorstypicallyarenotrequired. Likewise,
decoupling capacitors on the LT5524 control inputs typi-
Input Bias Voltage
The LT5524 IN+, IN– signal inputs are internally biased to
1.48V common mode when enabled, and to 1.26V in
cally are not needed. Note, however, that the Exposed Pad
5524f
10
LT5524
W U U
APPLICATIO S I FOR ATIO
U
ontheLT5524packagemustbesolderedtoagoodground
ROUT values, more gain and output power is available, and
better OIP3 figures can be achieved. However, high ROUT
values are not easily implemented in practice, limited by
theavailabilityofhighratiooutputimpedancetransforma-
tion networks.
plane on the PCB.
PGA Function, Linearity and NF
As described in the Circuit Operation section, the LT5524
consists of a variable (step) attenuator followed by a high
gain output amplifier. The overall gain of the LT5524 is
digitally controlled by means of four gain control pins with
internal pull-down. Minimum gain is programmed when
the gain control pins are set low or left floating. In
shutdown mode, these PGA inputs draw <10µA leakage
current, regardless of the applied voltage.
Linearity can also be limited by the output RC time con-
stant (bandwidth limitations), particularly for high ROUT
values. AsolutionisoutlinedintheBandpassApplications
section.
The LT5524 linearity degrades when common mode sig-
nal is present. The input transformer center tap should be
decoupled to ground to provide a balanced input differen-
tial signal and to avoid linearity degradation for high
attenuationsteps.Whenthesignalfrequencyislowerthan
50MHz, and there is significant common mode signal,
then high attenuation settings may result in degraded
linearity.
The6dBand12dBattenuationsteps(PGA2andPGA3)are
implemented by switching the amplifier inputs to an input
attenuator tap. The 3dB attenuation step (PGA1) changes
theamplifiertransconductance.TheoutputIP3isapproxi-
mately independent of the PGA1, PGA2 and PGA3 gain
settings. However, the 1.5dB attenuation step utilizes a
currentsteeringtechniquethatdisablestheinternallinear-
ity compensation circuit, and the OIP3 can be reduced by
as much as 6dB when PGA0 is low. Therefore, to achieve
the LT5524’s highest linearity performance, the PGA0 pin
should be set high.
At signal frequencies below 100MHz, the LT5524’s inter-
nal linearity compensation circuitry may provide “sweet
spots” with very high OIP3, in excess of +52dBm. This
almost perfect distortion correction cannot be sustained
over the full operating temperature range and with varia-
tions of the LT5524 output load (complex impedance
ZOUT). Users are advised to rely on data shown in the
Typical Performance Characteristics curves to estimate
the dependable linearity performance.
The LT5524 noise figure is 8.6dB at 100MHz in the maxi-
mum gain state. For the –3dB attenuation setting, the NF
is 9.2dB. The noise figure increases in direct proportion to
the amount of programmed gain reduction for the 1.5dB,
6dB and 12dB steps.
Wideband Applications
The output noise floor is proportional to the output load
impedance, ROUT. It is almost constant for PGA1 = high
and for any PGA0, PGA2, PGA3 state. When PGA1 = low,
the output noise floor is 2dB lower (see Typical Perfor-
mance Characteristics).
Atlowfrequencies, thevalueofthedecouplingcapacitors,
choke inductors and choice of transformer will set the
minimum frequency of operation. Output DC coupling is
possible, but this typically reduces the LT5524’s output
DC bias voltage, and thus the output swing and available
power.
Other Linearity Considerations
At high frequencies, the output RC time constants set an
upper limit to the maximum frequency of operation in the
case of the wideband output networks presented so far.
ForexampletheLT5524outputcapacitance,COUT =1.7pF,
and a pure resistive load, ROUT = 200Ω, will set the –3dB
bandwidth to about 400MHz. In an actual application, the
RLOAD • CLOAD product may be even more restrictive. The
use of wideband output networks will not only limit the
LT5524 linearity is a strong function of signal frequency.
OIP3 decreases about 13dB for every octave of frequency
increase above 100MHz.
As noted in the Circuit Operation section, at any given
frequency and input level, the LT5524 provides a current
output with fairly constant intermodulation distortion fig-
ure in dBc, regardless of the output load value. For higher
5524f
11
LT5524
W U U
U
APPLICATIO S I FOR ATIO
bandwidth, but will also degrade linearity because part of
network, giving improved linearity performance for signal
frequencies greater than 100MHz. Figure 8 is an example
of such a network.
the available power is wasted driving the capacitive load.
The LT5524’s output reactance is capacitive. Therefore
improvedACresponseispossiblebyusingexternalseries
output inductors. When driving purely resistive loads, an
inductor in series with the LT5524 output may help to
achieve maximally flat AC response as exemplified in the
characterization setup schematic (Figure 9).
The network consists of two parallel resonant LC tank
circuits critically coupled by capacitors C1 and C2. The
ROUT to RLOAD transformation ratio in this particular
implementation is 2. The choice of impedance transfor-
mation ratio is more flexible than in the wideband case.
The LC network is a bandpass filter, a useful feature in
many applications.
The series inductor can extend the application bandwidth,
but it provides no improvement in linearity performance.
A variety of bandpass matching network configurations
are conceivable, depending on the requirements of the
particular application. The design of these networks is
facilitated by the fact that the LT5524 outputs are not
destabilized by reactive loading.
Series inductance may also produce peaking in the AC
response. This can be the case when (high Q) choke
inductors are used in an output interface such as in
Figure 5, and the PCB trace (connection) to the load is too
long. Since the LT5524’s output impedance is relatively
high, the PCB trace acts as a series inductor. The most
direct solution is to shorten the connection lines by
placing the driver closer to the load. Another solution to
flatten the AC response is to place resistance close to the
LT5524 outputs. In this way the connection line behaves
more like a terminated transmission line, and the AC
peaking due to the capacitive load can be removed.
Note that these LC networks may distort the output signal
if their amplitude and phase response exhibit nonlinear
behavior. For example, if resistors R1 and R2 in Figure 5
are replaced with LC resonant tank circuits, then severe
OIP3 degradation may occur.
Low Output Noise Floor Applications
In some applications the maximum output noise floor is
specified. The LT5524 outputnoise flooris elevated above
the available noise power (–174dBm/Hz into 50Ω) by the
NF+Gain. Consequently, reductionoftheLT5524’spower
gain is the only way to reduce the output noise floor.
Bandpass Applications
For narrow band IF applications, the LT5524’s output
capacitance and the application load capacitance can be
incorporated as part of an LC impedance transformation
NOTE:
C3 + C
C4 + C
= 12pF
= 12pF
LOAD
LOAD
V
OSUP
C7
0.1µF
V
CC
L5
L6
C1
C8
L3
56nH
56nH
56nH
C3
12pF
0.1µF
T1
LT5524
1:2
+
–
R
IN
–
LOAD
C
C
LOAD
50Ω
R
C6
2.2pF
C5
5.6pF L4
56nH
R
OUT
LOAD
DUT
C2
12pF
200Ω
100Ω
R
SRC
IN
+
50Ω
C9
0.33µF
R
LOAD
TC2-1T
V
LOAD
SRC
C4
50Ω
GAIN = 27dB
1dB BANDWIDTH:
f
f
= 130MHz
= 220MHz
L
U
PGA0 PGA1 PGA2 PGA3
5524 F08
Figure 8. Bandpass Output Transformation Network Example
5524f
12
LT5524
W U U
APPLICATIO S I FOR ATIO
U
In fixed gain applications, the LT5524 can be set to 3dB
attenuation relative to maximum gain. As shown in the
Typical Performance Characteristics, this gives a 2dB
reduction in the output noise floor with no loss of linearity.
Rather, it represents a compromise that most accurately
measures the actual operation of the part by itself,
undistortedbytheartifactsoftheimpedancetransformation
network, or by external bandwidth limiting factors. Balun
transformers are used to interface with single-ended test
equipment. Input and output resistive attenuators (not
shown) provide broadband I/O impedance control. The
L1, L2 inductors are selected for maximally flat AC output
response. COUT (normally open) shows the placement of
capacitive loading when this is specified as a
characterization variable. The VCCO monitor pin allows
setting the output DC level (5V typical) by adjusting
In general, the output noise floor can be reduced by
decreasing ROUT (and hence power gain), at the cost of
reduced OIP3.
LT5524 Characterization
The LT5524’s typical performance data are based on the
test circuits shown in Figures 9 and 10. Figure 9 does not
necessarily reflect the use of the LT5524 in an actual
application. (For that, see the Application Boards section.)
voltage VOSUP
.
V
V
OSUP
CC
C4
C3
4.7µF
C2
R1
R2
0.1µF
R10
R9
0.1µF
25Ω 25Ω
C1
35.7Ω
35.7Ω
0.33µF
C
OUT
C7
47nF
C5
47nF
L1
R3
37.4Ω
R7
(OPT)
(OPT)
LT5524
T1
1:1
35.7Ω
T1
1:1
+
IN
–
C8
47nF
C6
47nF
R
R
L2
(OPT)
LOAD
R8
OUT
R4
37.4Ω
DUT
50Ω
35.7Ω
–
R
50Ω
SRC
IN +
C
ETC-1-
1-13
ATT =
7.7dB
ETC-1-
1-13
OUT
R5
51k 51k
R6
(OPT)
V
SRC
R
R3, R4 ATT L1, L2
OUT
100Ω 37.4Ω 9dB 0Ω
200Ω 87.4Ω 12dB 33nH
V
CCO
PGA0 PGA1 PGA2 PGA3
MONITOR
5524 F09
Figure 9. Characterization Board (Simplified Schematic)
V
CC
C2
0.1µF
EN
V
OSUP
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
C4
0.1µF
C3
EN
V
NC
NC
IF
4.7µF
V
OUT
IF
IN
CC1
CC2
T2
4:1
T1
1:2
GND
GND
GND
GND
LT5524
•
•
•
+
–
R
LOAD
50Ω
IN
IN
OUT
R
R
MATCH
OUT
–
+
255Ω
100Ω
OUT
GND
GND
PGA0
PGA1
GND
GND
PGA3
PGA2
C1
0.47µF
J2
0Ω
J1
0Ω
TC4-1W
TC2-1T
10
PGA0 PGA1
PGA2 PGA3
TRANSFORMER DEMO BOARD
5524 F10
Figure 10. Output Transformer Application Board (Simplified Schematic)
5524f
13
LT5524
W U U
U
APPLICATIO S I FOR ATIO
Application (Demo) Boards
(T2 transformer). For the Typical Performance Character-
istics curves, all linearity tests are performed on this
board. By removing RMATCH, the performance with ROUT
= 200Ω can be evaluated (provided the lack of impedance
back-matching is suitably remedied).
The LT5524 demo boards are provided in the versions
shown in Figure 10 (with output transformer) and Fig-
ure 11 (without output transformer). All I/O signal ports
are matched to 50Ω. Moreover, 40k resistors (not shown)
connect all five control pins (EN, PGA0, PGA1, PGA2,
PGA3) to VCC, such that the LT5524 is shipped in maxi-
mum gain state.
The transformer board can provide a differential output
when Jumper J2 is removed.
The Wideband Differential Output Application Board (Fig-
ure 11) is an example of direct coupling (no transformer)
to the load, and has wider output bandwidth. This board
gives direct access to the LT5524’s output pins, and was
used for stability tests. Higher VOSUP (6.5V) is required to
compensate for the DC voltage drop on R1 and R2. Use
TP2, TP3 to monitor the actual LT5524 output bias volt-
age. ByreplacingR1andR2withinductors, thisboardcan
operate with a 5V supply. However, this may limit the
minimum signal frequency. For example, an 820nH choke
inductor will limit the lowest signal frequency to 40MHz.
The gain setting can be changed by connecting the control
pins to ground. Test points (TP1, TP2, TP3) are provided
to monitor the input and output DC bias voltage. Jumper
J1 can be removed when differential input is desired, but
in that case, T1 should be changed to a 1:1 center-tap
transformer to preserve 50Ω input matching. The demo
board is shipped with optional output back-matching
resistor RMATCH = 255Ω. This results in a net output load,
ROUT = 100Ω, presented to the LT5524.
The Output Transformer Application Board (Figure 10) is
one example of an output impedance transformation
V
CC
EN
C2
0.1µF
V
OSUP
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
C4
C3
EN
V
NC
NC
R1
R2
IF
0.1µF
4.7µF
50Ω 50Ω
V
OUT
IF
IN
CC1
CC2
T1
1:2
GND
GND
GND
GND
LT5524
+
–
C5
47nF
R
LOAD
IN
IN
OUT
OUT
R
OUT
100Ω
–
+
50Ω
GND
GND
PGA0
PGA1
GND
GND
PGA3
PGA2
C1
0.47µF
J1
0Ω
TC2-1T
J2
0PEN
C6
47nF
10
DIFFERENTIAL OUTPUT
RESISTIVE DEMO BOARD
PGA0 PGA1
PGA2 PGA3
5524 F11
Figure 11. Wideband Differential Output Application Board (Simplified Schematic)
5524f
14
LT5524
U
PACKAGE DESCRIPTIO
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation CB
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
3.86
(.152)
20 1918 17 16 15 14 1312 11
6.60 ±0.10
2.74
(.108)
4.50 ±0.10
6.40
(.252)
BSC
2.74
(.108)
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
5
7
8
1
2
3
4
6
9 10
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.047)
MAX
4.30 – 4.50*
(.169 – .177)
0.25
REF
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.20
(.0035 – .0079)
0.50 – 0.75
(.020 – .030)
0.05 – 0.15
(.002 – .006)
FE20 (CB) TSSOP 0204
0.195 – 0.30
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
5524f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LT5524
RELATED PARTS
PART NUMBER DESCRIPTION
Infrastructure
COMMENTS
LT5511
LT5512
LT5514
High Linearity Upconverting Mixer
RF Output to 3GHz, 17dBm IIP3, Integrated LO Buffer
DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
DC-3GHz High Signal Level Downconverting Mixer
Ultralow Distortion IF Amplifier/ADC Driver with Digitally
Controlled Gain
47dBm OIP3 at 100MHz, 33dB Maximum Gain, 22.5dB Gain
Control Range
LT5515
LT5516
LT5517
LT5519
1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator
0.8GHz to 1.5GHz Direct Conversion Quadrature Demodulator
40MHz to 900MHz Quadrature Demodulator
20dBm IIP3, Integrated LO Quadrature Generator
21.5dBm IIP3, Integrated LO Quadrature Generator
21dBm IIP3, Integrated LO Quadrature Generator
0.7GHz to 1.4GHz High Linearity Upconverting Mixer
17.1dBm IIP3 at 1GHz, Integrated RF Output Transformer with 50Ω
Matching, Single-Ended LO and RF Ports Operation
LT5520
LT5521
LT5522
LT5526
1.3GHz to 2.3GHz High Linearity Upconverting Mixer
3.7GHz Very High Linearity Upconverting Mixer
15.9dBm IIP3 at 1.9GHz, Integrated RF Output Transformer with 50Ω
Matching, Single-Ended LO and RF Ports Operation
24.2dBm IIP3 at 1.9GHz, Wide 3.15V to 5.25V Supply Range,
–5dBm LO Drive, –42dBm LO-RF Leakage
600MHz to 2.7GHz High Signal Level Downconverting Mixer
High Linearity, Low Power Downconverting Mixer
4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB,
50Ω Single-Ended RF and LO Ports
16.5dBm IIP3, 0.6dB Gain, 11dB NF at 900MHz,
28mA Supply Current
RF Power Detectors
LT5504
800MHz to 2.7GHz RF Measuring Receiver
80dB Dynamic Range, Temperature Compensated,
2.7V to 5.25V Supply
LTC®5505
LTC5507
LTC5508
LTC5509
LTC5530
LTC5531
LTC5532
LT5534
RF Power Detectors with >40dB Dynamic Range
100kHz to 1000MHz RF Power Detector
300MHz to 3GHz, Temperature Compensated, 2.7V to 6V Supply
100kHz to 1GHz, Temperature Compensated, 2.7V to 6V Supply
44dB Dynamic Range, Temperature Compensated, SC70 Package
36dB Dynamic Range, Low Power Consumption, SC70 Package
300MHz to 7GHz RF Power Detector
300MHz to 3GHz RF Power Detector
300MHz to 7GHz Precision RF Power Detector
300MHz to 7GHz Precision RF Power Detector
300MHz to 7GHz Precision RF Power Detector
50MHz to 3GHz Wide Dynamic Range Log RF Power Detector
Precision V
Precision V
Precision V
Offset Control, Shutdown, Adjustable Gain
Offset Control, Shutdown, Adjustable Offset
Offset Control, Adjustable Gain and Offset
OUT
OUT
OUT
60dB Dynamic Range, Superb Temperature Stability and Accuracy,
Low Supply Current, SC70 Package
LTC5535
Precision RF Detector with 12MHz Baseband Bandwidth
600MHz to 7GHz Adjustable Gain, Precision V
Offset Control
OUT
Low Voltage RF Building Blocks
LT5500
LT5502
1.8GHz to 2.7GHz Receiver Front End
1.8V to 5.25V Supply, Dual-Gain LNA, Mixer, LO Buffer
400MHz Quadrature IF Demodulator with RSSI
1.8V to 5.25V Supply, 70MHz to 400MHz IF, 84dB Limiting Gain,
90dB RSSI Range
LT5503
LT5506
LT5546
1.2GHz to 2.7GHz Direct IQ Modulator and
Upconverting Mixer
1.8V to 5.25V Supply, Four-Step RF Power Control,
120MHz Modulation Bandwidth
500MHz Quadrature IF Demodulator with VGA
1.8V to 5.25V Supply, 40MHz to 500MHz IF, –4dB to 57dB
Linear Power Gain, 8.8MHz Baseband Bandwidth
500MHz Ouadrature IF Demodulator with
VGA and 17MHz Baseband Bandwidth
17MHz Baseband Bandwidth, 40MHz to 500MHz IF, 1.8V to 5.25V
Supply, –7dB to 56dB Linear Power Gain
5524f
LT/TP 0904 1K • PRINTED IN THE USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
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相关型号：
LT5525EUF#PBF
LT5525 - High Linearity, Low Power Downconverting Mixer; Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C
Linear
LT5525EUF#TR
LT5525 - High Linearity, Low Power Downconverting Mixer; Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C
Linear
LT5525EUF#TRPBF
LT5525 - High Linearity, Low Power Downconverting Mixer; Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C
Linear
LT5526EUF#PBF
LT5526 - High Linearity, Low Power Downconverting Mixer; Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C
Linear
LT5526EUF#TRPBF
LT5526 - High Linearity, Low Power Downconverting Mixer; Package: QFN; Pins: 16; Temperature Range: -40°C to 85°C
Linear
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