LTC1657LIN#PBF_技术文档

LTC1657

Parallel 16-Bit Rail-to-Rail

Micropower DAC

U

DESCRIPTIO

FEATURES

The LTC^®1657 is a complete single supply, rail-to-rail

voltageoutput, 16-bitdigital-to-analogconverter(DAC)in

a 28-pin SSOP or PDIP package. It includes a rail-to-rail

output buffer amplifier, an internal 2.048V reference and

a double buffered parallel digital interface.

■

16-Bit Monotonic Over Temperature

■

Deglitched Rail-to-Rail Voltage Output: 8nV•s

■

5V Single Supply Operation

■

I_CC: 650µA Typ

■

Maximum DNL Error: ±1LSB

■

Settling Time: 20µs to ±1LSB

The LTC1657 operates from a 4.5V to 5.5V supply. It has

a separate reference input pin that can be driven by an

external reference. The full-scale output can be 1 or 2

times the reference voltage depending on how the X1/X2

pin is connected.

■

Internal or External Reference

■

Internal Power-On Reset to Zero Volts

■

Asynchronous CLR Pin

■

Output Buffer Configurable for Gain of 1 or 2

■

Parallel 16-Bit or 2-Byte Double Buffered Interface

TheLTC1657issimilartoLinearTechnologyCorporation’s

LTC1450 12-bit V_OUTDAC family allowing an upgrade

path. It is the only buffered 16-bit parallel DAC in a 28-lead

SSOP package and includes an onboard reference for

stand alone performance.

■

Narrow 28-Lead SSOP Package

Multiplying Capability

■

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APPLICATIO S

■

Instrumentation

, LTC and LT are registered trademarks of Linear Technology Corporation.

■

Digital Calibration

■

Industrial Process Control

Automatic Test Equipment

Communication Test Equipment

■

W

BLOCK DIAGRA

5V

24

23

22

V

REFOUT

REFHI

CC

19 D15 (MSB)

18

17

16

15

14

13

12

D8

REFERENCE

2.048V

MSB

8-BIT

Differential Nonlinearity

vs Input Code

INPUT

REGISTER

1.0

0.8

16-BIT

DAC

REGISTER

DATA IN FROM

MICROPROCESSOR

DATA BUS

16-BIT

DAC

+

–

V

OUT

25

11

10

9

D7

0V TO

4.096V

0.6

0.4

LSB

8-BIT

0.2

8

R

7

0.0

INPUT

6

REGISTER

–0.2

–0.4

–0.6

–0.8

–1.0

R

5

D0 (LSB)

CSMSB

4

3

1

2

WR

FROM

MICROPROCESSOR

DECODE LOGIC

0

16384

DIGITAL INPUT CODE

32768

49152

65535

CSLSB

1657 G01

28 LDAC

27 CLR

POWER-ON

RESET

FROM

SYSTEM RESET

GND

20

REFLO

21

X1/X2

26

1657 TA01

1

LTC1657

W W U W

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ABSOLUTE MAXIMUM RATINGS

PACKAGE/ORDER INFORMATION

(Note 1)

TOP VIEW

V_CCto GND .............................................. –0.5V to 7.5V

TTL Input Voltage, REFHI, REFLO,

X1/X2....................................................... –0.5V to 7.5V

ORDER PART

NUMBER

1

2

LDAC

CLR

28

27

26

25

24

23

22

21

20

19

18

17

16

15

WR

CSLSB

CSMSB

(LSB) D0

D1

LTC1657CGN

LTC1657CN

LTC1657IGN

LTC1657IN

3

X1/X2

V

_OUT, REFOUT ............................ –0.5V to (V_CC+ 0.5V)

4

V

OUT

Operating Temperature Range

5

V

CC

LTC1657C ............................................. 0°C to 70°C

LTC1657I ........................................ –40°C to 85°C

Maximum Junction Temperature .......................... 125°C

Storage Temperature Range ................ –65°C to 150°C

Lead Temperature (Soldering, 10 sec)................. 300°C

6

REFOUT

REFHI

REFLO

GND

D2

7

D3

8

D4

9

D5

10

11

12

13

14

D15 (MSB)

D14

D6

D7

D13

D8

D12

D9

D11

D10

N PACKAGE

28-LEAD PDIP

GN PACKAGE

28-LEAD PLASTIC SSOP

T_JMAX= 125°C, θ_JA= 95°C/ W (G)

_JMAX= 125°C, θ_JA= 58°C/ W (N)

T

Consult factory for Military grade parts.

ELECTRICAL CHARACTERISTICS ^The● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= 4.5V to 5.5V, V_OUTunloaded, REFOUT tied to REFHI,

REFLO tied to GND, X1/X2 tied to GND, unless otherwise noted.

SYMBOL PARAMETER

DAC (Note 2)

CONDITIONS

MIN

TYP

MAX

UNITS

Resolution

●

16

Bits

Monotonicity

DNL

INL

Differential Nonlinearity

Guaranteed Monotonic (Note 3)

(Note 3)

±0.5

±4

±1.0

±12

2

LSB

Integral Nonlinearity

Zero Scale Error

Offset Error

LSB

ZSE

0

mV

V

Measured at Code 200

±0.3

±5

±3

mV

OS

TC

Offset Error Tempco

Gain Error

µV/°C

LSB

●

±2

±16

Gain Error Drift

0.5

ppm/°C

Power Supply

V

Positive Supply Voltage

Supply Current

For Specified Performance

●

4.5

5.5

V

CC

I

4.5V ≤ V ≤ 5.5V (Note 4)

650

1200

µA

CC

Op Amp DC Performance

Short-Circuit Current Low

V

Shorted to GND

●

70

80

40

120

140

120

4

mA

OUT

Short-Circuit Current High

Output Impedance to GND

Output Line Regulation

Shorted to V

CC

Input Code = 0

Input Code = 65535, V = 4.5V to 5.5V

Ω

mV/V

CC

2

LTC1657

ELECTRICAL CHARACTERISTICS ^The● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= 4.5V to 5.5V, V_OUTunloaded, REFOUT tied to REFHI,

REFLO tied to GND, X1/X2 tied to GND, unless otherwise noted.

SYMBOL PARAMETER

AC Performance

CONDITIONS

MIN

TYP

MAX

UNITS

Voltage Output Slew Rate

(Note 5)

●

±0.3

±0.7

V/µs

Voltage Output Settling Time

(Note 5) to 0.0015% (16-Bit Settling Time)

(Note 5) to 0.012% (13-Bit Settling Time)

20

10

µs

Digital Feedthrough

0.3

8

nV•s

Midscale Glitch Impulse

DAC Switch Between 8000 and 7FFF

H

Output Voltage Noise Spectral Density

At 1kHz

250

nV/√Hz

Digital I/O

V

Digital Input High Voltage

Digital Input Low Voltage

Digital Output High Voltage

Digital Output Low Voltage

Digital Input Leakage

●

2.4

V

IH

IL

0.8

V

– 1

CC

V

OH

OL

0.4

±10

10

V

I

V

= GND to V

CC

µA

pF

LEAK

IN

C

Digital Input Capacitance

(Note 6)

IN

Switching Characteristics

t

CS (MSB or LSB) Pulse Width

WR Pulse Width

●

40

ns

CS

40

0

WR

CS to WR Setup

CWS

CWH

DWS

DWH

LDAC

CLR

CS to WR Hold

0

Data Valid to WR Setup

Data Valid to WR Hold

LDAC Pulse Width

CLR Pulse Width

40

0

40

Reference Output (REFOUT)

Reference Output Voltage

●

2.036

2.048

15

2.060

V

Reference Output

ppm/°C

Temperature Coefficient

Reference Line Regulation

Reference Load Regulation

Short-Circuit Current

V

= 4.5V to 5.5V

●

±1.5

5

mV/V

mV/A

mA

CC

Measured at I

= 100µA

OUT

REFOUT Shorted to GND

50

100

Reference Input

REFHI, REFLO Input Range

(Note 6) See Applications Information

X1/X2 Tied to V

X1/X2 Tied to GND

●

0

V

– 1.5

V /2

CC

V

OUT

CC

REFHI Input Resistance

●

16

25

kΩ

Note 4: Digital inputs at 0V or V

.

Note 1: Absolute Maximum Ratings are those values beyond which the life

CC

of a device may be impaired.

Note 2: External reference REFHI = 2.2V. V = 5V.

Note 5: DAC switched between all 1s and all 0s.

Note 6: Guaranteed by design. Not subject to test.

CC

Note 3: Nonlinearity is defined from code 128 to code 65535 (full scale).

See Applications Information.

3

LTC1657

TYPICAL PERFOR A CE CHARACTERISTICS

U W

Minimum Supply Headroom for

Full Output Swing vs Load Current

Differential Nonlinearity

Integral Nonlinearity

1.0

0.8

5

4

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

CODE ALL 1’S

OUT

∆V

≤ 1LSB

0.6

3

0.4

2

125°C

0.2

1

0.0

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1

–2

–3

–4

–5

25°C

–55°C

0

16384

32768

49152

65535

0

16384

32768

49152

65535

0

5

10

DIGITAL INPUT CODE

LOAD CURRENT (mA)

1657 G01

1657 G02

1657 G03

Minimum Output Voltage vs

Output Sink Current

Full-Scale Voltage vs

Temperature

Offset Error vs Temperature

1.2

1.0

0.8

0.6

0.4

0.2

0

4.110

4.105

4.100

4.095

4.090

4.085

4.080

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

CODE ALL 0’S

OUT

∆V

≤ 1LSB

125°C

25°C

–55°C

0

5

10

15

–55

–25

5

35

65

95

125

–55

–10

35

80

125

OUTPUT SINK CURRENT (mA)

TEMPERATURE (°C)

1657 G04

1657 G05

1657 G06

Supply Current vs Logic Input

Voltage

Supply Current vs Temperature

Large-Signal Transient Response

8

7

6

5

4

3

2

1

0

700

680

660

640

620

600

580

560

540

520

500

5

V

A

UNLOADED

OUT

T

= 25°C

4

3

2

1

0

V

= 5.5V

CC

V

= 5V

CC

= 4.5V

CC

0

1

2

3

4

5

–55 –35 –15

5

25 45 65 85 105 125

LOGIC INPUT VOLTAGE (V)

TEMPERATURE (°C)

TIME (20µs/DIV)

1657 G07

1657 G08

1657 G09

4

LTC1657

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PIN FUNCTIONS

WR (Pin 1): Write Input (Active Low). Used with CSMSB

and/orCSLSBtocontroltheinputregisters. WhileWRand

CSMSB and/or CSLSB are held low, data writes into the

input register.

the output buffer to this end of the ladder. Can be used to

offset the zero scale above ground.

REFHI (Pin 22): Upper input terminal of the DAC’s internal

resistor ladder. Typically connected to REFOUT. An input

code of (FFFF)_Hwill connect the positive input of the

output buffer to 1LSB below this voltage.

CSLSB (Pin 2): Chip Select Least Significant Byte (Active

Low). Used with WR to control the LSB 8-bit input regis-

ters. While WR and CSLSB are held low, the LSB byte

writes into the LSB input register. Can be connected to

CSMSB for simultaneous loading of both sets of input

latches on a 16-bit bus.

REFOUT(Pin23):Outputoftheinternal2.048Vreference.

TypicallyconnectedtoREFHItodriveinternalDACresistor

ladder.

V

_CC(Pin 24): Positive Power Supply Input. 4.5V ≤ V_CC≤

CSMSB (Pin 3): Chip Select Most Significant Byte (Active

Low). Used with WR to control the MSB 8-bit input

registers. While WR and CSMSB are held low, the MSB

byte writes into the MSB input register. Can be connected

to CSLSB for simultaneous loading of both sets of input

latches on a 16-bit bus.

5.5V. Requires a 0.1µF bypass capacitor to ground.

V_OUT(Pin 25): Buffered DAC Output.

X1/X2(Pin26):GainSettingResistorPin. ConnecttoGND

for G = 2 or to V_OUTfor G = 1. This pin should always be

tied to a low impedance source, such as ground or V_OUT

,

to ensure stability of the output buffer when driving

capacitive loads.

D0toD7(Pins4to11):InputdatafortheLeastSignificant

Byte. Written into LSB input register when WR = 0 and

CSLSB = 0.

CLR (Pin 27): Clear Input (Asynchronous Active Low). A

low on this pin asynchronously resets all input and DAC

registers to 0s.

D8 to D15 (Pins 12 to 19): Input data for the Most Signifi-

cant Byte. Written into MSB input register when WR = 0

and CSMSB = 0.

LDAC (Pin 28): Load DAC (Asynchronous Active Low).

Used to asynchronously transfer the contents of the input

registers to the DAC register which updates the output

voltage. If held low, the DAC register loads data from the

GND (Pin 20): Ground.

REFLO (Pin 21): Lower input terminal of the DAC’s inter-

nal resistor ladder. Typically connected to Analog Ground.

An input code of (0000)_Hwill connect the positive input of

input registers which will immediately update V_OUT

.

5

LTC1657

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DIGITAL INTERFACE TRUTH TABLE

CLR

CSMSB

CSLSB

WR

LDAC

FUNCTION

L

X

L

H

L

X

H

X

L

X

H

L

X

L

Clears input and DAC registers to zero

Loads DAC register with contents of input registers

Freezes contents of DAC register

Writes MSB byte into MSB input register

Writes LSB byte into LSB input register

Writes MSB and LSB bytes into MSB and LSB input registers

Inhibits write to MSB and LSB input registers

Inhibits write to MSB input register

H

X

L

H

X

L

H

X

L

X

H

L

Inhibits write to LSB input register

Data bus flows directly through input and DAC registers

H

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W

TIMING DIAGRAM

t

CS

CSLSB

t

CS

CSMSB

t

WR

CWH

CWS

t

WR

t

LDAC

DWH

t

DWS

DAC UPDATE

DATA VALID

DATA

1657 TD

6

LTC1657

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DEFI ITIO S

Resolution (n): Resolution is defined as the number of

digital input bits (n). It defines the number of DAC output

states(2ⁿ)thatdividethefull-scalerange.Resolutiondoes

not imply linearity.

Zero-Scale Error (ZSE): The output voltage when the

DAC is loaded with all zeros. Since this is a single supply

part, this value cannot be less than 0V.

Integral Nonlinearity (INL): End-point INL is the maxi-

mum deviation from a straight line passing through the

end points of the DAC transfer curve. Because the part

operates from a single supply and the output cannot go

below zero, the linearity is measured between full scale

and the code corresponding to the maximum offset

specification. The INL error at a given input code is

calculated as follows:

Full-Scale Voltage (V_FS): This is the output of the DAC

when all bits are set to 1.

VoltageOffsetError(V_OS): Normally,theDACoffsetisthe

voltageattheoutputwhentheDACisloadedwithallzeros.

The DAC can have a true negative offset, but because the

partisoperatedfromasinglesupply, theoutputcannotgo

below zero. If the offset is negative, the output will remain

near 0V resulting in the transfer curve shown in Figure 1.

INL (In LSBs) = [V_OUT– V_OS– (V_FS– V_OS)

(code/65535)]

V_OUT= The output voltage of the DAC measured at

the given input code

OUTPUT

VOLTAGE

Differential Nonlinearity (DNL): DNL is the difference

between the measured change and the ideal one LSB

change between any two adjacent codes. The DNL error

between any two codes is calculated as follows:

0V

NEGATIVE

OFFSET

DAC CODE

1657 F01

Figure 1. Effect of Negative Offset

DNL = (∆V_OUT– LSB)/LSB

∆V_OUT= The measured voltage difference between

two adjacent codes

The offset of the part is measured at the code that corre-

sponds to the maximum offset specification:

DigitalFeedthrough: Theglitchthatappearsattheanalog

outputcausedbyACcouplingfromthedigitalinputswhen

they change state. The area of the glitch is specified in

nV • s.

V_OS= V_OUT– [(Code)(V_FS)/(2ⁿ– 1)]

Least Significant Bit (LSB): One LSB is the ideal voltage

difference between two successive codes.

LSB = (V_FS– V_OS)/(2ⁿ– 1) = (V_FS– V_OS)/65535

Nominal LSBs:

LTC1657 LSB = 4.096V/65535 = 62.5µV

DAC Transfer Characteristic:

REFHI–REFLO

V_OUT= G•

CODE +REFLO

(

)

65536

G = 1 for X1/X2 connected to V_OUT

G = 2 for X1/X2 connected to GND

CODE = Decimal equivalent of digital input

(0 ≤ CODE ≤ 65535)

7

LTC1657

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OPERATION

Parallel Interface

to the DAC resistor ladder, an external reference can be

used or the resistor ladder can be driven by an external

source in multiplying applications. The external reference

or source must be capable of driving the 16k (minimum)

DAC ladder resistance.

The data on the input of the DAC is written into the DAC’s

inputregisterswhenChipSelect(CSLSBand/orCSMSB)

and WR are at a logic low. The data that is written into the

input registers will depend on which of the Chip Selects

areatalogiclow(seeDigitalInterfaceTruthTable). IfWR

and CSLSB are both low and CSMSB is high, then only

data on the eight LSBs (D0 to D7) is written into the input

registers. Similarly, if WR and CSMSB are both low and

CSLSB is high, then only data on the eight MSBs (D8 to

D15) is written into the input registers. Data is written into

both the Least Significant Data Bits (D0 to D7) and the Most

Significant Bits (D8 to D15) at the same time if WR, CSLSB

and CSMSB are low. If WR is high or both CSMSB and

CSLSB are high, then no data is written into the input

registers.

Internal reference output noise can be reduced with a

bypass capacitor to ground. (Note: The reference does not

require a bypass capacitor to ground for nominal opera-

tion.)Whenbypassingthereference,asmallvalueresistor

inserieswiththecapacitorisrecommendedtohelpreduce

peakingontheoutput.A10Ωresistorinserieswitha4.7µF

capacitor is optimum for reducing reference generated

noise. Internal reference output voltage noise spectral

density at 1kHz is typically 150nV/√Hz.

DAC Resistor Ladder

The high and low end of the DAC ladder resistor string

(REFHI and REFLO, respectively) are not connected inter-

nally on this part. Typically, REFHI will be connected to

REFOUT and REFLO will be connected to GND. X1/X2

connectedtoGNDwillgivetheLTC1657afull-scaleoutput

swing of 4.096V.

Once data is written into the input registers, it can be

written into the DAC register. This will update the analog

voltage output of the DAC. The DAC register is written by

a logic low on LDAC. The data in the DAC register will be

held when LDAC is high.

When WR, CSLSB, CSMSB and LDAC are all low, the

registers are transparent and data on pins D0 to D15 flows

directly into the DAC register.

Either of these pins can be driven up to V_CC– 1.5V when

usingthebufferinthegain-of-1configuration.Theresistor

string pins can be driven to V_CC/2 when the buffer is in the

gain of 2 configuration. The resistance between these two

pins is typically 25k (16k min).

For an 8-bit data bus connection, tie the MSB byte data

pins to their corresponding LSB byte pins (D15 to D7, D14

to D6, etc).

Voltage Output

Power-On Reset

The output buffer for the LTC1657 can be configured for

two different gain settings. By tying the X1/X2 pin to GND,

the gain is set to 2. By tying the X1/X2 pin to V_OUT, the gain

is set to unity.

TheLTC1657hasaninternalpower-onresetthatresetsall

internal registers to 0’s on power-up (equivalent to the

CLR pin function).

Reference

The LTC1657 rail-to-rail buffered output can source or

sink 5mA within 500mV of the positive supply voltage or

groundatroomtemperature. Theoutputstageisequipped

with a deglitcher that results in a midscale glitch impulse

of 8nV • s. The output swings to within a few millivolts of

either supply rail when unloaded and has an equivalent

output resistance of 40Ω when driving a load to the rails.

The LTC1657 includes an internal 2.048V reference, giv-

ing the LTC1657 a full-scale range of 4.096V in the gain-

of-2 configuration. The onboard reference in the LTC1657

is not internally connected to the DAC’s reference resistor

string but is provided on an adjacent pin for flexibility.

Because the internal reference is not internally connected

8

LTC1657

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APPLICATIONS INFORMATION

Rail-to-Rail Output Considerations

Similarly, limiting can occur near full scale when the REF

pin is tied to V_CC/2. If V_REF= V_CC/2 and the DAC full-scale

error (FSE) is positive, the output for the highest codes

limits at V_CCas shown in Figure 1c. No full-scale limiting

can occur if V_REFis less than (V_CC– FSE)/2.

In any rail-to-rail DAC, the output swing is limited to

voltages within the supply range.

If the DAC offset is negative, the output for the lowest

codes limits at 0V as shown in Figure 1b.

Offset and linearity are defined and tested over the region

of the DAC transfer function where no output limiting can

occur.

POSITIVE

FSE

V

CC

V

= V /2

CC

OUTPUT

VOLTAGE

REF

INPUT CODE

(c)

V

CC

V

= V /2

CC

OUTPUT

VOLTAGE

REF

0

32768

65535

INPUT CODE

(a)

OUTPUT

VOLTAGE

0V

NEGATIVE

OFFSET

INPUT CODE

(b)

1657 F02

Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative

Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When V_REF= V_CC/2

9

LTC1657

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TYPICAL APPLICATIO S

the onboard reference is always sourcing current and

never has to sink any current even when V_OUTis at full

scale. The LT1077 output will have a wide bipolar output

swing of –4.096V to 4.096V as shown in the figure below.

With this output swing, 1LSB = 125µV.

This circuit shows how to make a bipolar output 16-bit

DAC with a wide output swing using an LTC1657 and an

LT1077. R1 and R2 resistively divide down the LTC1657

output and an offset is summed in using the LTC1657

onboard2.048VreferenceandR3andR4. R5ensuresthat

A Wide Swing, Bipolar Output 16-Bit DAC

5V

0.1µF

24

5:19

2

V

CC

DATA (0:15)

CSLSB

CSMSB

WR

3

25

µP

V

LTC1657

OUT

1

R1

100k

1%

28

27

5V

LDAC

CLR

3

2

X1/X2 REFLO GND REFHI REFOUT

7

+

–

26

21

20

22

23

6

(2)(D )(4.096)

IN

R2

200k

1%

LT1077

4

V

:

– 4.096V

OUT

65536

TRANSFER CURVE

4.096

R3

100k

1%

R4

200k

1%

–5V

1657 TA05

R5

100k

1%

32768

65535

0

V

D

IN

OUT

–4.096

Thiscircuitshowsadigitallyprogrammablecurrentsource

from an external voltage source using an external op amp,

an LT1218 and an NPN transistor (2N3440). Any digital

word from 0 to 65535 is loaded into the LTC1657 and its

output correspondingly swings from 0V to 4.096V. This

voltage will be forced across the resistor R_A. If R_Ais

chosen to be 412Ω, the output current will range from

0mA at zero scale to 10mA at full scale. The minimum

voltage for V_Sis determined by the load resistor R_Land

Q1’s V_CESATvoltage. With a load resistor of 50Ω, the

voltage source can be 5V.

Digitally Programmable Current Source

5V

22

23

5V < V < 100V

S

FOR R ≤ 50Ω

0.1µF

5:19

2

L

REFHI REFOUT

V

CC

DATA (0:15)

CSLSB

CSMSB

WR

(D )(4.096)

IN

3

R

L

I

=

7

OUT

25

3

(65536)(R )

µP

A

LTC1657

V

OUT

+

1

≈ 0mA TO 10mA

6

Q1

2N3440

28

27

LT1218

LDAC

2

CLR

–

X1/X2 REFLO GND

26 21 20

4

R

A

412Ω

1%

1657 TA04

10

LTC1657

U

PACKAGE DESCRIPTIO

Dimensions in inches (millimeters) unless otherwise noted.

GN Package

28-Lead Plastic SSOP (Narrow 0.150)

(LTC DWG # 05-08-1641)

0.386 – 0.393*

(9.804 – 9.982)

0.033

(0.838)

REF

28 27 26 25 24 23 22 21 20 19 18 17 1615

0.229 – 0.244

(5.817 – 6.198)

0.150 – 0.157**

(3.810 – 3.988)

1

2

3

4

5

6

7

8

9

10 11 12 13 14

0.004 – 0.009

0.015 ± 0.004

(0.38 ± 0.10)

0.053 – 0.069

× 45°

(1.351 – 1.748)

(0.102 – 0.249)

0.0075 – 0.0098

(0.191 – 0.249)

0° – 8° TYP

0.016 – 0.050

(0.406 – 1.270)

0.008 – 0.012

(0.203 – 0.305)

0.0250

(0.635)

BSC

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

GN28 (SSOP) 1098

N Package

28-Lead PDIP (Narrow 0.300)

(LTC DWG # 05-08-1510)

1.370*

(34.789)

MAX

28 27 26 25 24

23 22 21 20

19 18 17 16 15

0.255 ± 0.015*

(6.477 ± 0.381)

1

2

3

4

5

6

7

8

9

10

11 12

13 14

0.300 – 0.325

(7.620 – 8.255)

0.045 – 0.065

(1.143 – 1.651)

0.130 ± 0.005

(3.302 ± 0.127)

0.020

(0.508)

MIN

0.065

(1.651)

TYP

0.009 – 0.015

(0.229 – 0.381)

+0.035

0.125

(3.175)

MIN

0.005

(0.127)

MIN

0.018 ± 0.003

(0.457 ± 0.076)

0.100

(2.54)

BSC

0.325

–0.015

+0.889

8.255

(

)

–0.381

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

N28 1098

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

11

LTC1657

U

TYPICAL APPLICATIO

This circuit shows how to measure negative offset. Since

LTC1657 operates on a single supply, if its offset is

negative, the output for code 0 limits at 0V. To measure

this negative offset, a negative supply is needed, connect

resistor R1 as shown in the figure. The output voltage is

the negative offset when code 0 is loaded in.

Negative Offset Measurement

5V

22

23

24

0.1µF

5:19

2

REFHI REFOUT

V

CC

DATA (0:15)

CSLSB

CSMSB

WR

3

25

µP

LTC1657

V

OUT

1

R1

100k

28

27

LDAC

CLR

X1/X2 REFLO GND

–5V

26

21

20

1657 TA06

Although LTC1657 output is up to 4.096V with its internal

reference, highervoltagescanbeachievedwiththehelpof

another op amp. The following circuit shows how to

increasetheoutputswingofLTC1657byusinganLT1218.

As shown in the configuration, the output of LTC1657 is

amplified by 8 for an output swing of 0V to 32.768V, or a

convenient 0.5mV/LSB.

A Higher Voltage Output DAC

5V

24

TRANSFER CURVE

V

OUT

36V

22

23

0.1µF

5:19

2

REFHI REFOUT

V

CC

32.768 (V)

DATA (0:15)

CSLSB

CSMSB

WR

0.1µF

3

7

25

3

2

µP

LTC1657

V

+

1

OUT

6

28

27

LT1218

4

LDAC

(D )(4.096)

IN

65536

R2

R1

CLR

–

X1/X2 REFLO GND

26 21 20

V

=

1 +

OUT

(

)

D

IN

0

65535

R1

R2

6.98k

1%

1k

1%

1657 TA07

RELATED PARTS

PART NUMBER

LTC1446(L)

LTC1450(L)

LTC1458(L)

LTC1650

DESCRIPTION

COMMENTS

Dual 12-Bit V

DACs in SO-8 Package

V

CC

V

CC

V

CC

V

CC

V

CC

= 5V (3V), V

= 0V to 4.095V (0V to 2.5V)

OUT

Single 12-Bit V

DACs with Parallel Interface

OUT

Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality

Single 16-Bit V

Industrial DAC in 16-Pin SO

= ±5V, Low Power, Deglitched, 4-Quadrant Multiplying V

OUT

LTC1655(L)

DAC with Serial Interface in SO-8

= 5V (3V), Low Power, Deglitched, V

= 0V to 4.096V

OUT

(0V to 2.5V)

1657f LT/TP 0400 4K • PRINTED IN USA

LINEAR TECHNOLOGY CORPORATION 1999

12 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408)432-1900 FAX:(408)434-0507 www.linear-tech.com


型号：	LTC1657LIN#PBF
厂家：	Linear
描述：	LTC1657 - Parallel 16-Bit Rail-to-Rail Micropower DAC; Package: PDIP; Pins: 28; Temperature Range: -40°C to 85°C
文件：	总12页 (文件大小：197K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1657LIN#PBF [Linear]

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