LTC1657LIN [Linear]
Parallel 16-Bit Rail-to-Rail Micropower DAC; 并行16位轨至轨微DAC
| 型号： | LTC1657LIN |
| 厂家： | 
Linear |
| 描述： | Parallel 16-Bit Rail-to-Rail Micropower DAC |
| 文件： | 总12页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Final Electrical Specifications
LTC1657L
Parallel 16-Bit Rail-to-Rail
Micropower DAC
U
April 2000
DESCRIPTION
FEATURES
The LTC®1657L is a complete single supply, rail-to-rail
voltageoutput, 16-bitdigital-to-analogconverter(DAC)in
a 28-pin SSOP or PDIP package. It includes a rail-to-rail
output buffer amplifier, an internal 1.25V reference and a
double buffered parallel digital interface.
■
16-Bit Monotonic Over Temperature
■
3V Single Supply Operation
■
Deglitched Rail-to-Rail Voltage Output: 8nV • s
■
ICC: 650µA Typ
■
Maximum DNL Error: ±1LSB
■
Settling Time: 20µs to ±1LSB
The LTC1657L operates from a 2.7V to 5.5V supply. It has
a separate reference input pin that can be driven by an
external reference. The full-scale output can be 1 or 2
times the reference voltage depending on how the X1/X2
pin is connected.
■
Internal or External Reference
■
Internal Power-On Reset to 0V
■
Asynchronous CLR Pin
■
Output Buffer Configurable for Gain of 1 or 2
■
Parallel 16-Bit or 2-Byte Double Buffered Interface
■
TheLTC1657LissimilartoLinearTechnologyCorporation’s
LTC1450 12-bit VOUT DAC family allowing an easy up-
grade path. It is the only buffered 16-bit parallel DAC in a
28-lead SSOP package and includes an onboard reference
for stand alone performance.
Narrow 28-Lead SSOP Package
5V Version Available (LTC1657)
■
U
APPLICATIONS
■
Instrumentation
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
Industrial Process Control
■
Automatic Test Equipment
Communication Test Equipment
■
W
BLOCK DIAGRA
2.7V TO 5.5V
24
23
22
V
REFOUT
REFHI
CC
19 D15 (MSB)
18
17
16
15
14
13
12
D8
REFERENCE
1.25V
MSB
8-BIT
Differential Nonlinearity
vs Input Code
INPUT
REGISTER
1.0
0.8
16-BIT
DAC
REGISTER
DATA IN FROM
MICROPROCESSOR
DATA BUS
16-BIT
DAC
+
–
V
OUT
25
11
10
9
D7
0V TO
2.5V
0.6
0.4
LSB
8-BIT
8
0.2
R
7
0
INPUT
6
REGISTER
–0.2
–0.4
–0.6
–0.8
–1.0
R
5
D0 (LSB)
CSMSB
4
3
1
2
WR
FROM
MICROPROCESSOR
DECODE LOGIC
0
16484
32768
CODE
49152
65535
CSLSB
28 LDAC
27 CLR
1657 TA02
POWER-ON
RESET
FROM
SYSTEM RESET
GND
20
REFLO
21
X1/X2
26
1657 TA01
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
1
LTC1657L
W W U W
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ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Note 1)
TOP VIEW
VCC to GND .............................................. –0.5V to 7.5V
TTL Input Voltage,
ORDER PART
NUMBER
1
2
LDAC
CLR
28
27
26
25
24
23
22
21
20
19
18
17
16
15
WR
CSLSB
CSMSB
(LSB) D0
D1
REFHI, REFLO, X1/X2 .......................... –0.5V to 7.5V
LTC1657LCGN
LTC1657LCN
LTC1657LIGN
LTC1657LIN
3
X1/X2
V
OUT, REFOUT ............................ –0.5V to (VCC + 0.5V)
4
V
OUT
Operating Temperature Range
5
V
CC
LTC1657LC ............................................. 0°C to 70°C
LTC1657LI......................................... –40°C to 85°C
Maximum Junction Temperature .......................... 125°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
6
REFOUT
REFHI
REFLO
GND
D2
7
D3
8
D4
9
D5
10
11
12
13
14
D15 (MSB)
D14
D6
D7
D13
D8
D12
D9
D11
D10
N PACKAGE
28-LEAD PDIP
GN PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 95°C/ W (G)
JMAX = 125°C, θJA = 58°C/ W (N)
T
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded, REFOUT tied to REFHI,
REFLO tied to GND, X1/X2 tied to GND, unless otherwise noted.
SYMBOL PARAMETER
DAC (Note 2)
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
●
●
●
●
●
●
16
16
Bits
Bits
Monotonicity
DNL
INL
Differential Nonlinearity
Guaranteed Monotonic (Note 3)
(Note 3)
±0.5
±4
±1.0
±12
2
LSB
Integral Nonlinearity
Zero Scale Error
Offset Error
LSB
ZSE
0
mV
V
V
Measured at Code 200
±0.3
±5
±2
1
±4
mV
OS
OS
TC
Offset Error Tempco
Gain Error
µV/°C
LSB
●
±16
Gain Error Drift
ppm/°C
Power Supply
V
Positive Supply Voltage
Supply Current
For Specified Performance
●
●
2.7
5.5
V
CC
I
2.7V ≤ V ≤ 5.5V (Note 4)
650
1200
µA
CC
CC
Op Amp DC Performance
Short-Circuit Current Low
V
V
Shorted to GND
●
●
●
●
60
70
120
140
275
3
mA
mA
OUT
OUT
Short-Circuit Current High
Output Impedance to GND
Output Line Regulation
Shorted to V
CC
Input Code = 0
Input Code = 65535, V = 2.7V to 5.5V
120
Ω
mV/V
CC
2
LTC1657L
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded, REFOUT tied to REFHI,
REFLO tied to GND, X1/X2 tied to GND, unless otherwise noted.
SYMBOL PARAMETER
AC Performance
CONDITIONS
MIN
TYP
MAX
UNITS
Voltage Output Slew Rate
(Note 5)
●
±0.3
±0.7
V/µs
Voltage Output Settling Time
(Note 5) to 0.0015% (16-Bit Settling Time)
(Note 5) to 0.012% (13-Bit Settling Time)
20
10
µs
µs
Digital Feedthrough
0.3
8
nV•s
nV•s
Midscale Glitch Impulse
DAC Switch Between 8000 and 7FFF
H
H
Output Voltage Noise
Spectral Density
At 1kHz
200
nV/√Hz
Digital I/O (V = 3V)
CC
V
V
Digital Input High Voltage
●
●
●
2.0
V
V
IH
Digital Input Low Voltage
Digital Input Leakage
0.6
±10
10
IL
I
V
= GND to V
CC
µA
pF
LEAK
IN
C
Digital Input Capacitance
(Note 6)
IN
Switching Characteristics (V = 3V)
CC
t
t
t
t
t
t
t
t
CS (MSB or LSB) Pulse Width
WR Pulse Width
●
●
●
●
●
●
●
●
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
CS
WR
CS to WR Setup
CWS
CWH
DWS
DWH
LDAC
CLR
CS to WR Hold
0
Data Valid to WR Setup
Data Valid to WR Hold
LDAC Pulse Width
CLR Pulse Width
60
0
60
60
Reference Output (REFOUT)
Reference Output Voltage
●
1.24
1.25
15
1.26
V
Reference Output
ppm/°C
Temperature Coefficient
Reference Line Regulation
Reference Load Regulation
Short-Circuit Current
V
= 2.7V to 5.5V
●
●
●
±1
3
mV/V
mV/A
mA
CC
Measured at I
= 100µA
OUT
REFOUT Shorted to GND
50
23
100
Reference Input
REFHI, REFLO Input Range
(Note 6) See Applications Information
X1/X2 Tied to V
●
●
0
0
V
– 1.5
CC
V /2
CC
V
OUT
X1/X2 Tied to GND
REFHI Input Resistance
●
16
kΩ
Note 4: Digital inputs at 0V or V
.
Note 1: Absolute Maximum Ratings are those values beyond which the life
CC
of a device may be impaired.
Note 5: DAC switched between all 1s all 0s, slew rate is measured from
0.8V to 2V. V =3V.
Note 2: External reference REFHI = 1.3V, V = 3V
CC
CC
Note 6: Guaranteed by design. Not subject to test.
Note 3: Nonlinearity is defined from code 128 to code 65535 (full scale).
See Applications Information.
3
LTC1657L
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PIN FUNCTIONS
WR (Pin 1): Write Input (Active Low). Used with CSMSB
and/orCSLSBtocontroltheinputregisters. WhileWRand
CSMSB and/or CSLSB are held low, data writes into the
input register.
the output buffer to this end of the ladder. Can be used to
offset the zero scale above ground.
REFHI (Pin 22): Upper input terminal of the DAC’s internal
resistor ladder. Typically connected to REFOUT. An input
code of (FFFF)H will connect the positive input of the
output buffer to 1LSB below this voltage.
CSLSB (Pin 2): Chip Select Least Significant Byte (Active
Low). Used with WR to control the LSB 8-bit input regis-
ters. While WR and CSLSB are held low, the LSB byte
writes into the LSB input register. Can be connected to
CSMSB for simultaneous loading of both sets of input
latches on a 16-bit bus.
REFOUT (Pin 23): Output of the internal 1.25V reference.
TypicallyconnectedtoREFHItodriveinternalDACresistor
ladder.
V
CC (Pin 24): Positive Power Supply Input. 2.7V ≤ VCC ≤
CSMSB (Pin 3): Chip Select Most Significant Byte (Active
Low). Used with WR to control the MSB 8-bit input
registers. While WR and CSMSB are held low, the MSB
byte writes into the MSB input register. Can be connected
to CSLSB for simultaneous loading of both sets of input
latches on a 16-bit bus.
5.5V. Requires a 0.1µF bypass capacitor to ground.
VOUT (Pin 25): Buffered DAC Output.
X1/X2(Pin26):GainSettingResistorPin. ConnecttoGND
for G = 2 or to VOUT for G = 1. This pin should always be
tied to a low impedance source, such as ground or VOUT
,
to ensure stability of the output buffer when driving
capacitive loads.
D0toD7(Pins4to11):InputdatafortheLeastSignificant
Byte. Written into LSB input register when WR = 0 and
CSLSB = 0.
CLR (Pin 27): Clear Input (Asynchronous Active Low). A
low on this pin asynchronously resets all input and DAC
registers to 0s.
D8 to D15 (Pins 12 to 19): Input data for the Most Signifi-
cant Byte. Written into MSB input register when WR = 0
and CSMSB = 0.
LDAC (Pin 28): Load DAC (Asynchronous Active Low).
Used to asynchronously transfer the contents of the input
registers to the DAC register which updates the output
voltage. If held low, the DAC register loads data from the
GND (Pin 20): Ground.
REFLO (Pin 21): Lower input terminal of the DAC’s inter-
nal resistor ladder. Typically connected to Analog Ground.
An input code of (0000)H will connect the positive input of
input registers which will immediately update VOUT
.
4
LTC1657L
U
DIGITAL INTERFACE TRUTH TABLE
CLR
L
H
H
H
H
H
H
H
CSMSB
CSLSB
WR
X
X
X
L
L
L
H
X
X
LDAC
FUNCTION
X
X
X
L
H
L
X
H
X
L
X
X
X
H
L
X
L
Clears input and DAC registers to zero
Loads DAC register with contents of input registers
Freezes contents of DAC register
Writes MSB byte into MSB input register
Writes LSB byte into LSB input register
Writes MSB and LSB bytes into MSB and LSB input registers
Inhibits write to MSB and LSB input registers
Inhibits write to MSB input register
H
X
X
X
X
X
X
L
L
X
X
H
L
H
H
Inhibits write to LSB input register
Data bus flows directly through input and DAC registers
L
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W
TIMING DIAGRAM
t
CS
CSLSB
t
CS
CSMSB
t
t
t
t
WR
CWH
DWH
CWS
t
WR
WR
t
LDAC
LDAC
t
DWS
DAC UPDATE
DATA VALID
DATA VALID
DATA
1657 TD
5
LTC1657L
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DEFI ITIO S
Resolution (n): Resolution is defined as the number of
digital input bits (n). It defines the number of DAC output
states(2n)thatdividethefull-scalerange.Resolutiondoes
not imply linearity.
G = 1 for X1/X2 connected to VOUT
G = 2 for X1/X2 connected to GND
CODE = Decimal equivalent of digital input
(0 ≤ CODE ≤ 65535)
Full-Scale Voltage (VFS): This is the output of the DAC
when all bits are set to 1.
Zero-Scale Error (ZSE): The output voltage when the
DAC is loaded with all zeros. Since this is a single supply
part, this value cannot be less than 0V.
VoltageOffsetError(VOS): Normally,theDACoffsetisthe
voltageattheoutputwhentheDACisloadedwithallzeros.
The DAC can have a true negative offset, but because the
partisoperatedfromasinglesupply, theoutputcannotgo
below zero. If the offset is negative, the output will remain
near 0V resulting in the transfer curve shown in Figure 1.
Integral Nonlinearity (INL): End-point INL is the maxi-
mum deviation from a straight line passing through the
end points of the DAC transfer curve. Because the part
operates from a single supply and the output cannot go
below zero, the linearity is measured between full scale
and the code corresponding to the maximum offset
specification. The INL error at a given input code is
calculated as follows:
OUTPUT
VOLTAGE
INL (In LSBs) = [VOUT – VOS – (VFS – VOS)
(code/65535)]
0V
NEGATIVE
OFFSET
DAC CODE
1657 F01
VOUT = The output voltage of the DAC measured at
the given input code
Figure 1. Effect of Negative Offset
Differential Nonlinearity (DNL): DNL is the difference
between the measured change and the ideal one LSB
change between any two adjacent codes. The DNL error
between any two codes is calculated as follows:
The offset of the part is measured at the code that corre-
sponds to the maximum offset specification:
VOS = VOUT – [(Code)(VFS)/(2n – 1)]
DNL = (∆VOUT – LSB)/LSB
∆VOUT = The measured voltage difference between
two adjacent codes
Least Significant Bit (LSB): One LSB is the ideal voltage
difference between two successive codes.
LSB = (VFS – VOS)/(2n – 1) = (VFS – VOS)/65535
Nominal LSBs:
DigitalFeedthrough: Theglitchthatappearsattheanalog
outputcausedbyACcouplingfromthedigitalinputswhen
they change state. The area of the glitch is specified in
nV • s.
LTC1657L LSB = 2.5V/65535 = 38.1µV
DAC Transfer Characteristic:
REFHI–REFLO
VOUT = G•
CODE +REFLO
(
)
65536
6
LTC1657L
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OPERATION
Parallel Interface
used or the resistor ladder can be driven by an external
source in multiplying applications. The external reference
or source must be capable of driving the 16k (minimum)
DAC ladder resistance.
The data on the input of the DAC is written into the DAC’s
inputregisterswhenChipSelect(CSLSBand/orCSMSB)
and WR are at a logic low. The data that is written into the
input registers will depend on which of the Chip Selects
areatalogiclow(seeDigitalInterfaceTruthTable). IfWR
and CSLSB are both low and CSMSB is high, then only
data on the eight LSBs (D0 to D7) is written into the input
registers. Similarly, if WR and CSMSB are both low and
CSLSB is high, then only data on the eight MSBs (D8 to
D15) is written into the input registers. Data is written into
both the Least Significant Data Bits (D0 to D7) and the Most
Significant Bits (D8 to D15) at the same time if WR, CSLSB
and CSMSB are low. If WR is high or both CSMSB and
CSLSB are high, then no data is written into the input
registers.
Internal reference output voltage noise spectral density
can be reduced with a bypass capacitor to ground. (Note:
The reference does not require a bypass capacitor to
groundfornominaloperation.)Whenbypassingtherefer-
ence, a small value resistor in series with the capacitor is
recommended to help reduce peaking on the output. A
10Ω resistor in series with a 4.7µF capacitor is optimum
for reducing reference generated noise. Internal reference
output noise at 1kHz is typically 80nV/√Hz.
DAC Resistor Ladder
The high and low end of the DAC ladder resistor string
(REFHI and REFLO, respectively) are not connected inter-
nally on this part. Typically, REFHI will be connected to
REFOUT and REFLO will be connected to GND. X1/X2
connected to GND will give the LTC1657L a full-scale
output swing of 2.5V.
Once data is written into the input registers, it can be
written into the DAC register. This will update the analog
voltage output of the DAC. The DAC register is written by
a logic low on LDAC. The data in the DAC register will be
held when LDAC is high.
Either of these pins can be driven up to VCC – 1.5V when
using the buffer in the gain-of-1 configuration. The resis-
tor string pins can be driven to VCC/2 when the buffer is in
the gain of 2 configuration. The resistance between these
two pins is typically 30k (16k min).
When WR, CSLSB, CSMSB and LDAC are all low, the
registers are transparent and data on pins D0 to D15 flows
directly into the DAC register.
For an 8-bit data bus connection, tie the MSB byte data
pins to their corresponding LSB byte pins (D15 to D7, D14
to D6, etc).
Voltage Output
The output buffer for the LTC1657L can be configured for
two different gain settings. By tying the X1/X2 pin to GND,
the gain is set to 2. By tying the X1/X2 pin to VOUT, the gain
is set to unity.
Power-On Reset
The LTC1657L has an internal power-on reset that resets
all internal registers to 0’s on power-up (equivalent to the
CLR pin function).
The LTC1657L rail-to-rail buffered output can source or
sink 5mA to within 500mV of the positive supply voltage
or ground at room temperature. The output stage is
equipped with a deglitcher that results in a midscale glitch
impulse of 8nV • s. The output swings to within a few
millivolts of either supply rail when unloaded and has an
equivalentoutputresistanceof40Ωwhendrivingaloadto
the rails.
Reference
The LTC1657L includes an internal 1.25V reference, giv-
ing the LTC1657L a full-scale range of 2.5V in the gain-of-
2configuration.TheonboardreferenceintheLTC1657Lis
not internally connected to the DAC’s reference resistor
string but is provided on an adjacent pin for flexibility.
Because the internal reference is not internally connected
to the DAC resistor ladder, an external reference can be
7
LTC1657L
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APPLICATIONS INFORMATION
Rail-to-Rail Output Considerations
error (FSE) is positive, the output for the highest codes
limits at VCC as shown in Figure 1c. No full-scale limiting
can occur if VREF is less than (VCC – FSE)/2.
In any rail-to-rail DAC, the output swing is limited to
voltages within the supply range.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 1b.
Similarly, limiting can occur near full scale when the REF
pin is tied to VCC/2. If VREF = VCC/2 and the DAC full-scale
POSITIVE
FSE
V
CC
V
= V /2
CC
OUTPUT
VOLTAGE
REF
INPUT CODE
(c)
V
CC
V
= V /2
CC
OUTPUT
VOLTAGE
REF
0
32768
65535
INPUT CODE
(a)
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
INPUT CODE
(b)
1657 F02
Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC/2
8
LTC1657L
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TYPICAL APPLICATION
this negative offset, a negative supply is needed. Connect
resister R1 as shown in the figure, the output voltage is the
offset when code 0 is loaded in.
This circuit shows how to measure negative offset. Since
LTC1657L operates on a single supply, if its offset is
negative, the output for code 0 limits at 0V. To measure
3V
24
V
CC
22
23
0.1µF
REFHI REFOUT
5:19
2
3
1
28
27
DATA 10:15
CSLSB
CSMSB
WR
LDAC
CLR
25
V
OUT
µP
LTC1657L
R1
100k
GND
20
X1/X2 REFLO
26 21
–3V
1657 TA03
9
LTC1657L
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PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
GN Package
28-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.386 – 0.393*
(9.804 – 9.982)
0.033
(0.838)
REF
28 27 26 25 24 23 22 21 20 19 18 17 1615
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
2
3
4
5
6
7
8
9
10 11 12 13 14
0.004 – 0.009
0.015 ± 0.004
(0.38 ± 0.10)
0.053 – 0.069
× 45°
(1.351 – 1.748)
(0.102 – 0.249)
0.0075 – 0.0098
(0.191 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.008 – 0.012
(0.203 – 0.305)
0.0250
(0.635)
BSC
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN28 (SSOP) 1098
10
LTC1657L
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PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
N Package
28-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
1.370*
(34.789)
MAX
28 27 26 25 24
23 22 21 20
19 18 17 16 15
0.255 ± 0.015*
(6.477 ± 0.381)
1
2
3
4
5
6
7
8
9
10 11 12
13 14
0.300 – 0.325
(7.620 – 8.255)
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
0.020
(0.508)
MIN
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
+0.035
0.125
(3.175)
MIN
0.005
(0.127)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.100
(2.54)
BSC
0.325
–0.015
+0.889
8.255
(
)
–0.381
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
N28 1098
11
LTC1657L
RELATED PARTS
PART NUMBER
LTC1446(L)
LTC1450(L)
LTC1458(L)
DESCRIPTION
COMMENTS
Dual 12-Bit V
DACs in SO-8 Package
V
V
V
= 5V (3V), V
= 5V (3V), V
= 5V (3V), V
= 0V to 4.095V (0V to 2.5V)
= 0V to 4.095V (0V to 2.5V)
= 0V to 4.095V (0V to 2.5V)
OUT
CC
CC
CC
OUT
OUT
OUT
Single 12-Bit V
DACs with Parallel Interface
OUT
Quad 12-Bit Rail-to-Rail Output DACs
with Added Functionality
LTC1650
Single 16-Bit V
Single 16-Bit V
Single 16-Bit V
Industrial DAC in 16-Pin SO
DAC with Serial Interface in SO-8
DAC with Parallel Interface
V
V
V
= ±5V, Low Power, Deglitched, 4-Quadrant Multiplying V
OUT
OUT
OUT
OUT
CC
CC
CC
LTC1655(L)
LTC1657
= 5V (3V), Low Power, Deglitched, V
= 0V to 4.096V (0V to 2.5V)
OUT
= 5V, Low Power, Deglitched, V
= 0V to 4.096V
OUT
with Internal Reference
1657Li LT/TP 0400 4K • PRINTED IN USA
LINEAR TECHNOLOGY CORPORATION 2000
12 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
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