LTC1737_技术文档

LTC4267

Power over Ethernet

IEEE 802.3af PD Interface with

Integrated Switching Regulator

U

FEATURES

DESCRIPTIO

Complete Power Interface Port for IEEE 802^®.3af

The LTC^®4267 combines an IEEE 802.3af compliant Pow-

ered Device (PD) interface with a current mode switching

regulator, providing a complete power solution for PD

applications. The LTC4267 integrates the 25kΩ signature

resistor,classiﬁcationcurrentsource,thermaloverloadpro-

tection,signaturedisableandpowergoodsignalalongwith

an undervoltage lockout optimized for use with the IEEE-

requireddiodebridge.Theprecisionduallevelinputcurrent

limit allows the LTC4267 to charge large load capacitors

and interface with legacy PoE systems.

■

Powered Device (PD)

■

Onboard 100V, 400mA UVLO Switch

■

Precision Dual Level Inrush Current Limit

■

Integrated Current Mode Switching Regulator

■

Onboard 25kΩ Signature Resistor with Disable

■

Programmable Classiﬁcation Current (Class 0-4)

■

Thermal Overload Protection

Power Good Signal

■

Integrated Error Ampliﬁer and Voltage Reference

■

Low Proﬁle 16-Pin SSOP and 3mm × 5mm DFN

The current mode switching regulator is designed for

driving a 6V rated N-channel MOSFET and features pro-

grammable slope compensation, soft-start, and constant

frequency operation, minimizing noise even with light

loads. The LTC4267 includes an onboard error ampliﬁer

and voltage reference allowing use in both isolated and

nonisolated conﬁgurations.

Packages

U

APPLICATIO S

■

IP Phone Power Management

■

Wireless Access Points

■

Security Cameras

Power over Ethernet

■

The LTC4267 is available in space saving, low proﬁle

16-pin SSOP or DFN packages.

, LTC and LT are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

802 is a registered trademark of Institute of Electrical and Electronics Engineers, Inc.

U

TYPICAL APPLICATIO

Class 2 PD with 3.3V Isolated Power Supply

PA1133 SBM1040

3.3V

1.5A

10k

+

–48V

•

HD01

FROM

V

P

PORTP

VCC

+

320µF

P

CHASSIS

DATA PAIR

5µF

VCC

+

–

•

MIN

4.7µF

PWRGD

LTC4267

SMAJ58A

NGATE

SENSE

/RUN

Si3440

10k

0.1µF

0.1Ω

P

VCC

6.8k

R

I

CLASS

TH

470

+

HD01

R

–48V

FROM

SPARE PAIR

CLASS

68.1Ω

V

FB

1%

–

100k

SIGDISA

22nF

PGND

BA5516

V

P

OUT

PORTN

PS2911

60.4k

TLV431

4267 TA01

4267f

1

LTC4267

W W U W

ABSOLUTE AXI U RATI GS

(Note 1)

V

P

with Respect to V

Voltage...0.3V to –100V

SENSE to PGND Voltage ..............................–0.3V to 1V

NGATE Peak Output Current (<10μs) ..........................1A

Operating Ambient Temperature Range

LTC4267C ................................................ 0°C to 70°C

LTC4267I .............................................–40°C to 85°C

Junction Temperature

GN Package ...................................................... 150°C

DHC Package.................................................... 125°C

Storage Temperature Range...................–65°C to 150°C

Lead Temperature (Soldering, 10 sec) .................. 300°C

PORTN

, SIGDISA, PWRGD

OUT

PORTP

Voltage..................... V

+ 100V to V

–0.3V

PORTN

P

to PGND Voltage (Note 2)

VCC

Low Impedance Source ...........................–0.3V to 8V

Current Fed..........................................5mA into P

VCC

– 0.3V

R

Voltage.................V

+ 7V to V

CLASS

PORTN

PWRGD Current.....................................................10mA

R

Current.....................................................100mA

CLASS

NGATE to PGND Voltage ...........................–0.3V to P

VCC

V , I /RUN to PGND Voltages................–0.3V to 3.5V

FB TH

U

W

U

PACKAGE/ORDER I FOR ATIO

TOP VIEW

ORDER PART

TOP VIEW

NUMBER

I

/RUN

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

V

TH

FB

PGND

/RUN

1

2

3

4

5

6

7

8

16 PGND

PGND

I

15

14

13

12

11

10

9

V

LTC4267CDHC

LTC4267IDHC

TH

FB

LTC4267CGN

LTC4267IGN

NGATE

SENSE

NGATE

SENSE

P

VCC

V

PORTP

P

VCC

V

17

PORTP

R

SIGDISA

PWRGD

CLASS

NC

R

SIGDISA

PWRGD

CLASS

NC

DFN PART*

MARKING

GN PART

MARKING

V

P

PORTN

NC

OUT

V

P

PORTN

PGND

OUT

NC

PGND

4267

4267I

DHC16 PACKAGE

GN PACKAGE

16-LEAD NARROW PLASTIC SSOP

= 150°C, θ = 90°C/W

16-LEAD (3mm × 5mm) PLASTIC DFN

T

= 125°C, θ = 43.5°C/W

JMAX

JA

T

JMAX

JA

EXPOSED PAD (PIN 17)

MUST BE SOLDERED TO ELECTRICALLY

ISOLATED PCB HEAT SINK

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grades are identiﬁed by a label on the shipping container.

The ● denotes the speciﬁcations which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Supply Voltage

Maximum Operating Voltage

Signature Range

Classiﬁcation Range

UVLO Turn-On Voltage

UVLO Turn-Off Voltage

Voltage with Respect to V

(Notes 4, 5, 6)

PORTP

PORTN

●

–57

–9.5

–21

–37.2

–31.5

V

–1.5

–12.5

–34.8

–29.3

–36.0

–30.5

V

P

Turn-On Voltage

Turn-Off Voltage

Hysteresis

Voltage with Respect to PGND

●

7.8

4.6

1.5

8.3

8.7

5.7

3.0

9.4

9.2

6.8

V

TURNON

TURNOFF

HYST

VCC

V

– V

TURNOFF

TURNON

Shunt Regulator Voltage

I

= 1mA, V /RUN = 0V, Voltage

10.3

CLAMP1mA

PVCC

ITH

with Respect to PGND

4267f

2

LTC4267

The ● denotes the speciﬁcations which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS

MIN

TYP

MAX

UNITS

V

P

– V Margin

TURNON

●

0.05

0.6

MARGIN

CLAMP1mA

I

Supply Current when ON

V

= –48V, P , PWRGD, SIGDISA Floating

3

mA

VPORTN_ON

PVCC_ON

PORTN

OUT

Supply Current

(Note 7)

VCC

Normal Operation

Start-Up

V

P

/RUN – PGND = 1.3V

●

240

40

350

90

µA

ITH

– PGND = V

– 100mV

VCC

TURNON

I

V

Supply Current

V

= –17.5V, P

Tied to V , R ,

PORTP CLASS

●

0.35

0.5

0.65

mA

VPORTN_CLASS

PORTN

OUT

During Classiﬁcation

SIGDISA Floating (Note 8)

∆I

Current Accuracy

During Classiﬁcation

10mA < I < 40mA, –12.5V ≤ V

(Notes 9, 10)

≤ –21V

PORTN

3.5

%

CLASS

R

Signature Resistance

–1.5V ≤ V

≤ – 9.5V, P

Tied to V ,

PORTP

23.25

26.00

11.8

kΩ

SIGNATURE

PORTN

OUT

IEEE 802.3af 2-Point Measurement (Notes 4, 5)

Invalid Signature Resistance

–1.5V ≤ V ≤ – 9.5V, SIGDISA and P Tied to

9

INVALID

PORTN

OUT

V

, IEEE 802.3af 2-Point Measurement

PORTP

(Notes 4, 5)

V

Signature Disable

High Level Input Voltage

With Respect to V

High Level Invalidates Signature (Note 11)

●

3

57

V

IH

PORTN

Signature Disable

Low Level Input Voltage

With Respect to V

Low Level Enables Signature

0.45

IL

PORTN

R

Signature Disable, Input Resistance With Respect to V

●

100

kΩ

INPUT

PORTN

V

Power Good Output Low Voltage

I = 1mA V

= –48V,

0.5

V

PG_OUT

PORTN

PWRGD Referenced to V

PORTN

Power Good Trip Point

V

P

= –48V, Voltage between V

Falling

Rising

and P

PORTN OUT

PORTN

V

●

1.3

2.7

1.5

3.0

1.7

3.3

V

PG _FALL

PG_RISE

OUT

I

Power Good Leakage Current

On-Resistance

V

= 0V, PWRGD FET Off, V = 57V

PWRGD

●

1

µA

PG_LEAK

PORTN

R

I = 350mA, V

= –48V, Measured from

PORTN

1.0

1.6

2

Ω

ON

V

P

V

to P

(Note 10)

●

PORTN

OUT

V

I

Shutdown Threshold (at I /RUN)

– PGND = V + 100mV

TURNON

0.15

0.2

0.28

0.3

0.45

0.4

V

µA

ITHSHDN

TH

VCC

Start-Up Current Source at I /RUN

/RUN – PGND = 0V, P

ITH

– P

= 8V

VCC

– P

GND

= 8V (Note 12)

GND

THSTART

TH

V

Regulated Feedback Voltage

Referenced to PGND, P

●

0.780

0.800

10

0.812

50

V

VCC

= 8V (Note 12)

FB

I

V

Input Current

FB

P

– P

GND

nA

VCC

/RUN Pin Load = 5µA (Note 12)

FB

g

Error Ampliﬁer Transconductance

Output Voltage Line Regulation

Output Voltage Load Regulation

I

200

333

0.05

500

µA/V

mV/V

m

TH

∆V

V

< P

< V

(Note 12)

CLAMP

O(LINE)

TURNOFF

VCC

I

TH

/RUN Sinking 5µA, P

VCC

– P

= 8V (Note 12)

3

mV/µA

GND

– P = 8V (Note 12)

O(LOAD)

I

/RUN Sourcing 5µA, P

VCC

GND

= 0V, Power MOSFET Off,

PORTN

TH

I

P

Leakage

V

P

●

150

µA

POUT_LEAK

OUT

= 57V (Note 13)

OUT

Input Current Limit, High Level

V

= –48V, P

= –43V (Note 14, 15)

LIM_HI

PORTN

OUT

0°C ≤ T ≤ 70°C

●

325

300

375

400

mA

A

–40°C ≤ T ≤ 85°C

A

I

f

Input Current Limit, Low Level

Oscillator Frequency

V

= –48V, P = –43V (Note 14, 15)

OUT

●

80

140

200

6

180

240

8

mA

kHz

%

LIM_LO

OSC

PORTN

/RUN – PGND = 1.3V, P

VCC

– P

= 8V

180

GND

ITH

DC

Minimum Switch On Duty Cycle

V

P

/RUN – PGND = 1.3V, V – PGND = 0.8V,

ON(MIN)

ITH

VCC

FB

– P

= 8V

GND

DC

Maximum Switch On Duty Cycle

V

P

/RUN – PGND = 1.3V, V – PGND = 0.8V,

70

80

90

%

ON(MAX)

ITH

FB

– P

= 8V

VCC

GND

4267f

3

LTC4267

The ● denotes the speciﬁcations which apply over the full operating

ELECTRICAL CHARACTERISTICS

temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

40

MAX

UNITS

ns

t

NGATE Drive Rise Time

C

LOAD

C

LOAD

= 3000pF, P

– P

= 8V

VCC

GND

RISE

t

NGATE Drive Fall Time

= 3000pF, P

40

ns

FALL

V

Peak Current Sense Voltage

Peak Slope Compensation Output Current

Soft-Start Time

R

= 0, P

– P

= 8V (Note 16)

●

90

100

5

115

mV

µA

VCC

GND

IMAX

SL

I

P

– P

= 8V (Note 17)

= 8V

VCC

SLMAX

t

1.4

140

ms

°C

VCC

SFST

T

Thermal Shutdown Trip Temperature

(Notes 14, 18)

SHUTDOWN

Note 1: Absolute Maximum Ratings are those values beyond which the life

of the device may be impaired.

Note 10: For the DHC package, this parameter is assured by design and

wafer level testing.

Note 2: P

PGND.

internal clamp circuit self regulates to 9.4V with respect to

Note 11: To disable the 25kΩ signature, tie SIGDISA to V

or hold

VCC

PORTP

SIGDISA high with respect to V

. See Applications Information.

PORTN

Note 3: The LTC4267 operates with a negative supply voltage in the range

of – 1.5V to – 57V. To avoid confusion, voltages for the PD interface

are always referred to in terms of absolute magnitude. Terms such as

“maximum negative voltage” refer to the largest negative voltage and

a “rising negative voltage” refers to a voltage that is becoming more

negative.

Note 12: The switching regulator is tested in a feedback loop that servos

to the output of the error ampliﬁer while maintaining I /RUN at the

midpoint of the current limit range.

V

FB

TH

Note 13: I includes current drawn through P

by the power

OUT

POUT_LEAK

good status circuit. This current is compensated for in the 25kΩ signature

resistance and does not affect PD operation.

Note 4: The LTC4267 is designed to work with two polarity protection

diode drops between the PSE and PD. Parameter ranges speciﬁed in the

Electrical Characteristics section are with respect to this product pins and

are designed to meet IEEE 802.3af speciﬁcations when these diode drops

are included. See the Application Information section.

Note 5: Signature resistance is measured via the two-point ΔV/ΔI method

as deﬁned by IEEE 802.3af. The PD signature resistance is offset from the

25kΩ to account for diode resistance. With two series diodes, the total PD

resistance will be between 23.75kΩ and 26.25kΩ and meet IEEE 802.3af

speciﬁcations. The minimum probe voltages measured at the LTC4267

pins are –1.5V and –2.5V. The maximum probe voltages are –8.5V and

–9.5V.

Note 14: The LTC4267 PD Interface includes thermal protection. In the

event of an overtemperature condition, the PD interface will turn off

the switching regulator until the part cools below the overtemperature

limit. The LTC4267 is also protected against thermal damage from

incorrect classiﬁcation probing by the PSE. If the LTC4267 exceeds the

overtemperature threshold, the classiﬁcation load current is disabled.

Note 15: The PD interface includes dual level input current limit. At turn-

on, before the P

to a low level. After the load capacitor is charged and the P

load capacitor is charged, the PD current level is set

OUT

– V

OUT

PORTN

voltage difference is below the power good threshold, the PD switches to

high level current limit. The PD stays in high level current limit until the

input voltage drops below the UVLO turn-off threshold.

Note 6: The PD interface includes hysteresis in the UVLO voltages to

preclude any start-up oscillation. Per IEEE 802.3af requirements, the PD

will power up from a voltage source with 20Ω series resistance on the ﬁrst

trial.

Note 7: Dynamic Supply current is higher due to the gate charge being

delivered at the switching frequency.

Note 16: Peak current sense voltage is reduced dependent on duty cycle

and an optional external resistor in series with the SENSE pin (R ). For

SL

details, refer to the programmable slope compensation feature in the

Applications Information section.

Note 17: Guaranteed by design.

Note 18: The PD interface includes overtemperature protection that is

intended to protect the device from momentary overload conditions.

Junction temperature will exceed 125°C when overtemperature protection

is active. Continuous operation above the speciﬁed maximum operating

junction temperature may impair device reliability.

Note 8: I

programmed at the R

does not include classiﬁcation current

VPORTN_CLASS

pin. Total current in classiﬁcation mode will be

CLASS

I

+ I

(See note 9).

VPORTN_CLASS

CLASS

Note 9: I

is the measured current ﬂowing through R

. ΔI

= 1.237/

CLASS

CLASS CLASS

accuracy is with respect to the ideal current deﬁned as I

CLASS

R

CLASS

. The current accuracy does not include variations in R

CLASS

resistance. The total classiﬁcation current for a PD also includes the IC

quiescent current (I ). See Applications Information.

VPORTN_CLASS

4267f

4

LTC4267

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Input Current vs Input Voltage

25k Detection Range

Input Current vs Input Voltage

0.5

0.4

0.3

0.2

50

40

30

20

12.0

11.5

T

= 25°C

T = 25°C

A

CLASS 1 OPERATION

A

CLASS 4

CLASS 3

11.0

85°C

–40°C

10.5

10.0

CLASS 2

CLASS 1

0.1

0

10

0

9.5

9.0

CLASS 0

0

–4

–6

–8

–10

0

–20

–30

–40

–50

–60

–2

–10

–12

–14

–16

–18

VOLTAGE (V)

–20

–22

V

VOLTAGE (V)

V

PORTN

VOLTAGE (V)

V

PORTN

4267 G01

4267 G02

4267 G03

Signature Resistance vs

Input Voltage

Normalized UVLO Threshold vs

Temperature

Input Current vs Input Voltage

3

2

1

0

28

27

2

1

EXCLUDES ANY LOAD CURRENT

∆V V2 – V1

APPLICABLE TO TURN-ON

AND TURN-0FF THRESHOLDS

RESISTANCE =

DIODES: S1B

=

T

= 25°C

A

∆I

I – I

2 1

T

= 25C

A

IEEE UPPER LIMIT

26

LTC4267 + 2 DIODES

25

24

0

–1

LTC4267 ONLY

IEEE LOWER LIMIT

23

22

–2

–40

–45

–50

–55

–60

V1: –1

V2: –2

–3

–4

–5

–6

PORTN

–7

–8

–9

–10

–40 –20

0

20

40

60

80

V

VOLTAGE (V)

TEMPERATURE (C)

PORTN

V

VOLTAGE (V)

4267 G04

4267 G05

4267 G06

Power Good Output Low Voltage

vs Current

P_OUTLeakage Current

Current Limit vs Input Voltage

4

3

2

1

0

120

90

60

30

0

400

300

200

100

T

= 25°C

A

V

A

= 0V

IN

85°C

T

= 25°C

– 40°C

HIGH CURRENT MODE

LOW CURRENT MODE

85°C

– 40°C

0

2

4

6

8

10

0

20

40

60

–50

–55

VOLTAGE (V)

–40

–45

–60

CURRENT (mA)

P

PIN VOLTAGE (V)

V

OUT

PORTN

4267 G07

4267 G08

4267 G09

4267f

5

LTC4267

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Oscillator Frequency vs

Temperature

Reference Voltage vs

Temperature

Reference Voltage vs

Supply Voltage

812

808

804

800

796

792

788

240

230

220

210

200

190

180

801.0

800.8

800.6

800.4

800.2

800.0

799.8

799.6

799.4

799.2

799.0

P

= 8V

P

= 8V

VCC

T

= 25°C

A

(WITH RESPECT TO PGND)

P

≤ V

VCC

CLAMP1mA

50 70

–50 –30 –10 10 30

TEMPERATURE (°C)

–30 –10 10 30 50

TEMPERATURE (°C)

110

90 110

–50

70 90

6

7

7.5

8

8.5

9

9.5

6.5

P

SUPPLY VOLTAGE (V)

VCC

4267 G13

4267 G10

4267 G11

P_VCCUndervoltage Lockout

Thresholds vs Temperature

P_VCCShunt Regulator Voltage vs

Temperature

Oscillator Frequency vs

Supply Voltage

10.0

9.5

9.0

8.5

8.0

7.5

7.0

6.5

6.0

5.5

5.0

10.0

9.9

9.8

9.7

9.6

9.5

9.4

9.3

9.2

9.1

9.0

210

208

206

204

202

200

198

196

194

192

190

T

= 25°C

A

V

TURNON

I

= 1mA

PVCC

V

TURNOFF

–50

30

80 90

–50

30

TEMPERATURE (°C)

70 90

–30 –10 10

50

110

–30 –10 10

50

110

6

6.5

P

7.5

8

8.5

9

7

TEMPERATURE (°C)

SUPPLY VOLTAGE (V)

VCC

4267 G16

4267 G17

4267 G14

I_PVCCSupply Current vs

Temperature

265

260

255

250

245

240

235

230

225

220

215

P

V

= 8V

VCC

ITH/RUN

= 1.3V

–50

30

TEMPERATURE (°C)

70 90

–30 –10 10

50

110

4267 G18

4267f

6

LTC4267

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Start-Up I_PVCCSupply Current vs

Temperature

I_TH/RUN Shutdown Threshold vs

Temperature

I_TH/RUN Start-Up Current Source

vs Temperature

450

400

60

50

40

30

20

10

0

600

500

400

300

200

100

0

P

= V

– 0.1V

P

V

= V

ITH/RUN

+ 0.1V

VCC

TURNON

VCC

TURNON

= 0V

350

300

250

200

150

100

–30 –10 10 30 50

TEMPERATURE (°C)

110

50 70

–50 –30 –10 10 30

TEMPERATURE (°C)

–50

70 90

50 70

–50 –30 –10 10 30

TEMPERATURE (°C)

90 110

4267 G20

4267 G19

4267 G21

Peak Current Sense Voltage vs

Temperature

Soft-Start Time vs Temperature

120

115

110

105

100

95

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

P

VCC

= 8V

90

85

80

30 50

–50 –30 –10 10

TEMPERATURE (°C)

30 50

TEMPERATURE (°C)

70 90 110

–50 –30 –10 10

70 90 110

4267 G22

4267 G23

4267f

7

LTC4267

U

PI FU CTIO S

(GN/DHC)

I /RUN (Pin 2/Pin 1): Current Threshold/Run Input. This

PWRGD(Pin11/Pin11):PowerGoodOutput,Open-Drain.

Indicates that the PD MOSFET is on and the switching

regulator can start operation. Low impedance indicates

power is good. PWRGD is high impedance during detec-

tion, classiﬁcation and in the event of a thermal overload.

TH

pin performs two functions. It serves as the switching

regulator error ampliﬁer compensation point as well as

the run/shutdown control input. Nominal voltage range is

0.7V to 1.9V. Forcing the pin below 0.28V with respect to

PGND causes the controller to shut down.

PWRGD is referenced to V

.

PORTN

PGND (Pin 1, 8, 9, 16/Pin 2, 15): Switching Regulator

SIGDISA(Pin12/Pin12):SignatureDisableInput.SIGDISA

Negative Supply. This pin is the negative supply rail for the

allows the PD to present an invalid signature resistance

switching regulator controller and must be tied to P

.

andremaininactive.ConnectingSIGDISAtoV

lowers

OUT

PORTP

the signature resistance to an invalid value and disables

all functions of the LTC4267. If unused, tie SIGDISA to

PORTN

NGATE (Pin 3/Pin 3): Gate Driver Output. This pin drives

the regulator’s external N-Channel MOSFET and swings

V

.

from PGND to P

.

VCC

V

(Pin 13/Pin 13): Positive Power Input. Tie to the

PORTP

P

(Pin 4/Pin 4): Switching Regulator Positive Supply.

VCC

input port power return through the input diodes.

This pin is the positive supply rail for the switching regula-

tor and must be closely decoupled to PGND.

SENSE (Pin 14/Pin 14): Current Sense. This pin performs

two functions. It monitors the regulator switch current by

readingthevoltageacrossanexternalsenseresistor.Italso

injectsacurrentrampthatdevelopsaslopecompensation

voltageacrossanoptionalexternalprogrammingresistor.

See the Applications Information section.

R

(Pin5/Pin5):ClassSelectInput.Usedtosetthecur-

CLASS

rent value the PD maintains during classiﬁcation. Connect

a resistor between R and V (see Table 2).

CLASS

PORTN

V

(Pin 7/Pin 7): Negative Power Input. Tie to the

PORTN

–48V input port through the input diodes.

V

(Pin 15/Pin 16): Feedback Input. Receives the feed-

FB

P

(Pin 10/Pin 10): Power Output. Supplies –48V to

OUT

back voltage from the external resistor divider across the

the switching regulator PGND pin and any additional PD

output.

loads through an internal power MOSFET that limits input

current. P

NC (Pin 6/Pin 6, 8, 9): No Internal Connection.

is high impedance until the voltage reaches

OUT

the turn-on UVLO threshold. The output is then current

limited. See the Application Information section.

Backside Connection (DHC Only, Pin 17): Exposed Pad.

Thisexposedpadmustbesolderedtoanelectricallyisolated

and thermally conductive PC board heat sink.

4267f

8

LTC4267

W

BLOCK DIAGRA

V

SIGDISA

P

VCC

PORTP

CLASSIFICATION

CURRENT LOAD

SHUTDOWN

COMPARATOR

1.237V

+

–

P

<

0.3µA 0.28V

+

–

VCC

V

TURNON

UNDERVOLTAGE

LOCKOUT

V

CC

SHUNT

9k

25k

SIGNATURE

RESISTOR

800mV

REFERENCE

REGULATOR

EN

R

CLASS

16k

PWRGD

SHUTDOWN

SOFT-

START

CLAMP

POWER GOOD

CONTROL

CIRCUITS

CURRENT

P

–

VCC

ERROR

AMPLIFIER

COMPARATOR

+

–

SWITCHING

NGATE

R

LOGIC AND

BLANKING

CIRCUIT

+

Q

V

FB

INPUT

CURRENT

LIMIT

GATE

DRIVER

S

375mA

I

/RUN

TH

EN

+

SLOPE

140mA

COMP

CURRENT

RAMP

20mV

200kHz

OSCILLATOR

–

1.2V

V

PORTN

SENSE

4267 BD

P

PGND

OUT

BOLD LINE INDICATES HIGH CURRENT PATH

W U U

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APPLICATIO S I FOR ATIO

OVERVIEW

LTC4267 has been speciﬁcally designed to interface with

both IEEE compliant Power Sourcing Equipment (PSE)

and legacy PSEs which do not meet the inrush current

requirement of the IEEE 802.3af speciﬁcation. By setting

the initial inrush current limit to a low level, a PD using

the LTC4267 minimizes the current drawn from the PSE

during start-up. After powering up, the LTC4267 switches

to the high level current limit, thereby allowing the PD to

consume up to 12.95W if an IEEE 802.3af PSE is present.

This low level current limit also allows the LTC4267 to

charge arbitrarily large load capacitors without exceeding

the inrush limits of the IEEE 802.3af speciﬁcation. This

dual level current limit provides the system designer with

ﬂexibility to design PDs which are compatible with legacy

PSEs while also being able to take advantage of the higher

power available in an IEEE 802.3af system.

The LTC4267 is partitioned into two major blocks: a

Powered Device (PD) interface controller and a current

mode ﬂyback switching regulator. The Powered Device

(PD) interface is intended for use as the front end of a

PD adhering to the IEEE 802.3af standard, and includes

a trimmed 25kΩ signature resistor, classiﬁcation current

source, and an input current limit circuit. With these

functions integrated into the LTC4267, the signature and

power interface for a PD can be built that meets all the

requirements of the IEEE 802.3af speciﬁcation with a

minimum of external components.

The switching regulator portion of the LTC4267 is a con-

stant frequency current mode controller that is optimized

for Power over Ethernet applications. The regulator is

designed to drive a 6V N-channel MOSFET and features

soft-start and programmable slope compensation. The

integrated error ampliﬁer and precision reference give the

PD designer the option of using a nonisolated topology

withouttheneedforanexternalampliﬁerorreference. The

Using an LTC4267 for the power and signature interface

functions of a PD provides several advantages. The

LTC4267 current limit circuit includes an onboard 100V,

400mA power MOSFET. This low leakage MOSFET is

4267f

9

LTC4267

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APPLICATIO S I FOR ATIO

DETECTION V1

DETECTION V2

TIME

speciﬁed to avoid corrupting the 25kΩ signature resistor

while also saving board space and cost. In addition, the in-

rushcurrentlimitrequirementoftheIEEE802.3afstandard

can cause large transient power dissipation in the PD. The

LTC4267 is designed to allow multiple turn-on sequences

without overheating the miniature 16-lead package. In the

event of excessive power cycling, the LTC4267 provides

thermal overload protection to keep the onboard power

MOSFET within its safe operating area.

–10

–20

–30

–40

–50

CLASSIFICATION

UVLO

TURN-OFF

UVLO

TURN-ON

TIME

C1

τ = R

LOAD

–10

–20

–30

–40

–50

UVLO

OFF

UVLO

ON

UVLO

OFF

OPERATION

I

dV

=

LIMIT

C1

dt

The LTC4267 PD interface has several modes of opera-

tion depending on the applied input voltage as shown in

Figure 1 and summarized in Table 1. These modes satisfy

therequirementsdeﬁnedintheIEEE802.3afspeciﬁcation.

TIME

–10

–20

–30

–40

–50

The input voltage is applied to the V

pin and must

POWER

BAD

POWER

GOOD

POWER

BAD

PORTN

be negative relative to the V

pin. Voltages in the data

PORTP

sheet for the PD interface portion of the LTC4267 are with

respect to V while the voltages for the switching

PWRGD TRACKS

PORTP

V

PORTN

regulatorarereferencedtoPGND.ItisassumedthatPGND

is tied to P . Note the use of different ground symbols

OUT

CURRENT

LIMIT, I

throughout the data sheet.

I

LIM_LO

Table 1. LTC4267 Operational Mode

as a Function of Input Voltage

LOAD, I

(UP TO I

)

LIM_HI

LOAD

I

CLASS

CLASSIFICATION

CLASS

INPUT VOLTAGE

I

(V

PORTN

with RESPECT to V

)

LTC4267 MODE OF OPERATION

Inactive

PORTP

TIME

DETECTION I

2

0V to –1.4V

DETECTION I

1

–1.5V to –10V

–11V to –12.4V

25kΩ Signature Resistor Detection

VOLTAGES WITH RESPECT TO V

V1 – 2 DIODE DROPS

PORTP

Classiﬁcation Load Current Ramps up

from 0% to 100%

I

1

=

25kΩ

–12.5V to UVLO*

UVLO* to –57V

Classiﬁcation Load Current Active

V2 – 2 DIODE DROPS

I

=

2

25kΩ

Power Applied to Switching Regulator

I

DEPENDENT ON R

SELECTION

CLASS

* V

UVLO includes hysteresis.

Rising input threshold ≅ –36.0V

Falling input threshold ≅ –30.5V

PORTN

= 140mA (NOMINAL), I

= 375mA (NOMINAL)

LIM_LO

LIM_HI

V

IN

I

=

(UP TO I

)

LOAD

LIM_HI

R

LOAD

R9

I

IN

R

V

CLASS PORTP

PSE

V

OUT

IN

LTC4267

R

CLASS

C1

PWRGD

V

P

OUT

PORTN

4267 F01

PGND

Figure 1. Output Voltage, PWRGD and PD

Current as a Function of Input Voltage

4267f

10

LTC4267

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APPLICATIO S I FOR ATIO

U

Series Diodes

The signature range extends below the IEEE range to ac-

commodate the voltage drop of the two diodes. The IEEE

speciﬁcationrequiresthePSEtouseaΔV/ΔImeasurement

technique to keep the DC offset of these diodes from af-

fecting the signature resistance measurement. However,

the diode resistance appears in series with the signature

resistor and must be included in the overall signature

resistance of the PD. The LTC4267 compensates for the

two series diodes in the signature path by offsetting the

resistance so that a PD built using the LTC4267 will meet

the IEEE speciﬁcation.

The IEEE 802.3af-deﬁned operating modes for a PD refer-

ence the input voltage at the RJ45 connector on the PD.

The PD must be able to accept power of either polarity

at each of its inputs, so it is common to install diode

bridges (Figure 2). The LTC4267 takes this into account

by compensating for these diode drops in the threshold

points for each range of operation. A similar adjustment

is made for the UVLO voltages.

Detection

During detection, the PSE will apply a voltage in the

range of –2.8V to –10V on the cable and look for a 25kΩ

signature resistor. This identiﬁes the device at the end of

the cable as a PD. With the terminal voltage in this range,

the LTC4267 connects an internal 25kΩ resistor between

In some applications it is necessary to control whether or

not the PD is detected. In this case, the 25kΩ signature

resistor can be enabled and disabled with the use of the

SIGDISA pin (Figure 3). Disabling the signature via the

SIGDISA pin will change the signature resistor to 9kΩ

(typical) which is an invalid signature per the IEEE 802.3af

speciﬁcation. ThisinvalidsignatureispresentforPDinput

voltagesfrom–2.8Vto–10V.Iftheinputrisesabove–10V,

the signature resistor reverts to 25kΩ to minimize power

dissipation in the LTC4267. To disable the signature, tie

the V

and V

pins. This precision, temperature

PORTP

PORTN

compensated resistor presents the proper signature to

alert the PSE that a PD is present and desires power to be

applied. The internal low-leakage UVLO switch prevents

the switching regulator circuitry from affecting the detec-

tion signature.

SIGDISA to V

. Alternately, the SIGDISA pin can be

PORTP

drivenhighwithrespecttoV

.WhenSIGDISAishigh,

PORTN

The LTC4267 is designed to compensate for the voltage

and resistance effects of the IEEE required diode bridge.

all functions of the PD interface are disabled.

RJ45

+

1

T1

TX

–

TX

BR1

2

3

+

TO PHY

RX

–

RX

6

POWERED DEVICE (PD)

INTERFACE

8

V

PORTP

AS DEFINED

+

–

SPARE

BY IEEE 802.3af

4

5

LTC4267

BR2

D3

4

V

PORTN

7

8

4267 F02

SPARE

Figure 2. LTC4267 PD Front End Using

Diode Bridges on Main and Spare Inputs

4267f

11

LTC4267

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APPLICATIO S I FOR ATIO

CURRENT PATH

LTC4267

V

PORTP

PSE

PROBING

LTC4267

SIGNATURE DISABLE

SIGDISA

9k

VOLTAGE

TO

PSE

V

R

25k SIGNATURE

RESISTOR

PORTP

CLASS

SOURCE

–15.5V TO –20.5V

16k

CONSTANT

LOAD

R

CLASS

CURRENT

INTERNAL

TO LTC4267

V

PORTN

V

PORTN

4267 F04

4267 F03

V

PSE CURRENT MONITOR

Figure 3. 25k Signature Resistor with Disable

PSE

PD

Figure 4. IEEE 802.3af Classiﬁcation Probing

Classiﬁcation

Once the PSE has detected a PD, the PSE may option-

ally classify the PD. Classiﬁcation provides a method for

more efﬁcient allocation of power by allowing the PSE

to identify lower power PDs and allocate less power for

these devices. The IEEE 802.3af speciﬁcation deﬁnes ﬁve

classes (Table 2) with varying power levels. The designer

selects the appropriate classiﬁcation based on the power

consumption of the PD. For each class, there is an as-

sociated load current that the PD asserts onto the line

during classiﬁcation probing. The PSE measures the PD

load current to determine the proper classiﬁcation and

PD power requirements.

The IEEE 802.3af speciﬁcation limits the classiﬁcation

time to 75ms because a signiﬁcant amount of power is

dissipatedinthePD.TheLTC4267isdesignedtohandlethe

power dissipation for this time period. If the PSE probing

exceeds75ms,theLTC4267mayoverheat.Inthissituation,

the thermal protection circuit will engage and disable the

classiﬁcation current source in order to protect the part.

The LTC4267 stays in classiﬁcation mode until the input

voltage rises above the UVLO turn-on voltage.

V

Undervoltage Lockout

PORTN

TheIEEEspeciﬁcationdictatesamaximumturn-onvoltage

of 42V and a minimum turn-off voltage of 30V for the PD.

In addition, the PD must maintain large on-off hysteresis

to prevent resistive losses in the wiring between the PSE

andthePDfromcausingstart-uposcillation.TheLTC4267

incorporates an undervoltage lockout (UVLO) circuit that

During classiﬁcation (Figure 4), the PSE presents a ﬁxed

voltage between –15.5V and –20.5V to the PD. With the

input voltage in this range, the LTC4267 asserts a load

current from the V

pin through the R

resistor.

PORTP

CLASS

The magnitude of the load current is set by the R

CLASS

resistor. The resistor values associated with each class

are shown in Table 2. Note that the switching regulator

willnotinterferewiththeclassiﬁcationmeasurementsince

the LTC4267 has not passed power to the regulator.

monitors the line voltage at V

to determine when

PORTN

to apply power to the integrated switching regulator

(Figure 5). Before the power is applied to the switching

regulator, the P

pin is high impedance and sitting at

OUT

the ground potential since there is no charge on capacitor

C1. When the input voltage rises above the UVLO turn-on

threshold, the LTC4267 removes the detection and clas-

siﬁcation loads and turns on the internal power MOSFET.

C1 charges up under the LTC4267 current limit control

Table 2. Summary of IEEE 802.3af Power Classiﬁcations and

LTC4267 R_CLASSResistor Selection

Maximum

Power Levels

at Input of PD

(W)

Nominal

Classiﬁcation

Load Current

(mA)

LTC4267

R

CLASS

Resistor

(Ω, 1%)

Class

Usage

Default

and the P

pin transitions from 0V to V

. This

OUT

PORTN

0

1

2

3

4

0.44 to 12.95

0.44 to 3.84

3.84 to 6.49

6.49 to 12.95

Reserved*

<5

10.5

18.5

28

Open

124

sequence is shown in Figure 1. The LTC4267 includes

a hysteretic UVLO circuit on V that keeps power

Optional

Reserved

PORTN

68.1

45.3

30.9

applied to the load until the input voltage falls below the

UVLO turn-off threshold. Once the input voltage drops

below –30V, the internal power MOSFET is turned off and

40

*Class 4 is currently reserved and should not be used.

4267f

12

LTC4267

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APPLICATIO S I FOR ATIO

U

the classiﬁcation current is reenabled. C1 will discharge

limit because the load capacitor is charged with a current

below the IEEE inrush current limit speciﬁcation.

through the PD circuitry and the P

impedance state.

pin will go to a high

OUT

AstheLTC4267switchesfromthelowtohighlevelcurrent

limit, the current will increase momentarily. This current

spike is a result of the LTC4267 charging the last 1.5V at

the high level current limit. When charging a 10µF capaci-

tor, the current spike is typically 100µs wide and 125%

of the nominal low level current limit.

+

C1

LTC4267

V

PORTP

5µF

MIN

TO

PSE

UNDERVOLTAGE

LOCKOUT

CIRCUIT

PGND

The LTC4267 stays in the high level current limit mode

until the input voltage drops below the UVLO turn-off

threshold. This dual level current limit provides the sys-

tem designer with the ﬂexibility to design PDs which are

compatible with legacy PSEs while also being able to take

advantage of the higher power allocation available in an

IEEE 802.3af system.

V

P

OUT

PORTN

4267 F05

CURRENT-LIMITED

TURN ON

INPUT

VOLTAGE

0V TO UVLO*

>UVLO*

LTC4267

POWER MOSFET

OFF

ON

*UVLO INCLUDES HYSTERESIS

RISING INPUT THRESHOLD ≅ –36V

FALLING INPUT THRESHOLD ≅ –30.5V

During the current limited turn on, a large amount of

power is dissipated in the power MOSFET. The LTC4267

PD interface is designed to accept this thermal load and

is thermally protected to avoid damage to the onboard

power MOSFET. Note that in order to adhere to the IEEE

802.3af standard, it is necessary for the PD designer to

ensurethePDsteadystatepowerconsumptionfallswithin

the limits shown in Table 2. In addition, the steady state

Figure 5. LTC4267 V_PORTNUndervoltage Lockout

Input Current Limit

IEEE802.3afspeciﬁesamaximuminrushcurrentandalso

speciﬁes a minimum load capacitor between the V

PORTP

and P

pins. To control turn-on surge current in the

OUT

system, the LTC4267 integrates a dual level current limit

circuit with an onboard power MOSFET and sense resis-

tor to provide a complete inrush control circuit without

additional external components. At turn-on, the LTC4267

will limit the input current to the low level, allowing the

loadcapacitortorampuptothelinevoltageinacontrolled

manner.

current must be less than I

.

LIM_HI

Power Good

The LTC4267 PD Interface includes a power good circuit

(Figure 6) that is used to indicate that load capacitor C1

is fully charged and that the switching regulator can start

operation. The power good circuit monitors the voltage

across the internal UVLO power MOSFET and PWRGD is

asserted when the voltage falls below 1.5V. The power

good circuit includes hysteresis to allow the LTC4267 to

operate near the current limit point without inadvertently

disabling PWRGD. The MOSFET voltage must increase to

3V before PWRGD is disabled.

The LTC4267 has been speciﬁcally designed to interface

with legacy PSEs which do not meet the inrush current

requirement of the IEEE 802.3af speciﬁcation. At turn-on

the LTC4267 current limit is set to the lower level. After C1

is charged up and the P

– V

voltage difference is

OUT

PORTN

below the power good threshold, the LTC4267 switches

to the high level current limit. The dual level current limit

allowslegacyPSEswithlimitedcurrentsourcingcapability

to power up the PD while also allowing the PD to draw full

power from an IEEE 802.3af PSE. The dual level current

limit also allows use of arbitrarily large load capacitors.

The IEEE 802.3af speciﬁcation mandates that at turn-on

the PD not exceed the inrush current limit for more than

50ms. The LTC4267 is not restricted to the 50ms time

If a sudden increase in voltage appears on the input line,

this voltage step will be transferred through capacitor C1

and appear across the power MOSFET. The response of

the LTC4267 will depend on the magnitude of the voltage

step, the rise time of the step, the value of capacitor C1

and the switching regulator load. For fast rising inputs,

4267f

13

LTC4267

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APPLICATIO S I FOR ATIO

R9

100k

LTC4267

PWRGD

Q1

2N7002

R9

100k

I

TH

/RUN

I

/RUN

V

THERMAL SHUTDOWN

TH

PORTP

PWRGD

LTC4267

TO

PSE

LTC3803

I

/RUN

TH

C17

UVLO

+

R18

5µF

100V

C1

C15

–

+

GND

C1

5µF

MIN

+

10k

TO

PSE

0.047µF

OPTIONAL

AUXILIARY

SWITCHING

REGULATOR

D6

MMBD4148

PGND

300k

V

P

–48V

PORTN

OUT

+

1.125V

PGND

–

300k

ACTIVE-HIGH ENABLE FOR RUN PIN WITH INTERNAL PULL-UP

V

P

OUT

PORTN

PGND

R

4267 F06

START

Q1

R9

Figure 6. LTC4267 Power Good

2N7002

100k

P

V

VCC

PORTP

PWRGD

LTC4267

TO

PSE

C

PVCC

+

R18

C1

C15

the LTC4267 will attempt to quickly charge capacitor C1

using an internal secondary current limit circuit. In this

scenario, the PSE current limit should provide the overall

limit for the circuit. For slower rising inputs, the 375mA

current limit in the LTC4267 will set the charge rate of the

capacitor C1. In either case, the PWRGD signal may go

inactive brieﬂy while the capacitor is charged up to the

new line voltage. In the design of a PD, it is necessary

to determine if a step in the input voltage will cause the

PWRGD signal to go inactive and how to respond to this

event. In some designs, it may be desirable to ﬁlter the

PWRGD signal so that intermittent power bad conditions

are ignored. Figure 7 demonstrates a method to insert a

lowpass ﬁlter on the power good interface.

10k

5µF

100V

0.047µF

D6

MMBD4148

PGND

V

P

–48V

PORTN

OUT

PGND

ALTERNATE ACTIVE-HIGH ENABLE FOR P

VCC

SEE APPLICATIONS INFORMATION SECTION

4267 F07

Figure 7. Power Good Interface Examples

PD Interface Thermal Protection

The LTC4267 PD Interface includes thermal overload

protection in order to provide full device functionality

in a miniature package while maintaining safe operat-

ing temperatures. Several factors create the possibility

of signiﬁcant power dissipation within the LTC4267. At

turn-on, before the load capacitor has charged up, the

instantaneous power dissipated by the LTC4267 can be

as much as 10W. As the load capacitor charges up, the

power dissipation in the LTC4267 will decrease until it

reaches a steady-state value dependent on the DC load

current. The size of the load capacitor determines how

fast the power dissipation in the LTC4267 will subside. At

room temperature, the LTC4267 can typically handle load

capacitors as large as 800µF without going into thermal

shutdown. With large load capacitors, the LTC4267 die

temperature will increase by as much as 50°C during a

single turn-on sequence. If for some reason power were

removed from the part and then quickly reapplied so that

theLTC4267hadtochargeuptheloadcapacitoragain, the

temperature rise would be excessive if safety precautions

were not implemented.

For PD designs that use a large load capacitor and also

consume a lot of power, it is important to delay activation

of the switching regulator with the PWRGD signal. If the

regulatorisnotdisabledduringthecurrent-limitedturn-on

sequence, the PD circuitry will rob current intended for

charging up the load capacitor and create a slow rising

input, possibly causing the LTC4267 to go into thermal

shutdown.

The PWRGD pin connects to an internal open drain, 100V

transistor capable of sinking 1mA. Low impedance to

V

indicates power is good. PWRGD is high imped-

PORTN

ance during signature and classiﬁcation probing and in

the event of a thermal overload. During turn-off, PWRGD

is deactivated when the input voltage drops below 30V.

In addition, PWRGD may go active brieﬂy at turn-on for

fast rising input waveforms. PWRGD is referenced to the

V

pin and when active, will be near the V

tential. ConnectthePWRGDpintotheswitchingregulator

circuitry as shown in Figure 7.

po-

The LTC4267 PD interface protects itself from thermal

damage by monitoring the die temperature. If the die

PORTN

4267f

14

LTC4267

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APPLICATIO S I FOR ATIO

U

temperature exceeds the overtemperature trip point, the

current is reduced to zero and very little power is dissi-

pated in the part until it cools below the overtemperature

set point. Once the LTC4267 has charged up the load

capacitor and the PD is powered and running, there will

be minor residual heating due to the DC load current of

the PD ﬂowing through the internal MOSFET. The DHC

packageofferssuperiorthermalperformancebyincluding

an exposed pad that is soldered to an electrically isolated

heat sink on the printed circuit board.

topology is desired, the LTC4267 features a feedback port

and an internal error ampliﬁer that can be enabled for this

speciﬁc application.

In the typical application circuit (Figure 11), the isolated

topology employs an external resistive voltage divider

to present a fraction of the output voltage to an external

error ampliﬁer. The error ampliﬁer responds by pulling

an analog current through the input LED on an optoiso-

lator. The collector of the optoisolator output presents a

corresponding current into the I /RUN pin via a series

TH

During classiﬁcation, excessive heating of the LTC4267

can occur if the PSE violates the 75ms probing time limit.

ToprotecttheLTC4267,thermaloverloadcircuitrywilldis-

able classiﬁcation current if the die temperature exceeds

the overtemperature trip point. When the die cools down

below the trip point, classiﬁcation current is reenabled.

diode. This method generates a feedback voltage on the

I /RUN pin while maintaining isolation.

TH

The voltage on the I /RUN pin controls the pulse-width

TH

modulator formed by the oscillator, current comparator,

and RS latch. Speciﬁcally, the voltage at the I /RUN pin

TH

sets the current comparator’s trip threshold. The current

comparator monitors the voltage across a sense resistor

in series with the source terminal of the external N-Chan-

nel MOSFET. The LTC4267 turns on the external power

MOSFET when the internal free-running 200kHz oscillator

sets the RS latch. It turns off the MOSFET when the cur-

rent comparator resets the latch or when 80% duty cycle

is reached, whichever happens ﬁrst. In this way, the peak

current levels through the ﬂyback transformer’s primary

The PD is designed to operate at a high ambient tem-

perature and with the maximum allowable supply (57V).

However, there is a limit to the size of the load capacitor

that can be charged up before the LTC4267 reaches the

overtemperature trip point. Hitting the overtemperature

trip point intermittently does not harm the LTC4267, but it

willdelaythecompletionofcapacitorcharging.Capacitors

up to 200µF can be charged without a problem over the

full operating temperature range.

and secondary are controlled by the I /RUN voltage.

TH

In applications where a nonisolated topology is desirable

(Figure11),anexternalresistivevoltagedividercanpresent

Switching Regulator Main Control Loop

Due to space limitations, the basics of current mode

DC/DC conversion will not be discussed here. The reader

is referred to the detail treatment in Application Note 19

or in texts such as Abraham Pressman’s Switching Power

Supply Design.

a fraction of the output voltage directly to the V pin of

FB

the LTC4267. The divider must be designed so when the

output is at its desired voltage, the V pin voltage will

FB

equal the 800mV onboard internal reference. The internal

error ampliﬁer responds by driving the I /RUN pin. The

TH

LTC4267switchingregulatorperformsinasimilarmanner

In a Power over Ethernet System, the majority of ap-

plications involve an isolated power supply design. This

means that the output power supply does not have any

DC electrical path to the PD interface or the switching

regulator primary. The DC isolation is achieved typically

through a transformer in the forward path and an op-

toisolator in the feedback path or a third winding in the

transformer. The typical application circuit shown on the

front page of the datasheet represents an isolated design

using an optoisolator. In applications where a nonisolated

as described previously.

Regulator Start-Up/Shutdown

The LTC4267 switching regulator has two shutdown

mechanisms to enable and disable operation: an un-

dervoltage lockout on the P

supply pin and a forced

VCC

shutdown whenever external circuitry drives the I /RUN

TH

pin low. The LTC4267 switcher transitions into and out of

shutdown according to the state diagram (Figure 8). It is

4267f

15

LTC4267

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APPLICATIO S I FOR ATIO

prevented from reaching maximum until 1.4ms have

passed. This allows the input current of the PD to rise in a

smoothandcontrolledmanneronstart-upandstaywithin

the current limit requirement of the LTC4267 interface.

important not to confuse the undervoltage lockout of the

PD interface at V

with that of the switching regulator

PORTN

at P . They are independent functions.

VCC

LTC4267

PWM

SHUTDOWN

Adjustable Slope Compensation

The LTC4267 switching regulator injects a 5µA peak cur-

rent ramp out through its SENSE pin which can be used

for slope compensation in designs that require it. This

current ramp is approximately linear and begins at zero

current at 6% duty cycle, reaching peak current at 80%

duty cycle. Programming the slope compensation via a

series resistor is discussed in the External Interface and

Component Selection section.

V

/RUN

ITHSHDN

ITH

V

> V

ITHSHDN

VCC

ITH/RUN

< V

P

< V

AND P

> V

TURNON

VCC

TURNOFF

(NOMINALLY

0.28V)

(NOMINALLY 8.7V)

LTC4267

PWM

ENABLED

ALL VOLTAGES WITH

RESPECT TO PGND

4267 F08

Figure 8. LTC4267 Switching Regulator

Start-Up/Shutdown State Diagram

EXTERNAL INTERFACE AND COMPONENT SELECTION

Input Interface Transformer

The undervoltage lockout mechanism on P

prevents

VCC

the LTC4267 switching regulator from trying to drive the

external N-Channel MOSFET with insufﬁcient gate-to-

Nodes on an Ethernet network commonly interface to the

outside world via an isolation transformer (Figure 9). For

PoE devices, the isolation transformer must include a

center tap on the media (cable) side. Proper termination

is required around the transformer to provide correct

impedance matching and to avoid radiated and conducted

emissions. Transformer vendors such as Pulse, Bel Fuse,

Tyco and others (Table 3) can provide assistance with

selectionofanappropriateisolationtransformerandproper

termination methods. These vendors have transformers

speciﬁcally designed for use in PD applications.

source voltage. The voltage at the P

pin must exceed

VCC

V

(nominally 8.7V with respect to PGND) at least

TURNON

momentarily to enable operation. The P

voltage must

VCC

fall to V

(nominally 5.7V with respect to PGND)

TURNOFF

before the undervoltage lockout disables the switching

regulator. This wide UVLO hysteresis range supports

applications where a bias winding on the ﬂyback trans-

former is used to increase the efﬁciency of the LTC4267

switching regulator.

The I /RUN can be driven below V

(nominally

ITHSHDN

TH

Table 3. Power over Ethernet Transformer Vendors

0.28VwithrespecttoPGND)toforcetheLTC4267switching

VENDOR

CONTACT INFORMATION

regulator into shutdown. An internal 0.3µA current source

Pulse Engineering

12220 World Trade Drive

San Diego, CA 92128

Tel: 858-674-8100

always tries to pull the I /RUN pin towards P . When

TH

VCC

ITHSHDN

the I /RUN pin voltage is allowed to exceed V

and

TH

VCC

P

exceeds V , the LTC4267 switching regulator

TURNON

FAX: 858-674-8262

http://www.pulseeng.com

begins to operate and an internal clamp immediately pulls

the I /RUN pin to about 0.7V. In operation, the I /RUN

pinvoltagewillvaryfromroughly0.7Vto1.9Vtorepresent

current comparator thresholds from zero to maximum.

Bel Fuse Inc.

206 Van Vorst Street

Jersey City, NJ 07302

Tel: 201-432-0463

TH

FAX: 201-432-9542

http://www.belfuse.com

Internal Soft-Start

Tyco Electronics

308 Constitution Drive

Menlo Park, CA 94025-1164

Tel: 800-227-7040

FAX: 650-361-2508

http://www.circuitprotection.com

An internal soft-start feature is enabled whenever the

LTC4267 switching regulator comes out of shutdown.

Speciﬁcally, the I /RUN voltage is clamped and is

TH

4267f

16

LTC4267

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APPLICATIO S I FOR ATIO

Diode Bridge

falls into and then select the appropriate value of R

CLASS

from Table 2. If a unique load current is required, the value

IEEE 802.3af allows power wiring in either of two conﬁgu-

rations: on the TX/RX wires or via the spare wire pairs in

the RJ45 connector. The PD is required to accept power in

eitherpolarityoneitherthemainorspareinputs;therefore

it is common to install diode bridges on both inputs in

ordertoaccommodatethedifferentwiringconﬁgurations.

Figure 9 demonstrates an implementation of these diode

bridges. The IEEE 802.3af speciﬁcation also mandates

that the leakage back through the unused bridge be less

than 28µA when the PD is powered with 57V.

of R

can be calculated as:

CLASS

R

= 1.237V/(I

– I

)

CLASS

DESIRED

IN_CLASS

where I

is the LTC4267 IC supply current during

classiﬁcation and is given in the electrical speciﬁcations.

TheR resistormustbe1%orbettertoavoiddegrading

IN_CLASS

CLASS

the overall accuracy of the classiﬁcation circuit. Resistor

powerdissipationwillbe50mWmaximumandistransient

so heating is typically not a concern. In order to maintain

loop stability, the layout should minimize capacitance at

TheIEEEstandardincludesanACimpedancerequirement

in order to implement the AC disconnect function. Capaci-

tor C14 in Figure 9 is used to meet this AC impedance

requirement. A 0.1µF capacitor is recommended for this

application.

the R

node. The classiﬁcation circuit can be disabled

CLASS

by ﬂoating the R

shorted to V

pin. The R

pin should not be

as this would force the LTC4267 clas-

CLASS

PORTN

siﬁcation circuit to attempt to source very large currents

and quickly go into thermal shutdown.

The LTC4267 has several different modes of operation

Power Good Interface

based on the voltage present between V

and V

PORTN

PORTP

The PWRGD signal is controlled by a high voltage, open-

drain transistor. The designer has the option of using this

signal to enable the onboard switching regulator through

pins. The forward voltage drop of the input diodes in a PD

design subtracts from the input voltage and will affect the

transitionpointbetweenmodes.WhenusingtheLTC4267,

itisnecessarytopaycloseattentiontothisforwardvoltage

drop. Selection of oversized diodes will help keep the PD

thresholds from exceeding IEEE speciﬁcations.

the I /RUN or the P

pins. Examples of active-high

TH

VCC

interface circuits for controlling the switching regulator

are shown in Figure 7.

In some applications, it is desirable to ignore intermittent

power bad conditions. This can be accomplished by in-

cluding capacitor C15 in Figure 7 to form a lowpass ﬁlter.

With the components shown, power bad conditions less

than about 200µs will be ignored. Conversely, in other

applications it may be desirable to delay assertion of

The input diode bridge of a PD can consume over 4%

of the available power in some applications. It may be

desirable to use Schottky diodes in order to reduce power

loss. However, if the standard diode bridge is replaced

with a Schottky bridge, the transition points between the

modes will be affected. Figure 10 shows a technique for

usingSchottkydiodeswhilemaintainingproperthreshold

points to meet IEEE 802.3af compliance. D13 is added to

compensateforthechangeinUVLOturn-onvoltagecaused

by the Schottky diodes and consumes little power.

PWRGD to the switching regulator using C

as shown in Figure 7.

or C17

PVCC

It is recommended that the designer use the power

good signal to enable the switching regulator. Using

PWRGD ensures the capacitor C1 has reached within

1.5V of the ﬁnal value and is ready to accept a load. The

LTC4267 is designed with wide power good hysteresis

to handle sudden ﬂuctuations in the load voltage and

current without prematurely shutting off the switching

regulator. Please refer to the Power-Up Sequencing of the

Application Information section.

Classiﬁcation Resistor Selection (R

)

CLASS

The IEEE speciﬁcation allows classifying PDs into four

distinct classes with class 4 being reserved for future use

(Table 2). An external resistor connected from R

PORTN

designer should determine which power category the PD

to

CLASS

V

(Figure 4) sets the value of the load current. The

4267f

17

LTC4267

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APPLICATIO S I FOR ATIO

RJ45

+

TX

16 T1

1

BR1

HD01

15

2

–

TX

14

11

3

6

2

3

+

TO PHY

RX

10

9

7

8

–

RX

6

PULSE H2019

V

PORTP

+

–

SPARE

4

5

7

8

BR2

HD01

LTC4267

C14

0.1µF

100V

D3

SMAJ58A

TVS

SPARE

V

PORTN

4267 F09

Figure 9. PD Front End with Isolation Transformer, Diode Bridges and Capacitor

D11

B1100

D9

B1100

R2

75Ω

R1

75Ω

C3

C7

0.01µF

D10

B1100

D12

B1100

200V

C11

0.1µF

100V

D6

SMAJ58A

C2

1000pF

2kV

OUT

J2

TO PHY

T1

+

–

16

1

2

3

TX

+

TXOUT

1

15

14

D13

MMSD4148

–

TXOUT

2

3

6

C25

0.01µF

200V

C24

0.01µF

200V

+

–

RX

11

10

9

6

7

8

+

RXOUT

IN

FROM

PSE

R31

75Ω

R30

75Ω

–

RXOUT

D14

B1100

4

+

SPARE

5

7

8

D15

B1100

–

RJ45

R

V

V_PORTP

CLASS

D17

B1100

D16

B1100

LTC4267

R

CLASS

NOTES: UNLESS OTHERWISE SPECIFIED

1. ALL RESISTORS ARE 5%

1%

2. SELECT R

FOR CLASS 1-4 OPERATION. REFER

PORTN

CLASS

TO DATA SHEET APPLICATIONS INFORMATION SECTION

C2: AVX 1808GC102MAT

4267 F10

D9 TO D12, D14 TO D17: DIODES INC., B1100

T1: PULSE H2019

Figure 10. PD Front End with Isolation Transformer, 2nd Schottky Diode Bridge

4267f

18

LTC4267

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APPLICATIO S I FOR ATIO

U

Signature Disable Interface

output voltage reaches its ﬁnal value, the input current

limit will be restored to its nominal value.

Todisablethe25kΩsignatureresistor,connectSIGDISApin

to the V

pin. Alternately, SIGDISA pin can be driven

The load capacitor can store signiﬁcant energy when fully

charged. The design of a PD must ensure that this energy

is not inadvertently dissipated in the LTC4267. The polar-

ity-protection diode(s) prevent an accidental short on the

PORTP

high with respect to V

. An example of a signature

PORTN

disable interface is shown in Figure 16, option 2. Note that

the SIGDISA input resistance is relatively large and the

threshold voltage is fairly low. Because of high voltages

presentontheprintedcircuitboard, leakagecurrentsfrom

cable from causing damage. However, if the V

PORTN

is shorted to V

inside the PD while the capacitor

PORTP

the V

pin could inadvertently pull SIGDISA high. To

is charged, current will ﬂow through the parasitic body

diode of the internal MOSFET and may cause permanent

damage to the LTC4267.

PORTP

ensure trouble-free operation, use high voltage layout

techniques in the vicinity of SIGDISA. If unused, connect

SIGDISA to V

.

PORTN

Maintain Power Signature

Load Capacitor

In an IEEE 802.3af system, the PSE uses the maintain

power signature (MPS) to determine if a PD continues to

require power. The MPS requires the PD to periodically

draw at least 10mA and also have an AC impedance less

than 26.25kΩ in parallel with 0.05µF. If either the DC

current is less than 10mA or the AC impedance is above

26.25kΩ, the PSE may disconnect power. The DC current

must be less than 5mA and the AC impedance must be

above 2MΩ to guarantee power will be removed.

TheIEEE802.3afspeciﬁcationrequiresthatthePDmaintain

a minimum load capacitance of 5µF (provided by C1 in

Figure 11). It is permissible to have a much larger load

capacitor and the LTC4267 can charge very large load

capacitors before thermal issues become a problem. The

load capacitor must be large enough to provide sufﬁcient

energy for proper operation of the switching regulator.

However, the capacitor must not be too large or the PD

design may violate IEEE 802.3af requirements.

Selecting Feedback Resistor Values

If the load capacitor is too large, there can be a problem

with inadvertent power shutdown by the PSE. Consider

the following scenario. If the PSE is running at –57V

(maximumallowed)andthePDhasdetectedandpowered

up, the load capacitor will be charged to nearly –57V. If

for some reason the PSE voltage is suddenly reduced to

–44V(minimumallowed),theinputbridgewillreversebias

and the PD power will be supplied by the load capacitor.

DependingonthesizeoftheloadcapacitorandtheDCload

of the PD, the PD will not draw any power for a period of

time.IfthisperiodoftimeexceedstheIEEE802.3af300ms

disconnect delay, the PSE will remove power from the PD.

For this reason, it is necessary to ensure that inadvertent

shutdown cannot occur.

The regulated output voltage of the switching regulator is

determined by the resistor divider across V

(R1 and

OUT

R2 in Figure 11) and the error ampliﬁer reference voltage

. The ratio of R2 to R1 needed to produce the desired

V

REF

voltage can be calculated as:

R2 = R1 • (V – V )/V

OUT

REF REF

Inanisolatedpowersupplyapplication,V isdetermined

REF

by the designer’s choice of an external error ampliﬁer.

Commercially available error ampliﬁers or programmable

shunt regulators may include an internal reference of

1.25V or 2.5V. Since the LTC4267 internal reference and

error ampliﬁer are not used in an isolated design, tie the

V

pin to PGND.

FB

Very small output capacitors (≤10µF) will charge very

quickly in current limit. The rapidly changing voltage at

the output may reduce the current limit temporarily, caus-

ing the capacitor to charge at a somewhat reduced rate.

Conversely, charging a very large capacitor may cause the

current limit to increase slightly. In either case, once the

In a nonisolated power supply application, the LTC4267

onboard internal reference and error ampliﬁer can be

used. The resistor divider output can be tied directly to

the V pin. The internal reference of the LTC4267 is 0.8V

FB

nominal.

4267f

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APPLICATIO S I FOR ATIO

Choose resistance values for R1 and R2 to be as large as

selecting the transformer turns ratio. The PD designer

can use simple ratios of small integers (i.e. 1:1, 2:1, 3:2)

which yields more freedom in setting the total turns and

mutual inductance and may allow the use of an off the

shelf transformer.

possible to minimize any efﬁciency loss due to the static

current drawn from V , but just small enough so that

OUT

whenV isinregulation,theerrorcausedbythenonzero

OUT

input current from the output of the resistor divider to the

error ampliﬁer pin is less that 1%.

Transformer leakage inductance on either the primary or

secondarycausesavoltagespiketooccuraftertheoutput

switch (Q1 in Figure 11) turns off. The input supply volt-

age plus the secondary-to-primary referred voltage of the

ﬂyback pulse (including leakage spike) must not exceed

theallowedexternalMOSFETbreakdownrating.Thisspike

is increasingly prominent at higher load currents, where

more stored energy must be dissipated. In some cases,

a “snubber” circuit will be required to avoid overvoltage

breakdown at the MOSFET’s drain node. Application

Note 19 is a good reference for snubber design.

Error Ampliﬁer and Optoisolator Considerations

In an isolated topology, the selection of the external error

ampliﬁer depends on the output voltage of the switching

regulator. Typical error ampliﬁers include a voltage refer-

ence of either 1.25V or 2.5V. The output of the ampliﬁer

and the ampliﬁer upper supply rail are often tied together

internally. The supply rail is usually speciﬁed with a wide

upper voltage range, but it is not allowed to fall below the

reference voltage. This can be a problem in an isolated

switcher design if the ampliﬁer supply voltage is not prop-

erly managed. When the switcher load current decreases

and the output voltage rises, the error ampliﬁer responds

by pulling more current through the LED. The LED voltage

Current Sense Resistor Consideration

The external current sense resistor (R

in Figure 11)

SENSE

allows the designer to optimize the current limit behavior

for a particular application. As the current sense resistor

is varied from several ohms down to tens of milliohms,

peak swing current goes from a fraction of an ampere to

several amperes. Care must be taken to ensure proper

circuit operation, especially for small current sense resis-

tor values.

can be as large as 1.5V, and along with R , reduces the

LIM

supply voltage to the error ampliﬁer. If the error amp does

not have enough headroom, the voltage drop across the

LED and R

may shut the ampliﬁer off momentarily,

LIM

causingalock-upconditioninthemainloop. Theswitcher

will undershoot and not recover until the error ampliﬁer

releases its sink current. Care must be taken to select the

Choose R

such that the switching current exercises

SENSE

referencevoltageandR valuesothattheerrorampliﬁer

LIM

theentirerangeoftheI /RUNvoltage.Thenominalvoltage

TH

always has enough headroom. An alternate solution that

avoids these problems is to utilize the LT1431 or LTC4430

wheretheoutputoftheerrorampliﬁerandampliﬁersupply

rail are brought out to separate pins.

range is 0.7V to 1.9V and R

can be determined by

SENSE

experiment. The main loop can be temporarily stabilized

byconnectingalargecapacitoronthepowersupply.Apply

the maximum load current allowable at the power sup-

The PD designer must also select an optoisolator such

that its bandwidth is sufﬁciently wider than the bandwidth

of the main control loop. If this step is overlooked, the

main control loop may be difﬁcult to stabilize. The output

collector resistor of the optoisolator can be selected for

an increase in bandwidth at the cost of a reduction in gain

of this stage.

ply output based on the class of the PD. Choose R

SENSE

such that I /RUN approaches 1.9V. Finally, exercise the

TH

output load current over the entire operating range and

ensure that I /RUN voltage remains within the 0.7V to

TH

1.9V range. Layout is critical around the R

resistor.

SENSE

For example, a 0.020Ω sense resistor, with one milliohm

(0.001Ω)ofparasiticresistancewillcausea5%reduction

in peak switch current. The resistance of printed circuit

copper traces cannot necessarily be ignored and good

layout techniques are mandatory.

Output Transformer Design Considerations

Since the external feedback resistor divider sets the

output voltage, the PD designer has relative freedom in

4267f

20

LTC4267

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APPLICATIO S I FOR ATIO

U

ISOLATED DESIGN EXAMPLE

D1

T1

V

PORTP

V

+

–

OUT

–48V

FROM

•

C1

R

C

START

L

SEC

OUT

PRI

DATA PAIR

PGND

P

•

VCC

C

PVCC

P

VCC

PGND

NGATE

V

Q1

PORTP

0.1µF

100V

R

LIM

R

SL

CLASS

SENSE

LTC4267

R

CLASS

+

–

–48V

FROM

SPARE PAIR

R

SENSE

SIGDISA

PGND

PORTP

V

PORTN

V

FB

PORTN

I

/RUN

OUT

TH

OPTOISOLATOR

P

PGND

P

ERROR

AMPLIFIER

VCC

PGND

R

C

R2

R1

C

PGND

C

ISO

NONISOLATED DESIGN EXAMPLE

T1

L

BIAS

D2

•

D1

PGND

C1

V

+

–

OUT

–48V

FROM

R

V

R3

START

L

SEC

C

PRI

OUT

DATA PAIR

PGND

•

C

PVCC

PGND

P

PGND

VCC

0.1µF

100V

NGATE

Q1

PORTP

R

CLASS

SL

SENSE

LTC4267

R

CLASS

+

–

–48V

FROM

SPARE PAIR

R

SENSE

SIGDISA

R2

PGND

V

PORTN

V

FB

I

/RUN

TH

P

PGND

R1

OUT

C

4267 F11

PGND

Figure 11. Typical LTC4267 Application Circuits

4267f

21

LTC4267

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APPLICATIO S I FOR ATIO

Programmable Slope Compensation

is providing virtually all the supply current required by the

LTC4267 switching regulator.

TheLTC4267switchingregulatorinjectsarampingcurrent

throughitsSENSEpinintoanexternalslopecompensation

One potential design pitfall is under-sizing the value of

resistor (R in Figure 11). This current ramp starts at

capacitor C

. In this case, the normal supply current

SL

PVCC

zero after the NGATE pin has been high for the LTC4267’s

minimum duty cycle of 6%. The current rises linearly to-

wards a peak of 5µA at the maximum duty cycle of 80%,

shutting off once the NGATE pin goes low. A series resis-

drawnthroughP willdischargeC

rapidlybeforethe

VCC

PVCC

third winding drive becomes effective. Depending on the

particular situation, this may result in either several off-on

cycles before proper operation is reached or permanent

tor (R ) connecting the SENSE pin to the current sense

relaxation oscillation at the P

node.

SL

VCC

resistor (R

) develops a ramping voltage drop. From

SENSE

Resistor R

should be selected to yield a worst-case

START

the perspective of the LTC4267 SENSE pin, this ramping

voltage adds to the voltage across the sense resistor,

effectively reducing the current comparator threshold in

proportion to duty cycle. This stabilizes the control loop

against subharmonic oscillation. The amount of reduction

in the current comparator threshold (∆V

calculated using the following equation:

minimumchargingcurrentgreaterthatthemaximumrated

LTC4267start-upcurrenttoensurethereisenoughcurrent

to charge C

to the P

turn-on threshold. R

VCC START

PVCC

should also be selected large enough to yield a worst-case

maximum charging current less than the minimum-rated

) can be

SENSE

P

supply current, so that in operation, most of the

current is delivered through the third winding. This

results in the highest possible efﬁciency.

VCC

∆V

= 5µA • R • [(Duty Cycle – 6%)/74%]

SENSE

SL

Note: The LTC4267 enforces 6% < Duty Cycle < 80%.

CapacitorC shouldthenbemadelargeenoughtoavoid

PVCC

the relaxation oscillation behavior described previously.

This is difﬁcult to determine theoretically as it depends on

the particulars of the secondary circuit and load behavior.

Empirical testing is recommended.

DesignsnotneedingslopecompensationmayreplaceR

with a short-circuit.

SL

Applications Employing a Third Transformer Winding

The third transformer winding should be designed so

that its output voltage, after accounting for the forward

A standard operating topology may employ a third

winding on the transformer’s primary side that provides

diode voltage drop, exceeds the maximum P

turn-off

VCC

power to the LTC4267 switching regulator via its P

VCC

threshold.Also,thethirdwinding’snominaloutputvoltage

(Figure 11). However, this arrangement is not inherently

self-starting.Start-upisusuallyimplementedbytheuseof

should be at least 0.5V below the minimum rated P

VCC

clamp voltage to avoid running up against the LTC4267

an external “trickle-charge” resistor (R

) in conjunc-

START

shunt regulator, needlessly wasting power.

tionwiththeinternalwidehysteresisundervoltagelockout

circuit that monitors the P

pin voltage.

VCC

P

Shunt Regulator

VCC

R

is connected to V

and supplies a current,

START

PORTP

In applications including a third transformer winding,

the internal P shunt regulator serves to protect the

typically 100µA, to charge C

. After some time, the

turn-on threshold. The

PVCC

VCC

voltage on C

reaches the P

PVCC

LTC4267 switching regulator from overvoltage transients

as the third winding is powering up.

LTC4267 switching regulator then turns on abruptly and

draws its normal supply current. The NGATE pin begins

switching and the external MOSFET (Q1) begins to deliver

If a third transformer winding is undesirable or unavail-

able, the shunt regulator allows the LTC4267 switching

regulatortobepoweredthroughasingledroppingresistor

power. The voltage on C

begins to decline as the

PVCC

switchingregulatordrawsitsnormalsupplycurrent,which

exceedsthedeliveryfromR .Aftersometime,typically

from V

as shown in Figure 12. This simplicity comes

START

PORTP

tens of milliseconds, the output voltage approaches the

desired value. By this time, the third transformer winding

at the expense of reduced efﬁciency due to static power

dissipation in the R dropping resistor.

START

4267f

22

LTC4267

W U U

APPLICATIO S I FOR ATIO

U

actual current needed to power the LTC4267 switching

The shunt regulator can sink up to 5mA through the P

VCC

must be

regulator goes through Q1 and P

sources current on

pin to PGND. The values of R

and C

VCC

START

PVCC

an “as-needed” basis. The static current is then limited

selected for the application to withstand the worst-case

load conditions and drop on P , ensuring that the P

only to the current through R and D1.

B

VCC

turn-off threshold is not reached. C

should be sized

PVCC

+

sufﬁcientlytohandletheswitchingcurrentneededtodrive

NGATE while maintaining minimum switching voltage.

R

B

R

V

START

PORTP

Q1

D1

8.2V

–48

FROM

PSE

+

P

VCC

PGND

LTC4267

PGND

V

PORTP

C

PVCC

R

START

–48

FROM

PSE

PGND

P

VCC

P

–

V

PORTN

OUT

LTC4267

PGND

C

PVCC

4267 F15

PGND

Figure 13. Powering the LTC4267 Switching

Regulator with an External Preregulator

P

–

V

PORTN

OUT

PGND

4267 F14

Figure 12. Powering the LTC4267 Switching

Regulator via the Shunt Regulator

Compensating the Main Loop

Inanisolatedtopology,thecompensationpointistypically

chosenbythecomponentsconﬁguredaroundtheexternal

error ampliﬁer. Shown in Figure 14, a series RC network

is connected from the compare voltage of the error am-

pliﬁer to the error ampliﬁer output. In PD designs where

External Preregulator

The circuit in Figure 13 shows a third way to power the

LTC4267 switching regulator circuit. An external series

preregulator consists of a series pass transistor Q1, zener

transient load response is not critical, replace R with a

Z

short.TheproductofR2andC shouldbesufﬁcientlylarge

C

diode D1, and a bias resistor R . The preregulator holds

B

to ensure stability. When fast settling transient response

P

at7.6Vnominal, wellabovethemaximumratedP

VCC

is critical, introduce a zero set by R C . The PD designer

Z C

turn-off threshold of 6.8V. Resistor R

momentarily

START

turn-on threshold,

must ensure that the faster settling response of the output

charges the P

node up to the P

VCC

voltage does not compromise loop stability.

enabling the switching regulator. The voltage on C

PVCC

begins to decline as the switching regulator draws its

In a nonisolated design, the LTC4267 incorporates an

normal supply current, which exceeds the delivery of

internal error ampliﬁer where the I /RUN pin serves as

TH

R

. After some time, the output voltage approaches

START

a compensation point. In a similar manner, a series RC

the desired value. By this time, the pass transistor Q1

network can be connected from I /RUN to PGND as

TH

catchesthedecliningvoltageontheP pin,andprovides

VCC

shown in Figure 15. C and R are chosen for optimum

C

Z

virtually all the supply current required by the LTC4267

load and line transient response.

switching regulator. C

should be sized sufﬁciently to

PVCC

C

R

Z

handle the switching current needed to drive NGATE while

maintaining minimum switching voltage.

V

OUT

TO OPTO-

ISOLATOR

R2

The external preregulator has improved efﬁciency over

the simple resistor-shunt regulator method mentioned

R1

previously. R can be selected so that it provides a small

4267 F14

B

current necessary to maintain the zener diode voltage and

themaximumpossiblebasecurrentQ1willencounter.The

Figure 14. Main Loop Compensation for an Isolated Design

4267f

23

LTC4267

W U U

U

APPLICATIO S I FOR ATIO

of the LTC4267. In this case, it is necessary to ensure the

user cannot access the terminals of the wall transformer

jack on the PD since this would compromise the 802.3af

isolation safety requirements.

LTC4267

I

/RUN

PGND

Z

TH

C

R

Figure 16 demonstrates three methods of diode ORing

external power into a PD. Option 1 inserts power before

the LTC4267 interface controller while options 2 and 3

bypasstheLTC4267interfacecontrollersectionandpower

the switching regulator directly.

4267 F15

Figure 15. Main Loop Compensation for a Nonisolated Design

If power is inserted before the LTC4267 interface con-

troller, it is necessary for the wall transformer to exceed

the LTC4267 UVLO turn-on requirement and include a

transient voltage suppressor (TVS) to limit the maximum

voltage to 57V. This option provides input current limit

for the transformer, provides a valid power good signal,

and simpliﬁes power priority issues. As long as the wall

transformer applies power to the PD before the PSE, it

will take priority and the PSE will not power up the PD

because the wall power will corrupt the 25kΩ signature. If

the PSE is already powering the PD, the wall transformer

power will be in parallel with the PSE. In this case, prior-

ity will be given to the higher supply voltage. If the wall

transformer voltage is higher, the PSE should remove the

line voltage since no current will be drawn from the PSE.

On the other hand, if the wall transformer voltage is lower,

the PSE will continue to supply power to the PD and the

walltransformerwillnotbeused. Properoperationshould

occur in either scenario.

Selecting the Switching Transistor

With the N-channel power MOSFET driving the primary of

the transformer, the inductance will cause the drain of the

MOSFET to traverse twice the voltage across V

PGND. The LTC4267 operates with a maximum supply of

– 57V; thus the MOSFET must be rated to handle 114V or

morewithsufﬁcientdesignmargin.Typical transistorshave

150V ratings while some manufacturers have developed

120V rated MOSFETs speciﬁcally for Power-over-Ethernet

applications.

and

PORTP

The NGATE pin of the LTC4267 drives the gate of the

N-channel MOSFET. NGATE will traverse a rail-to-rail volt-

age from PGND to P . The designer must ensure the

VCC

MOSFET provides a low “ON” resistance when switched

to P

as well as ensure the gate of the MOSFET can

VCC

handle the P

supply voltage.

VCC

For high efﬁciency applications, select an N-channel

MOSFET with low total gate charge. The lower total gate

charge improves the efﬁciency of the NGATE drive circuit

and minimizes the switching current needed to charge

and discharge the gate.

IfauxiliarypowerisapplieddirectlytotheLTC4267switch-

ing regulator (bypassing the LTC4267 PD interface), a

different set of tradeoffs arise. In the conﬁguration shown

in option 2, the wall transformer does not need to exceed

the LTC4267 turn-on UVLO requirement; however, it is

necessary to include diode D9 to prevent the transformer

from applying power to the LTC4267 interface controller.

The transformer voltage requirement will be governed by

the needs of the onboard switching regulator. However,

power priority issues require more intervention. If the

wall transformer voltage is below the PSE voltage, then

priority will be given to the PSE power. The LTC4267

interface controller will draw power from the PSE while

the transformer will sit unused. This conﬁguration is not

a problem in a PoE system. On the other hand, if the wall

4267f

Auxiliary Power Source

In some applications, it may be desirable to power the

PD from an auxiliary power source such as a wall trans-

former. The auxiliary power can be injected into the PD at

several locations and various trade-offs exist. Power can

be injected at the 3.3V or 5V output of the isolated power

supply with the use of a diode ORing circuit. This method

accesses the internal circuits of the PD after the isolation

barrier and therefore meets the 802.3af isolation safety

requirements for the wall transformer jack on the PD.

Power can also be injected into the PD interface portion

24

LTC4267

W U U

U

APPLICATIO S I FOR ATIO

OPTION 1: AUXILIARY POWER INSERTED BEFORE LTC4267 PD

RJ45

1

+

T1

TX

D3

SMAJ58A

TVS

~

+

–

C14

0.1µF

100V

TX

R

START

2

3

+

–

BR1

HD01

TO PHY

RX

C1

RX

6

V

PORTP

+

–

P

SPARE

VCC

LTC4267

PGND

4

5

7

8

~

+

–

BR2

HD01

C

PVCC

SPARE

V

P

PORTN OUT

PGND

+

D8

S1B

ISOLATED

WALL

TRANSFORMER

38V TO 57V

–

OPTION 2: AUXILIARY POWER INSERTED AFTER LTC4267 PD WITH SIGNATURE DISABLED

RJ45

1

+

T1

TX

D3

SMAJ58A

~

+

–

TVS

100k

C14

0.1µF

100V

R

START

2

3

+

BR1

HD01

TO PHY

RX

–

C1

BSS63

RX

6

V

PORTP

100k

+

–

SIGDISA

SPARE

4

5

7

8

~

+

–

P

VCC

LTC4267

PGND

BR2

HD01

C

PVCC

SPARE

V

P

PORTN OUT

PGND

D9

+

–

S1B

ISOLATED

WALL

TRANSFORMER

D10

S1B

OPTION 3: AUXILIARY POWER APPLIED TO LTC4267 PD AND SWITCHING REGULATOR

RJ45

1

+

T1

TX

D3

SMAJ58A

~

+

–

TVS

C14

0.1µF

100V

R

START

2

3

+

BR1

HD01

TO PHY

RX

–

C1

RX

6

V

PORTP

P

+

–

VCC

LTC4267

SPARE

4

5

7

8

~

+

–

BR2

HD01

C

PVCC

PGND

SPARE

V

P

PORTN OUT

PGND

+

D10

S1B

ISOLATED

WALL

TRANSFORMER

38V TO 57V

4267 F16

–

Figure 16. Auxiliary Power Source for PD

4267f

25

LTC4267

W U U

U

APPLICATIO S I FOR ATIO

transformer voltage is higher than the PSE voltage, the

LTC4267 switching regulator will draw power from the

transformer.Inthissituation,itisnecessarytoaddressthe

issue of power cycling that may occur if a PSE is present.

The PSE will detect the PD and apply power. If the switcher

is being powered by the wall transformer, then the PD will

not meet the minimum load requirement and the PSE will

subsequently remove power. The PSE will again detect

the PD and power cycling will start. With a transformer

voltage above the PSE voltage, it is necessary to either

disable the signature, as shown in option 2, or install a

minimum load on the output of the LTC4267 interface to

prevent power cycling.

to drive the I /RUN port below the shutdown threshold

TH

(typically 0.28V). The second example drives P

below

VCC

theP turn-offthreshold.Employingthesecondexample

VCC

has the added advantage of adding delay to the switching

regulator start-up beyond the time the power good signal

becomes active. The second example ensures additional

timingmarginatstart-upwithouttheneedforaddeddelay

components. In applications where it is not desirable to

utilize the power good signal, sufﬁcient timing margin can

be achieved with R

and C

. R

and C

START

PVCC START PVCC

should be set to a delay of two to three times longer than

the duration needed to charge up C1.

Layout Considerations for the LTC4267

ThethirdoptionalsoappliespowerdirectlytotheLTC4267

switching regulator, bypassing the LTC4267 interface

controller and omitting diode D9. With the diode omit-

ted, the transformer voltage is applied to the LTC4267

interface controller in addition to the switching regulator.

For this reason, it is necessary to ensure that the trans-

former maintain the voltage between 38V and 57V to keep

the LTC4267 interface controller in its normal operating

range. The third option has the advantage of automatically

disabling the 25kΩ signature resistor when the external

voltage exceeds the PSE voltage.

The most critical layout considerations for the LTC4267

are the placement of the supporting external components

associatedwiththeswitching regulator.Efﬁciency,stability,

and load transient response can deteriorate without good

layout practices around critical components.

For the LTC4267 switching regulator, the current loop

through C1, T1 primary, Q1, and R

must be given

SENSE

careful layout attention. (Refer to Figure 11.) Because of

the high switching current circulating in this loop, these

components should be placed in close proximity to each

other. In addition, wide copper traces or copper planes

should be used between these components. If vias are

necessary to complete the connectivity of this loop,

placing multiple vias lined perpendicular to the ﬂow of

currentisessentialforminimizingparasiticresistanceand

reducing current density. Since the switching frequency

and the power levels are substantial, shielding and high

frequency layout techniques should be employed. A low

current, low impedance alternate connection should be

employed between the PGND pins of the LTC4267 and the

Power-Up Sequencing the LTC4267

The LTC4267 consists of two functional cells, the PD

interface and the switching regulator, and the power up

sequencingofthesetwocellsmustbecarefullyconsidered.

ThePDdesignershouldensurethattheswitchingregulator

does not begin operation until the interface has completed

charging up the load capacitor. This will ensure that the

switcher load current does not compete with the load

capacitor charging current provided by the PD interface

current limit circuit. Overlooking this consideration may

resultinslowpowersupplyrampup,power-uposcillation,

and possibly thermal shutdown.

PGND side of R

, away from the high current loop.

SENSE

ThisKelvinsensingwillensureanaccuraterepresentation

of the sense voltage is measured by the LTC4267.

TheLTC4267 includesa power good signalin the PD inter-

face that can be used to indicate to the switching regulator

that the load capacitor is fully charged and ready to handle

the switcher load. Figure 7 shows two examples of ways

the PWRGD signal can be used to control the switching

regulator.TheﬁrstexampleemploysanN-channelMOSFET

The placement of the feedback resistors R1 and R2 as

well as the compensation capacitor C is very important

C

in the accuracy of the output voltage, the stability of the

main control loop, and the load transient response. In

an isolated design application, R1, R2, and C should be

C

placed as close as possible to the error ampliﬁer’s input

4267f

26

LTC4267

W U U

APPLICATIO S I FOR ATIO

U

or capacitive may inadvertently disable the signature

resistance. To ensure consistent behavior, the SIGDISA

pin should be electrically connected and not left ﬂoating.

Voltages in a PD can be as large as –57V, so high voltage

layout techniques should be employed.

with minimum trace lengths and minimum capacitance.

In a nonisolated application, R1, and R2 should be placed

as close as possible to the V pin of the LTC4267 and

FB

C should be placed close to the I /RUN pin of the

C

TH

LTC4267.

In essence, a tight overall layout of the high current loop

and careful attention to current density will ensure suc-

cessful operation of the LTC4267 in a PD.

Electro Static Discharge and Surge Protection

The LTC4267 is speciﬁed to operate with an absolute

maximum voltage of –100V and is designed to tolerate

brief overvoltage events. However, the pins that interface

The PD interface section of the LTC4267 is relatively im-

munetolayoutproblems. Excessiveparasiticcapacitance

to the outside world (primarily V

and V

) can

PORTN

PORTP

on the R

pin should be avoided. If using the DHC

CLASS

routinely see peak voltages in excess of 10kV. To protect

the LTC4267, it is highly recommended that a transient

voltage suppressor be installed between the diode bridge

and the LTC4267 (D3 in Figure 2).

package, includeanelectricallyisolatedheatsinktowhich

the exposed pad on the bottom of the package can be

soldered. For optimum thermal performance, make the

heatsinkaslargeaspossible. TheSIGDISApinisadjacent

to the V

pin and any coupling, whether resistive

PORTP

4267f

27

LTC4267

U

TYPICAL APPLICATIO S

A High-Efﬁciency Class 3 PD with 3.3V Isolated Power Supply

470pF

10Ω

PULSE

PA1136

SBM1040

570µF**

3.3V

2.6A

•

5µF*

MIN

220k

330Ω

CHASSIS

•

510Ω

MMTBA42

BAS516

150pF

9.1V

4.7µF

10k

MMSD4148

BAS516

–48V

FROM

DATA PAIR

P

VCC

•

V

P

PORTP

VCC

LTC4267

SMAJ58A

B1100

(8 PLACES)

Si3440

NGATE

SENSE

/RUN

0.1µF

P

VCC

0.068Ω

500Ω

1%

R

I

–48V

FROM

CLASS

TH

6.8k

P

VCC

SPARE PAIR

100k

1%

45.3Ω

1%

33nF

100k

10k

BAS516

2N7002

SIGDISA

PWRGD

PS2911

V

FB

PORTN

MMSD4148

60.4k

1%

P

PGND

OUT

*1µF CERAMIC + 4.7µF TANTALUM

**100µF CERAMIC + 470µF TANTALUM

TLV431

2200pF

4267 TA02

“Y” CAP

250VAC

4267f

28

LTC4267

U

TYPICAL APPLICATIO S

A Class 3 PD with 5V Nonisolated Power Supply

COILTRONICS

CTX-02-15242

5V

1.8A

5µF*

MIN

220k

UPS840

300µF*

100k

MMBTA42

BAS516

•

+

–48V

9.1V

HD01

FROM

V

R

•

P

PORTP

VCC

DATA PAIR

–

1µF

LTC4267

SMAJ58A

NGATE

PWRGD

SENSE

150pF

200V

FDC2512

10k

0.1µF

220Ω

CLASS

+

HD01

–48V

FROM

SPARE PAIR

45.3Ω

1%

0.04Ω

V

FB

1%

–

42.2k

1%

SIGDISA

I

/RUN

TH

22nF

27k

4267 TA03

V

PORTN

P

OUT

PGND

8.06k

1%

*1µF CERAMIC + 4.7µF TANTALUM

** THREE 100µF CERAMICS

4267f

29

LTC4267

U

PACKAGE DESCRIPTIO

DHC Package

16-Lead Plastic DFN (5mm × 3mm)

(Reference LTC DWG # 05-08-1706)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

9

16

(DHC16) DFN 1103

8

1

NOTE:

1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC

PACKAGE OUTLINE MO-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

4267f

30

LTC4267

U

PACKAGE DESCRIPTIO

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.189 – .196*

(4.801 – 4.978)

.045 .005

.009

(0.229)

REF

16 15 14 13 12 11 10 9

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 .0015

.0250 BSC

RECOMMENDED SOLDER PAD LAYOUT

1

2

3

4

5

6

7

8

.015 .004

(0.38 0.10)

× 45°

.0532 – .0688

(1.35 – 1.75)

.004 – .0098

(0.102 – 0.249)

.007 – .0098

(0.178 – 0.249)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.0250

(0.635)

BSC

.008 – .012

GN16 (SSOP) 0204

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

4267f

InformationfurnishedbyLinearTechnologyCorporationisbelievedtobeaccurateandreliable.However,

no responsibility is assumed for its use. Linear Technology Corporation makes no representation that

the interconnection of its circuits as described herein will not infringe on existing patent rights.

31

LTC4267

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

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Wide Input Range, No R

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Quad IEEE 802.3af Power over Ethernet Controller

DC Disconnect Only, IEEE-Compliant PD Detection and Classiﬁcation,

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Burst Mode is a registered trademark of Linear Technology Corporation.

ThinSOT is a trademark of Linear Technology Corporation.

I²C is a trademark of Philips Electronics N.V.

4267f

LT/TP 1004 1K • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

32

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC1737
厂家：	Linear
描述：	Power over Ethernet IEEE 802.3af PD Interface with Integrated Switching Regulator 权力与集成开关稳压器的以太网IEEE 802.3af PD接口稳压器开关光电二极管以太网
文件：	总32页 (文件大小：1975K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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