LTC1873EG#PBF_技术文档

LTC1873

Dual 550kHz Synchronous

2-Phase Switching Regulator

Controller with 5-Bit VID

U

FEATURES

DESCRIPTIO

The LTC^®1873 is a dual switching regulator controller opti-

mized for high efficiency with low input voltages. It includes

twocomplete,on-chip,independentswitchingregulatorcon-

trollers. Each is designed to drive a pair of external

N-channel MOSFETs in a voltage mode feedback, synchro-

nous buck configuration. The LTC1873 includes digital out-

put voltage adjustment on side 1 that conforms to the Intel

Desktop VID specification. A constant-frequency, true PWM

design minimizes external component size and cost and

optimizesloadtransientperformance.Thesynchronousbuck

architectureautomaticallyshiftstodiscontinuousandthento

Burst Mode^TMoperation as the output load decreases, ensur-

ing maximum efficiency over a wide range of load currents.

■

Two Independent PWM Controllers in One Package

■

Side 1 Output Is Compliant with IntelDesktop

VRM 8.4 Specifications (Includes 5-Bit VID DAC)

■

1.3V to 3.5V Output Voltage with 50mV/100mV Steps

■

Two Sides Run Out-of-Phase to Minimize C_IN

■

All N-Channel External MOSFET Architecture

■

No External Current Sense Resistors Required

■

Precison Internal 0.8V ±1% Reference

■

550kHz Switching Frequency Minimizes External

Component Size

■

Very Fast Transient Response

■

Up to 25A Output Current per Channel

■

Low Shutdown Current: < 100µA

Small 28-Pin SSOP Package

■

The LTC1873 features an onboard reference trimmed to 1%

and delivers better than 1.5% regulation at the converter

outputs over all combinations of line, load and temperature.

Each channel can be enabled independently; with both chan-

nels disabled, the LTC1873 shuts down and supply current

drops below 100µA.

U

APPLICATIO S

■

Microprocessor Core and I/O Supplies

■

Multiple Logic Supply Generator

■

High Efficiency Power Conversion

Chipset Power Supply

, LTC and LT are registered trademarks of Linear Technology Corporation.

Burst Mode is a trademark of Linear Technology Corporation.

■

U

TYPICAL APPLICATIO

Low Cost Desktop CPU Supply with RDRAM Keepalive

4.5V TO 5.5V

IN OUT

LT1761

+

1µF

10Ω

C

IN

16.2k

0.1%

GND ADJ

MBR0530T

+

4.75k

0.1%

10µF

10k

V

PV

CC

0.1%

16.9k

0.1%

FB2

BOOST2

TG2

330pF

56pF

68k

QT2

1µF

L2

V

COMP2

RDRAM

2.5V/7A

SW2

+

2.45V/100mA STANDBY

RUN/SS2

RUN/SS1

QB2

BG2

1k

C

OUT2

47k

QSS1

I

MAX2

0.1µF

STBY/ON

QSS2

FAULT

MBR0530T

1µF

LTC1873

BOOST1

SENSE

FB1

QT1B

QB1B

220pF

TG1

SW1

BG1

QT1A

QB1A

L1

39pF

56k

V

CORE

COMP1

FCB

1.3V TO 3.5V

20A

+

C

OUT1

C

= SANYO 10MV1200GX (6 IN PARALLEL)

IN

= SANYO 6MV1500GX (8 IN PARALLEL)

= SANYO 6MV1500GX (3 IN PARALLEL)

OUT1

OUT2

33k

5-BIT VID

VID4:0

SGND

I

MAX1

L1: 1µH SUMIDA CEP125-1R0MC-H

L2: 2.2µH COILTRONICS UP2B-2R2

QSS1, QSS2: MOTOROLA MMBT3904LT1

QT1A, QT1B, QB1A, QB1B: FAIRCHILD FDS6670A

QT2, QB2: 1/2 SILICONIX Si4966

PGND

1873 TA01

1

LTC1873

W W

U W

U

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

TOP VIEW

ORDER PART

Supply Voltage

NUMBER

1

2

28

I

MAX2

PV

CC

V_CC........................................................................................... 7V

BOOSTn............................................................... 15V

BOOSTn – SWn .................................................... 7V

Input Voltage

27 BOOST2

26 BG2

BOOST1

BG1

LTC1873EG

3

4

25 TG2

TG1

5

24 SW2

SW1

6

23 PGND

22 FAULT

21 RUN/SS2

20 COMP2

19 FB2

I

MAX1

FCB

SWn .......................................................... –1V to 8V

VIDn ....................................................... –0.3V to 7V

All Other Inputs ......................... –0.3V to V_CC+ 0.3V

Peak Output Current < 10µs

TGn, BGn ............................................................... 5A

Operating Temperature Range

(Note 2) ............................................. –40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

7

8

RUN/SS1

COMP1

SGND

FB1

9

10

11

12

13

14

18

V

CC

17 VID4

16 VID3

15 VID2

SENSE

VID0

VID1

G PACKAGE

28-LEAD PLASTIC SSOP

T_JMAX= 125°C, θ_JA= 55°C/ W

Consult factory for Industrial and Military grade parts.

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C.

A

V_CC= 5V unless otherwise specified. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loop

V

Supply Voltage

●

3

7

V

CC

PV

BV

PV Supply Voltage

(Note 3)

CC

BOOST Pin Voltage

V

– V (Note 3)

2.7

CC

BOOST

SW

I

V

CC

Supply Current

Test Circuit 1

RUN/SS1 = RUN/SS2 = 0V (Note 6)

●

2.2

30

8

100

mA

µA

CC

IPV

PV Supply Current

CC

Test Circuit 1 (Note 5)

RUN/SS1 = RUN/SS2 = 0V (Note 6)

●

2.2

6

100

mA

µA

CC

I

BOOST Pin Current

Test Circuit 1 (Note 5)

RUN/SS1 = RUN/SS2 = 0V

●

1.3

0.1

3

10

mA

µA

BOOST

V

Feedback Voltage

Test Circuit 1

●

0.790

0.75

0.800

±0.005

±0.001

0.8

0.810

±0.05

±1

V

%/V

µA

V

FB

∆V

Feedback Voltage Line Regulation

Feedback Current

V

CC

= 3V to 7V

FB

I

FB2 Only (Note 7)

RUN/SSn = 0V

FB

V

FCB

FCB Threshold

0.85

∆V

FCB Feedback Hysteresis

FCB Pin Current

20

mV

µA

V

FCB

I

●

±0.001

0.55

±1

FCB

V

RUN

RUN/SS Pin RUN Threshold

Soft Start Source Current

0.45

–1.5

0.65

–5.5

I

–3.5

µA

SS

2

LTC1873

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C.

A

V_CC= 5V unless otherwise specified. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Switching Characteristics

V

Oscillator Amplitude

Oscillator Frequency

Controller 2 Oscillator Phase

Minimum Duty Cycle

Maximum Duty Cycle

Driver Nonoverlap

1

V

P-P

OSC

f

Test Circuit 1

●

475

550

180

10

750

kHz

DEG

%

OSC

Φ

Relative to Controller 1

OSC2

DC

V

< V

> V

●

7

0

MIN1

MIN2

MAX

FB

MAX

%

87

90

40

12

93

100

80

%

t

Test Circuit 1 (Note 9)

ns

NOV

t , t

r

Driver Rise/Fall Time

ns

f

Feedback Amplifier

A

FB DC Gain

●

74

±3

85

25

dB

MHz

mA

VFB

GBW

FB Gain Bandwidth

I

FB Sink/Source Current

MIN Comparator Threshold

MAX Comparator Threshold

COMP Output

●

±10

760

840

ERR

N

V

785

–14

mV

MIN

815

mV

MAX

Current Limit Loop

A

I

Gain

40

dB

VILIM

IMAX

LIM

I

Source Current

I

= 0V

●

–7

–10

µA

MAX

Status Outputs

V

FAULT Trip Point

V

Relative to Regulated V

●

+10

+15

0.03

–10

25

+20

0.1

%

V

FAULT

OLF

FB

OUT

FAULT Output Low Voltage

FAULT Output Current

FAULT Delay Time

I

= 1mA

= 0V

FAULT

I

t

V

µA

µs

FAULT

> V

to FAULT

FAULT

(Note 9)

FB

VID Inputs

R1

Resistance Between SENSE and FB1

Side 1 Only

Programmed from 1.3V to 3.5V

20

40

kΩ

%

V

Error % Output Voltage Accuracy

●

–1.5

1.6

1.5

OUT

R

VID Input Pull-Up Resistance

VID Input Voltage Threshold

V

= 0.6V (Note 8)

DIODE

kΩ

PULLUP

VID

V

(2.7V ≤ V ≤ 5.5V)

0.4

V

T

IL

IH

CC

(2.7V ≤ V ≤ 5.5V)

CC

I

VID Input Leakage Current

VID Pull-Up Voltage

V

< VID < 7V (Note 8)

0.01

±1

µA

VID-LEAK

CC

V

= 3.3V

= 5V

2.8

4.5

V

PULLUP

CC

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: The LTC1873 is guaranteed to meet performance specifications

from 0°C to 70°C. Specifications over the –40°C to 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls.

Note 5: Supply current in normal operation is dominated by the current

needed to charge and discharge the external MOSFET gates. This current

will vary with supply voltage and the external MOSFETs used.

Note 6: Supply current in shutdown is dominated by external MOSFET

leakage and may be significantly higher than the quiescent current drawn

by the LTC1873, especially at elevated temperature.

Note 3: PV and BV (V

the external MOSFETs used to ensure proper operation.

– V ) must be greater than V of

Note 7: Feedback current at FB1 will be higher due to internal VID

resistors.

CC

CC BOOST

SW

GS(ON)

Note 4: All currents into device pins are positive; all currents out of device

pins are negative. All voltages are referenced to ground unless otherwise

specified.

Note 8: Each built-in pull-up resistor attached to the VID inputs also has a

series diode connected to V to allow input voltages higher than the V

CC

supply without damage or clamping. (See Block Diagram.)

Note 9: Rise and fall times are measured at 20% to 80% levels. Delay and

nonoverlap times are measured using 50% levels.

3

LTC1873

TYPICAL PERFOR A CE CHARACTERISTICS

U W

MOSFET Driver Supply Current

vs Gate Capacitance

Efficiency vs Load Current

Transient Response

100

90

35

30

V

= 5V

TEST CIRCUIT 1

ONE DRIVER LOADED

MULTIPLY BY # OF ACTIVE

DRIVERS TO OBTAIN TOTAL

DRIVER SUPPLY CURRENT

V_IN= 5V

V_OUT= 1.8V

IN

V

OUT

= 3.3V

I

_LOAD= 0A-10A-0A

±2.2% MAX DEVIATION

V

= 2.5V

= 1.6V

OUT

25

20

15

10

5

20mV/

DIV

80

0

70

1873 G02

10µs/DIV

0

5

10

15

0

2000

4000

6000

8000

10000

LOAD CURRENT (A)

GATE CAPACITANCE (pF)

1873 G01

1873 G03

Supply Current vs Temperature

Driver R_ONvs Temperature

Frequency Drift vs Temperature

2.5

2.0

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

2.6

V

CC

= 5V

V

= 5V

PVCC

TEST CIRCUIT 1

L

V

– V = 5V

BOOST

SW

C

= 0pF

2.4

2.2

PV

CC

1.5

1.0

V

CC

2.0

1.8

1.6

1.4

1.2

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

BOOST1, BOOST2

1.0

–25

0

50

75 100 125

–50

0

25

50

75

125

–50

0

25

50

75

125

–50

25

100

–25

TEMPERATURE (°C)

1873 G04

1873 G05

1873 G06

RUN/SS Source Current

vs Temperature

Nonoverlap Time vs Temperature

Driver Rise/Fall vs Temperature

15

14

13

12

11

12

5.0

4.5

4.0

3.5

70

60

V

CC

= 5V

TEST CIRCUIT 1

L

TEST CIRCUIT 1

L

C

= 2000pF

C

= 2000pF

TG FALLING EDGE

BG RISING EDGE

50

40

30

20

10

BG FALLING EDGE

TG RISING EDGE

3.0

2.5

2.0

0

50

TEMPERATURE (°C)

100 125

50

0

TEMPERATURE (°C)

100 125

–50 –25

0

25

50

75

125

–50 –25

0

25

75

–50 –25

25

75

100

TEMPERATURE (°C)

1873 G07

1873 G08

1873 G09

4

LTC1873

U

PI FU CTIO S

PV_CC(Pin 1): Driver Power Supply Input. PV_CCprovides

power to the two BGn output drivers. PV_CCmust be

connected to a voltage high enough to fully turn on the

external MOSFETs QB1 and QB2. PV_CCshould generally

be connected directly to V_IN. PV_CCrequires at least a 1µF

bypass capacitor directly to PGND.

FCB (Pin 7): Force Continuous Bar. The FCB pin forces

both converters to maintain continuous synchronous

operation regardless of load when the voltage at FCB

drops below 0.8V. FCB is normally tied to V_CC. To force

continuous operation, tie FCB to SGND. FCB can also be

connected to a feedback resistor divider from a secondary

winding on one converter’s inductor to generate a third

regulated output voltage. Do not leave FCB floating.

BOOST1 (Pin 2): Controller 1 Top Gate Driver Supply. The

BOOST1 pin supplies power to the floating TG1 driver.

BOOST1 should be bypassed to SW1 with a 1µF capacitor.

An additional Schottky diode from V_INto BOOST1 pin will

create a complete floating charge-pumped supply at

BOOST1. No other external supplies are required.

RUN/SS1 (Pin 8): Controller 1 Run/Soft-Start. Pulling

RUN/SS1 to SGND will disable controller 1 and turn off

both of its external MOSFET switches. Pulling both

RUN/SS pins down will shut down the entire LTC1873,

dropping the quiescent supply current below 50µA. A

capacitor from RUN/SS1 to SGND will control the turn-on

time and rate of rise of the controller 1 output voltage at

power-up. An internal 3.5µA current source pull-up at

RUN/SS1 pin sets the turn-on time at approximately

50ms/µF.

BG1 (Pin 3): Controller 1 Bottom Gate Drive. The BG1 pin

drives the gate of the bottom N-channel synchronous

switch MOSFET, QB1. BG1 is designed to drive up to

10,000pF of gate capacitance directly. If RUN/SS1 goes

low, BG1 will go low, turning off QB1. If FAULT mode is

tripped, BG1 will go high and stay high, keeping QB1 on

until the power is cycled.

COMP1 (Pin 9): Controller 1 Loop Compensation. The

COMP1 pin is connected directly to the output of the first

controller’s error amplifier and the input to the PWM

comparator. An RC network is used at the COMP1 pin to

compensate the feedback loop for optimum transient

response.

TG1 (Pin 4): Controller 1 Top Gate Drive. The TG1 pin

drives the gate of the top N-channel MOSFET, QT1. The

TG1driverdraws powerfromtheBOOST1pinandreturns

to the SW1 pin, providing true floating drive to QT1. TG1

is designed to drive up to 10,000pF of gate capacitance

directly. In shutdown or fault modes, TG1 will go low.

SGND (Pin 10): Signal Ground. All internal low power

circuitry returns to the SGND pin. Connect to a low

impedance ground, separated from the PGND node. All

feedback,compensationandsoft-startconnectionsshould

return to SGND. SGND and PGND should connect only at

a single point, near the PGND pin and the negative plate of

the C_INbypass capacitor.

SW1 (Pin 5): Controller 1 Switching Node. SW1 should be

connected to the switching node of converter 1. The TG1

driver ground returns to SW1, providing floating gate

drive to the top N-channel MOSFET switch, QT1. The

voltage at SW1 is compared to I_MAX1by the current limit

comparator while the bottom MOSFET, QB1, is on.

FB1 (Pin 11): Controller 1 Feedback Input. The loop

compensation network for controller 1 should be con-

nected to FB1. FB1 is connected internally to the VID

resistor network to set the output voltage at side 1.

I_MAX1(Pin 6): Controller 1 Current Limit Set. The I_MAX1

pin sets the current limit comparator threshold for

controller1.IfthevoltagedropacrossthebottomMOSFET,

QB1, exceeds the magnitude of the voltage at I_MAX1

,

controller 1 will go into current limit. The I_MAX1pin has an

internal 10µA current source pull-up, allowing the current

threshold to be set with a single external resistor to PGND.

ThiscurrentsettingresistorshouldbeKelvinconnectedto

the source of QB1. See the Current Limit Programming

SENSE (Pin 12): Output Sense. Connect to V_OUT1

.

VID0 to VID4 (Pins 13 to 17): VID Programming Inputs.

These are logic inputs that set the output voltage at side 1

to a preprogrammed value (see Table 1). VID4 is the MSB,

VID0 is the LSB. The codes selected by the VIDn inputs

correspond to the Intel Desktop VID specification. Each

section for more information on choosing R_IMAX

.

5

LTC1873

U

PI FU CTIO S

VIDn pin includes an on-chip 40kΩ pull-up resistor in

disabled. When FAULT is high, both BG pins will go high,

turning on the bottom MOSFET switches and pulling down

the high output voltage. The LTC1873 will remain latched

in this state until the power is cycled. When FAULT mode

is active, the FAULT pin will be pulled up with an internal

10µA current source. Tying FAULT directly to SGND will

disable latched FAULT mode and will allow the LTC1873 to

resume normal operation when the overvoltage fault is

removed.

series with a diode (see Block Diagram).

V_CC(Pin 18): Power Supply Input. All internal circuits

except the output drivers are powered from this pin. V_CC

should be connected to a low noise power supply voltage

between 3V and 7V and should be bypassed to SGND with

at least a 1µF capacitor in close proximity to the LTC1873.

FB2 (Pin 19): Controller 2 Feedback Input. FB2 should be

connected through a resistor divider network to V_OUT2to

set the ouput voltage. The loop compensation network for

controller 2 also connects to FB2.

PGND (Pin 23): Power Ground. The BGn drivers return to

this pin. Connect PGND to a high current ground node in

close proximity to the sources of external MOSFETs, QB1

and QB2, and the V_INand V_OUTbypass capacitors.

COMP2 (Pin 20): Controller 2 Loop Compensation. See

COMP1.

SW2 (Pin 24): Controller 2 Switching Node. See SW1.

TG2 (Pin 25): Controller 2 Top Gate Drive. See TG1.

BG2 (Pin 26): Controller 2 Bottom Gate Drive. See BG1.

RUN/SS2 (Pin 21): Controller 2 Run/Soft-Start. See RUN/

SS1.

FAULT (Pin 22): Output Overvoltage Fault (Latched). The

FAULT pin is an open-drain output with an internal 10µA

pull-up. If either regulated output voltage rises more than

15% above its programmed value for more than 25µs, the

FAULT output will go high and the entire LTC1873 will be

BOOST2 (Pin 27): Controller 2 Top Gate Driver Supply.

See BOOST1.

I_MAX2(Pin 28): Controller 2 Current Limit Set. See I_MAX1

.

TEST CIRCUIT

Test Circuit 1

5V

+

I

BOOST2

BOOST1

CC

PVCC

0.1µF

100µF

V

PV

CC

BOOST1

TG1

BOOST2

f

OSC

TG2

MEASURED

BG1

BG2

SW1

SW2

2000pF

I

MAX2

MAX1

LTC1873

FCB

V

NC

VID0:4

FAULT

RUN/SS1

COMP1

FB1

RUN/SS2

COMP2

FB2

NC

2k

V

FB1

FB2

SENSE

GND

PGND

1873 TC

6

LTC1873

W

BLOCK DIAGRA

PV

FCB

CC

V

BOOST1,2

TG1,2

CC

BURST

LOGIC

DRIVE

LOGIC

SW1,2

BG1,2

PGND

90% DUTY CYCLE

OSC

550kHz

SGND

DIS

3.5µA

SOFT

START

10µA

RUN/SS1,2

FAULT

COMP1,2

0V

25µs

DELAY

I

LIM

10µA

FB

MIN

MAX

FLT

+

–

FROM

I

MAX1,2

OTHER

800mV

760mV

840mV

920mV

CONTROLLER

FB1,2

SHUTDOWN TO

THIS CONTROLLER

40k

V

CC

SHUTDOWN TO

ENTIRE CHIP

VID0

VID1

VID2

VID3

500mV

SENSE

R11

20k

FROM

OTHER

CONTROLLER

TO FB1

SWITCH

CONTROL

LOGIC

R

B1

40k

V

CC

VID4

1873 BD

W U U

U

APPLICATIO S I FOR ATIO

OVERVIEW

erly designed circuit. The 550kHz switching frequency

allows the use of physically small, low value external

components without compromising performance. An

onboard DAC sets the output voltage at channel 1, consis-

tent with the Intel desktop VID specification (Table 1).

The LTC1873 is a dual, step-down (buck), voltage mode

feedback switching regulator controller. It is designed to

be used in a synchronous switching architecture with two

external N-channel MOSFETs per channel. It is intended to

operate from a low voltage input supply (7V maximum)

and provide a high power, high efficiency, precisely regu-

lated output voltage. Several features make it particularly

suitedformicroprocessorsupplyregulation.Outputregu-

lation is extremely tight, with DC line and load regulation

and initial accuracy better than 1.5%, and total regulation

including transient response inside of 3.5% with a prop-

The LTC1873’s internal feedback amplifier is a 25MHz

gain-bandwidth op amp, allowing the use of complex

multipole/zero compensation networks. This allows the

feedback loop to maintain acceptable phase margin at

higher frequencies than traditional switching regulator

controllers allow, improving stability and maximizing tran-

sient response. The 800mV internal reference at channel

2

7

LTC1873

W U U

U

APPLICATIO S I FOR ATIO

Table 1. VID Inputs and Corresponding Output Voltage for

Channel 1

CODE

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

VID4

GND

VID3

GND

Float

VID2

GND

Float

GND

Float

VID1

GND

Float

GND

Float

GND

Float

GND

Float

VID0

GND

Float

GND

Float

GND

Float

GND

Float

GND

Float

GND

Float

GND

Float

GND

Float

V_OUT1

2.05V

2.00V

1.95V

1.90V

1.85V

1.80V

1.75V

1.70V

1.65V

1.60V

1.55V

1.50V

1.45V

1.40V

1.35V

1.30V

CODE

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111*

VID4

Float

VID3

GND

Float

VID2

GND

Float

GND

Float

VID1

GND

Float

GND

Float

GND

Float

GND

Float

VID0

GND

Float

GND

Float

GND

Float

GND

Float

GND

Float

GND

Float

GND

Float

GND

Float

V_OUT1

3.50V

3.40V

3.30V

3.20V

3.10V

3.00V

2.90V

2.80V

2.70V

2.60V

2.50V

2.40V

2.30V

2.20V

2.10V

2.00V

* 11111 is defined by Intel to signify “no CPU.” The LTC1873

will generate the output voltage shown when this codes is selected.

allows regulated output voltages as low as 800mV without

external level shifting amplifiers.

capacitor. These large amplitude current pulses increased

the total RMS current flowing from the input capacitor,

requiring the use of more expensive input capacitors and

increasing both EMI and losses in the input capacitor and

input power supply.

The LTC1873’s synchronous switching logic transitions

automatically into Burst Mode operation, maximizing effi-

ciency with light loads. An onboard overvoltage (OV) fault

flag indicates when an OV fault has occurred. The OV flag

can be set to latch the device off when an OV fault has

occurred, or to automatically resume operation when the

fault is removed.

With 2-phase operation, the two channels of the LTC1873

are operated 180 degrees out of phase. This effectively

interleaves the current pulses coming from the switches,

greatlyreducingtheoverlaptimewheretheyaddtogether.

The result is a significant reduction in total RMS input

current, which in turn allows less expensive input capaci-

tors to be used, reduces shielding requirements for EMI

and improves real world operating efficiency.

2-Phase Operation

The LTC1873 dual switching regulator controller offers

considerable benefits using 2-phase operation. Circuit

benefits include lower input filtering requirements,

reducedelectromagneticinterference(EMI)andincreased

efficiency associated with 2-phase operation.

Figure 7 shows example waveforms for a single switching

regulator channel versus a 2-phase LTC1873 system with

both sides switching. A single-phase dual regulator with

both sides operating would exhibit double the single side

numbers. In this example, 2-phase operation reduced the

RMS input current from 9.3A_RMS(2 × 4.66A_RMS) to

Why the need for 2-phase operation? Until recently, con-

stant-frequency dual switching regulators operated both

channels in phase (i.e., single-phase operation). This

means that both topside MOSFETs turned on at the same

time, causing current pulses of up to twice the amplitude

of those for one regulator to be drawn from the input

4.8A_RMS. While this is an impressive reduction in itself,

2

rememberthatthepowerlossesareproportionaltoI_RMS

,

meaning that the actual power wasted is reduced by a

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factorof3.75.Thereducedinputripplevoltagealsomeans

less power is lost in the input power path, which could

include batteries, switches, trace/connector resistances

andprotectioncircuitry. Improvementsinbothconducted

and radiated EMI also directly accrue as a result of the

reduced RMS input current and voltage.

The voltage mode feedback loop and MOSFET V_DScurrent

limit sensing remove the need for an external current

sense resistor, eliminating an external component and a

source of power loss in the high current path. Properly

designed circuits using low gate charge MOSFETs are

capable of efficiencies exceeding 90% over a wide range

of output voltages.

Small Footprint

VID Programming

The LTC1873 operates at a 550kHz switching frequency,

allowing it to use low value inductors without generating

excessive ripple currents. Because the inductor stores

less energy per cycle, the physical size of the inductor can

be reduced without risking core saturation, saving PCB

board space. The high operating frequency also means

less energy is stored in the output capacitors between

cycles, minimizing their required value and size. The

remaining components, including the SSOP-28 LTC1873,

are tiny, allowing an entire dual-output LTC1873 circuit to

be constructed in 1.5in²of PCB space. Further, this space

is generally located right next to the microprocessor or in

some similarly congested area, where PCB real estate is at

a premium.

The LTC1873 includes an onboard feedback network that

programs the output voltage at side 1 in accordance with

the Intel Desktop VID specification (Table 1). The network

includes a 20k resistor (R1) connected from SENSE to

FB1, and a variable value resistor (R_B) from FB1 to SGND,

with the value set by the digital code present at the VID0:4

pins. SENSE should be connected to V_OUT1to allow the

network to monitor the output voltage. No additional

feedback components are required to set the output volt-

age at controller 1, although loop compensation compo-

nents are still required. Each VIDn pin includes an internal

40k pull-up resistor, allowing it to float high if left uncon-

nected.Thepull-upresistorsareconnectedtoV_CCthrough

diodes (see Block Diagram), allowing the VIDn pins to be

pulled above V_CCwithout damage.

Fast Transient Response

The LTC1873 uses a fast 25MHz GBW op amp as an error

amplifier. This allows the compensation network to be

designed with several poles and zeros in a more flexible

configuration than with a typical g_mfeedback amplifier.

The high bandwidth of the amplifier, coupled with the high

switching frequency and the low values of the external

inductor and output capacitor, allow very high loop cross-

over frequencies. The low inductor value is the other half

of the equation—with a typical value on the order of 1µH,

the inductor allows very fast di/dt slew rates. The result is

superior transient response compared with conventional

solutions.

Note that code 11111, defined by Intel to indicate “no CPU

present,”doesgenerateanoutputvoltageatV_OUT1(2.00V).

Note also that controller 2 on the LTC1873 is not con-

nected to the VID circuitry, and works independently from

controller 1.

ARCHITECTURE DETAILS

The LTC1873 dual switching regulator controller includes

two independent regulator channels. The two sides of the

chip and their corresponding external components act

independently of each other with the exception of the

common input bypass capacitor, the VID circuitry at side

1, and the FCB and FAULT pins, which affect both chan-

nels. In the following discussions, when a pin is referred

to without mentioning which side is involved, that discus-

sion applies equally to both sides.

High Efficiency

The LTC1873 uses a synchronous step-down (buck)

architecture, with two external N-channel MOSFETs per

output. A floating topside driver and a simple external

charge pump provide full gate drive to the upper MOSFET.

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Switching Architecture

frequency band with the 550kHz frequency designed to

leavethe455kHzIFbandfreeofinterference.Subharmonic

oscillation and slope compensation, common headaches

with constant frequency current mode switchers, are

absent in voltage mode designs like the LTC1873.

Each half of the LTC1873 is designed to operate as a

synchronous buck converter (Figure 1). Each channel

includes two high power MOSFET gate drivers to control

external N-channel MOSFETs QT and QB. These drivers

have 0.5Ω output impedances and can carry well over an

amp of continuous current with peak currents up to 5A to

slew large MOSFET gates quickly. The external MOSFETs

are connected with the drain of QT attached to the input

supply and the source of QT at the switching node SW. QB

is the synchronous rectifier with its drain at SW and its

source at PGND. SW is connected to one end of the

inductor,withtheotherendconnectedtoV_OUT.Theoutput

capacitor is connected from V_OUTto PGND.

During the time that QT is on, its source (the SW pin) is at

V_IN. V_INis also the power supply for the LTC1873. How-

ever, QT requires V_IN+ V_GS(ON)at its gate to achieve

minimumR_ON.ThispresentsaproblemfortheLTC1873—

it needs to generate a gate drive signal at TG higher than

its highest supply voltage. To accomplish this, the TG

driver runs from floating supplies, with its negative supply

attachedtoSWanditspowersupplyatBOOST.Thisallows

ittoslewupanddownwiththesourceofQT.Incombination

with a simple external charge pump (Figure 2), this allows

theLTC1873tocompletelyenhancethegateofQTwithout

requiring an additional, higher supply voltage.

When a switching cycle begins, QB is turned off and QT is

turned on. SW rises almost immediately to V_INand the

inductor current begins to increase. When the PWM pulse

finishes, QTturnsoffandonenonoverlapintervallater, QB

turnson. NowSWdropstoPGNDandtheinductorcurrent

decreases. The cycle repeats with the next tick of the

master clock. The percentage of time spent in each mode

is controlled by the duty cycle of the PWM signal, which in

turn is controlled by the feedback amplifier. The master

clockrunsata550kHzrateandturnsQTonceevery1.8µs.

In a typical application with a 5V input and a 1.5V output,

the duty cycle will be set at 1.5/5 × 100% or 30% by the

feedback loop. This will give roughly a 540ns on-time for

QT and a 1.26µs on-time for QB.

The two channels of the LTC1873 run from a common

clock, with the phasing chosen to be 180° from side 1 to

side 2. This has the effect of doubling the frequency of the

switching pulses seen by the input bypass capacitor,

significantlyloweringtheRMScurrentseenbythecapaci-

tor and reducing the value required (see the 2-Phase

section).

Feedback Amplifier

Each side of the LTC1873 senses the output voltage at

V_OUTwith an internal feedback op amp (see Block Dia-

gram). This is a real op amp with a low impedance output,

85dBopen-loopgainand25MHzgain-bandwidthproduct.

The positive input is connected internally to an 800mV

reference, while the negative input is connected to the FB

This constant frequency operation brings with it a couple

of benefits. Inductor and capacitor values can be chosen

with a precise operating frequency in mind and the feed-

back loop components can be similarly tightly specified.

Noise generated by the circuit will always be in a known

V

IN

+

D

C

CP

V

IN

PV

BOOST

TG

CC

C

1µF

CP

+

QT

C

IN

L

EXT

QT

QB

TG

SW

L

EXT

1/2

V

OUT

SW

BG

V

OUT

LTC1873

BG

+

QB

C

OUT

PGND

OUT

LTC1873

PGND

1873 F02

1873 F01

Figure 2. Floating TG Driver Supply

Figure 1. Synchronous Buck Architecture

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pin. The output is connected to COMP, which is in turn

connected to the soft-start circuitry and from there to the

PWM generator.

to resume normal operation when the fault is removed.

The overvoltage protection circuit can optionally be set to

latchtheoutputoffpermanently(seetheOvervoltageFault

section).

Unlike many regulators that use a resistor divider con-

nected to a high impedance feedback input, the LTC1873

is designed to use an inverting summing amplifier topol-

ogy with the FB pin configured as a virtual ground. This

allows flexibility in choosing pole and zero locations not

available with simple g_mconfigurations. In particular, it

allows the use of “type 3” compensation, which provides

a phase boost at the LC pole frequency and significantly

improves loop phase margin (see Figure 3). The Feedback

Loop/Compensation section contains a detailed explana-

tion of type 3 feedback loops. Note that side 1 of the

LTC1873 includes R1 and R_Binternally as part of the VID

DAC circuitry.

The MIN comparator (see Block Diagram) trips whenever

FB is more than 5% below 800mV and immediately forces

the switch duty cycle to 90% to bring the output voltage

back into range. It releases when FB is within the 5%

window. MIN is disabled when the soft-start or current

limit circuits are active—the only two times that the

output should legitimately be below its regulated value.

Notice that the FB pin is the virtual ground node of the

feedback amplifier. A typical compensation network does

not include local DC feedback around the amplifier, so that

the DC level at FB will be an accurate replica of the output

voltage, divided down by R1 and R_B(Figure 3). However,

the compensation capacitors will tend to attenuate AC

signals at FB, especially with low bandwidth type 1 feed-

back loops. This creates a situation where the MIN and

MAX comparators do not respond immediately to shifts in

the output voltage, since they monitor the output at FB.

Maximizing feedback loop bandwidth will minimize these

delays and allow MIN and MAX to operate properly. See

the Feedback Loop/Compensation section.

C3

0.8V

+

R3

COMP

FB

R1

FB

V

OUT

–

R

B

C2

C1

R2

1873 F03

SHUTDOWN/SOFT-START

Figure 3. “Type 3” Feedback Loop (Side 2 Shown)

Each half of the LTC1873 has a RUN/SS pin. The RUN/SS

pins perform two functions: when pulled to ground, each

shuts down its half of the LTC1873, and each acts as a

conventional soft-start pin, enforcing a maximum duty

cycle limit proportional to the voltage at RUN/SS. An

internal 3.5µA current source pull-up is connected to each

RUN/SS pin, allowing a soft-start ramp to be generated

with a single external capacitor to ground. The 3.5µA

current sources are active even when the LTC1873 is shut

down, ensuring the device will start when any external

pull-down at RUN/SS is released. Either side can be shut

down without affecting the operation of the other side. If

both sides are shut down at the same time, the LTC1873

goes into a micropower sleep mode, and quiescent cur-

rent drops typically below 50µA. Entering sleep mode also

resets the FAULT latch, if it was set.

MIN/MAX COMPARATORS

Two additional feedback loops keep an eye on the primary

feedback amplifier and step in if the feedback node moves

±5%fromitsnominal800mVvalue. TheMAXcomparator

(see Block Diagram) activates whenever FB rises more

than 5% above 800mV. It immediately turns the top

MOSFET (QT) off and the bottom MOSFET (QB) on and

keeps them that way until FB falls back within 5% of its

nominal value. This pulls the output down as fast as

possible, preventing damage to the (often expensive)

load. If FB rises because the output is shorted to a higher

supply, QB will stay on until the short goes away, the

higher supply current limits or QB dies trying to save the

load. This behavior provides maximum protection against

overvoltage faults at the output, while allowing the circuit

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EachRUN/SSpinshutsdownitshalfoftheLTC1873when

it falls below about 0.5V (Figure 4). Between 0.5V and

about 1V, that half is active, but the maximum duty cycle

is limited to 10%. The maximum duty cycle limit increases

linearly between 1V and 2.5V, reaching its final value of

90% when RUN/SS is above 2.5V. Somewhere before this

point, the feedback amplifier will assume control of the

loop and the output will come into regulation. When RUN/

SS rises to 0.5V below V_CC, the MIN feedback comparator

is enabled, and the LTC1873 is in full operation.

Any time QB is on and the current flowing to the output is

reasonably large, the SW node at the drain of QB will be

somewhat negative with respect to PGND. The LTC1873

senses this voltage and inverts it to allow it to compare the

sensed voltage with a positive voltage at the I_MAXpin. The

I_MAXpin includes a trimmed 10µA pull-up, enabling the

usertosetthevoltageatI_MAXwithasingleresistor, R_IMAX

,

to ground. The LTC1873 compares the two inputs and

begins limiting the output current when the magnitude of

the negative voltage at the SW pin is greater than the

voltage at I_MAX

.

CURRENT LIMIT

The current limit detector is connected to an internal g_m

amplifier that pulls a current from the RUN/SS pin propor-

tional to the difference in voltage magnitudes between the

SW and I_MAXpins. This current begins to discharge the

soft-start capacitor at RUN/SS, reducing the duty cycle

and controlling the output voltage until the current drops

below the limit. The soft-start capacitor needs to move a

fair amount before it has any effect on the duty cycle,

addingadelayuntilthecurrentlimittakeseffect(Figure4).

This allows the LTC1873 to experience brief overload

conditionswithoutaffectingtheoutputvoltageregulation.

The delay also acts as a pole in the current limit loop to

TheLTC1873includesanonboardcurrentlimitcircuitthat

limitsthemaximumoutputcurrenttoauser-programmed

level. It works by sensing the voltage drop across QB

during the time that QB is on and comparing that voltage

toauser-programmedvoltageatI_MAX. SinceQBlookslike

a low value resistor during its on-time, the voltage drop

across it is proportional to the current flowing in it. In a

buckconverter,theaveragecurrentintheinductorisequal

to the output current. This current also flows through QB

during its on-time. Thus, by watching the voltage across

QB, the LTC1873 can monitor the output current.

V

OUT

0V

5V

4.5V

V

2.5V

RUN/SS

1.0V

0.5V

0V

LTC1873 ENABLED

RUN/SS CONTROLS

DUTY CYCLE

RUN/SS CONTROLS

DUTY CYCLE

COMP CONTROLS DUTY CYCLE

MIN COMPARATOR ENABLED

START-UP

NORMAL OPERATION

CURRENT LIMIT

1873 F04

Figure 4. Soft-Start Operation in Start-Up and Current Limit

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Selection section for a detailed description of ripple

current.

enhance loop stability. Larger overloads cause the soft-

start capacitor to pull down quickly, protecting the output

components from damage. The current limit g_mamplifier

includes a clamp to prevent it from pulling RUN/SS below

0.5V and shutting off the device.

As the output load current decreases in continuous mode,

theaveragecurrentintheinductorwillreachapointwhere

it drops below half the ripple current. At this point, the

current in the inductor will reverse during a portion of the

switching cycle, or begin to flow from the output back to

the input. This does not adversely affect regulation, but

does cause additional losses as a portion of the inductor

current flows back and forth through the resistive power

switches, giving away a little more power each time and

lowering the efficiency. There are some benefits to allow-

ing this reverse current flow: the circuit will maintain

regulation even if the load current drops below zero (the

load supplies current to the LTC1873) and the output

ripple voltage and frequency remain constant at all loads,

easing filtering requirements. Circuits that take advantage

of this behavior can force the LTC1873 to operate in

continuous mode at all loads by tying the FCB (Force

Continuous Bar) pin to ground.

Power MOSFET R_DS(ON)varies from MOSFET to MOSFET,

limitingtheaccuracyobtainablefromtheLTC1873current

limit loop. Additionally, ringing on the SW node due to

parasitics can add to the apparent current, causing the

loop to engage early. The LTC1873 current limit is

designed primarily as a disaster prevention, “no blow up”

circuit, and is not useful as a precision current regulator.

It should typically be set around 50% above the maximum

expected normal output current to prevent component

tolerances from encroaching on the normal current range.

See the Current Limit Programming section for advice on

choosing a valve for R_IMAX

.

DISCONTINUOUS/Burst Mode OPERATION

Theory of operation

Discontinuous Mode

The LTC1873 switching logic has three modes of opera-

tion. Under heavy loads, it operates as a fully synchro-

nous, continuous conduction switching regulator. In this

modeofoperation(“continuous”mode), thecurrentinthe

inductorflowsinthepositivedirection(towardtheoutput)

during the entire switching cycle, constantly supplying

current to the load. In this mode, the synchronous switch

(QB) is on whenever QT is off, so the current always flows

through a low impedance switch, minimizing voltage drop

and power loss. This is the most efficient mode of opera-

tionatheavyloads, wheretheresistivelossesinthepower

devices are the dominant loss term.

To minimize the efficiency loss due to reverse current flow

at light loads, the LTC1873 switches to a second mode of

operation:discontinuousmode(Figure5b).Indiscontinu-

ousmode, theLTC1873detectswhentheinductorcurrent

approaches zero and turns off QB for the remainder of the

switch cycle. During this time, the voltage at the SW pin

will float about V_OUT, the voltage across the inductor will

be zero, and the inductor current remains zero until the

next switching cycle begins andQT turns on again. This

prevents current from flowing backwards in QB, eliminat-

ing that power loss term. It also reduces the ripple current

in the inductor as the output current approaches zero.

Continuous mode works efficiently when the load current

is greater than half of the ripple current in the inductor. In

a buck converter like the LTC1873, the average current in

the inductor (averaged over one switching cycle) is equal

to the load current. The ripple current is the difference

between the maximum and the minimum current during a

switching cycle (see Figure 5a). The ripple current

depends on inductor value, clock frequency and output

voltage, but is constant regardless of load as long as the

LTC1873 remains in continuous mode. See the Inductor

TheLTC1873detectsthattheinductorcurrenthasreached

zero by monitoring the voltage at the SW pin while QB is

on. SinceQBactslikearesistor, SWshouldideallyberight

at0Vwhentheinductorcurrentreacheszero.Inreality,the

SW node will ring to some degree immediately after it is

switched to ground by QB, causing some uncertainty as to

the actual moment the average current in QB goes to zero.

The LTC1873 minimizes this effect by ignoring the SW

node for a fixed 50ns after QB turns on when the ringing

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is most severe, and by including a few millivolts offset in

the comparator that monitors the SW node. Despite these

precautions, some combinations of inductor and layout

parasitics can cause the LTC1873 to enter discontinuous

mode erratically. In many cases, the time that QB turns off

will correspond to a peak in the ringing waveform at the

SW pin (Figure 6). This erratic operation isn’t pretty, but

retains much of the efficiency benefit of discontinuous

mode and maintains regulation at all times.

Burst Mode Operation

Discontinuous mode removes a loss term due to resistive

drop in QB, but the LTC1873 is still switching QT and QB

on and off once a cycle. Each time an external MOSFET is

turned on, the internal driver must charge its gate to V_CC.

Each time it is turned off, that charge is lost to ground. At

the high switching frequencies that the LTC1873 operates

at, the charge lost to the gates can add up to tens of

milliampsfromV_CC. Astheloadcurrentcontinuestodrop,

thisquicklybecomethedominantpowerlossterm, reduc-

ing efficiency once again.

I

RIPPLE

Once again, the LTC1873 switches to a new mode to

minimize efficiency loss: Burst Mode operation. As the

circuit goes deeper and deeper into discontinuous mode,

thetotaltimeQTandQBareonreduces.However,theratio

of the time that QT is on to the time that QB is on must

remain constant for the output to stay in regulation. An

internal timer circuit forces QT to stay on for at least 10%

of a normal switching cycle. When the load drops to the

pointthattheoutputrequireslessthan10%on-timeatQT,

the output voltage will begin to rise. The LTC1873 senses

this rise and shuts both QT and QB off completely, skip-

ping several switching cycles until the output falls back

into range. It then resumes switching in discontinuous

mode with QT at 10% duty cycle and the burst sequence

repeats. The total deviation from the regulated output is

within the 1.5% regulation tolerance of the LTC1873.

I

AVERAGE

TIME

1873 F05a

Figure 5a. Continuous Mode

I

RIPPLE

I

AVERAGE

TIME

1873 F05b

InBurstModeoperation, bothresistivelossandswitching

loss are minimized while keeping the output in regulation.

The ripple current will be set by the 10% QT on-time and

the input supply voltage and is the lowest of all three

operating modes. As the load current falls to zero in Burst

Mode operation, the most significant loss term becomes

the 3mA quiescent current drawn by each side of the

LTC1873—usually much less than the minimum load

current in a typical low voltage logic system. Burst Mode

operation maximizes efficiency at low load currents, but

can cause low frequency ripple in the output voltage as the

cycle-skipping circuitry switches on and off.

Figure 5b. Discontinuous Mode

DISCONTINUOUS

COMPARATOR

TURNS OFF BG

V

SW

0V

TIME

50ns

BLANK

TIME

5V

V

BG

0V

1873 F06

TIME

Figure 6. Ringing at SW Causes Discontinuous

Comparator to Trip Early

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FCB Pin

OVERVOLTAGE FAULT

Insomecircumstances, itisdesirabletocontrolordisable

discontinuousandBurstModeoperations.TheFCB(Force

Continuous Bar) pin allows the user to do this. When the

FCB pin is high, the LTC1873 is allowed to enter discon-

tinuous and Burst Mode operations at either side as

required. If FCB is taken low, discontinuous and Burst

Mode operations are disabled and both sides of the

LTC1873 run in continuous mode regardless of load. This

does not affect output regulation but does reduce effi-

ciency at low output currents. The FCB pin threshold is

specified at 0.8V ±50mV, and includes 20mV of hyster-

esis, allowing it to be used as a precision small-signal

comparator.

The LTC1873 includes a single overvoltage fault flag for

both channels: FAULT. FAULT is an open-drain output

with an internal 10µA pull-up. If either FB pin rises more

than 15% above the nominal 800mV value for more than

25µs, the overvoltage comparator will trip, setting an

internal latch. This latch releases the pull-down at FAULT,

allowing the 10µA pull-up to take it high. When FAULT

goes high, the LTC1873 stops all switching, turns both QB

(bottom synchronous) MOSFETs on continuously and

remainsinthisstateuntil bothRUN/SSpinsarepulledlow

simultaneously, the power supply is recycled, or the

FAULT pin is pulled low externally. This behavior is

intended to protect a potentially expensive load from

overvoltage damage at all costs. Under some conditions,

this behavior can cause the output voltage to undershoot

below ground. If latched FAULT mode is used, a Schottky

diode should be added with its cathode at the output and

its anode at ground to clamp the negative voltage to a safe

level and prevent possible damage to the load and the

output capacitors.

Paralleling Outputs

Synchronous regulators (like the LTC1873) are known for

their bullheadedness when their outputs are paralleled

with other regulators. In particular, a synchronous regu-

lator paralleled with another regulator whose output is

slightly higher (perhaps just by millivolts) will happily sink

amps of current attempting to pull its own output back

down to what it thinks is the right value.

Note that in overvoltage conditions, the MAX comparator

will kick in at just +5%, turning QB on continuously long

before the output reaches +15%. Under most fault condi-

tions, this is adequate to bring the output back down

without firing the fault latch. Additionally, if MAX success-

fully keeps the output below +15%, the LTC1873 will

resume normal regulation as soon as the output overvolt-

age fault is resolved.

The LTC1873 discontinuous mode allows it to be paral-

leled with another regulator without fighting. A typical

system might use the LTC1873 as a primary regulator and

a small LDO as a backup regulator to keep SRAM alive

when the main power is off. When the LTC1873 is shut

down(bypullingRUN/SStoground), bothQTandQBturn

off and the output goes into a high impedance state,

allowing the smaller regulator to support the output volt-

age. However, if the LTC1873 is powered back up in

continuous mode, it will begin a soft-start cycle with a low

duty cycle, pulling the output down and corrupting the

data stored in SRAM. The solution is to tie FCB high,

allowing the device to start in discontinuous mode. Any

reversecurrentflowinQBwilltripthediscontinuousmode

circuitry, preventing the LTC1873 from pulling down the

output.

In some circuits, the OV latch can be a liability. Consider

a circuit where the output voltage at one channel may be

changed on the fly by changing the VID code or switching

in different feedback resistors. A downward adjustment

of greater than 15% will fire the fault latch, disabling both

sides of the LTC1873 until the power is recycled. In

circuits such as this, the fault latch can be disabled by

groundingtheFAULTpin.Theinternallatchwillstillbeset

the first time the output exceeds +15%, but the 10µA

current source pull-up will not be able to pull FAULT high,

and the LTC1873 will ignore the latch and continue

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normal operation. The MAX comparator will act as usual,

turning on QB until output is within range and then

allowing the loop to resume normal operation. FAULT can

also be pulled down with external open-collector logic to

restart a fault-latched LTC1873 as an alternative to recy-

cling the power. Note that this will not reset the internal

latch; if the external pull-down is released, the LTC1873

willreenterFAULTmode.Toresetthelatch,pullbothRUN/

SS pins low simultaneously or cycle the power.

other hand, voltage breakdown requirements in a typical

LTC1873 circuit are pretty tame: the 7V maximum input

voltage limits the V_DSand V_GSthe MOSFETs can see to

safe levels for most devices.

Low R_DS(ON)

R_DS(ON)calculations are pretty straightforward. R_DS(ON)is

the resistance from the drain to the source of the MOSFET

when the gate is fully on. Many MOSFETs have R_DS(ON)

specified at 4.5V gate drive—this is the right number to

use in LTC1873 circuits running from a 5V supply. As

current flows through this resistance while the MOSFET is

on, it generates I²R watts of heat, where I is the current

flowing (usually equal to the output current) and R is the

MOSFET R_DS(ON). This heat is only generated when the

MOSFET is on. When it is off, the current is zero and the

power lost is also zero (and the other MOSFET is busy

losing power).

VID Considerations

Some applications change the VID codes at channel 1 on

the fly. This is possible with the LTC1873, but care must

be taken to avoid tripping the overvoltage fault circuit.

Stepping the voltage upwards abruptly is safe, but step-

pingdownquicklybymorethan15%canleavethesystem

in a state where the output voltage is still at the old higher

level, but the feedback node is set to expect a new,

substantially lower voltage. If this condition persists for

morethan25µs,theovervoltagefaultcircuitrywillactivate

and latch off the LTC1873.

This lost power does two things: it subtracts from the

power available at the output, costing efficiency, and it

makes the MOSFET hotter—both bad things. The effect is

worst at maximum load when the current in the MOSFETs

and thus the power lost are at a maximum. Lowering

R_DS(ON)improves heavy load efficiency at the expense of

additional gate charge (usually) and more cost (usually).

Proper choice of MOSFET R_DS(ON)becomes a trade-off

between tolerable efficiency loss, power dissipation and

cost. Note that while the lost power has a significant effect

on system efficiency, it only adds up to a watt or two in a

typical LTC1873 circuit, allowing the use of small, surface

mount MOSFETs without heat sinks.

The simplest solution is to disable the fault circuit by

grounding the FAULT pin. Systems that must keep the

fault circuit active should ensure that the output voltage is

never programmed to step down by more than 15% in any

single step. A safe strategy is to step the output down by

10% or less at a time and wait for the output to settle to the

new value before taking subsequent steps. Regardless of

the state of the FAULT pin, the load is always protected

against overvoltage faults by the +5% MAX comparator.

EXTERNAL COMPONENT SELECTION

POWER MOSFETs

Gate Charge

Gate charge is the amount of charge (essentially, the

number of electrons) that the LTC1873 needs to put into

the gate of an external MOSFET to turn it on. The easiest

waytovisualizegatechargeistothinkofitasacapacitance

fromthegatepinoftheMOSFETtoSW(forQT)ortoPGND

(for QB). This capacitance is composed of MOSFET chan-

nel charge, actual parasitic drain-source capacitance and

Miller-multiplied gate-drain capacitance, but can be

approximated as a single capacitance from gate to source.

Regardless of where the charge is going, the fact remains

GettingpeakefficiencyoutoftheLTC1873dependsstrongly

on the external MOSFETs used. The LTC1873 requires at

least two external MOSFETs per side—more if one or

more of the MOSFETs are paralleled to lower on-resis-

tance. To work efficiently, these MOSFETs must exhibit

low R_DS(ON)at 5V V_GS(3.3V V_GSif the PV_CCinput supply

is 3.3V) to minimize resistive power loss while they are

conducting current. They must also have low gate charge

to minimize transition losses during switching. On the

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that it all has to come out of V_CCto turn the MOSFET gate

on, and when the MOSFET is turned back off, that charge

all ends up at ground. In the meanwhile, it travels through

the LTC1873’s gate drivers, heating them up. More power

lost!

INPUT SUPPLY

The BiCMOS process that allows the LTC1873 to include

large MOSFET drivers on-chip also limits the maximum

input voltage to 7V. This limits the practical maximum

input supply to a loosely regulated 5V or 6V rail. The

LTC1873willoperateproperlywithinputsuppliesdownto

about 3V, so a typical 3.3V supply can also be used if the

externalMOSFETsarechosenappropriately(seethePower

MOSFETs section).

Inthiscase,thepowerislostinlittlebite-sizedchunks,one

chunk per switch per cycle, with the size of the chunk set

bythegatechargeoftheMOSFET. EverytimetheMOSFET

switches, another chunk is lost. Clearly, the faster the

clock runs, the more important gate charge becomes as a

lossterm.Old-fashionedswitchersthatranat20kHzcould

pretty much ignore gate charge as a loss term; in the

550kHz LTC1873, gate charge loss can be a significant

efficiency penalty. Gate charge loss can be the dominant

loss term at medium load currents, especially with large

MOSFETs. Gate charge loss is also the primary cause of

power dissipation in the LTC1873 itself.

At the same time, the input supply needs to supply several

amps of current without excessive voltage drop. The input

supply must have regulation adequate to prevent sudden

load changes from causing the LTC1873 input voltage to

dip. In most typical applications where the LTC1873 is

generating a secondary low voltage logic supply, all of

these input conditions are met by the main system logic

supply when fortified with an input bypass capacitor.

TG Charge Pump

INPUT BYPASS CAPACITOR

There’sanothernuanceofMOSFETdrivethattheLTC1873

needs to get around. The LTC1873 is designed to use

N-channel MOSFETs for both QT and QB, primarily

becauseN-channelMOSFETsgenerallycostlessandhave

lower R_DS(ON)than similar P-channel MOSFETs. Turning

QB on is no big deal since the source of QB is attached to

PGND; the LTC1873 just switches the BG pin between

PGND and V_CC. Driving QT is another matter. The source

of QT is connected to SW which rises to V_CCwhen QT is

on. To keep QT on, the LTC1873 must get TG one MOSFET

V_GS(ON)above V_CC. It does this by utilizing a floating driver

with the negative lead of the driver attached to SW (the

source of QT) and the V_CClead of the driver coming out

separately at BOOST. An external 1µF capacitor (C_CP)

connected between SW and BOOST (Figure 2) supplies

power to BOOST when SW is high, and recharges itself

through D_CPwhen SW is low. This simple charge pump

keeps the TG driver alive even as it swings well above V_CC.

The value of the bootstrap capacitor C_CPneeds to be at

least 100 times that of the total input capacitance of the

topside MOSFET(s). For very large external MOSFETs (or

multiple MOSFETs in parallel), C_CPmay need to be

increased beyond the 1µF value.

A typical LTC1873 circuit running from a 5V logic supply

might provide 1.6V at 10A at one of its outputs. 5V to 1.6V

implies a duty cycle of 32%, which means QT is on 32%

of each switching cycle. During QT’s on-time, the current

drawn from the input equals the load current and during

the rest of the cycle, the current drawn from the input is

near zero. This 0A to 10A, 32% duty cycle pulse train adds

up to 4.7A_RMSat the input. At 550kHz, switching cycles

last about 1.8µs—most system logic supplies have no

hope of regulating output current with that kind of speed.

A local input bypass capacitor is required to make up the

difference and prevent the input supply from dropping

drastically when QT kicks on. This capacitor is usually

chosen for RMS ripple current capability and ESR as well

as value.

The input bypass capacitor in an LTC1873 circuit is

common to both channels. Consider our 10A example

casewiththeothersideoftheLTC1873disabled.Theinput

bypass capacitor gets exercised in three ways: its ESR

must be low enough to keep the initial drop as QT turns on

within reason (100mV or so); its RMS current capability

must be adequate to withstand the 4.7A_RMSripple current

at the input and the capacitance must be large enough to

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maintain the input voltage until the input supply can make

up the difference. Generally, a capacitor that meets the

first two parameters will have far more capacitance than is

required to keep capacitance-based droop under control.

Inourexample, weneed0.01ΩESRtokeeptheinputdrop

under 100mV with a 10A current step and 4.7A_RMSripple

current capacity to avoid overheating the capacitor. These

requirements can be met with multiple low ESR tantalum

or electrolytic capacitors in parallel, or with a large mono-

lithic ceramic capacitor.

Calculating RMS Current in C_IN

A buck regulator like the LTC1873 draws pulses of

current from the input capacitor during normal opera-

tion. The input capacitor sees this as AC current, and

dissipates power proportional to the RMS value of the

input current waveform. To properly specify the capaci-

tor, we need to know the RMS value of the input current.

Calculating the approximate RMS value of a pulse train

withafixeddutycycleis straightforward,buttheLTC1873

complicatesmattersbyrunningtwosidessimultaneously

and out of phase, creating a complex waveform at the

input.

ThetwosidesoftheLTC1873runoffasinglemasterclock

and are wired 180° out of phase with each other to

significantly reduce the total capacitance/ESR needed at

the input. Assuming 100mV of ripple and 10A output

current, we needed an ESR of 0.01Ω and 4.7A ripple

current capability for one side. Now, assume both sides

are running simultaneously with identical loading. If the

two sides switched in phase, all the loading conditions

would double and we’d need enough capacitance for

9.4A_RMSand 0.005Ω ESR. With the two sides out of

phase, the input current is 4.8A_RMS—barely larger than

the single case (Figure 7)! The peak current deltas are still

only 10A, requiring the same 0.01Ω ESR rating. As long

as the capacitor we chose for the single side application

can support the slightly higher 4.8A_RMScurrent, we can

add the second channel without changing the input ca-

pacitor at all. As a general rule, an input bypass capacitor

capable of supporting the larger output current channel

To calculate the approximate RMS value of the input

current, we first need to calculate the average DC value

with both sides of the LTC1873 operating at maximum

load. Over a single period, the system will spend some

time with one top switch on and the other off, perhaps

some time with both switches on, and perhaps some

time with both switches off. During the time each top

switch is on, the current will equal that side’s full load

output current. When both switches are on, the total

current will be the sum of the two full load currents, and

when both are off, the current is effectively zero. Multiply

each current value by the percentage of the period that

the current condition lasts, and sum the results—this is

the average DC current value.

As an example, consider a circuit that takes a 5V input

and generates 3.3V at 3A at side 1 and 1.6V at 10A at

side 2. When a cycle starts, TG1 turns on and 3A flows

32%

10A

QT CURRENT, SIDE 1 ONLY

(FOR 1-PHASE, 2 SIDES:

MULTIPLY CURRENT BY 2)

68%

0

50%

16% 16% 18%

13

10

32%

6.8A

CURRENT IN C , SIDE 1 ONLY

IN

I

= 4.66A

, (1-PHASE,

CIN

RMS

2 SIDES: I = 9.3A

CIN RMS

)

0

–3.2A

32% 18% 32% 18%

10A

0

5.2

3

I

AVE

QT1 CURRENT

QT2 CURRENT

BOTH SIDES EQUAL LOAD

2-PHASE OPERATION

0

A

B

TIME

C

D

3.6A

0

CURRENT IN C

IN

,

BOTH SIDES EQUAL LOAD

1873 SB1

I

= 4.8A

CIN

RMS

1873 F07

–6.4A

Figure SB1. Average Current Calculation

Figure 7. Current Waveforms

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from C_IN(time point A). 50% of the way through, TG2

turns on and the total current is 13A (time point B).

Shortly thereafter, TG1 turns off and the current drops to

10A (time point C). Finally, TG2 turns off and the current

spends a short time at 0 before TG1 turns on again (time

point D).

current and resistive losses, but this approximate value

is adequate for input capacitor calculation purposes.

–2.18²• 0.5 + 7.82²• 0.16 +

(

) (

)

I_RMS

=

4.82²• 0.16 + –5.18²• 0.18

) (

)

I

_AVG= 3A • 0.5 + 13A • 0.16 +

= 4.55A_RMS

(

) (

)

Ifthecircuitislikelytospendtimewithonesideoperating

and the other side shut down, the RMS current will need

to be calculated for each possible case (side 1 on, side 2

off; side 1 off, side 2 on; both sides on). The capacitor

must be sized to withstand the largest RMS current of the

three—sometimes this occurs with one side shut down!

10A • 0.16 + 0A • 0.18 = 5.18A

) (

)

Now we can calculate the RMS current. Using the same

waveform we used to calculate the average DC current,

subtract the average current from each of the DC values.

Squareeachcurrenttermandmultiplythesquaresbythe

same period percentages we used to calculate the aver-

ageDCcurrent. Sumtheresultsandtakethesquareroot.

The result is the approximate RMS current as seen by the

input capacitor with both sides of the LTC1873 at full

load. Actual RMS current will differ due to inductor ripple

Side1only:

I_AVE1= 3A • 0.67 + 0A • 0.33 = 2.01A

(

) (

)

2

I_RMS1

=

1 • 0.67 + –2²• 0.33 = 1.42A_RMS

(

)

50%

16% 16% 18%

Side 2 only:

7.8

4.8

I_AVE2= 10A • 0.32 + 0A • 0.68 = 3.2A

(

) (

)

I_RMS2

=

6.8²• 0.32 + –3.2²• 0.68

(

)

0

= 4.66A_RMS> 4.55A_RMS

–2.2

Consider the case where both sides are operating at the

same load, with a 50% duty cycle at each side. The RMS

current with both sides running is near zero, while the

RMS current with one side active is 1/2 the total load

current of that side.

–5.2

0

A

B

TIME

C

D

1873 SB2

Figure SB2. AC Current Calculation

can support both channels running simultaneously (see

the 2-Phase Operation section for more information).

Details on how to calculate the maximum RMS input

current can be found in Application Note 77.

At some random time after they are turned on, they can

blow up for no apparent reason. The capacitor manufac-

turers are aware of this and sell special “surge tested”

tantalum capacitors specifically designed for use with

switching regulators. When choosing a tantalum input

capacitor, make sure that it is rated to carry the RMS

current that the LTC1873 will draw. If the data sheet

doesn’t give an RMS current rating, chances are the

capacitor isn’t surge tested. Don’t use it!

Tantalum capacitors are a popular choice as input capaci-

tors for LTC1873 applications, but they deserve a special

caution here. Generic tantalum capacitors have a destruc-

tive failure mechanism when they are subjected to large

RMS currents (like those seen at the input of a LTC1873).

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OUTPUT BYPASS CAPACITOR

inductor should be rated to withstand 15A + 1/2 I_RIPPLE

or 16.5A without saturating.

,

The output bypass capacitor has quite different require-

ments from the input capacitor. The ripple current at the

output of a buck regulator like the LTC1873 is much lower

than at the input, due to the fact that the inductor current

is constantly flowing at the output whenever the LTC1873

is operating in continuous mode. The primary concern at

the output is capacitor ESR. Fast load current transitions

at the output will appear as voltage across the ESR of the

output bypass capacitor until the feedback loop in the

LTC1873 can change the inductor current to match the

newloadcurrentvalue. ThisESRstepattheoutputisoften

the single largest budget item in the load regulation

calculation. As an example, our hypothetical 1.6V, 10A

switcher with a 0.01Ω ESR output capacitor would expe-

rience a 100mV step at the output with a 0 to 10A load

step—a 6.3% output change!

FEEDBACK LOOP/COMPENSATION¹

Feedback Loop Types

In a typical LTC1873 circuit, the feedback loop consists of

the modulator, the external inductor and output capacitor,

and the feedback amplifier and its compensation network.

All of these components affect loop behavior and need to

beaccountedforintheloopcompensation.Themodulator

consistsoftheinternalPWMgenerator,theoutputMOSFET

drivers and the external MOSFETs themselves. From a

feedback loop point of view, it looks like a linear voltage

transferfunctionfromCOMPtoSWandhasagainroughly

equal to the input voltage. It has fairly benign AC behavior

at typical loop compensation frequencies with significant

phase shift appearing at half the switching frequency.

Usually the solution is to parallel several capacitors at the

output. For example, to keep the transient response inside

of 3% with the previous design, we’d need an output ESR

better than 0.0048Ω. This can be met with three 0.014Ω,

470µF tantalum capacitors in parallel.

Theexternalinductor/outputcapacitorcombinationmakes

a more significant contribution to loop behavior. These

components cause a second order LC roll-off at the

output, with the attendant 180° phase shift. This roll-off is

what filters the PWM waveform, resulting in the desired

DC output voltage, but the phase shift complicates the

loop compensation if the gain is still higher than unity at

the pole frequency. Eventually (usually well above the LC

pole frequency), the reactance of the output capacitor will

approach its ESR, and the roll-off due to the capacitor will

stop, leaving 6dB/octave and 90° of phase shift (Figure 8).

INDUCTOR

The inductor in a typical LTC1873 circuit is chosen prima-

rily for value and saturation current. The inductor value

sets the ripple current, which is commonly chosen at

around 30% of the anticipated full load current. Ripple

current is set by:

¹The information in this section is based on the paper “The K Factor: A New Mathematical Tool for

Stability Analysis and Synthesis” by H. Dean Venable, Venable Industries, Inc. For complete paper,

see “Reference Reading #4” at www.linear-tech.com.

t_ON(QB)

V

OUT

(

)

GAIN

(dB)

PHASE

(DEG)

I_RIPPLE

=

L

In our hypothetical 1.6V, 10A example, we'd set the ripple

current to 30% of 10A or 3A, and the inductor value would

be:

GAIN

A

V

0

–12dB/OCT

0

t_ON(QB)

V

1.2µs 1.6V

(

)

(

)(

)

OUT

L =

=

= 0.5µH

–90

PHASE

I_RIPPLE

4A

1.6V

5V

–180

with t_ON(QB)= 1−

/550kHz = 1.2µs

–6dB/OCT

1873 F08

The inductor must not saturate at the expected peak

current. In this case, if the current limit was set to 15A, the

Figure 8. Ideal Transfer Function of Buck Modulator

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C2

So far, the AC response of the loop is pretty well out of the

user’scontrol.Themodulatorisafundamentalpieceofthe

LTC1873 design, and the external L and C are usually

chosen based on the regulation and load current require-

ments without considering the AC loop response. The

feedback amplifier, on the other hand, gives us a handle

with which to adjust the AC response. The goal is to have

180° phase shift at DC (so the loop regulates) and some-

thing less than 360° phase shift at the point that the loop

gain falls to 0dB. The simplest strategy is to set up the

feedback amplifier as an inverting integrator, with the 0dB

frequency lower than the LC pole (Figure 9). This “type 1”

configuration is stable but transient response will be less

than exceptional if the LC pole is at a low frequency.

C1

R2

R1

–

+

IN

OUT

R

B

1873 F10a

V

REF

Figure 10a. Type 2 Amplifier Schematic Diagram

GAIN

(dB)

PHASE

(DEG)

–6dB/OCT

GAIN

0

C1

–6dB/OCT

R1

–90

–180

–

+

IN

OUT

R

B

1873 F09a

V

REF

PHASE

–270

Figure 9a. Type 1 Amplifier Schematic Diagram

1873 F10b

Figure 10b. Type 2 Amplifier Transfer Function

GAIN

(dB)

PHASE

(DEG)

Type 2 loops work well in systems where the ESR zero in

the LC roll-off happens close to the LC pole, limiting the

total phase shift due to the LC. The additional phase

compensation in the feedback amplifier allows the 0dB

point to be at or above the LC pole frequency, improving

loop bandwidth substantially over a simple type 1 loop. It

has limited ability to compensate for LC combinations

where low capacitor ESR keeps the phase shift near 180°

for an extended frequency range. LTC1873 circuits using

conventional switching grade electrolytic output capaci-

tors can often get acceptable phase margin with type 2

compensation.

GAIN

0

–6dB/OCT

–90

–180

PHASE

–270

1873 F09b

Figure 9b. Type 1 Amplifier Transfer Function

“Type 3” loops (Figure 11) use two poles and two zeros to

obtain a 180° phase boost in the middle of the frequency

band. A properly designed type 3 circuit can maintain

acceptable loop stability even when low output capacitor

ESR causes the LC section to approach 180° phase shift

wellabovetheinitialLCroll-off. Aswithatype2circuit, the

Figure 10 shows an improved “type 2” circuit that uses an

additional pole-zero pair to temporarily remove 90° of

phase shift. This allows the loop to remain stable with 90°

more phase shift in the LC section, provided the loop

reaches 0dB gain near the center of the phase “bump.”

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C2

Modulator gain and phase can be measured directly from

a breadboard, or can be simulated if the appropriate

parasitic values are known. Measurement will give more

accurateresults,butsimulationcanoftengetcloseenough

to give a working system. To measure the modulator gain

and phase directly, wire up a breadboard with an LTC1873

and the actual MOSFETs, inductor, and input and output

capacitors that the final design will use. This breadboard

should use appropriate construction techniques for high

speed analog circuitry: bypass capacitors located close to

the LTC1873, no long wires connecting components,

appropriately sized ground returns, etc. Wire the feedback

amplifier as a simple type 1 loop, with a 10k resistor from

C3

R3

C1

R2

R1

–

+

IN

OUT

R

B

1873 F11a

V

REF

Figure 11a. Type 3 Amplifier Schematic Diagram

GAIN

(dB)

PHASE

(DEG)

–6dB/OCT

+6dB/OCT

–6dB/OCT

V_OUTto FB and a 0.1µF feedback capacitor from COMP to

GAIN

FB. Choose the bias resistor (R_B) as required to set the

desired output voltage. Disconnect R_Bfrom ground and

connect it to a signal generator or to the source output of

a network analyzer (Figure 12) to inject a test signal into

the loop. Measure the gain and phase from the COMP pin

to the output node at the positive terminal of the output

capacitor. Make sure the analyzer’s input is AC coupled so

that the DC voltages present at both the COMP and V_OUT

nodes don’t corrupt the measurements or damage the

analyzer.

0

–90

–180

PHASE

–270

1873 F11b

Figure 11b. Type 3 Amplifier Transfer Function

If breadboard measurement is not practical, a SPICE

simulation can be used to generate approximate gain/

phase curves. Plug the expected capacitor, inductor and

MOSFET values into the following SPICE deck and gener-

ate an AC plot of V(V_OUT)/V(COMP) in dB and phase of

loop should cross through 0dB in the middle of the phase

bump to maximize phase margin. Many LTC1873 circuits

using low ESR tantalum or OS-CON output capacitors

need type 3 compensation to obtain acceptable phase

margin with a high bandwidth feedback loop.

5V

Feedback Component Selection

+

10Ω MBR0530T

C

IN

+

Selecting the R and C values for a typical type 2 or type 3

loopisanontrivialtask.Theapplicationsshowninthisdata

sheet show typical values, optimized for the power com-

ponentsshown.Theyshouldgiveacceptableperformance

with similar power components, but can be way off if even

one major power component is changed significantly.

Applicationsthatrequireoptimizedtransientresponsewill

need to recalculate the compensation values specifically

forthecircuitinquestion. Theunderlyingmathematicsare

complex, but the component values can be calculated in a

straightforward manner if we know the gain and phase of

the modulator at the crossover frequency.

10µF

V

PV

CC

BOOST2

1µF

QT

QB

TG

L

EXT

V

1/2 LTC1873

COMP

TO

OUT

TO

SW

0.1µF

ANALYZER

+

FB

BG

C

OUT

NC

RUN/SS

FCB

R

10k

B

FAULT

PGND

AC

SOURCE

FROM

SGND

ANALYZER

1873 F12

Figure 12. Modulator Gain/Phase Measurement Set-Up

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V(OUT) in degrees. Refer to your SPICE manual for details Now calculate the remaining values:

of how to generate this plot.

(K is a constant used in the calculations)

*1873 modulator gain/phase

ƒ = chosen crossover frequency

G = 10^(GAIN/20)(this converts GAIN in dB to G in absolute

gain)

*this file written to run with PSpice 8.0

*may require modifications for other SPICE

simulators

Type 2 Loop:

*MOSFETs

rfet mod sw 0.02

;MOSFET rdson

BOOST

*inductor

lext sw out1 1u

rl out1 out 0.005

K = Tan

C2 =

+ 45°

;inductor value

;inductor series R

2

1

*output cap

cout out out2 1000u

resr out2 0 0.01

2πƒGKR1

;capacitor value

;capacitor ESR

C1= C2 K²– 1

(

)

*1873 internals

emod mod 0 laplace {v(comp)} =

+ {5*exp(–s*909e–9)} ;5 -> 3.3 for 3.3 VCC

*emod mod 0 comp 0 5 ;use if above lines fail

vstim comp 0 0 ac 1

.ac dec 100 1k 1meg

.probe

K

R2 =

R_B=

2πƒC1

V_REFR1

;ac stimulus

( )

V_OUT– V_REF

.end

Type 3 Loop:

With the gain/phase plot in hand, a loop crossover fre-

quency can be chosen. Usually the curves look something

like Figure 8. Choose the crossover frequency in the rising

or flat parts of the phase curve, beyond the external LC

poles. Frequencies between 10kHz and 50kHz usually

work well. Note the gain (GAIN, in dB) and phase (PHASE,

in degrees) at this point. The desired feedback amplifier

gain will be –GAIN to make the loop gain 0dB at this

frequency.Nowcalculatetheneededphaseboost,assum-

ing 60° as a target phase margin:

BOOST

K = Tan²

+ 45°

4

1

C2 =

2πƒGR1

C1= C2 K – 1

(

)

K

R2 =

R3 =

BOOST = –(PHASE + 30°)

2πƒC1

R1

If the required BOOST is less than 60°, a type 2 loop can

be used successfully, saving two external components.

BOOST values greater than 60° usually require type 3

loops for satisfactory performance.

K – 1

(

)

1

C3 =

R_B=

Finally, choose a convenient resistor value for R1 (10k is

usually a good value). Note that channel 1 includes R1 and

R_Binternally as part of the VID DAC circuitry. R1 is fixed

at 20k and R_Bvaries depending on the VID code selected.

2πƒ K R3

V_REFR1

( )

V_OUT– V_REF

23

LTC1873

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CURRENT LIMIT PROGRAMMING

Accuracy Trade-Offs

ProgrammingthecurrentlimitontheLTC1873isstraight-

forward. The I_MAXpin sets the current limit by setting the

maximum allowable voltage drop across QB (the bottom

MOSFET) before the current limit circuit engages. The

voltage across QB is set by its on-resistance and the

current flowing in the inductor, which is the same as the

output current. The LTC1873 current limit circuit inverts

the voltage at I_MAXbefore comparing it with the negative

voltage across QB, allowing the current limit to be set with

a positive voltage.

The V_DSsensing scheme used in the LTC1873 is not

particularly accurate, primarily due to uncertainty in the

R_DS(ON)from MOSFET to MOSFET. A second error term

arises from the ringing present at the SW pin, which

causes the V_DSto look larger than (I_LOAD)(R_DS(ON)) at the

beginning of QB’s on-time. These inaccuracies do not

prevent the LTC1873 current limit circuit from protecting

itself and the load from damaging overcurrent conditions,

but they do prevent the user from setting the current limit

to a tight tolerance if more than one copy of the circuit is

being built. The 50% factor in the current setting equation

above reflects the margin necessary to ensure that the

circuitwillstayoutofcurrentlimitatthemaximumnormal

load, even with a hot MOSFET that is running quite a bit

higher than its R_DS(ON)spec.

To set the current limit, calculate the expected voltage

drop across QB at the maximum desired current:

V_PROG= I

R

+ 100mV

DS(ON)

(

)

(

)

ILIM

I_LIMshould be chosen to be quite a bit higher than the

expected operating current, to allow for MOSFET R_DS(ON)

changes with temperature. Setting I_LIMto 150% of the

maximumnormaloperatingcurrentisusuallysafeandwill

adequately protect the power components if they are

chosen properly. The 100mV term is an approximate

factor that corrects for errors caused by ringing on the

switch node (illustrated in Figure 6). This factor will

change depending on the layout and the components

used, but 100mV is usually a good starting point. V_DROPis

then programmed at the I_MAXpin using the internal 10µA

pull-up and an external resistor:

FCB OPERATION/SECONDARY WINDINGS

The FCB pin can be used in conjunction with a secondary

winding on one side of the LTC1873 to generate a third

regulated voltage output. This output can be directly

regulated at the FCB pin. In theory, a fourth output could

be added, either unregulated or with additional external

circuitry at the FCB pin.

The extra auxiliary output is taken from a second winding

on the core of the inductor on one channel, converting it

intoatransformer(Figure13).Theauxiliaryoutputvoltage

is set by the main output voltage and the turns ratio of the

extra winding to the primary winding. Load regulation at

the auxiliary output will be relatively good as long as the

mainoutputisrunningincontinuousmode. Astheloadon

the main channel drops and the LTC1873 switches to

discontinuous or Burst Mode operation, the auxiliary

output will not be able to maintain regulation, especially if

the load at the auxiliary output remains heavy.

R_ILIM= V_PROG/10µA

The resulting value of R_ILIMshould be checked in an actual

circuit to ensure that the I_LIMcircuit kicks in as expected.

MOSFET R_DS(ON)specs are like horsepower ratings in

automobiles, and should be taken with a grain of salt.

Circuits that use very low values for R_IMAX(<20k) should

be checked carefully, since small changes in R_IMAXcan

cause large I_LIMchanges when the 100mV correction

factor makes up a large percentage of the total V_PROG

value. If V_PROGis set too low, the LTC1873 may fail to

start up.

To avoid this, the auxiliary output voltage is divided down

with a conventional feedback resistor string with the

divided auxiliary output voltage fed back to the FCB pin

(Figure 13). The FCB pin threshold is trimmed to 800mV

24

LTC1873

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APPLICATIO S I FOR ATIO

U

with 20mV of hysteresis, allowing fairly precise control of

the auxiliary voltage. If the LTC1873 is in discontinuous or

Burst Mode operation and the auxiliary output voltage

drops, the FCB pin will trip and the LTC1873 will resume

continuous operation regardless of the load on the main

output. The FCB pin removes the requirement that power

must be drawn from the inductor primary in order to

extractpowerfromtheauxiliarywindings. Withtheloopin

continuous mode, the auxiliary outputs may be loaded

withoutregardtotheprimaryload.NotethatiftheLTC1873

is already running in continuous mode and the auxiliary

output drops due to excessive loading, no additional

action can be taken by the LTC1873 to regulate the

auxiliary output.

later removed, the LTC1873 will latch off again unless the

latch is reset by cycling the power or RUN/SS pins.

OPTIMIZING PERFORMANCE

Maximizing High Load Current Efficiency

Efficiency at high load currents (when the LTC1873 is

operating in continuous mode) is primarily controlled by

the resistance of the components in the power path

(QT, QB, L_EXT) and power lost in the gate drive circuits due

to MOSFET gate charge. Maximizing efficiency in this

region of operation is as simple as minimizing these

terms.

The behavior of the load over time affects the efficiency

strategy. Parasitic resistances in the MOSFETs and the

inductor set the maximum output current the circuit can

supply without burning up. A typical efficiency curve

(Figure 14) shows that peak efficiency occurs near 30%

of this maximum current. If the load current will vary

around the efficiency peak and will spend relatively little

time at the maximum load, choosing components so that

the average load is at the efficiency peak is a good idea.

This puts the maximum load well beyond the efficiency

peak, but usually gives the greatest system efficiency over

time, which translates to the longest run time in a battery-

powered system. If the load is expected to be relatively

constantatthemaximumlevel,thecomponentsshouldbe

chosen so that this load lands at the peak efficiency point,

well below the maximum possible output of the converter.

V

IN

V

OUT(AUX)

+

C

IN

+

C

QT

TG

BG

OUT(AUX)

1/2

V

LTC1873

OUT

QB

FCB

C

OUT

R

FCB1

FCB2

1873 F13

Figure 13. Regulating an Auxiliary Output with the FCB Pin

FAULT FLAG

TheFAULTpinisanopen-drainoutputthatindicatesifone

or both of the outputs has exceeded 15% of its pro-

grammedoutputvoltage.FAULTincludesaninternal10µA

pull-up to V_CCand does not require an external pull-up to

interface to standard logic. FAULT pulls low in normal

operation, and releases when a overvoltage fault is

detected.

100

V

= 5V

IN

V

OUT

= 3.3V

V

= 2.5V

= 1.6V

OUT

90

80

70

When an overvoltage fault occurs, an internal latch sets

and FAULT goes high, disabling the LTC1873 until the

latch is cleared by recycling the power or pulling both

RUN/SS pins low simultaneously. Alternately, the FAULT

pin can be pulled back low externally with an open-

collector/open-drain device or an N-channel MOSFET or

NPN, which will allow the LTC1873 to resume normal

operation, but will not reset the latch. If the pull-down is

0

5

10

15

LOAD CURRENT (A)

1873 G01

Figure 14. Typical LTC1873 Efficiency Curves

25

LTC1873

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Maximizing Low Load Current Efficiency

pin, which encompasses both reference accuracy and any

op amp offset. This accounts for 1% error at the output

with a 5V input supply. The feedback voltage line regula-

tion spec adds an additional 0.05%/V term that accounts

for change in reference output with change in input supply

voltage. With a 5V supply, the errors contributed by the

LTC1873 itself typically add up to less than 1% DC error at

the output.

Low load current efficiency depends strongly on proper

operation in discontinuous and Burst Mode operations. In

anideallyoptimizedsystem, discontinuousmodereduces

conduction losses but not switching losses, since each

power MOSFET still switches on and off once per cycle. In

a typical system, there is additional loss in discontinuous

mode due to a small amount of residual current left in the

inductor when QB turns off. This current gets dissipated

across the body diode of either QT or QB. Some LTC1873

systems lose as much to body diode conduction as they

save in MOSFET conduction. The real efficiency benefit of

discontinuousmodehappenswhenBurstModeoperation

is invoked. At typical power levels, when Burst Mode

operation is activated, gate drive is the dominant loss

term. Burst Mode operation turns off all output switching

for several clock cycles in a row, significantly cutting gate

drive losses. As the load current in Burst Mode operation

falls toward zero, the current drawn by the circuit falls to

the LTC1873’s background quiescent level—about 3mA

per channel.

At side 2, the output voltage setting resistors (R1 and R_B

in Figure 3) are the other major contributor to DC error. At

a typical 1.xV output voltage, the resistors are of roughly

the same value, which tends to halve their error terms,

improving accuracy. Still, using 1% resistors for R1 and

R_Bwill add 1% to the total output error budget, equal to

thatofallerrorsduetotheLTC1873combined.Using0.1%

resistorsinjustthosetwopositionscannearlyhalvetheDC

output error for very little additional cost. Side 1 uses the

internal VID network to set the output voltage, and is

specified to be within ±1.5% of the values shown in

Table 1.

Load Regulation

To maximize low load efficiency, make sure the LTC1873

is allowed to enter discontinuous and Burst Mode opera-

tion as cleanly as possible. FCB must be above its 0.8V

threshold. Minimize ringing at the SW node so that the

discontinuous comparator leaves as little residual current

in the inductor as possible when QB turns off. It helps to

connect the SW pin of the LTC1873 as close to the drain

of QB as possible. An RC snubber network can also be

added from SW to PGND.

Load regulation is affected by feedback voltage, feedback

amplifier gain and external ground drops in the feedback

path. Feedback voltage is covered above and is within 1%

over temperature. A full-range load step might require a

10% duty cycle change to keep the output constant,

requiring the COMP pin to move about 100mV. With

amplifier gain at 85dB, this adds up to only a 10µV shift at

FB, negligible compared to the reference accuracy terms.

External ground drops aren’t so negligible. The LTC1873

can sense the positive end of the output voltage by

attaching the feedback resistor directly at the load, but it

cannot do the same with the ground lead. Just 0.001Ω of

resistanceinthegroundleadat10Aloadwillcausea10mV

error in the output voltage—as much as all the other DC

errors put together. Proper layout becomes essential to

achieving optimum load regulation from the LTC1873.

See the Layout/Troubleshooting section for more infor-

mation. A properly laid out LTC1873 circuit should move

less than a millivolt at the output from zero to full load.

REGULATION OVER COMPONENT TOLERANCE/

TEMPERATURE

DC Regulation Accuracy

The LTC1873 initial DC output accuracy depends mainly

on internal reference accuracy, op amp offset and external

resistor accuracy (side 2 only). Two LTC1873 specs come

into play: feedback voltage and feedback voltage line

regulation. The feedback voltage spec is 800mV ± 8mV

over the full temperature range, and is specified at the FB

26

LTC1873

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APPLICATIO S I FOR ATIO

U

TRANSIENT RESPONSE

does so (Figure 15). Positive di/dt in the inductor causes

positive dv/dt in the ESR, regardless of what the “pure”

capacitance is doing. The output voltage will turn around

when the positive dv/dt across the ESR exceeds the

negativedv/dtacrossthepurecapacitance.Iftheexpected

load step (∆I) is known, an optimum inductor value can be

chosen:

Transient response is the other half of the regulation

equation. The LTC1873 can keep the DC output voltage

constant to within 1% when averaged over hundreds of

cycles. Over just a few cycles, however, the external

componentsconspiretolimitthespeedthattheoutputcan

move. Consider our typical 5V to 1.5V circuit, subjected to

a 1A to 5A load transient. Initially, the loop is in regulation

and the DC current in the output capacitor is zero.

Suddenly, an extra 4A start flowing out of the output

capacitor while the inductor is still supplying only 1A. This

sudden change will generate a (4A)(C_ESR)voltage step at

the output; with a typical 0.015Ω output capacitor ESR,

this is a 60mV step at the output, or 4% (for a 1.5V output

voltage).

ESR

∆I

L ≤ V – V_OUT•C •

(

IN

)

MakingLsmallerthanthisoptimumvalueyieldslittleorno

improvement in transient response. As the output voltage

recovers, the inductor current will briefly rise above the

leveloftheoutputcurrenttoreplenishthechargelostfrom

the output capacitor. With a properly compensated loop,

the entire recovery time will be inside of 10µs.

Very quickly, the feedback loop will realize that something

has changed and will move at the bandwidth allowed by

the external compensation network towards a new duty

cycle. If the bandwidth is set to 50kHz, the COMP pin will

get to 60% of the way to 90% duty cycle in 3µs. Now the

inductor is seeing 3.5V across itself for a large portion of

the cycle, and its current will increase from 1A at a rate set

by di/dt = V/L. If the inductor value is 0.5µH, the di/dt will

be 3.5V/0.5µH or 7A/µs. Sometime in the next few micro-

secondsaftertheswitchcyclebegins,theinductorcurrent

will have risen to the 5A level of the load current and the

output capacitor will stop losing charge.

Most loads care only about the maximum deviation from

ideal, whichoccurssomewhereinthefirsttwocyclesafter

the load step hits. During this time, the output capacitor

does all the work until the inductor and control loop regain

control. The initial drop (or rise if the load steps down) is

entirelycontrolledbytheESRofthecapacitorandamounts

to most of the total voltage drop. To minimize this drop,

reduce the ESR as much as possible by choosing low ESR

capacitors and/or paralleling multiple capacitors at the

output. The capacitance value accounts for the rest of the

voltage drop until the inductor current rises. With most

output capacitors, several devices paralleled to get the

ESR down will have so much capacitance that this drop

term is negligible. Ceramic capacitors are an exception; a

small ceramic capacitor can have suitably low ESR with

relatively small values of capacitance, making this second

drop term significant.

Note that the output voltage will stop dropping before the

inductor current reaches this new output current level.

Recall that any practical output capacitor looks like a pure

capacitance in series with some amount of ESR. When a

load transient hits, virtually all of the initial voltage drop at

the output is due to IR drop across the ESR. The output

capacitance begins to discharge at the same time and

continuesuntiltheinductorcurrentrisestomatchthenew

output current level.

Optimizing Loop Compensation

Loop compensation has a fundamental impact on tran-

sient recovery time, the time it takes the LTC1873 to

recover after the output voltage has dropped due to

output capacitor ESR. Optimizing loop compensation

entails maintaining the highest possible loop bandwidth

while ensuring loop stability. The Feedback Component

The output voltage, however, will turn around and start

heading the right way before this happens. The next time

the top MOSFET turns on, the inductor current will begin

increasing linearly. This increasing current flows almost

entirely into the capacitor, going through the ESR as it

27

LTC1873

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APPLICATIO S I FOR ATIO

I

L

V

OUT

V

SW

L

+

V

ESR

–

C

OUT

I

OUT

+

V

CAP

–

1873 F15a

Figure 15a. Capacitor Parasitics Affecting Transient Recovery

I

L

I

OUT

I

L

I

OUT

V

ESR

V

ESR

V

CAP

V

CAP

OUT

V

OUT

V

OUT(NOMINAL)

1873 F15b

TRANSIENT

HITS

I

> I

TIME

L

OUT

V

OUT

TURNS

AROUND

Figure 15b. Transient Recovery Curves

Selection section describes in detail how to design an

optimized feedback loop, appropriate for most LTC1873

systems.

allowable value at maximum load. With the load at zero,

any transient that comes along will be a current increase

whichwillcausetheoutputvoltagetofall. Sincetheoutput

voltage is initially at a high value, it can fall further before

itgoesoutofspec.Similarly,atfullload,theoutputcurrent

can only decrease, causing a positive shift in the output

voltage; the initial low value allows it to rise further before

the spec is exceeded. The primary benefit of voltage

positioning is it increases the allowable ESR of the output

capacitors, saving cost. An additional bonus is that at

maximum load, the output voltage is near the minimum

allowable, decreasing the power dissipated in the load.

Voltage Positioning

If the load transients consist primarily of load steps from

near zero load to full load and back, the transient response

can be traded off against DC regulation performance by

using a technique known as “voltage positioning.” The

goal is to intentionally compromise the DC regulation loop

such that the output rides near the maximum allowable

value (often +5%) with no load and near the minimum

28

LTC1873

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APPLICATIO S I FOR ATIO

U

Implementing voltage positioning is as simple as creating

an intentional resistance in the output path to generate the

required voltage drop. This resistance can be a low value

resistor, a length of PCB trace, or even the parasitic

resistance of the inductor if an appropriate filter is used. If

theLTC1873sensestheoutputvoltageupstreamfromthe

resistance (Figure 16c), the output voltage will move with

load as I • R_VP, where I is the load current and R_VPis the

value of the voltage positioning resistor. If the feedback

networkisthenresettoregulateneartheupperedgeofthe

specified tolerance, the output voltage will ride high when

Measurement Techniques

Measuring transient response presents a challenge in two

respects: obtaining an accurate measurement and gener-

ating a suitable transient to use to test the circuit. Output

measurements should be taken with a scope probe

directly across the output capacitor. Proper high fre-

quency probing techniques should be used. In particular,

don’t use the 6" ground lead that comes with the probe!

Use an adapter that fits on the tip of the probe and has a

short ground clip to ensure that inductance in the ground

path doesn’t cause a bigger spike than the transient signal

beingmeasured.Conveniently,thetypicalprobetipground

clipisspacedjustrighttospantheleadsofatypicaloutput

capacitor.

I

_LOADislowandwillridelowwhenI_LOADishigh.Compared

to a traditional regulator (Figure 16a), a voltage position-

ing regulator can theoretically stand as much as twice the

ESR drop across the output capacitor while maintaining

output voltage regulation. This means smaller, cheaper

output capacitors can be used while keeping the output

voltage within acceptable limits.

Now that we know how to measure the signal, we need to

have something to measure. The ideal situation is to use

V

IN

MAXIMUM

+5%

NOM

–5%

ALLOWABLE

V

OUT

TRANSIENT

LTC1873

FB

V

OUT

MAX

0

+

LOAD

CURRENT

1873 F16a

1873 F16b

TIME

Figure 16a. Standard Regulator

Figure 16b. Standard Regulator—Transient Response

V

IN

VOLTAGE

POSITIONING

RESISTOR

+5%

NOM

–5%

MAXIMUM

ALLOWABLE

TRANSIENT

V

OUT

(R

)

VP

≈2× FIGURE 16b

LTC1873

FB

V

OUT

MAX

0

+

LOAD

CURRENT

1873 F16c

1873 F16d

TIME

Figure 16c. Voltage Positioning Regulator

Figure 16d. Positioning Regulator—Transient Response

29

LTC1873

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APPLICATIO S I FOR ATIO

the actual load for the test, and switch it on and off while

watching the output. If this isn’t convenient, a current step

generator is needed. This generator needs to be able to

turn on and off in nanoseconds to simulate a typical

switching logic load, so stray inductance and long clip

leads between the LTC1873 and the transient generator

must be minimized.

Changing the Output Voltage on the Fly

Thevoltageatside1oftheLTC1873canbechangedonthe

fly by changing the VID code while the output is enabled,

but care must be taken to avoid tripping the overvoltage

faultcircuit.Steppingthevoltageupwardsabruptlyissafe,

butsteppingdownquicklybymorethan15%canleavethe

system in a state where the output voltage is still at the old

higher level, but the feedback node is set to expect a new,

substantially lower voltage. If this condition persists for

more than 10µs, the overvoltage fault circuitry will fire and

latch off the LTC1873.

Figure 17 shows an example of a simple transient genera-

tor. Be sure to use a noninductive resistor as the load

element—many power resistors use an inductive spiral

pattern and are not suitable for use here. A simple solution

is to take ten 1/4W film resistors and wire them in parallel

to get the desired value. Surface mount resistors are best.

This gives a noninductive resistive load which can dissi-

pate 2.5W continuously or 50W if pulsed with a 5% duty

cycle, enough for most LTC1873 circuits. Solder the

MOSFET and the resistor(s) as close to the output of the

LTC1873 circuit as possible and set up the signal genera-

tor to pulse at a 100Hz rate with a 5% duty cycle. This

pulses the LTC1873 with 500µs transients 10ms apart,

adequate for viewing the entire transient recovery time for

both positive and negative transitions while keeping the

load resistor cool.

The simplest solution is to disable the fault circuit by

grounding the FAULT pin. Systems that must keep the

fault circuit active should ensure that the output voltage is

never programmed to step down by more than 15% in any

single step. The safest strategy is to step the output down

by 10% or less at a time and wait for the output to settle

to the new value before taking subsequent steps.

LTC1873

V

OUT

R

LOAD

IRFZ44 OR

EQUIVALENT

LOCATE CLOSE

TO THE OUTPUT

PULSE

GENERATOR

50Ω

1873 F17

0V TO 10V

100Hz, 5%

DUTY CYCLE

Figure 17. Transient Load Generator

30

LTC1873

U

PACKAGE DESCRIPTIO

Dimensions in inches (millimeters) unless otherwise noted.

G Package

28-Lead Plastic SSOP (0.209)

(LTC DWG # 05-08-1640)

10.07 – 10.33*

(0.397 – 0.407)

28 27 26 25 24 23 22 21 20 19 18

16 15

17

7.65 – 7.90

(0.301 – 0.311)

5

7

8

1

2

3

4

6

9 10 11 12 13 14

5.20 – 5.38**

(0.205 – 0.212)

1.73 – 1.99

(0.068 – 0.078)

0° – 8°

0.65

(0.0256)

BSC

0.13 – 0.22

0.55 – 0.95

(0.005 – 0.009)

(0.022 – 0.037)

0.05 – 0.21

(0.002 – 0.008)

0.25 – 0.38

(0.010 – 0.015)

NOTE: DIMENSIONS ARE IN MILLIMETERS

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.152mm (0.006") PER SIDE

**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE

G28 SSOP 1098

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

31

LTC1873

U

TYPICAL APPLICATIO

Single Output, 2-Phase, 25A VID Converter

(V_IN= 5V, V_OUT= 1.3V to 3.5V)

V

IN

5V

10Ω

0.1µF

0.003Ω

0.5W

0.003Ω

0.5W

7

10k

–

2

5

+

6

LT^®1218

10k

470µF*

+

3

+

4

0.1µF

470µF*

10µF

+

MBR0530T

470µF*

MBR

0530T

V

PV

CC

SENSE

330pF

11k

BOOST1

FB1

120pF

47k

1µF

1Ω

220pF

L1

1µH

Q1

Q3

COMP1

TG1

V

OUT

SW1

1.3V TO 3.5V

25A

RUN/SS1

RUN/SS2

1Ω

0.1µF

MBR

330T

Q2

BG1

+

470µF*

× 2

LTC1873

BOOST2

TG2

FB2

20k

10k

120pF

47k

220pF

10k

1µF

COMP2

L2

SW2

Q4

Q6

1µH

BG2

I

MAX1

MAX2

FAULT

VID4:2

22k

VID1:0

1Ω

MBR

330T

Q5

VID1:0

FCB

VID4:2

SGND

PGND

1873 TA02

*KEMET T510X477M006AS

Q1 TO Q6: FAIRCHILD FDS6670A

L1, L2: MURATA LQT12535C1R5N12

RELATED PARTS

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2-Phase, 5-Bit VID Synchronous Step-Down Controller

Synchronous Step-Down Controller with 5-Bit VID Control

5-Bit Programmable Synchronous Switching Rregulator

2-Phase, Synchronous High Efficiency Converter

Current Mode, V to 36V, I Up to 42A

IN OUT

Fault Protection, PowerGood, 3.5V to 36V Input, Current Mode

1.3V to 3.5V Programmable Output Using Internal 5-Bit DAC

Current Mode Ensures Accurate Current Sensing,

V

IN

Up to 36V, I Up to 42A

OUT

No R

is a trademark of Linear Technology Corporation.

SENSE

1873f LT/TP 0200 4K • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

32

●

(408)432-1900 FAX:(408)434-0507 www.linear-tech.com

LINEAR TECHNOLOGY CORPORATION 1999


型号：	LTC1873EG#PBF
厂家：	Linear
描述：	LTC1873 - Dual 550kHz Synchronous 2-Phase Switching Regulator Controller with 5-Bit VID; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C 稳压器开关控制器
文件：	总32页 (文件大小：310K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC1873EG#PBF [Linear]

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