LTC1878EMS8#TRPBF [Linear]
LTC1878 - High Efficiency Monolithic Synchronous Step-Down Regulator; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C;
| 型号： | LTC1878EMS8#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC1878 - High Efficiency Monolithic Synchronous Step-Down Regulator; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C 开关 光电二极管 |
| 文件： | 总16页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC1878
High Efficiency
Monolithic Synchronous
Step-Down Regulator
U
DESCRIPTIO
FEATURES
The LTC®1878 is a high efficiency monolithic synchro-
nous buck regulator using a constant frequency, current
mode architecture. Supply current during operation is
only 10µA and drops to < 1µA in shutdown. The 2.65V to
6V input voltage range makes the LTC1878 ideally suited
forsingleLi-Ionbattery-poweredapplications. 100%duty
cycle provides low dropout operation, extending battery
life in portable systems.
■
High Efficiency: Up to 95%
■
Very Low Quiescent Current: Only 10µA
During Operation
■
600mA Output Current at VIN = 3.3V
■
2.65V to 6V Input Voltage Range
■
550kHz Constant Frequency Operation
Synchronizable from 400kHz to 700kHz
Selectable Burst ModeTM Operation or
Pulse Skipping Mode
■
■
Switching frequency is internally set at 550kHz, allowing
the use of small surface mount inductors and capacitors.
For noise sensitive applications the LTC1878 can be
externally synchronized from 400kHz to 700kHz. Burst
Mode operation is inhibited during synchronization or
when the SYNC/MODE pin is pulled low, preventing low
frequency ripple from interfering with audio circuitry.
■
■
■
■
■
■
No Schottky Diode Required
Low Dropout Operation: 100% Duty Cycle
0.8V Reference Allows Low Output Voltages
Shutdown Mode Draws < 1µA Supply Current
±2% Output Voltage Accuracy
Current Mode Control for Excellent Line and
Load Transient Response
Overcurrent and Overtemperature Protected
■
■
The internal synchronous switch increases efficiency and
eliminates the need for an external Schottky diode. Low
output voltages are easily supported with the 0.8V feed-
back reference voltage. The LTC1878 is available in a
space saving 8-lead MSOP package.
Available in 8-LeUad MSOP Package
APPLICATIO S
■
Cellular Telephones
■
Wireless Modems
For higher input voltage (11V abs max) applications, refer
to the LTC1877 data sheet.
■
Personal Information Appliances
■
Portable Instruments
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Distributed Power Systems
Burst Mode is a trademark of Linear Technology Corporation.
■
Battery-Powered Equipment
U
Efficiency vs Output Load Current
TYPICAL APPLICATIO
100
V
= 3.6V
= 4.2V
95
90
85
80
75
70
IN
High Efficiency Step-Down Converter
10µH*
V
†
IN
7
6
1
2
5
V
OUT
V
SYNC
SW
2.65V
TO 6V
IN
3.3V
20pF
887k
22µF**
CER
V
IN
+
LTC1878
47µF***
V
IN
= 6V
RUN
3
I
V
FB
TH
GND
4
280k
220pF
Burst Mode OPERATION
V
= 3.3V
OUT
1878 TA01
L = 10µH
*TOKO D62CB A920CY-100M
0.1
1
10
100
1000
**TAIYO-YUDEN CERAMIC JMK325BJ226MM
***SANYO POSCAP 6TPA47M
OUTPUT CURRENT (mA)
†V
CONNECTED TO V FOR 2.65V < V < 3.3V
1878 TA02
OUT
IN IN
1
LTC1878
W W U W
U W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
Input Supply Voltage (VIN)...........................–0.3V to 7V
ITH, PLL LPF Voltage ................................–0.3V to 2.7V
RUN, VFB Voltages ......................................–0.3V to VIN
SYNC/MODE Voltage ..................................–0.3V to VIN
SW Voltage ................................... –0.3V to (VIN + 0.3V)
P-Channel MOSFET Source Current (DC) ........... 800mA
N-Channel MOSFET Sink Current (DC) ............... 800mA
Peak SW Sink and Source Current ........................ 1.5A
Operating Ambient Temperature Range
(Note 2) .................................................. –40°C to 85°C
Junction Temperature (Note 3)............................ 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
TOP VIEW
RUN 1
8 PLL LPF
7 SYNC/MODE
I
TH
2
3
4
LTC1878EMS8
V
FB
6 V
5
SW
IN
GND
MS8 PACKAGE
8-LEAD PLASTIC MSOP
MS8 PART MARKING
LTNX
TJMAX = 125°C, θJA = 150°C/ W
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C.
A
VIN=3.6Vunlessotherwisespecified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Feedback Current
Regulated Output Voltage
(Note 4)
●
4
30
nA
VFB
V
(Note 4) 0°C ≤ T ≤ 85°C
(Note 4) –40°C ≤ T ≤ 85°C
0.784
0.74
0.8
0.8
0.816
0.84
V
V
FB
A
●
●
A
∆V
∆V
Output Overvoltage Lockout
∆V
= V
– V
FB
20
50
110
0.2
mV
OVL
OVL
OVL
Reference Voltage Line Regulation
Output Voltage Load Regulation
V
= 2.65V to 6V (Note 4)
0.05
%/V
FB
IN
V
Measured in Servo Loop; V = 0.9V to 1.2V
Measured in Servo Loop; V = 1.6V to 1.2V
●
●
0.1
–0.1
0.5
–0.5
%
%
LOADREG
ITH
ITH
V
Input Voltage Range
●
2.65
6
V
IN
I
f
Input DC Bias Current
Pulse Skipping Mode
Burst Mode Operation
Shutdown
(Note 5)
2.65V < V < 6V, V
Q
= 0V, I = 0A
OUT
230
10
0
350
15
1
µA
µA
µA
IN
SYNC/MODE
V
V
= V , I
IN
= 0A
SYNC/MODE
IN OUT
= 0V, V = 6V
RUN
Oscillator Frequency
V
V
= 0.8V
= 0V
495
400
550
80
605
kHz
kHz
OSC
FB
FB
f
I
SYNC Capture Range
700
kHz
SYNC
Phase Detector Output Current
Sinking Capability
Sourcing Capability
PLL LPF
f
f
< f
> f
●
●
3
–3
10
–10
20
–20
µA
µA
PLLIN
PLLIN
OSC
OSC
R
R
R
R
of P-Channel MOSFET
of N-Channel MOSFET
I
I
= 100mA
0.5
0.6
0.7
0.8
Ω
Ω
PFET
DS(ON)
DS(ON)
SW
SW
= –100mA
NFET
2
LTC1878
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are T = 25°C.
A
VIN=3.6Vunlessotherwisespecified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
1.0
MAX
1.25
±1
UNITS
A
I
I
Peak Inductor Current
SW Leakage
V
V
V
= 3.3V, V = 0.7V, Duty Cycle < 35%
0.8
PK
IN
FB
= 0V, V = 0V or 6V, V = 6V
±0.01
1.0
µA
V
LSW
RUN
SW
IN
V
SYNC/MODE Threshold
SYNC/MODE Leakage Current
RUN Threshold
Rising
●
●
0.3
0.3
1.5
±1
SYNC/MODE
SYNC/MODE
I
±0.01
0.7
µA
V
SYNC/MODE
V
V
Rising
RUN
1.5
±1
RUN
I
RUN Input Current
±0.01
µA
RUN
Note 1: Absolute Maximum Ratings are those values beyond which the life
Note 4: The LTC1878 is tested in a feedback loop which servos V to the
FB
of a device may be impaired.
balance point for the error amplifier (V = 1.2V).
ITH
Note 2: The LTC1878E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 3: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formulas:
D
LTC1878EMS8: T = T + (P )(150°C/W)
J
A
D
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Input Voltage
Efficiency vs Output Current
Efficiency vs Output Current
95
90
85
80
75
70
65
60
55
50
100
90
80
70
60
50
40
30
20
10
0
100
95
V
= 3.6V
IN
L = 15µH
L = 10µH
I
= 100mA
= 300mA
LOAD
LOAD
I
= 10mA
LOAD
V
IN
= 4.2V
90
I
85
I
= 1mA
LOAD
V
= 3.6V
IN
80
75
V = 4.2V
IN
I
= 0.1mA
LOAD
70
65
60
PULSE SKIPPING MODE
Burst Mode OPERATION
Burst Mode OPERATION
Burst Mode OPERATION
= 2.5V
L = 10µH
V
V
= 6V
V
OUT
IN
OUT
V
= 1.8V
OUT
= 2.5V
L = 10µH
0.1
1
10
100
1000
3
4
6
0.1
1
10
100
1000
2
7
8
5
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
INPUT VOLTAGE (V)
1878 G03
1878 G02
1878 G01
3
LTC1878
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Reference Voltage
vs Temperature
Oscillator Frequency
vs Temperature
Efficiency vs Output Current
95
0.814
0.809
0.804
0.799
0.794
0.789
0.784
605
595
585
575
565
555
545
535
525
515
505
495
V
= 3.6V
V
= 3.6V
IN
IN
V
= 3V
IN
90
85
V
IN
= 3.6V
V
IN
= 4.2V
80
75
V
= 6V
IN
70
65
V
= 1.8V
OUT
L = 10µH
50
TEMPERATURE (°C)
100 125
0.1
1
10
100
1000
–50 –25
0
25
75
–50 –25
0
25
50
75 100 125
OUTPUT CURRENT (mA)
TEMPERATURE (°C)
1878 G04
1878 G05
1878 G06
Oscillator Frequency
vs Supply Voltage
Output Voltage vs Load Current
RDS(ON) vs Input Voltage
1.83
1.82
605
595
585
575
565
555
545
535
525
515
505
495
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
SYNCHRONOUS
SWITCH
1.81
MAIN
1.80
1.79
SWITCH
PULSE SKIPPING MODE
1.78
1.77
V
= 3.6V
IN
L = 10µH
0
2
4
6
0
100 200 300
400
500
600
700 800 900
0
1
2
3
4
5
6
7
8
8
LOAD CURRENT (mA)
SUPPLY VOLTAGE (V)
INPUT VOLTAGE (V)
1878 G07
1878 G08
1878 G09
DC Supply Current
vs Input Voltage
DC Supply Current
vs Temperature
RDS(ON) vs Temperature
250
200
150
100
50
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
300
250
200
150
100
50
V
OUT
= 1.8V
SYNCHRONOUS SWITCH
MAIN SWITCH
V
IN
= 3.6V
PULSE SKIPPING
MODE
PULSE SKIPPING
MODE
V
= 3V
IN
V
IN
= 5V
Burst Mode
OPERATION
Burst Mode
OPERATION
0
0.3
0
0
1
2
3
4
5
6
7
–50 –25
0
25
50
125
–50 –25
0
25
50
75 100 125
75 100
INPUT VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
1878 G11
1878 G10
1878 G12
4
LTC1878
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Switch Leakage vs Temperature
Switch Leakage vs Input Voltage
Burst Mode Operation
2.5
2.0
1.5
1.0
0.5
0
1.2
1.0
0.8
0.6
0.4
0.2
0
V
= 7V
RUN = 0V
IN
RUN = 0V
SW
SYNCHRONOUS
SWITCH
5V/DIV
V
OUT
50mV/DIV
AC
COUPLED
MAIN
SWITCH
MAIN
SYNCHRONOUS
SWITCH
SWITCH
I
L
200mA/DIV
5
6
–25
0
50
75 100 125
0
1
2
3
4
7
8
–50
25
10µs/DIV
= 22µF
INPUT VOLTAGE (V)
V
V
= 4.2V
C
C
TEMPERATURE (°C)
IN
OUT
IN
= 1.5V
= 47µF
OUT
LOAD
1878 G20
1878 G13
L = 10µH
I
= 50mA
1878 G14
Pulse Skipping Mode Operation
Start-Up from Shutdown
Load Step Response
SW
5V/DIV
RUN
V
OUT
2V/DIV
50mV/DIV
AC
COUPLED
V
OUT
V
OUT
1V/DIV
20mV/DIV
AC
I
L
500mA/DIV
COUPLED
I
L
500mA/DIV
I
L
I
200mA/DIV
TH
1V/DIV
1µs/DIV
40µs/DIV
40µs/DIV
V
V
= 4.2V
C
C
LOAD
= 22µF
V
V
= 3.6V
C
C
LOAD
= 22µF
V
V
= 3.6V
C
= 22µF
IN
OUT
IN
IN
OUT
IN
IN
OUT
IN
= 1.5V
= 47µF
= 1.5V
= 47µF
= 1.5V
C
= 47µF
OUT
OUT
OUT
L = 10µH
I
= 50mA
1878 G15
L = 10µH
I
= 500mA
1878 G16
L = 10µH
I
= 200mA TO 500mA 1878 G17
LOAD
PULSE SKIPPING MODE
Load Step Response
Load Step Response
V
V
OUT
OUT
100mV/DIV
AC
100mV/DIV
AC
COUPLED
COUPLED
I
I
L
L
500mA/DIV
500mA/DIV
I
TH
I
TH
1V/DIV
1V/DIV
40µs/DIV
40µs/DIV
V
V
= 3.6V
C
C
LOAD
= 22µF
V
V
= 3.6V
C
= 22µF
IN
OUT
IN
IN
OUT
IN
= 1.5V
= 47µF
= 1.5V
C
= 47µF
OUT
OUT
L = 10µH
I
= 50mA TO 500mA 1878 G18
L = 10µH
I
= 50mA TO 500mA 1878 G19
LOAD
PULSE SKIPPING MODE
Burst Mode OPERATION
5
LTC1878
U
U
U
PI FU CTIO S
connects to the drains of the internal main and synchro-
nous power MOSFET switches.
RUN (Pin 1): Run Control Input. Forcing this pin below
0.4V shuts down the LTC1878. In shutdown all functions
are disabled drawing <1µA supply current. Forcing this
pin above 1.2V enables the LTC1878. Do not leave RUN
floating.
VIN (Pin 6): Main Supply Pin. Must be closely decoupled
to GND, Pin 4.
SYNC/MODE (Pin 7): External Clock Synchronization and
Mode Select Input. To synchronize with an external clock,
apply a clock with a frequency between 400kHz and
700kHz.ToselectBurstModeoperation,tietoVIN.Ground-
ing this pin selects pulse skipping mode. Do not leave this
pin floating.
ITH (Pin 2): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is from 0.5V
to 1.9V.
V
FB (Pin 3): Feedback Pin. Receives the feedback voltage
from an external resistive divider across the output.
PLL LPF (Pin 8):Outputofthe Phase DetectorandControl
Input of Oscillator. Connect a series RC lowpass network
from this pin to ground if externally synchronized. If
unused, this pin may be left open.
GND (Pin 4): Ground Pin.
SW (Pin 5): Switch Node Connection to Inductor. This pin
U
U
W
FU CTIO AL DIAGRA
V
IN
BURST
DEFEAT
Y = “0” ONLY WHEN X IS A CONSTANT “1”
Y
X
PLL LPF
8
SLOPE
COMP
SYNC/MODE
7
0.8V
VCO
OSC
0.6V
3
–
V
IN
6
FREQ
+
–
+
SHIFT
V
FB
EN
–
+
SLEEP
+
–
V
0.8V
REF
6Ω
+
–
0.55V
I
COMP
EA
BURST
SLEEP
V
IN
Ω
Q
Q
S
V
g
m
= 0.5m
IN
R
SWITCHING
LOGIC
AND
I
TH
2
RS LATCH
V
IN
ANTI-
SHOOT-
THRU
BLANKING
CIRCUIT
RUN
1
SW
5
4
0.8V REF
–
OVDET
+
0.85V
SHUTDOWN
+
–
I
RCMP
GND
1878 BD
6
LTC1878
U
OPERATIO
Main Control Loop
BURSTcomparator trips, causingtheinternalsleeplineto
go high and forces off both power MOSFETs. The ITH pin
is then disconnected from the output of the EA amplifier
and parked a diode voltage above ground.
The LTC1878 uses a constant frequency, current mode
step-down architecture. Both the main (P-channel
MOSFET)andsynchronous(N-channelMOSFET)switches
are internal. During normal operation, the internal top
powerMOSFETisturnedoneachcyclewhentheoscillator
sets the RS latch, and turned off when the current com-
parator, ICOMP, resets the RS latch. The peak inductor
current at which ICOMP resets the RS latch is controlled by
the voltage on the ITH pin, which is the output of error
amplifier EA. The VFB pin, described in the Pin Functions
section, allows EA to receive an output feedback voltage
from an external resistive divider. When the load current
increases, it causes a slight decrease in the feedback
voltage relative to the 0.8V reference, which in turn,
causes the ITH voltage to increase until the average induc-
tor current matches the new load current. While the top
MOSFET is off, the bottom MOSFET is turned on until
eithertheinductorcurrentstartstoreverseasindicatedby
thecurrentreversalcomparatorIRCMP, orthebeginningof
the next clock cycle.
In sleep mode, both power MOSFETs are held off and a
majority of the internal circuitry is partially turned off,
reducing the quiescent current to 10µA. The load current
is now being supplied solely from the output capacitor.
When the output voltage drops, the ITH pin reconnects to
the output of the EA amplifier and the top MOSFET is again
turned on and this process repeats.
Short-Circuit Protection
Whentheoutputisshortedtoground, thefrequencyofthe
oscillator is reduced to about 80kHz, 1/7 the nominal
frequency. This frequency foldback ensures that the
inductor current has ample time to decay, thereby pre-
venting runaway. The oscillator’s frequency will progres-
sively increase to 550kHz (or the synchronized frequency)
when VFB rises above 0.3V.
Frequency Synchronization
Comparator OVDET guards against transient overshoots
>6.25% by turning the main switch off and keeping it off
until the fault is removed.
A phase-locked loop (PLL) is available on the LTC1878 to
allow the internal oscillator to be synchronized to an
external source connected to the SYNC/MODE pin. The
output of the phase detector at the PLL LPF pin operates
over a 0V to 2.4V range corresponding to 400kHz to
700kHz.Whenlocked,thePLLalignstheturn-onofthetop
MOSFET to the rising edge of the synchronizing signal.
Burst Mode Operation
The LTC1878 is capable of Burst Mode operation in which
the internal power MOSFETs operate intermittently based
on load demand. To enable Burst Mode operation, simply
tie the SYNC/MODE pin to VIN or connect it to a logic high
(VSYNC/MODE>1.5V).TodisableBurstModeoperationand
enable PWM pulse skipping mode, connect the SYNC/
MODE pin to GND. In this mode, the efficiency is lower at
light loads, but becomes comparable to Burst Mode
operation when the output load exceeds 50mA. The ad-
vantage of pulse skipping mode is lower output ripple and
less interference to audio circuitry.
When the LTC1878 is clocked by an external source, Burst
Mode operation is disabled; the LTC1878 then operates in
PWM pulse skipping mode. In this mode, when the output
load is very low, current comparator ICOMP may remain
trippedforseveralcyclesandforcethemainswitchtostay
off for the same number of cycles. Increasing the output
load slightly allows constant frequency PWM operation to
resume. This mode exhibits low output ripple as well as
low audio noise and reduced RF interference while provid-
ing reasonable low current efficiency.
When the converter is in Burst Mode operation, the peak
current of the inductor is set to approximately 250mA,
even though the voltage at the ITH pin indicates a lower
value. The voltage at the ITH pin drops when the inductor’s
average current is greater than the load requirement. As
the ITH voltage drops below approximately 0.55V, the
Frequency synchronization is inhibited when the feedback
voltage VFB is below 0.6V. This prevents the external clock
from interfering with the frequency foldback for short-
circuit protection.
7
LTC1878
U
OPERATIO
Dropout Operation
Another important detail to remember is that at low input
supply voltages, the RDS(ON) of the P-channel switch
increases. Therefore, the user should calculate the power
dissipation when the LTC1878 is used at 100% duty cycle
with a low input voltage (see Thermal Considerations in
the Applications Information section).
When the input supply voltage decreases toward the
output voltage, the duty cycle increases toward the maxi-
mum on-time. Further reduction of the supply voltage
forces the main switch to remain on for more than one
cycle until it reaches 100% duty cycle. The output voltage
will then be determined by the input voltage minus the
voltage drop across the internal P-channel MOSFET and
the inductor.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscilla-
tions at high duty cycles. It is accomplished internally by
adding a compensating ramp to the inductor current
signal at duty cycles in excess of 40%. As a result, the
maximuminductorpeakcurrentisreducedfordutycycles
>40%. This is shown in the decrease of the inductor peak
current as a function of duty cycle graph in Figure 2.
Low Supply Operation
The LTC1878 is designed to operate down to an input
supply voltage of 2.65V although the maximum allowable
output current is reduced at this low voltage. Figure 1
shows the reduction in the maximum output current as a
function of input voltage for various output voltages.
1200
1100
L = 10µH
V
IN
= 3.3V
1000
1000
900
800
700
600
V
OUT
= 1.5V
800
600
400
200
0
V
= 3.3V
OUT
V
= 2.5V
OUT
2.5
4.5
5.5
6.5
7.5
3.5
0
20
40
60
80
100
INPUT VOLTAGE (V)
DUTY CYCLE (%)
1878 F01
1878 F02
Figure 1. Maximum Output Current vs Input Voltage
Figure 2. Maximum Inductor Peak Current vs Duty Cycle
W U U
U
APPLICATIO S I FOR ATIO
ThebasicLTC1878applicationcircuitisshownonthefirst
page. External component selection is driven by the load
requirementandbeginswiththeselectionofLfollowedby
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. However, oper-
ating at a higher frequency generally results in lower
efficiencybecauseofincreasedinternalgatechargelosses.
CIN and COUT
.
Inductor Value Calculation
Theinductorvaluehasadirecteffectonripplecurrent.The
The inductor selection will depend on the operating fre-
quency of the LTC1878. The internal nominal frequency is
550kHz, but can be externally synchronized from 400kHz
to 700kHz.
ripple current ∆IL decreases with higher inductance or
frequency and increases with higher VIN or VOUT
.
8
LTC1878
W U U
APPLICATIO S I FOR ATIO
U
New designs for surface mount inductors are available
from Coiltronics, Coilcraft, Dale and Sumida.
VOUT
1
∆IL =
VOUT 1−
(1)
f L
( )( )
V
IN
CIN and COUT Selection
Accepting larger values of ∆IL allows the use of low
inductance, but results in higher output voltage ripple and
greater core losses. A reasonable starting point for setting
ripple current is ∆IL = 0.4(IMAX).
Incontinuousmode,thesourcecurrentofthetopMOSFET
is a square wave of duty cycle VOUT/VIN. To prevent large
voltage transients, a low ESR input capacitor sized for the
maximum RMS current must be used. The maximum
RMS capacitor current is given by:
The inductor value also has an effect on Burst Mode
operation. The transition to low current operation begins
when the inductor current peaks fall to approximately
250mA. Lower inductor values (higher ∆IL) will cause this
to occur at lower load currents, which can cause a dip in
efficiency in the upper range of low current operation. In
Burst Mode operation, lower inductance values will cause
the burst frequency to increase.
1/2
]
V
V − V
OUT
(
)
[
OUT IN
CIN required IRMS IOMAX
V
IN
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is com-
monlyusedfordesignbecauseevensignificantdeviations
donotoffermuchrelief.Notethecapacitormanufacturer’s
ripplecurrentratingsareoftenbasedon2000hoursoflife.
This makes it advisable to further derate the capacitor, or
choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design. Always
consult the manufacturer if there is any question.
Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot
affordthecorelossfoundinlowcostpowderedironcores,
forcing the use of more expensive ferrite, molypermalloy,
or Kool Mµ® cores. Actual core loss is independent of core
size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses will
increase.
The selection of COUT is driven by the required effective
series resistance (ESR). Typically, once the ESR require-
ment is satisfied, the capacitance is adequate for filtering.
The output ripple ∆VOUT is determined by:
Ferrite designs have very low core losses and are pre-
ferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design cur-
rent is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
1
∆VOUT ∆IL ESR +
8fCOUT
where f = operating frequency, COUT = output capacitance
and ∆IL = ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆IL increases
with input voltage. For the LTC1878, the general rule for
proper operation is:
Kool Mµ (from Magnetics, Inc.) is a very good, low loss
corematerialfortoroidswitha“soft”saturationcharacter-
istic. Molypermalloy is slightly more efficient at high
(>200kHz) switching frequencies but quite a bit more
expensive. Toroids are very space efficient, especially
when you can use several layers of wire, while inductors
wound on bobbins are generally easier to surface mount.
COUT required ESR < 0.25Ω
The choice of using a smaller output capacitance
increases the output ripple voltage due to the frequency
dependent term but can be compensated for by using
capacitor(s) of very low ESR to maintain low ripple
voltage. The ITH pin compensation components can be
Kool Mµ is a registered trademark of Magnetics, Inc.
9
LTC1878
W U U
U
APPLICATIO S I FOR ATIO
optimized to provide stable high performance transient
response regardless of the output capacitor selected.
external and internal oscillators. This type of phase detec-
tor will not lock up on input frequencies close to the har-
monicsoftheVCO centerfrequency.ThePLLhold-inrange
∆fH is equal to the capture range, ∆fH = ∆fC = ±150kHz.
ESR is a direct function of the volume of the capacitor.
ManufacturerssuchasTaiyo-Yuden,AVX,Kemet,Sprague
and Sanyo should be considered for high performance
capacitors. The POSCAP solid electrolytic chip capacitor
available from Sanyo is an excellent choice for output bulk
capacitors due to its low ESR/size ratio. Once the ESR
requirement for COUT has been met, the RMS current
rating generally far exceeds the IRIPPLE(P-P) requirement.
The output of the phase detector is a pair of complemen-
tary current sources charging or discharging the external
filter network on the PLL LPF pin. The relationship
between the voltage on the PLL LPF pin and operating
frequencyisshowninFigure4. Asimplifiedblockdiagram
is shown in Figure 5.
When using tantalum capacitors, it is critical that they are
surge tested for use in switching power supplies. A good
choice is the AVX TPS series of surface mount tantalum,
availableincaseheightsrangingfrom2mmto4mm.Other
capacitor types include KEMET T510 and T495 series and
Sprague 593D and 595D series. Consult the manufacturer
for other specific recommendations.
800
700
600
500
400
300
Output Voltage Programming
The output voltage is set by a resistive divider according
to the following formula:
0
0.8
1.2
1.6
2.0
0.4
VPLL LPF (V)
1878 F04
R2
R1
VOUT = 0.8V 1+
(2)
Figure 4. Relationship Between Oscillator
Frequency and Voltage at PLL LPF Pin
The external resistive divider is connected to the output,
allowing remote voltage sensing as shown in Figure 3.
R
LP
2.4V
PHASE
DETECTOR
C
LP
0.8V ≤ V
≤ 6V
OUT
PLL LPF
VCO
R2
SYNC/
MODE
V
FB
DIGITAL
PHASE/
FREQUENCY
DETECTOR
LTC1878
R1
GND
1878 F03
Figure 3. Setting the LTC1878 Output Voltage
Phase-Locked Loop and Frequency Synchronization
1878 F05
The LTC1878 has an internal voltage-controlled oscillator
and phase detector comprising a phase-locked loop. This
allows the top MOSFET turn-on to be locked to the rising
edgeofanexternalfrequencysource.Thefrequencyrange
ofthevoltage-controlledoscillatoris400kHzto700kHz.The
phase detector used is an edge sensitive digital type that
provides zero degrees phase shift between the
Figure 5. Phase-Locked Loop Block Diagram
If the external frequency (VSYNC/MODE) is greater than
550kHz, the center frequency, current is sourced
continuously, pulling up the PLL LPF pin. When the
external frequency is less than 550kHz, current is sunk
continuously, pulling down the PLL LPF pin. If the
10
LTC1878
W U U
APPLICATIO S I FOR ATIO
U
1
externalandinternalfrequenciesarethesamebutexhibit
a phase difference, the current sources turn on for an
amount of time corresponding to the phase difference.
Thus the voltage on the PLL LPF pin is adjusted until the
phase and frequency of the external and internal oscilla-
tors are identical. At this stable operating point the phase
comparator output is high impedance and the filter
capacitor CLP holds the voltage.
V
= 4.2V
IN
L = 10µH
V
OUT
V
OUT
V
OUT
= 1.5V
= 2.5V
= 3.3V
0.1
0.01
Burst Mode OPERATION
0.001
0.0001
0.00001
The loop filter components CLP and RLP smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
component’s CLP and RLP determine how fast the loop
acquires lock. Typically RLP = 10k and CLP is 2200pF to
0.01µF. When not synchronized to an external clock, the
internal connection to the VCO is disconnected. This
disallows setting the internal oscillator frequency by a DC
voltage on the VPLL LPF pin.
0.1
1
10
100
1000
LOAD CURRENT (mA)
1878 F06
Figure 6. Power Lost vs Load Current
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge dQ moves from VIN to ground. The resulting
dQ/dtisthecurrentoutofVINthatistypicallylargerthan
Efficiency Considerations
the DC bias current. In continuous mode, IGATECHG
=
f(QT + QB) where QT and QB are the gate charges of the
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to VIN and thus
their effects will be more pronounced at higher supply
voltages.
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
oftenusefultoanalyzeindividuallossestodeterminewhat
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
2. I2R losses are calculated from the resistances of the
internal switches, RSW, and external inductor RL. In
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET RDS(ON) and the duty cycle
(DC) as follows:
Efficiency = 100% – (L1 + L2 + L3 + ...)
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC1878 circuits: VIN quiescent current and I2R
losses. The VIN quiescent current loss dominates the
efficiency loss at very low load currents whereas the I2R
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence as illustrated in Figure 6.
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
beobtainedfromtheTypicalPerformanceCharateristics
curves. Thus, to obtain I2R losses, simply add RSW to
RL and multiply the result by the square of the average
output current.
1. The VIN quiescent current is due to two components:
the DC bias current as given in the electrical character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
Other losses including CIN and COUT ESR dissipative
losses and inductor core losses generally account for less
than 2% total additional loss.
11
LTC1878
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APPLICATIO S I FOR ATIO
Thermal Considerations
P-channel switch at 70°C is approximately 0.7Ω. There-
fore, power dissipated by the part is:
In most applications the LTC1878 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC1878 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such
as in dropout, the heat dissipated may exceed the maxi-
mum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both power
switches will be turned off and the SW node will become
high impedance.
PD = ILOAD2 • RDS(ON) = 0.175W
For the MSOP package, the θJA is 150°C/W. Thus, the
junction temperature of the regulator is:
TJ = 70°C + (0.175)(150) = 96°C
which is below the maximum junction temperature of
125°C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (RDS(ON)).
To avoid the LTC1878 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to (∆ILOAD • ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT, which generates a feedback error signal.
The regulator loop then acts to return VOUT to its steady-
state value. During this recovery time VOUT can be moni-
tored for overshoot or ringing that would indicate a stabil-
ityproblem.Theinternalcompensationprovidesadequate
compensation for most applications. But if additional
compensation is required, the ITH pin can be used for
external compensation using RC, CC1 as shown in
Figure 7. (The 220pF capacitor, CC2, is typically needed for
noise decoupling.)
TR = (PD)(θJA)
where PD is the power dissipated by the regulator and qJA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, TJ, is given by:
TJ = TA + TR
where TA is the ambient temperature.
As an example, consider the LTC1878 in dropout at an
input voltage of 3V, a load current of 500mA, and an
ambient temperature of 70°C. From the typical perfor-
mance graph of switch resistance, the RDS(ON) of the
C
C2
LTC1878
OPTIONAL
1
2
3
4
8
7
6
5
RUN
PLL LPF
SYNC/MODE
C
C1
R
C
I
TH
BOLD LINES INDICATE
HIGH CURRENT PATHS
V
FB
V
IN
+
L1
GND
SW
R1
R2
+
C
IN
+
V
V
IN
OUT
C
OUT
–
–
1878 F07
Figure 7. LTC1878 Layout Diagram
12
LTC1878
W U U
APPLICATIO S I FOR ATIO
U
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with COUT, causing a rapid drop in VOUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 • CLOAD).
Thus, a 10µF capacitor charging to 3.3V would require a
250µs rise time, limiting the charging current to about
130mA.
Design Example
As a design example, assume the LTC1878 is used in a
singlelithium-ionbattery-poweredcellularphoneapplica-
tion. The input voltage will be operating from a maximum
of 4.2V down to about 2.7V. The load current requirement
is a maximum of 0.3A but most of the time it will be in
standby mode, requiring only 2mA. Efficiency at both low
and high load currents is important. Output voltage is
2.5V. With this information we can calculate L using
equation (1),
1
f ∆I
VOUT
L =
VOUT 1−
PC Board Layout Checklist
(3)
V
( )(
)
L
IN
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1878. These items are also illustrated graphically in
the layout diagram of Figure 7. Check the following in your
layout:
Substituting VOUT = 2.5V, VIN = 4.2V, ∆IL=120mA and
f = 550kHz in equation (3) gives:
2.5V
2.5V
4.2V
L =
1−
= 15.3µH
550kHz(120mA)
1. Are the signal and power grounds segregated? The
LTC1878 signal ground consists of the resistive
divider, the optional compensation network (RC and
CC1) and CC2. The power ground consists of the (–)
plate of CIN, the (–) plate of COUT and Pin 4 of the
LTC1878. The power ground traces should be kept
short, direct and wide. The signal ground and power
ground should converge to a common node in a star-
ground configuration.
A 15µH inductor works well for this application. For best
efficiency choose a 1A inductor with less than 0.25Ω
series resistance.
CIN will require an RMS current rating of at least 0.15A at
temperature and COUT will require an ESR of less than
0.25Ω. In most applications, the requirements for these
capacitors are fairly similar.
2. Does the VFB pin connect directly to the feedback
resistors? The resistive divider R1/R2 must be con-
nected between the (+) plate of COUT and signal ground.
For the feedback resistors, choose R1 = 412k. R2 can
then be calculated from equation (2) to be:
VOUT
0.8
3. Does the (+) plate of CIN connect to VIN as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
R2 =
−1 R1= 875.5k; use 887k
Figure 8 shows the complete circuit along with its effi-
ciency curve.
4. Keep the switching node SW away from sensitive small
signal nodes.
13
LTC1878
W U U
U
APPLICATIO S I FOR ATIO
95
90
85
80
75
70
V
= 3V
IN
V
IN
2.65V
V
IN
= 3.6V
TO 4.2V
LTC1878
22µF**
1
2
3
4
8
7
6
5
220pF
CER
RUN
PLL LPF
V
= 4.2V
IN
I
SYNC/MODE
TH
V
FB
V
IN
15µH*
V
2.5V
OUT
GND
SW
+
47µF***
V
= 2.5V
OUT
L = 15µH
887k
20pF
1878 F08a
0.1
1
10
100
1000
*SUMIDA CD54-150
**TAIYO-YUDEN CERAMIC JMK325BJ226MM
***SANYO POSCAP 6TPA47M
412k
OUTPUT CURRENT (mA)
1878 F08b
Figure 8. Single Lithium-Ion to 2.5V/0.3A Regulator from Design Example
U
TYPICAL APPLICATIO S
Single Li-Ion to 2.5V/0.6A Regulator
Using All Ceramic Capacitors
LTC1878
PLL LPF
1
2
3
4
8
RUN
7
6
5
I
SYNC/MODE
TH
220pF
V
IN
V
FB
V
IN
3V TO 4.2V
10µH*
C
**
V
2.5V
0.6A
IN
OUT
GND
SW
22µF
CER
C
**
OUT
20pF
887k
22µF
CER
*TOKO D62CB A920CY-100M
**TAIYO-YUDEN CERAMIC JMK325BJ226MM
412k
1878 TA03
3- to 4-Cell NiCd/NiMH to 1.8V/0.5A Regulator
Using All Ceramic Capacitors
LTC1878
1
2
3
4
8
7
6
5
RUN
PLL LPF
I
TH
SYNC/MODE
220pF
V
IN
V
V
IN
FB
2.7V TO 6V
10µH*
V
1.8V
0.5A
C
**
OUT
IN
GND
SW
22µF
C
**
OUT
CER
887k
22µF
20pF
CER
*TOKO D62CB A920CY-100M
**TAIYO-YUDEN CERAMIC JMK325BJ226MM
698k
1878 TA04
14
LTC1878
U
TYPICAL APPLICATIO S
Externally Synchronized 2.5V/0.6A Regulator
Using All Ceramic Capacitors
LTC1878
0.01µF
10k
1
2
3
4
8
7
6
5
RUN
PLL LPF
SYNC/MODE
EXT CLOCK
700kHz
I
TH
220pF
V
IN
V
V
IN
FB
3V TO 6V
10µH*
V
2.5V
0.6A
C
**
OUT
IN
GND
SW
22µF
C
**
OUT
CER
20pF
22µF
887k
CER
*TOKO D62CB A920CY-100M
**TAIYO-YUDEN CERAMIC JMK325BJ226MM
412k
1878 TA04
Low Noise 2.5V/0.3A Regulator
LTC1878
1
2
3
4
8
7
6
5
RUN
PLL LPF
SYNC/MODE
I
TH
220pF
V
IN
V
FB
V
IN
2.65V TO 6V
15µH*
V
2.5V
0.3A
C
**
OUT
IN
GND
SW
22µF
+
C
***
OUT
CER
887k
47µF
20pF
6.3V
412k
*SUMIDA CD54-150
**TAIYO-YUDEN CERAMIC JMK325BJ226MM
***SANYO POSCAP CTPA47M
1878 TA06
3- to 4-Cell NiCd/NiMH to 3.3V/0.5A Regulator
Using All Ceramic Capacitors
LTC1878
1
2
3
4
8
RUN
PLL LPF
7
6
5
I
SYNC/MODE
TH
220pF
V
IN
V
FB
V
IN
†
2.7V TO 6V
10µH*
V
3.3V
0.5A
C
**
OUT
IN
GND
SW
22µF
C
**
CER
OUT
20pF
887k
22µF
CER
*TOKO D62CB A920CY-100M
**TAIYO-YUDEN CERAMIC JMK325BJ226MM
†V
CONNECTED TO V FOR 2.7V < V < 3.3V
280k
OUT
IN
IN
1878 TA06
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LTC1878
U
TYPICAL APPLICATIO
Single Li-Ion to 2.5V/0.5A Regulator with Precision 2.7V Undervoltage Lockout
0.1µF
10k
LTC1540
LTC1878
1.58M
1%
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
GND
OUT
RUN
PLL LPF
SYNC/MODE
–
+
V
V
I
TH
220pF
0.01µF
V
+
–
IN
2.7V TO 4.2V
IN
IN
REF
V
FB
V
IN
10µH*
V
2.5V
0.6A
44.2k
1%
C
**
OUT
IN
1.18M
1%
HYS
GND
SW
22µF
C
**
OUT
CER
20pF
887k
22µF
2.37M
1%
CER
412k
*TOKO D62CB A920CY-100M
**TAIYO-YUDEN CERAMIC JMK325BJ226MM
1878 TA08
U
PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 ± 0.004*
(3.00 ± 0.102)
8
7
6
5
0.040 ± 0.006
(1.02 ± 0.15)
0.034 ± 0.004
(0.86 ± 0.102)
0.007
(0.18)
0° – 6° TYP
0.118 ± 0.004**
(3.00 ± 0.102)
SEATING
PLANE
0.193 ± 0.006
(4.90 ± 0.15)
0.012
(0.30)
REF
0.021 ± 0.006
(0.53 ± 0.015)
0.006 ± 0.004
(0.15 ± 0.102)
0.0256
(0.65)
BSC
MSOP (MS8) 1098
1
2
3
4
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
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from 2.65V to 8.5V
LTC1772
LTC1877
Low Input Voltage Current Mode Step-Down DC/DC Controller
High Efficiency Monolithic Step-Down Regulator
550kHz, 6-Pin SOT-23, I
Up to 5A, V from 2.2V to 10V
OUT IN
550kHz, MS8, V Up to 10V, I = 10µA, I to 600mA
OUT
IN
Q
1878f LT/TP 1000 4K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
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(408)432-1900 FAX:(408)434-0507 www.linear-tech.com
LINEAR TECHNOLOGY CORPORATION 2000
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