LTC2308IUF#TRPBF_技术文档

LTC2308

Low Noise, 500ksps,

8-Channel, 12-Bit ADC

FEATURES

DESCRIPTION

The LTC^®2308 is a low noise, 500ksps, 8-channel, 12-bit

ADC with an SPI/MICROWIRE compatible serial interface.

This ADC includes an internal reference and a fully differ-

ential sample-and-hold circuit to reduce common mode

noise. The internal conversion clock allows the external

serial output data clock (SCK) to operate at any frequency

up to 40MHz.

n

12-Bit Resolution

n

500ksps Sampling Rate

n

Low Noise: SINAD = 73.3dB

n

Guaranteed No Missing Codes

n

Single 5V Supply

n

Auto-Shutdown Scales Supply Current with Sample

Rate

n

Low Power: 17.5mW at 500ksps

The LTC2308 operates from a single 5V supply and draws

just3.5mAatasamplerateof500ksps.Theauto-shutdown

feature reduces the supply current to 200µA at a sample

rate of 1ksps.

0.9mW Nap Mode

35µW Sleep Mode

n

Internal Reference

n

Internal 8-Channel Multiplexer

n

The LTC2308 is packaged in a small 24-pin 4mm × 4mm

QFN.Theinternal2.5Vreferenceand8-channelmultiplexer

further reduce PCB board space requirements.

Internal Conversion Clock

SPI/MICROWIRE^TMCompatible Serial Interface

Unipolar or Bipolar Input Ranges (Software Selectable)

Separate Output Supply OV (2.7V to 5.25V)

24-Pin 4mm × 4mm QFN Package

DD

The low power consumption and small size make the

LTC2308 ideal for battery operated and portable appli-

cations, while the 4-wire SPI compatible serial interface

makes this ADC a good match for isolated or remote data

acquisition systems.

APPLICATIONS

n

High Speed Data Acquisition

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

n

Industrial Process Control

n

Motor Control

n

Accelerometer Measurements

n

Battery Operated Instruments

n

Isolated and/or Remote Data Acquisition

TYPICAL APPLICATION

5V

8192 Point FFT, f_IN= 1kHz

0.1µF

10µF

0.1µF

0

–10

–20

f

= 500kHz

SMPL

OV

DD

2.7V TO 5.25 V

AV

DV

DD

SINAD = 73.6dB

THD = –89.5dB

DD

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

0.1µF

LTC2308

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–140

SDI

ANALOG

INPUT

MUX

12-ꢀIT

500ksps

ADC

+

–

SERIAL DATA LINK TO

ASIC, PLD, MPU, DSP

OR SHIFT REGISTER

SDO

SCK

SERIAL

PORT

CH0-CH7

ANALOG INPUTS

0V TO 4.096V UNIPOLAR

2.048V ꢀIPOLAR

CONVST

V

REF

INTERNAL

2.5V REF

2.2µF

0

50

100

150

200

250

FREQUENCY (kHz)

REFCOMP

10µF

2308 TA01b

GND

0.1µF

2308 TA01

2308fc

1

For more information www.linear.com/LTC2308

LTC2308

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Notes 1, 2)

TOP VIEW

Supply Voltage (AV , DV , OV )...........................6V

DD

Analog Input Voltage (Note 3)

24 23 22 21 20 19

CH0-CH7, COM, REF,

CH3

CH4

CH5

CH6

CH7

COM

1

2

3

4

5

6

18 GND

REFCOMP...................(GND – 0.3V) to (AV + 0.3V)

DD

SD0

SCK

17

16

Digital Input Voltage

25

(Note 3).......................... (GND – 0.3V) to (DV + 0.3V)

DD

15 SDI

Digital Output Voltage.... (GND – 0.3V) to (OV + 0.3V)

DD

14

CONVST

Power Dissipation.............................................. 500mW

13 AV

DD

Operating Temperature Range

7

8

9 10 11 12

LTC2308C................................................ 0°C to 70°C

LTC2308I .............................................–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

UF PACKAGE

24-LEAD (4mm × 4mm) PLASTIC QFN

= 150°C, θ = 37°C/W

T

JMAX

JA

EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB

http://www.linear.com/product/LTC2308#orderinfo

ORDER INFORMATION

LEAD FREE FINISH

LTC2308CUF#PBF

LTC2308IUF#PBF

TAPE AND REEL

PART MARKING*

2308

PACKAGE DESCRIPTION

TEMPERATURE RANGE

LTC2308CUF#TRPBF

LTC2308IUF#TRPBF

0°C to 70°C

24-Lead (4mm × 4mm) Plastic QFN

2308

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

CONVERTER AND MULTIPLEXER CHARACTERISTICS ^Thel denotes the specifications

which apply over the full operating temperature range, otherwise specifications are at T_A= 25°C. (Notes 4, 5)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Bits

l

Resolution (No Missing Codes)

Integral Linearity Error

Differential Linearity Error

Bipolar Zero Error

12

(Note 6)

0.3

0.25

1

6

LSB

(Note 7)

LSB

Bipolar Zero Error Drift

Bipolar Zero Error Match

Unipolar Zero Error

0.002

0.3

LSB/°C

LSB

l

3

(Note 7)

0.5

LSB

Unipolar Zero Error Drift

Unipolar Zero Error Match

0.002

0.3

LSB/°C

LSB

l

2

2308fc

2

For more information www.linear.com/LTC2308

LTC2308

CONVERTER AND MULTIPLEXER CHARACTERISTICS ^Thel denotes the specifications

which apply over the full operating temperature range, otherwise specifications are at T_A= 25°C. (Notes 4, 5)

PARAMETER

CONDITIONS

MIN

TYP

1

MAX

UNITS

LSB

l

Bipolar Full-Scale Error

External Reference (Note 8)

External Reference

9

Bipolar Full-Scale Error Drift

Bipolar Full-Scale Error Match

Unipolar Full-Scale Error

Unipolar Full-Scale Error Drift

Unipolar Full-Scale Error Match

0.05

0.5

1.5

0.05

0.4

LSB/°C

LSB

l

3

8

External Reference (Note 8)

External Reference

LSB

LSB/°C

LSB

l

3

ANALOG INPUT ^Thel denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T_A= 25°C. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

l

V

Absolute Input Range (CH0 to CH7)

(Note 9)

–0.05

REFCOMP

V

IN

–

l

Absolute Input Range (CH0 to CH7,

COM)

Unipolar (Note 9)

Bipolar (Note 9)

–0.05

0.25 • REFCOMP

0.75 • REFCOMP

V

+

–

+

–

l

V

– V

Input Differential Voltage Range

V

IN

V

IN

= V – V (Unipolar)

0 to REFCOMP

REFCOMP/2

V

IN

= V – V (Bipolar)

IN

l

I

Analog Input Leakage Current

Analog Input Capacitance

1

µA

IN

C

Sample Mode

Hold Mode

55

5

pF

CMRR

Input Common Mode Rejection Ratio

70

dB

DYNAMIC ACCURACY ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C and A_IN= –1dBFS. (Notes 4, 10)

SYMBOL

SINAD

SNR

PARAMETER

CONDITIONS

MIN

71

TYP

73.3

73.4

–90

90

MAX

UNITS

dB

l

Signal-to-(Noise + Distortion) Ratio

Signal-to-Noise Ratio

f

IN

f

IN

f

IN

f

IN

f

IN

= 1kHz

71

dB

THD

Total Harmonic Distortion

Spurious Free Dynamic Range

Channel-to-Channel Isolation

Full Linear Bandwidth

= 1kHz, First 5 Harmonics

–78

dB

SFDR

= 1kHz

80

dB

–109

700

25

dB

(Note 11)

kHz

MHz

ns

–3dB Input Linear Bandwidth

Aperture Delay

13

Transient Reponse

Full-Scale Step

240

ns

2308fc

3

For more information www.linear.com/LTC2308

LTC2308

INTERNAL REFERENCE CHARACTERISTICS ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C. (Note 4)

PARAMETER

CONDITIONS

MIN

TYP

2.50

25

MAX

UNITS

V

l

V

Output Voltage

Output Tempco

Output Impedance

I

= 0

2.47

2.53

REF

OUT

ppm/°C

kW

REF

–0.1mA ≤ I

≤ 0.1mA

OUT

8

REF

Output Voltage

I

= 0

4.096

0.8

V

REFCOMP

OUT

Line Regulation

AV = 4.75V to 5.25V

DD

mV/V

REF

DIGITAL INPUTS AND DIGITAL OUTPUTS ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

DV = 5.25V

MIN

TYP

MAX

UNITS

l

V

IH

V

IL

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Digital Input Capacitance

High Level Output Voltage

2.4

V

DD

DV = 4.75V

DD

0.8

10

I

IN

V

IN

= V

DD

µA

pF

C

V

5

IN

OV = 4.75V, I

= –10µA

= –200µA

4.74

V

OH

DD

OUT

l

OV = 4.75V, I

4

DD

V

Low Level Input Voltage

OV = 4.75V, I

DD

= 160µA

= 1.6mA

0.05

V

OL

DD

OUT

l

OV = 4.75V, I

0.4

10

I

OZ

Hi-Z Output Leakage

Hi-Z Output Capacitance

Output Source Current

Output Sink Current

V

OUT

= 0V to OV , CONVST High

µA

pF

DD

C

OZ

CONVST High

15

–10

10

I

V

OUT

V

OUT

= 0V

= OV

mA

SOURCE

SINK

DD

POWER REQUIREMENTS ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 4)

SYMBOL

AV

PARAMETER

CONDITIONS

MIN

4.75

2.7

TYP

5

MAX

5.25

UNITS

Analog Supply Voltage

Digital Supply Voltage

Output Driver Supply Voltage

V

DD

DV

DD

OV

DD

5

l

I

Supply Current

Nap Mode

Sleep Mode

C = 25pF

3.5

180

7

4.2

400

20

mA

µA

DD

L

CONVST = 5V, Conversion Done

P

D

Power Dissipation

Nap Mode

Sleep Mode

17.5

0.9

35

mW

µW

2308fc

4

For more information www.linear.com/LTC2308

LTC2308

TIMING CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

500

40

UNITS

kHz

MHz

ns

l

f

t

Maximum Sampling Frequency

Shift Clock Frequency

CONVST High Time

SMPL(MAX)

SCK

(Note 9)

20

2.5

0

WHCONV

HD

ns

Hold Time SDI After SCK↑

Setup Time SDI Valid Before SCK↑

SCK High Time

ns

SUDI

f

= f

10

410

20

ns

WHCLK

WLCLK

WLCONVST

HCONVST

CONV

ACQ

SCK

SCK(MAX)

SCK Low Time

ns

SCK

CONVST Low Time During Data Transfer

Hold Time CONVST Low After Last SCK↓

Conversion Time

(Note 9)

ns

1.3

1.6

µs

Acquisition Time

240

4

ns

7th SCK↑ to CONVST↑ (Note 9)

REFCOMP Wakeup Time (Note 12)

SDO Data Valid After SCK↓

SDO Hold Time After SCK↓

SDO Valid After CONVST↓

Bus Relinquish Time

C

= 10µF, C = 2.2µF

200

ms

ns

REFWAKE

dDO

REFCOMP

REF

l

C = 25pF (Note 9)

L

10.8

12.5

C = 25pF

L

ns

hDO

C = 25pF

L

11

4

15

ns

en

C = 25pF

L

ns

dis

SDO Rise Time

C = 25pF

L

ns

r

SDO Fall Time

C = 25pF

L

4

ns

f

Total Cycle Time

2

µs

CYC

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB

when the output code flickers between 0000 0000 0000 and 1111 1111

1111. Unipolar zero error is the offset voltage measured from +0.5LSB

when the output code flickers between 0000 0000 0000 and

0000 0000 0001.

Note 2: All voltage values are with respect to ground with AV , DV and

DD

OV wired together (unless otherwise noted).

Note 3: When these pin voltages are taken below ground or above V

they will be clamped by internal diodes. These products can handle input

currents greater than 100mA below ground or above V without latchup.

Note 8: Full-scale bipolar error is the worst-case of –FS or +FS untrimmed

deviation from ideal first and last code transitions and includes the effect

of offset error. Unipolar full-scale error is the deviation of the last code

transition from ideal and includes the effect of offset error.

DD

,

DD

Note 9: Guaranteed by design, not subject to test.

Note 4: AV = 5V, DV = 5V, OV = 5V, f = 500kHz, internal

DD

SMPL

reference unless otherwise specified.

Note 5: Linearity, offset and full-scale specifications apply for a single-

Note 10: All specifications in dB are referred to a full-scale 2.048V input

with a 2.5V reference voltage.

ended analog input with respect to COM.

Note 11: Full linear bandwidth is defined as the full-scale input frequency

at which the SINAD degrades to 60dB or 10 bits of accuracy.

Note 12: REFCOMP wakeup time is the time required for the REFCOMP pin

to settle within 0.5LSB at 12-bit resolution of its final value after waking up

from SLEEP mode.

Note 6: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

2308fc

5

For more information www.linear.com/LTC2308

LTC2308

T_A= 25°C, AV_DD= DV_DD= OV_DD= 5V,

1kHz Sine Wave

TYPICAL PERFORMANCE CHARACTERISTICS

f_SMPL= 500ksps, Internal Reference, unless otherwise noted.

Integral Nonlinearity vs

Output Code

Differential Nonlinearity vs

Output Code

8192 Point FFT Plot

1.00

0.75

0.50

0.25

0

–10

–20

–30

–40

–50

–60

–70

1.00

0.75

0.50

0.25

0

SNR = 73.7dB

SINAD = 73.6dB

THD = –89.5dB

–80

–90

–0.25

–0.50

–0.75

–1.00

–0.25

–0.50

–0.75

–1.00

–100

–110

–120

–130

–140

2048

0

1024

3072

4096

200

250

2048

0

50

100

150

0

1024

3072

4096

OUTPUT CODE

FREQUENCY (kHz)

OUTPUT CODE

2308 G01

2308 G03

2308 G02

Crosstalk vs Frequency for

an Adjacent Pair

SNR vs Input Frequency

SINAD vs Input Frequency

–60

–70

80

75

70

65

60

55

50

80

75

70

65

60

55

50

–80

–90

–100

–110

–120

–130

–140

0.1

1

10

100

1000

1

10

100

1000

1

10

100

1000

FREQUENCY (kHz)

3208 G04

3208 G05

3208 G06

Supply Current vs

Sampling Frequency

THD vs Input Frequency

Supply Current vs Temperature

5

4

3

2

1

0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

–60

–65

–70

–75

–80

–85

–90

–95

–100

1

10

100

1000

50

TEMPERATURE (°C)

125

–50 –25

0

25

75 100

1

10

100

1000

SAMPLING FREQUENCY (ksps)

FREQUENCY (kHz)

3208 G08

3208 G07

3208 G09

2308fc

6

For more information www.linear.com/LTC2308

LTC2308

T_A= 25°C, AV_DD= DV_DD= OV_DD= 5V,

TYPICAL PERFORMANCE CHARACTERISTICS

f_SMPL= 500ksps, Internal Reference, unless otherwise noted.

Analog Input Leakage Current vs

Temperature

Sleep Current vs Temperature

10

8

1000

f

= 0ksps

SMPL

800

600

400

200

0

6

CH (ON)

4

CH (OFF)

2

0

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

TEMPERATURE (°C)

3208 G10

3208 G11

Offset vs Temperature

Full-Scale Error vs Temperature

1.5

1.0

0.5

0

4

2

BIPOLAR

0

UNIPOLAR

–2

–4

–6

EXTERNAL REFERENCE

50 75 100 125

TEMPERATURE (°C)

EXTERNAL REFERENCE

–50 –25

0

25

50

75 100 125

–50 –25

0

25

TEMPERATURE (°C)

2308 G12

2308 G13

2308fc

7

For more information www.linear.com/LTC2308

LTC2308

PIN FUNCTIONS

CH3-CH7 (Pins 1, 2, 3, 4, 5): Channel 3 to Channel 7

Analog Inputs. CH3-CH7 can be configured as single-

ended or differential input channels. See the Analog Input

Multiplexer section.

SDI (Pin 15): Serial Data Input. The SDI serial bit stream

configures the ADC and is latched on the rising edge of

the first 6 SCK pulses.

SCK (Pin 16): Serial Data Clock. SCK synchronizes the

serial data transfer. The serial data input at SDI is latched

on the rising edge of SCK. The serial data output at SDO

transitions on the falling edge of SCK.

COM (Pin 6): Common Input. This is the reference point

for all single-ended inputs. It must be free of noise and

connectedtogroundforunipolarconversionsandmidway

between GND and REFCOMP for bipolar conversions.

SDO (Pin 17): Serial Data Out. SDO outputs the data from

the previous conversion. SDO is shifted out serially on the

falling edge of each SCK pulse.

V

REF

(Pin 7): 2.5V Reference Output. Bypass to GND with

a minimum 2.2µF tantalum capacitor or low ESR ceramic

capacitor. The internal reference may be over driven by an

external 2.5V reference at this pin.

OV (Pin 19): Output Driver Supply. Bypass OV to

DD

GND with a 0.1µF ceramic capacitor close to the pin. The

REFCOMP (Pin 8): Reference Buffer Output. Bypass to

GND with a 10µF tantalum and 0.1µF ceramic capacitor

in parallel. Nominal output voltage is 4.096V. The internal

reference buffer driving this pin is disabled by grounding

range of OV is 2.7V to 5.25V.

DD

DV (Pin 21): 5V Digital Supply. The range of DV is

DD

4.75Vto5.25V.BypassDV toGNDwitha0.1µFceramic

DD

and a 10µF tantalum capacitor in parallel.

V

, allowing REFCOMP to be overdriven by an external

REF

CH0-CH2 (Pins 22, 23, 24): Channel 0 to Channel 2

Analog Inputs. CH0-CH2 can be configured as single-

ended or differential input channels. See the Analog Input

Multiplexer section.

source (see Figure 6c).

GND (Pins 9, 10, 11, 18, 20): Ground. All GND pins must

be connected to a solid ground plane.

AV (Pins12,13):5VAnalogSupply.TherangeofAV is

DD

GND (Pin 25): Exposed Pad Ground. Must be soldered

directly to ground plane.

4.75V to 5.25V. Bypass AV to GND with a 0.1µF ceramic

DD

and a 10µF tantalum capacitor in parallel.

CONVST (Pin 14): Conversion Start. A rising edge at

CONVSTbeginsaconversion.Forbestperformance,ensure

that CONVST returns low within 40ns after the conversion

starts or after the conversion ends.

2308fc

8

For more information www.linear.com/LTC2308

LTC2308

BLOCK DIAGRAM

AV

DV

DD

OV

DD

LTC2308

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

SDI

ANALOG

INPUT

MUX

12-BIT

500ksps

ADC

+

–

SDO

SERIAL

PORT

SCK

CONVST

V

REF

8k

INTERNAL

2.5V REF

GAIN = 1.6384x

REFCOMP

2308 BD

GND

TEST CIRCUIT

Load Circuit for t_disWAVEFORM 1

Load Circuit for t_disWAVEFORM 2, t_en

V

DD

3k

SDO

TEST POINT

SDO

TEST POINT

C

3k

L

C

L

2308 TC02

2308 TC01

2308fc

9

For more information www.linear.com/LTC2308

LTC2308

TIMING DIAGRAM

Voltage Waveforms for SDO Delay Times, t_dDOand t_hDO

t_WLCLK(SCK Low Time)

t_WHCLK(SCK High Time)

t_HD(Hold Time SDI After SCK↑)

t_SUDI(Setup Time SDI Stable Before SCK↑)

SCK

V

IL

t

dDO

t

WHCLK

WLCLK

t

hDO

V

OH

OL

SCK

SDI

SDO

t

HD

2308 TD01

2308 TD03

t

SUDI

Voltage Waveforms for t_dis

Voltage Waveforms for t_en

V

CONVST

IH

CONVST

SDO

WAVEFORM 1

(SEE NOTE 1)

90%

2308 TD04

t

dis

SDO

WAVEFORM 2

(SEE NOTE 2)

t

en

10%

NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH

THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL

NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH

THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL

Voltage Waveforms for SDO Rise and Fall Times t_r, t_f

2308 TD02

V

OH

SDO

V

OL

t

2308 TD05

r

f

2308fc

10

For more information www.linear.com/LTC2308

LTC2308

APPLICATIONS INFORMATION

Overview

S/D

O/S

S1

S0

UNI

SLP

The LTC2308 is a low noise, 500ksps, 8-channel, 12-bit

successive approximation register (SAR) A/D converter.

The LTC2308 includes a precision internal reference, a

configurable 8-channel analog input multiplexer (MUX)

and an SPI-compatible serial port for easy data transfers.

The ADC may be configured to accept single-ended or

differential signals and can operate in either unipolar or

bipolar mode. A sleep mode option is also provided to

save power during inactive periods.

S/D = SINGLE-ENDED/DIFFERENTIAL BIT

O/S = ODD/SIGN BIT

S1 = ADDRESS SELECT BIT 1

S0 = ADDRESS SELECT BIT 0

UNI = UNIPOLAR/BIPOLAR BIT

SLP = SLEEP MODE BIT

Conversions are initiated by a rising edge on the CONVST

input. Once a conversion cycle has begun, it cannot be

Analog Input Multiplexer

The analog input MUX is programmed by the S/D, O/S,

restarted. Between conversions, a 6-bit input word (D )

IN

S1 and S0 bits of the D word. Table 1 lists the MUX

IN

at the SDI input configures the MUX and programs vari-

configurations for all combinations of the configuration

bits.Figure1ashowsseveralpossibleMUXconfigurations

and Figure 1b shows how the MUX can be reconfigured

from one conversion to the next.

ous modes of operation. As the D bits are shifted in,

IN

data from the previous conversion is shifted out on SDO.

After the 6 bits of the D word have been shifted in, the

IN

ADC begins acquiring the analog input in preparation for

the next conversion as the rest of the data is shifted out.

The acquire phase requires a minimum time of 240ns

for the sample-and-hold capacitors to acquire the analog

input signal.

Table 1. Channel Configuration

S/D O/S S1 S0

0

1

2

3

4

5

6

+

–

+

7

–

+

COM

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

+

–

+

–

During the conversion, the internal 12-bit capacitive

charge-redistribution DAC output is sequenced through a

successive approximation algorithm by the SAR starting

from the most significant bit (MSB) to the least significant

bit (LSB). The sampled input is successively compared

with binary weighted charges supplied by the capacitive

DACusingadifferentialcomparator.Attheendofaconver-

sion, the DAC output balances the analog input. The SAR

contents (a 12-bit data word) that represent the sampled

analog input are loaded into 12 output latches that allow

the data to be shifted out.

+

–

+

–

+

–

+

–

+

Programming the LTC2308

+

The various modes of operation of the LTC2308 are

programmed by a 6-bit D word. The SDI data bits are

+

IN

loaded on the rising edge of SCK, with the S/D bit loaded

on the first rising edge and the SLP bit on the sixth rising

edge (see Figure 8 in the Timing and Control section). The

input data word is defined as follows:

2308fc

11

For more information www.linear.com/LTC2308

LTC2308

APPLICATIONS INFORMATION

4 Differential

8 Single-Ended

Unipolar Mode

Bipolar Mode

CH0

CH1

+ (

)

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

+

–

+

{

(

–

+ ⁽

)

CH2

CH3

–

+

(

–

+ (

)

CH4

CH5

–

+

(

–

COM

CH6

CH7

+

+ (

)

–

+

REFCOMP/2

–

2308 F02

(

COM (

)

–

Figure 2. Driving COM in UNIPOLAR and BIPOLAR Modes

Combinations of Differential

and Single-Ended

mode. In conversion mode, the analog inputs draw only

a small leakage current. If the source impedance of the

drivingcircuitislow, theADCinputscanbedrivendirectly.

Otherwise, more acquisition time should be allowed for a

source with higher impedance.

CH0

+

{

CH1

–

CH2

CH3

–

{

+

CH4

CH5

CH6

CH7

Input Filtering

COM (

)

–

The noise and distortion of the input amplifier and other

circuitrymustbeconsideredsincetheywilladdtotheADC

noiseanddistortion.Therefore,noisyinputcircuitryshould

be filtered prior to the analog inputs to minimize noise. A

simple 1-pole RC filter is sufficient for many applications.

2308 F01a

Figure 1a. Example MUX Configurations

1st Conversion

2nd Conversion

The analog inputs of the LTC2308 can be modeled as

+

CH2

CH3

–

+

CH2

CH3

{

–

a 55pF capacitor (C ) in series with a 100W resistor

IN

+

–

CH4

CH5

+

CH4

CH5

(R ) as shown in Figure 3a. C gets switched to the

ON

IN

selected input once during each conversion. Large filter

RC time constants will slow the settling of the inputs. It

is important that the overall RC time constants be short

enough to allow the analog inputs to completely settle to

COM

(UNUSED)

COM (

)

–

2308 F01b

Figure 1b. Changing the MUX Assignment “On the Fly”

12-bit resolution within the acquisition time (t ) if DC

ACQ

Driving the Analog Inputs

accuracy is important.

The analog inputs of the LTC2308 are easy to drive. Each

of the analog inputs can be used as a single-ended input

relative to the COM pin (CH0-COM, CH1-COM, etc.) or in

differential input pairs (CH0 and CH1, CH2 and CH3, CH4

andCH5, CH6andCH7). Figure2showshowtodriveCOM

for single-ended inputs in unipolar and bipolar modes.

Regardless of the MUX configuration, the “+” and “–”

inputs are sampled at the same instant. Any unwanted

signal that is common to both inputs will be reduced by

thecommonmoderejectionofthesample-and-holdcircuit.

The inputs draw only one small current spike while charg-

ing the sample-and-hold capacitors during the acquire

When using a filter with a large C

value (e.g. 1µF),

FILTER

the inputs do not completely settle and the capacitive in-

put switching currents are averaged into a net DC current

(I ). In this case, the analog input can be modeled by an

DC

equivalent resistance (R = 1/(f

• C )) in series with

EQ

SMPL

IN

anidealvoltagesource(V

/2)asshowninFigure 3b.

REFCOMP

The magnitude of the DC current is then approximately

= (V – V /2)/R , which is roughly propor-

I

DC

IN

REFCOMP

EQ

tional to V . To prevent large DC drops across the resistor

FILTER

R

, a filter with a small resistor and large capacitor

should be chosen. When running at the minimum cycle

time of 2µs, the input current equals 106µA at V = 5V,

IN

2308fc

12

For more information www.linear.com/LTC2308

LTC2308

APPLICATIONS INFORMATION

50Ω

INPUT

CH0-CH7

LTC2308

ANALOG

INPUT

R

ON

CH0

R

SOURCE

100Ω

LTC2308

V

IN

2000pF

0.1µF

C

IN

C1

COM

55pF

2308 F03a

REFCOMP

10µF

2308 F04a

Figure 3a. Analog Input Equivalent Circuit

Figure 4a. Optional RC Input Filtering for Single-Ended Input

INPUT

I

DC

CH0-CH7

R

FILTER

LTC2308

V

1000pF

IN

50Ω

R

EQ

SMPL

C

CH0

FILTER

1/(f

• C )

IN

DIFFERENTIAL

ANALOG

LTC2308

1000pF

+

V

/2

REFCOMP

–

50Ω

INPUTS

CH1

2308 F03b

Figure 3b. Analog Input Equivalent Circuit

for Large Filter Capacitances

REFCOMP

10µF

0.1µF

2308 F04b

whichamountstoafull-scaleerrorof0.5LSBswhenusing

a filter resistor (R

Figure 4b. Optional RC Input Filtering for Differential Inputs

) of 4.7W. Applications requiring

FILTER

Signal-to-Noise and Distortion Ratio (SINAD)

lower sample rates can tolerate a larger filter resistor for

the same amount of full-scale error.

The signal-to-noise and distortion ratio (SINAD) is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency to the RMS amplitude of all other frequency

components at the A/D output. The output is band-limited

tofrequenciesfromaboveDCandbelowhalfthesampling

frequency. Figure 5 shows a typical SINAD of 73.3dB with

a500kHzsamplingrateanda1kHzinput. ASNRof73.4dB

can be achieved with the LTC2308.

Figures 4a and 4b show respective examples of input

filtering for single-ended and differential inputs. For the

single-ended case in Figure 4a, a 50W source resistor

and a 2000pF capacitor to ground on the input will limit

the input bandwidth to 1.6MHz. High quality capacitors

and resistors should be used in the RC filter since these

components can add distortion. NPO and silver mica type

dielectriccapacitorshaveexcellentlinearity.Carbonsurface

mount resistors can generate distortion from self heating

and from damage that may occur during soldering. Metal

film surface mount resistors are much less susceptible

to both problems.

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

Dynamic Performance

FFT (Fast Fourier Transform) test techniques are used to

test the ADC’s frequency response, distortion and noise

at the rated throughput. By applying a low distortion

sine wave and analyzing the digital output using an FFT

algorithm, the ADC’s spectral content can be examined

for frequencies outside the fundamental.

–100

–110

–120

–130

–140

0

50

100

150

200

250

FREQUENCY (kHz)

2308 TA01b

Figure 5. 1kHz Sine Wave 8192 Point FFT Plot

2308fc

13

For more information www.linear.com/LTC2308

LTC2308

APPLICATIONS INFORMATION

Total Harmonic Distortion (THD)

R1

8k

V

REF

BANDGAP

2.5V

Total Harmonic Distortion (THD) is the ratio of the RMS

sumofallharmonicsoftheinputsignaltothefundamental

itself. The out-of-band harmonics alias into the frequency

bandbetweenDCandhalfthesamplingfrequency(f

THD is expressed as:

REFERENCE

2.2µF

0.1µF

REFCOMP

4.096V

10µF

REFERENCE

AMP

/2).

SMPL

R2

V ²+V ²+V₄²...+V ²

R3

GND

2

3

N

THD=20log

LTC2308

V

1

2308 F06a

where V is the RMS amplitude of the fundamental fre-

1

Figure 6a. LTC2308 Reference Circuit

quencyandV throughV aretheamplitudesofthesecond

2

N

through Nth harmonics.

5V

0.1µF

V

IN

Internal Reference

LT1790A-2.5

V

The LTC2308 has an on-chip, temperature compensated

bandgap reference that is factory trimmed to 2.5V (Refer

to Figure 6a). It is internally connected to a reference

V

OUT

REF

2.2µF

0.1µF

LTC2308

REFCOMP

+

amplifier and is available at V

(Pin 7). V

should

REF

10µF

be bypassed to GND with a 2.2µF tantalum capacitor to

minimize noise. An 8k resistor is in series with the output

so that it can be easily overdriven by an external refer-

ence if more accuracy and/or lower drift are required as

shown in Figure 6b. The reference amplifier gains the

GND

2308 F06b

Figure 6b. Using the LT1790A-2.5 as an External Reference

5V

V

voltage by 1.638 to 4.096V at REFCOMP (Pin 8). To

REF

V

compensate the reference amplifier, bypass REFCOMP

with a 10µF ceramic or tantalum capacitor in parallel with

a0.1µFceramiccapacitorforbestnoiseperformance. The

internal reference buffer can also be overdriven from 1V

REF

V

IN

LTC2308

REFCOMP

LT1790A-4.096

V

OUT

+

0.1µF

10µF

to AV with an external reference at REFCOMP as shown

GND

DD

in Figure 6c. To do so V must be grounded to disable

REF

2308 F06c

the reference buffer. This will result in an input range of

Figure 6c. Overdriving REFCOMP Using the LT1790A-4.096

0V to V

in unipolar mode and 0.5 • V

in

REFCOMP

bipolar mode.

Internal Conversion Clock

The internal conversion clock is factory trimmed to

Digital Interface

The LTC2308 communicates via a standard 4-wire SPI

compatible digital interface. The rising edge of CONVST

initiates a conversion. After the conversion is finished,

pull CONVST low to enable the serial output (SDO). The

ADC shifts out the digital data in 2’s complement format

whenoperatinginbipolarmodeorinstraightbinaryformat

wheninunipolarmode, basedonthesettingoftheUNIbit.

achieve a typical conversion time (t ) of 1.3µs and a

CONV

maximum conversion time of 1.6µs over the full operat-

ing temperature range. With a typical acquisition time of

240ns, a throughput sampling rate of 500ksps is tested

and guaranteed.

2308fc

14

For more information www.linear.com/LTC2308

LTC2308

APPLICATIONS INFORMATION

For best performance, ensure that CONVST returns low

within40nsaftertheconversionstarts(i.e.,beforethefirst

bit decision) or after the conversion ends. If CONVST is

low when the conversion ends, the MSB bit will appear at

SDO at the end of the conversion and the ADC will remain

powered up.

Nap Mode

The ADC enters nap mode when CONVST is held high

after the conversion is complete (t

) if the SLP bit is

CONV

set to a logic 0. The supply current decreases to 180µA

in nap mode between conversions, thereby reducing the

average power dissipation as the sample rate decreases.

For example, the LTC2308 draws an average of 200µA

with a 1ksps sampling rate. The LTC2308 keeps only the

Timing and Control

The start of a conversion is triggered by a rising edge at

CONVST. Once initiated, a new conversion cannot be re-

started until the current conversion is complete. Figures 8

and9showthetimingdiagramsfortwodifferentexamples

of CONVST pulses. Example 1 (Figure 8) shows CONVST

staying HIGH after the conversion ends. If CONVST is high

reference(V )andreferencebuffer(REFCOMP)circuitry

REF

active when in nap mode.

Sleep Mode

The ADC enters sleep mode when CONVST is held high

after the conversion is complete (t ) if the SLP bit is

CONV

after the t

period, the LTC2308 enters NAP or SLEEP

CONV

set to a logic 1. The ADC draws only 7µA in sleep mode,

providedthatnoneofthedigitalinputsareswitching.When

CONVST returns low, the LTC2308 is released from the

SLEEP mode and requires 200ms to wake up and charge

the respective 2.2µF and 10µF bypass capacitors on the

mode, depending on the setting of SLP bit from the D

IN

word that was shifted in after the previous conversion.

(see Nap Mode and Sleep Mode for more detail).

When CONVST returns low, the ADC wakes up and the

most significant bit (MSB) of the output data sequence

at SDO becomes valid after the serial data bus is enabled.

All other data bits from SDO transition on the falling edge

V

REF

and REFCOMP pins.

Board Layout and Bypassing

of each SCK pulse. Configuration data (D ) is loaded into

IN

Toobtainthebestperformance,aprintedcircuitboardwith

a solid ground plane is required. Layout for the printed

circuit board should ensure digital and analog signal lines

are separated as much as possible. Care should be taken

not to run any digital signal alongside an analog signal. All

the LTC2308 at SDI, starting with the first SCK rising edge

after CONVST returns low. The S/D bit is loaded on the

first SCK rising edge.

Example 2 (Figure 9) shows CONVST returning low be-

fore the conversion ends. In this mode, the ADC and all

internal circuitry remain powered up. When the conver-

sion is complete, the MSB of the output data sequence at

SDO becomes valid after the data bus is enabled. At this

analoginputsshouldbeshieldedbyGND.V ,REFCOMP

REF

and AV should be bypassed to the ground plane as

DD

close to the pin as possible. Maintaining a low impedance

path for the common return of these bypass capacitors

is essential to the low noise operation of the ADC. These

traces should be as wide as possible. See Figure 7 for a

suggested layout.

point(t

1.3µs after the rising edge of CONVST), puls-

CONV

ing SCK will shift data out at SDO and load configuration

data (D ) into the LTC2308 at SDI. The first SCK rising

IN

edge loads the S/D bit into the LTC2308. SDO transitions

on the falling edge of each SCK pulse.

Figures 10 and 11 are the transfer characteristics for the

bipolar and unipolar modes. Data is output at SDO in 2’s

complement format for bipolar readings and in straight

binary for unipolar readings.

2308fc

15

For more information www.linear.com/LTC2308

LTC2308

APPLICATIONS INFORMATION

Figure 7b. Layer 1 Component Side

Figure 7a. Top Silkscreen

Figure 7c. Layer 2 Ground Plane

Figure 7d. Layer 3 Power Plane

2308fc

16

For more information www.linear.com/LTC2308

LTC2308

APPLICATIONS INFORMATION

Figure 7e. Layer Back Solder Side

JP1

CH0

JP4

C3

3

2

1

J1

CH0

1

2

3

E26

EXT OV

OV

DD

SMA

DD

R1

OPT

5V

C4

0.1µF

5V

OPEN

C2

10µF

C1

0.1µF

E1

TP1

OPT

21

19

0V

13

12

AV

E2

R2 100Ω

DV

AV

DD

CH0

DD

22 CH0

23 CH1

24 CH2

J2

E3

CH1

CONV 14

SDO 17

SCK 16

SDI 15

HEADER 12x2

R3 100Ω

R5 100Ω

CONV_AT_ADC

R4 301Ω

1

3

2

SDO_AT_ADC

SCK_AT_ADC

SDI_AT_ADC

1

2

3

4

5

6

CH3

CH4

CH5

CH6

CH7

COM

E4

CH2

4

5

6

LTC2308

E5

CH3

7

8

R6 100Ω

R7 100Ω

R8 100Ω

R10 100Ω

R11 100Ω

R12 100Ω

REFCOMP

8

7

R9 49.9Ω

C38

9

10

12

14

16

18

20

22

24

V

REF

E6

CH4

E8

REF

10µF

V

11

13

15

17

19

21

23

C5

E7

CH5

2.2µF

GND GND GND GND GND GND

25 10 11 20 18

E9

REFCOMP

9

E10

CH6

E11

CH7

JP3

COM

E12

TP2

OPT

E13

1

2

3

C7

C9

C11

C13

C14

47pF

EXTERNAL

OPEN

GND

C15

10µF

47pF

BIAS

JP2

C6

47pF

C8

47pF

C10

47pF

C12

47pF

DC BIAS

1

R13

4.99k

EXTERNAL

REFCOMP

2

3

C16

1µF

R14

4.99k

2308 F07F

E14

DC_BIAS/2

Figure 7f. Partial Demo Board Schematic

2308fc

17

For more information www.linear.com/LTC2308

LTC2308

APPLICATIONS INFORMATION

t

WLCONVST

t

ACQ

CONVST

NAP OR

SLEEP

t

CONV

t

CYC

1

2

3

4

5

6

7

8

9

10 11 12

SCK

SDI

S/D O/S S1 S0 UNI SLP

MSB

LSB

Hi-Z

SDO

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

2308 F08

Figure 8. LTC2308 Timing with a Long CONVST Pulse

t

ACQ

t

WHCONV

HCONVST

CONVST

t

CYC

t

CONV

1

2

3

4

5

6

7

8

9

10 11 12

SCK

SDI

S/D O/S S1 S0 UNI SLP

MSB

LSB

Hi-Z

SDO

B11

B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

2308 F09

Figure 9. LTC2308 Timing with a Short CONVST Pulse

2308fc

18

For more information www.linear.com/LTC2308

LTC2308

APPLICATIONS INFORMATION

011...111

011...110

BIPOLAR

ZERO

000...001

000...000

111...111

111...110

FS = 4.096V

1LSB = FS/2

100...001

100...000

N

1LSB = 1mV

–1 0V

1

–FS/2

FS/2 – 1LSB

LSB

INPUT VOLTAGE (V)

2308 F10

Figure 10. LTC2308 Bipolar Transfer

Characteristics (2’s Complement)

111...111

111...110

100...001

100...000

011...111

011...110

UNIPOLAR

ZERO

FS = 4.096V

1LSB = FS/2^N

1LSB = 1mV

000...001

000...000

0V

FS – 1LSB

INPUT VOLTAGE (V)

2308 F11

Figure 11. LTC2308 Unipolar Transfer

Characteristics (Straight Binary)

2308fc

19

For more information www.linear.com/LTC2308

LTC2308

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LTC2308#packaging for the most recent package drawings.

UF Package

24-Lead Plastic QFN (4mm × 4mm)

(Reference LTC DWG # 05-08-ꢀ697 Rev B)

0.70 0.05

4.50 0.05

3.ꢀ0 0.05

2.45 0.05

(4 SIDES)

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

BOTTOM VIEW—EXPOSED PAD

R = 0.ꢀꢀ5

PIN ꢀ NOTCH

R = 0.20 TYP OR

0.35 × 45° CHAMFER

0.75 0.05

4.00 0.ꢀ0

(4 SIDES)

TYP

23 24

PIN ꢀ

TOP MARK

(NOTE 6)

0.40 0.ꢀ0

ꢀ

2

2.45 0.ꢀ0

(4-SIDES)

(UF24) QFN 0ꢀ05 REV B

0.200 REF

0.25 0.05

0.50 BSC

0.00 – 0.05

NOTE:

ꢀ. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

2308fc

20

For more information www.linear.com/LTC2308

LTC2308

REVISION HISTORY ^{(Revision history begins at Rev C)}

REV

DATE

DESCRIPTION

PAGE NUMBER

C

10/16 Updated t

in Figure 8.

18

ACQ

2308fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

For more information www.linear.com/LTC2308

21

LTC2308

TYPICAL APPLICATION

Clock Squaring/Level Shifting Circuit Allows Testing with RF Sine Generator,

Convert Re-Timing Flip-Flop Preserves Low Jitter Clock Timing

5V

2.7V TO 5V

10µF

0.1µF

10µF

0.1µF

LTC2308

AV

DD

DV

OV

DD

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM

SDI

ANALOG

INPUT

MUX

SDO

12-BIT

500ksps

ADC

+

–

SERIAL

PORT

SCK

V

CONVST

CC

CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

V

REF

PRE

NL17SZ74

CLR

INTERNAL

2.5V REF

2.2µF

Q

D

CONVERT ENABLE

REFCOMP

10µF

GND

0.1µF

V

CC

RF SIGNAL GENERATOR OR

OTHER LOW JITTER SOURCE

0.1µF

1k

MASTER

CLOCK

NC7SVU04P5X

50Ω

1k

•

MASTER CLOCK

JITTER

•

CONVERT ENABLE

CONVST

2308 TA02

DATA TRANSFER

RELATED PARTS

PART NUMBER

LTC1417

DESCRIPTION

COMMENTS

14-Bit, 400ksps Serial ADC

20mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package

LT1468/LT1469

LTC1609

Single/Dual 90MHz, 22V/µs, 16-Bit Accurate Op Amps Low Input Offset: 75µV/125µV

16-Bit, 200ksps Serial ADC

65mW, Configurable Bipolar and Unipolar Input Ranges, 5V Supply

LT1790

Micropower Low Dropout Reference

10-Bit/12-Bit, 8-Channel, 1.25Msps ADC

10-Bit/12-Bit, 8-Channel, 400ksps ADC

12-Bit, 1-/2-Channel, 250ksps ADC in MSOP

60µA Supple Current, 10ppm/°C, SOT-23 Package

LTC1850/LTC1851

LTC1852/LTC1853

LTC1860/LTC1861

Parallel Output, Programmable MUX and Sequencer, 5V Supply

Parallel Output, Programmable MUX and Sequencer, 3V or 5V Supply

850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages

450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages

6.5mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package

2mW, Unipolar or Bipolar, Internal Reference, SSOP-16 Package

850µA at 250ksps, 2µA at 1ksps, SO-8 and MSOP Packages

450µA at 150ksps, 10µA at 1ksps, SO-8 and MSOP Packages

LTC1860L/LTC1861L 3V, 12-Bit, 1-/2-Channel, 150ksps ADC

LTC1863/LTC1867 12-/16-Bit, 8-Channel, 200ksps ADC

LTC1863L/LTC1867L 3V, 12-/16-Bit, 8-Channel, 175ksps ADC

LTC1864/LTC1865 16-Bit, 1-/2-Channel, 250ksps ADC in MSOP

LTC1864L/LTC1865L 3V, 16-Bit, 1-/2-Channel, 150ksps ADC in MSOP

2308fc

LT 1016 REV C • PRINTED IN USA

22 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

For more information www.linear.com/LTC2308

●

 LINEAR TECHNOLOGY CORPORATION 2007

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2308


型号：	LTC2308IUF#TRPBF
厂家：	Linear
描述：	LTC2308 - Low Noise, 500ksps, 8-Channel, 12-Bit ADC; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C 转换器
文件：	总22页 (文件大小：657K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2308IUF#TRPBF [Linear]

相关型号：

LTC2308IUF-PBF

LTC2308IUF-TRPBF

LTC2308IUFXPBF

LTC2308IUFXTRPBF

LTC2309

LTC2309CF#PBF

LTC2309CUF#PBF

LTC2309CUF-PBF

LTC2309CUF-TRPBF

LTC2309CUFXPBF

LTC2309CUFXTRPBF

LTC2309IUF#PBF