LTC2315ITS8-12#TRMPBF

LTC2315-12

12-Bit, 5Msps Serial

Sampling ADC in TSOT

FEATURES

DESCRIPTION

The LTC^®2315-12 is a 12-bit, 5Msps, serial sampling A/D

converterthatdrawsonly6.4mAfromawiderangeanalog

supply adjustable from 2.7V to 5.25V. The LTC2315-12

containsanintegratedbandgapandreferencebufferwhich

provide a low cost, high performance (20ppm/°C max)

and space saving applications solution. The LTC2315-12

achieves outstanding AC performance of 72.6dB SINAD

and–84dBTHDwhilesamplinga500kHzinputfrequency.

The extremely high sample rate-to-power ratio makes the

LTC2315-12 ideal for compact, low power, high speed

systems. The LTC2315-12 also provides both nap and

sleep modes for further optimization of the device power

within a system.

n

5Msps Throughput Rate

n

Guaranteed 12-Bit No Missing Codes

n

Internal Reference: 2.048V/4.096V Span

n

Low Noise: 73dB SNR

n

Low Power: 6.4mA at 5Msps and 5V

n

Dual Supply Range: 3V/5V operation

n

Sleep Mode with < 1µA Typical Supply Current

n

Nap Mode with Quick Wake-up < 1 conversion

n

Separate 1.8V to 5V Digital I/O Supply

n

High Speed SPI-Compatible Serial I/O

n

Guaranteed Operation from –40°C to 125°C

n

8-Lead TSOT-23 Package

APPLICATIONS

The LTC2315-12 has a high-speed SPI-compatible serial

interface that supports 1.8V, 2.5V, 3V and 5V logic. The

fast 5Msps throughput makes the LTC2315-12 ideally

suited for a wide variety of high speed applications.

n

Communication Systems

n

High Speed Data Acquisition

n

Handheld Terminal Interface

n

Medical Imaging

Complete 14-/12-Bit Pin-Compatible SAR ADC Family

n

Uninterrupted Power Supplies

500ksps

2.5Msps

4.5Msps

5Msps

n

Battery Operated Systems

14-Bit

12-Bit

LTC2312-14 LTC2313-14 LTC2314-14

LTC2312-12 LTC2313-12

n

Automotive

LTC2315-12

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Power 3V/5V 9mW/15mW 14mW/25mW 18mW/31mW 19mW/32mW

TYPICAL APPLICATION

5V Supply, Internal Reference, 5Msps, 12-bit Sampling ADC

16k Point FFT, f_S= 5Msps, f_IN= 500kHz

0

5V

V

= 5V

DD

LTC2315-12

2.2µF

SNR = 73.1dBFS

SINAD = 72.6dBFS

THD = –84dB

–20

–40

V

CS

DD

2.2µF

SFDR = 87dBc

SERIAL DATA LINK TO

ASIC, PLD, MPU, DSP

OR SHIFT REGISTERS

REF

SCK

SDO

–60

–80

GND

DIGITAL OUTPUT SUPPLY

1.8V TO 5V

ANALOG INPUT

0V TO 4.096V

A

OV

DD

IN

–100

–120

–140

2.2µF

231512 TA01

500

1000

0

1500

2000

2500

FREQUENCY (kHz)

231512 TA01a

231512fa

1

For more information www.linear.com/LTC2315-12

LTC2315-12

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Notes 1, 2)

Supply Voltage (V , OV ) .......................................6V

DD

Reference (REF) and Analog Input (A ) Voltage

IN

TOP VIEW

(Note 3)......................................(–0.3V) to (V + 0.3V)

DD

V

1

8 CS

7 SCK

6 SDO

DD

REF 2

GND 3

A

Digital Input Voltage (Note 3).. (–0.3V) to (OV + 0.3V)

DD

Digital Output Voltage............. (–0.3V) to (OV + 0.3V)

DD

4

5 OV

DD

IN

Power Dissipation...............................................100mW

TS8 PACKAGE

8-LEAD PLASTIC TSOT-23

Operating Temperature Range

T

= 150°C, θ = 195°C/W

JA

JMAX

LTC2315C ................................................ 0°C to 70°C

LTC2315I..............................................–40°C to 85°C

LTC2315H .......................................... –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature Range (Soldering, 10 sec)........300°C

ORDER INFORMATION

Lead Free Finish

TAPE AND REEL (MINI)

TAPE AND REEL

PART MARKING*

LTFZG

PACKAGE DESCRIPTION

8-Lead Plastic TSOT-23

TEMPERATURE RANGE

0°C to 70°C

LTC2315CTS8-12#TRMPBF

LTC2315ITS8-12#TRMPBF

LTC2315HTS8-12#TRMPBF

LTC2315CTS8-12#TRPBF

LTC2315ITS8-12#TRPBF

LTC2315HTS8-12#TRPBF

LTFZG

–40˚C to 85˚C

LTFZG

–40˚C to 125˚C

TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container.

Consult LTC Marketing for parts specified with wider operating temperature ranges.

Consult LTC Marketing for information on lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

231512fa

2

For more information www.linear.com/LTC2315-12

LTC2315-12

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 4)

SYMBOL PARAMETER

CONDITIONS

MIN

–0.05

0

TYP

MAX

+ 0.05

DD

UNITS

l

V

AIN

V

IN

Absolute Input Range

V

Input Voltage Range

(Note 11)

V

REF

I

Analog Input DC Leakage Current

Analog Input Capacitance

–1

1

µA

IN

C

Sample Mode

Hold Mode

13

3

pF

IN

CONVERTER CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 4)

SYMBOL PARAMETER

CONDITIONS

MIN

12

TYP

MAX

UNITS

Bits

l

Resolution

No Missing Codes

12

Bits

Transition Noise

(Note 6)

0.33

LSB

RMS

l

INL

Integral Linearity Error

V

= 5V (Note 5)

= 3V (Note 5)

–1.25

–1.5

0.25

0.3

1.25

1.5

LSB

DD

l

DNL

Differential Linearity Error

Offset Error

V

= 5V

= 3V

–0.99

0.15

0.2

0.99

LSB

DD

l

V

= 5V

= 3V

–4

–6

0.5

1

4

6

LSB

DD

l

Full-Scale Error

V

DD

V

DD

= 5V

= 3V

–7

–9

1.5

2

7

9

LSB

l

Total Unadjusted Error

V

DD

V

DD

= 5V

= 3V

–8

–10

2

2.5

8

10

LSB

DYNAMIC ACCURACY ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C and A_IN= –1dBFS. (Note 4)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

SINAD

Signal-to-(Noise + Distortion) Ratio

f

= 500kHz, V = 5V

69.5

67.5

72.6

69.5

dB

IN

DD

= 500kHz, V = 3V

DD

l

SNR

Signal-to-Noise Ratio

f

= 500kHz, V = 5V

70

68

73

70

dB

IN

DD

= 500kHz, V = 3V

DD

l

THD

Total Harmonic Distortion

First 5 Harmonics

f

= 500kHz, V = 5V

–84

–76

–75

dB

IN

DD

= 500kHz, V = 3V

DD

l

SFDR

IMD

Spurious Free Dynamic Range

f

= 500kHz, V = 5V

87

78

77

dB

IN

DD

= 500kHz, V = 3V

DD

Intermodulation Distortion

2nd Order Terms

3rd Order Terms

f

A

= 461kHz, f = 541kHz

IN1 IN2

–77

–89

dBc

IN1

IN2

, A = –7dBFS

Full Power Bandwidth

At 3dB

At 0.1dB

130

20

MHz

–3dB Input Linear Bandwidth

Aperture Delay

SINAD ≥ 68dB

5

1

MHz

ns

t

AP

Aperture Jitter

10

ps

RMS

JITTER

231512fa

3

For more information www.linear.com/LTC2315-12

LTC2315-12

REFERENCE INPUT/OUTPUT ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 4)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Output Voltage

2.7V ≤ V ≤ 3.6V

2.040

4.080

2.048

4.096

2.056

4.112

V

REF

DD

4.75 ≤ V ≤ 5.25V

DD

l

V

Temperature Coefficient

Output Resistance

7

20

ppm/°C

REF

Normal Operation

2

52

Ω

kΩ

REF

Overdrive Condition

(V

≥ V

+ 50mV)

REFOUT

REFIN

V

REF

Line Regulation

2.7V ≤ V ≤ 3.6V

2

0.8

mV/V

DD

4.75 ≤ V ≤ 5.25V

DD

V

2.048V/4.096V Supply Threshold

2.048V/4.096V Supply Threshold Hysteresis

Input Voltage Range

4.15

150

V

REF

mV

l

2.7V ≤ V ≤ 3.6V

V

REF

+50mV

V

DD

4.3

V

DD

REF

(External Reference Input)

4.75 ≤ V ≤ 5.25V

V

DD

DIGITAL INPUTS AND DIGITAL OUTPUTS ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C. (Note 4)

SYMBOL PARAMETER

CONDITIONS

MIN

0.8 • OV

TYP

MAX

UNITS

V

l

V

High Level Input Voltage

Low Level Input Voltage

Digital Input Current

IH

IL

DD

0.2 • OV

V

DD

I

V

= 0V to OV

DD

–10

10

μA

pF

IN

C

V

Digital Input Capacitance

High Level Output Voltage

Low Level Output Voltage

High-Z Output Leakage Current

High-Z Output Capacitance

Output Source Current

Output Sink Current

5

IN

l

I = –500µA (Source)

O

OV –0.2

DD

V

OH

OL

I = 500µA (Sink)

O

0.2

10

V

I

OZ

V

= 0V to OV , CS = High

–10

µA

pF

OUT

DD

C

OZ

CS = High

4

I

V

= 0V, OV = 1.8V

–20

20

mA

SOURCE

SINK

OUT

DD

= OV = 1.8V

DD

POWER REQUIREMENTS ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

DD

Supply Voltage

3V Operational Range

5V Operational Range

l

2.7

4.75

3

5

3.6

5.25

V

l

OV

DD

Digital Output Supply Voltage

1.71

5.25

V

l

I

=

IOV

Supply Current, Static Mode

Operational Mode

Nap Mode

CS = 0V, SCK = 0V

3.5

6.4

1.8

0.8

4

mA

µA

TOTAL

DD +

IV

7.5

DD

l

Sleep Mode

5

l

P

Power Dissipation, Static Mode

Operational Mode

Nap Mode

17.5

32

9

20

37.5

mW

µW

D

l

Sleep Mode

4

25

231512fa

4

For more information www.linear.com/LTC2315-12

LTC2315-12

ADC TIMING CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

(Notes 7, 8)

MIN

TYP

MAX

5

UNITS

MHz

ns

l

f

t

Maximum Sampling Frequency

Shift Clock Frequency

Shift Clock Period

SAMPLE(MAX)

87.5

SCK

11.4

SCK

Minimum Throughput Time, t

Conversion Time

+ t

CONV

200

ns

THROUGHPUT

ACQ

160

40

5

ns

CONV

Acquisition Time

ns

ACQ

1

Minimum CS Pulse Width

SCK Setup Time After CS↓

SDO Enable Time After CS↓

(Note 7)

ns

(Note 7)

5

ns

2

(Notes 7, 8)

(Notes 7, 8, 9)

10

ns

3

SDO Data Valid Access Time after SCK↓

SCLK Low Time

9.1

ns

4

4.5

1

ns

5

SCLK High Time

ns

6

SDO Data Valid Hold Time After SCK↓

SDO into Hi-Z State Time After 16th SCK↓

SDO into Hi-Z State Time After CS↑

CS↑ Setup Time After 14th SCK↓

Latency

(Notes 7, 8, 9)

(Notes 7, 8, 10)

(Note 7)

ns

7

3

10

ns

8

3

ns

9

5

ns

10

1 Cycle Latency

t

_

Power-Up Time from Nap Mode

Power-Up Time from Sleep Mode

See Nap Mode Section

See Sleep Mode Section

50

ns

WAKE NAP

_

1.1

ms

WAKE SLEEP

Note 1. Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 6. Typical RMS noise at code transitions.

Note 7. Parameter tested and guaranteed at OV = 2.5V. All input signals

DD

are specified with t = t = 1nS (10% to 90% of OV ) and timed from a

r

f

DD

voltage level of OV /2.

DD

Note 2. All voltage values are with respect to ground.

Note 8. All timing specifications given are with a 10pF capacitance load.

Note 3. When these pin voltages are taken below ground or above V

Load capacitances greater than this will require a digital buffer.

DD

(A , REF) or OV (SCK, CS, SDO) they will be clamped by internal

IN

DD

Note 9. The time required for the output to cross the V or V voltage.

Note 10. Guaranteed by design, not subject to test.

Note 11. Recommended operating conditions.

IH

IL

diodes. This product can handle input currents up to 100mA below ground

or above V or OV without latch-up.

DD

Note 4. V = 5V, OV = 2.5V, f

= 5MHz, f = 87.5MHz, A =

SCK IN

DD

SMPL

–1dBFS and internal reference unless otherwise noted.

Note 5. Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

231512fa

5

For more information www.linear.com/LTC2315-12

LTC2315-12

T_A= 25°C, V_DD= 5V, OV_DD= 2.5V, f_SMPL= 5Msps,

TYPICAL PERFORMANCE CHARACTERISTICS

unless otherwise noted.

Integral Nonlinearity

vs Output Code

Differential Nonlinearity

vs Output Code

DC Histogram Near Mid-Scale

(Code 2048)

1.0

0.8

1.0

0.8

60000

σ = 0.33

50000

40000

30000

20000

10000

0

0.6

0.4

0.2

0.0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

0

2048

3072

4096

0

2048

3072

4096

1024

2047

2049

2050

2051

2048

OUTPUT CODE

CODE

231512 G03

231512 G01

231512 G02

16k Point FFT, f_S= 5Msps

f_IN= 500kHz

SNR, SINAD vs Input Frequency

(100kHz to 2.2MHz)

THD, Harmonics vs Input

Frequency (100kHz to 2.2MHz)

0

–20

74

73

72

71

70

69

–75

–80

V

= 5V

R /C = 50Ω/47pF

IN IN

DD

SNR = 73.1dBFS

SINAD = 72.6dBFS

THD = –84dB

f = 5Msps

S

DD

V

= 3V

SNR

–40

V

DD

= 5V

SFDR = 87dBc

THD

SINAD

2ND

–85

–60

3RD

–80

–90

SNR

–100

–120

–140

V

DD

= 3V

SINAD

–95

–100

0

1500

2000

2500

0

1500

2000

2500

500

1000

500

1000

500

1000

0

1500

2000

2500

INPUT FREQUENCY (kHz)

231512 G04

231512 G05

231512 G06

THD, Harmonics vs Input

Frequency (100kHz to 2.2MHz)

SNR, SINAD vs Temperature,

f_IN= 500kHz

THD, Harmonics vs Temperature,

f_IN= 500kHz

–75

–80

75

74

73

72

71

70

69

68

–75

–80

V

DD

= 3V

R

/C = 50Ω/47pF

= 5Msps

= 5V

IN IN

f

V

S

DD

THD

2ND

V

DD

= 5V

SNR

THD

SINAD

–85

2ND

3RD

–90

SNR

V

DD

= 3V

SINAD

–95

–100

0

1500

2000

2500

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

500

1000

INPUT FREQUENCY (kHz)

TEMPERATURE (°C)

231512 G06a

231512 G07

231512 G08

231512fa

6

For more information www.linear.com/LTC2315-12

LTC2315-12

T_A= 25°C, V_DD= 5V, OV_DD= 2.5V, f_SMPL= 5Msps,

TYPICAL PERFORMANCE CHARACTERISTICS

unless otherwise noted.

THD, Harmonics vs Temperature,

f_IN= 500kHz

SNR, SINAD vs Reference Voltage

f_IN= 500kHz

Reference Current

vs Reference Voltage

–75

–80

74

73

72

71

70

600

500

400

300

200

100

0

V

DD

= 5V

f

= 5Msps

S

SNR

= 5V

f

= 5Msps

S

V

DD

V

DD

= 5V

SNR

THD

V = 3.6V

DD

–85

3RD

V

DD

= 3.6V

SINAD

= 3Msps

f

= 3Msps

SINAD

S

–90

2ND

OPERATION

NOT ALLOWED

OPERATION

–95

NOT ALLOWED

–100

–55 –35 –15

5

25 45 65 85 105 125

2

2.5

3

3.5

4

4.5

2

2.5

3

3.5

4

4.5

TEMPERATURE (°C)

REFERENCE VOLTAGE (V)

231512 G08a

231512 G10

231512 G11

Full-Scale Error vs Temperature

Offset Error vs Temperature

Supply Current vs Temperature

4

3

1

0.5

0

6.5

6.25

6

V

DD

= 5V

2

1

0

5.75

5.5

5.25

5

V

DD

= 3V

–1

–2

–3

–4

–0.5

–1

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

TEMPERATURE (°C)

231512 G12

231512 G13

231512 G14

Supply Current vs SCK Frequency

Shutdown Current vs Temperature

7

6

5

4

3

2

1

0

1

0.75

0.5

V

DD

= 3V

I

+ I

VDD OVDD

OV = 1.8V

DD

I

TOT

VDD

V

= 3V

= 5V

0.25

DD

I

OVDD

V

DD

0

10 20 30 40 50 60 70 80 90

–55 –35 –15

5

25 45 65 85 105 125

SCK FREQUENCY (MHz)

TEMPERATURE (°C)

231512 G16

231512 G15

231512fa

7

For more information www.linear.com/LTC2315-12

LTC2315-12

T_A= 25°C, V_DD= 5V, OV_DD= 2.5V, f_SMPL= 5Msps,

TYPICAL PERFORMANCE CHARACTERISTICS

unless otherwise noted.

Supply Current (I_VDD

)

Output Supply Current (I_OVDD)

vs Output Supply Voltage (OV_DD)

vs Supply Voltage (V_DD

)

6.50

6.25

6.00

5.75

5.50

5.25

5.00

4.75

4.50

2.5

2.0

1.5

1.0

0.5

0

5Msps

f

= 87.5MHz

5Msps

SCK

f

= 87.5MHz

SCK

OPERATION

NOT ALLOWED

3Msps

= 52.5MHz

3Msps

= 52.5MHz

f

SCK

2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3

1.7

2.3

2.9

3.5

4.1

4.7

5.3

SUPPLY VOLTAGE (V)

OUTPUT SUPPLY VOLTAGE (V)

231512 G17

231512 G18

PIN FUNCTIONS

V

(Pin 1): Power Supply. The ranges of V are 2.7V

SDO(Pin6):SerialDataOutput.TheA/Dconversionresult

is shifted out on SDO as a serial data stream with the MSB

first through the LSB last. There is 1 cycle of conversion

DD

to 3.6V and 4.75V to 5.25V. Bypass V to GND with a

DD

2.2µF ceramic chip capacitor.

latency. Logic levels are determined by OV .

DD

REF (Pin 2): Reference Input/Output. The REF pin volt-

age defines the input span of the ADC, 0V to V . By

SCK (Pin 7): Serial Data Clock Input. The SCK serial clock

falling edge advances the conversion process and outputs

a bit of the serialized conversion result, MSB first to LSB

last. SDO data transitions on the falling edge of SCK. A

continuous or burst clock may be used. Logic levels are

REF

default, REF is an output pin and produces a reference

voltage V

DD

of either 2.048V or 4.096V depending on

REF

V

(see Table 2). Bypass to GND with a 2.2µF, low ESR,

high quality ceramic chip capacitor. The REF pin may be

overdriven with a voltage at least 50mV higher than the

internal reference voltage output.

determined by OV .

DD

CS (Pin 8): Chip Select Input. This active low signal starts

a conversion on the falling edge and frames the serial data

transfer. Bringing CS high places the sample-and-hold

into sample mode and also forces the SDO pin into high

GND (Pin 3): Ground. The GND pin must be tied directly

to a solid ground plane.

A (Pin 4): Analog Input. A is a single-ended input with

IN

impedance. Logic levels are determined by OV .

DD

respect to GND with a range from 0V to V

.

REF

OV (Pin 5): I/O Interface Digital Power. The OV range

DD

is 1.71V to 5.25V. This supply is nominally set to the

same supply as the host interface (1.8V, 2.5V, 3.3V or

5V). Bypass to GND with a 2.2µF ceramic chip capacitor.

231512fa

8

For more information www.linear.com/LTC2315-12

LTC2315-12

BLOCK DIAGRAM

2.2µF

ANALOG SUPPLY

RANGE 2.7V TO 5.25V

DIGITAL SUPPLY

RANGE 1.71V TO 5.25V

1

5

V

DD

OV

DD

2.5V LDO

A

IN

ANALOG

INPUT RANGE

4

+

THREE-STATE

SERIAL

OUTPUT

PORT

SDO

0V TO V

REF

12-BIT SAR ADC

6

S/H

–

REF

SCK

2

3

7

8

TIMING

LOGIC

2.2µF

GND

CS

1.024V

BANDGAP

2×/4×

TS8 PACKAGE

231512 BD

ALL CAPACITORS UNLESS

NOTED ARE HIGH QUALITY,

CERAMIC CHIP TYPE

TIMING DIAGRAMS

16TH EDGE

t

9

8

SCK

CS

OV /2

DD

OV /2

DD

Hi-Z

SDO

Figure 1. SDO Into Hi-Z after 16TH SCK↓

Figure 2. SDO Into Hi-Z after CS↑

231512 TD01

231512 TD02

t

4

7

SCK

SDO

SCK

SDO

OV /2

DD

OV /2

DD

V

OH

V

OH

OL

V

OL

Figure 3. SDO Data Valid Hold after SCK↓

Figure 4. SDO Data Valid Access after SCK↓

231512 TD03

231512 TD04

t

10

CS

t

= 13.5 • t

+ t + t

10

t

= 40ns

CONV

2

SCK

2

ACQ-MIN

t

ACQ-MIN

CONV

t

6

2

1

3

4

12

13

14

SCK

SDO

t

5

t

9

3

4

7

0

B11*

(MSB)

B10

B9

B0

0

HI-Z STATE

t

THROUGHPUT

*NOTE: SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION

231512 TD05

Figure 5: LTC2315-12 Serial Interface Timing Diagram (SCK Low During t_ACQ

)

231512fa

9

For more information www.linear.com/LTC2315-12

LTC2315-12

TIMING DIAGRAMS

t

10

CS

t

= 13 • t

+ t + t

2 10

t

= 40ns

CONV(MIN)

SCK

ACQ-MIN

t

ACQ-MIN

CONV

t

6

2

SCK

SDO

1

2

3

4

5

13

14

t

5

t

9

3

4

7

0

B11*

(MSB)

B10

B9

B1

B0

0

HI-Z STATE

t

THROUGHPUT

*NOTE: SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION

231512 TD06

Figure 6: LTC2315-12 Serial Interface Timing Diagram (SCK High During t_ACQ

)

CS

t

= 14 • t

t

= 4 • t

CONV

SCK

ACQ

SCK

t

ACQ

CONV

t

10

2

6

18

1

2

3

4

5

13

14

15

16

17

18

SCK

SDO

t

5

t

9

3

4

7

t

0

B11*

(MSB)

B10

B9

B1

= 18 • t

B0

0

HI-Z STATE

THROUGHPUT

SCK

*NOTE: SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION

231512 TD07

Figure 7: LTC2315-12 Serial Interface Timing Diagram (SCK Continuous)

231512fa

10

For more information www.linear.com/LTC2315-12

LTC2315-12

APPLICATIONS INFORMATION

Overview

illustrate that for the SCK held high during acquisition or

continuous clocking mode two leading zeros are output.

Leading zeros allow the 12-bit data result to be framed

with both leading and trailing zeros for timing and data

verification. SincetherisingedgeofSCKwillbecoincident

TheLTC^®2315-12isalownoise,highspeed,12-bitsucces-

sive approximation register (SAR) ADC. The LTC2315-12

operates over a wide supply range (2.7V to 5.25V) and

provides a low drift (20ppm/°C maximum), internal refer-

ence and reference buffer. The internal reference buffer is

automatically configured to a 2.048V span in low supply

range (2.7V to 3.6V) and to a 4.096V span in the high

supply range (4.75V to 5.25V). The LTC2315-12 samples

at a 5Msps rate and supports an 87.5MHz data clock. The

LTC2315-12 achieves excellent dynamic performance

(73dBSNR,84dBTHD)whiledissipatingonly32mWfrom

a 5V supply at the 5Msps conversion rate.

with the falling edge of CS, delay t is the delay to the first

2

falling edge of SCK, which is simply 0.5 • t . Delays t

SCK

2

(CS falling edge to SCK leading edge) and t (14th falling

10

SCK edge to CS rising edge) must be observed for Figures

5, 6 and 7 and any timing implementation in order for the

conversion process and data readout to occur correctly.

The user can bring CS high after the 14th falling SCK edge

provided that timing delay t is observed. Prematurely

10

terminating the conversion by bringing CS high before

The LTC2315-12 outputs the conversion data with one

cycle of conversion latency on the SDO pin. The SDO pin

output logic levels are supplied by the dedicated OV

supplypinwhichhasawidesupplyrange(1.71Vto5.25V)

allowingtheLTC2315-12tocommunicatewith1.8V,2.5V,

3V or 5V systems.

the 14th falling SCK edge plus delay t will cause a loss

10

of conversion data for that sample. The sample-and-hold

is placed in sample mode when CS is brought high. As

showninFigure6, asamplerateof5Mspscanbeachieved

on the LTC2315-12 by using an 87.5MHz SCK data clock

and a minimum acquisition time of 40ns which results in

DD

TheLTC2315-12providesbothnapandsleeppower-down

modes through serial interface control to reduce power

dissipation during inactive periods.

the minimum throughput time (t ) of 200ns.

THROUGHPUT

Note that the maximum throughput of 5Msps can only be

achieved with the timing implementation of SCK held high

during acquisition as shown in Figure 6.

Serial Interface

The LTC2315-12 also supports a continuous data clock

as shown in Figure 7. With a continuous data clock the

acquisition time period and conversion time period must

be designed as an exact integer number of data clock

periods. Because the minimum acquisition time is not an

exact multiple of the minimum SCK period, the maximum

sample rate for the continuous SCK timing is less than

5Msps. For example, a 4.86Msps throughput is achieved

usingexactly18dataclockperiodswiththemaximumdata

clock frequency of 87.5MHz. For this particular case, the

acquisition time period and conversion clock period are

TheLT2315-12communicateswithmicrocontrollers,DSPs

and other external circuitry via a 3-wire interface. A falling

CS edge starts a conversion and frames the serial data

transfer.SCKprovidestheconversionclockforthecurrent

sample and controls the data readout on the SDO pin of

the previous sample. CS transitioning low clocks out the

first leading zero and subsequent SCK falling edges clock

out the remaining data as shown in Figures 5, 6 and 7 for

threedifferenttimingschemes.DataisseriallyoutputMSB

first through LSB last, followed by trailing zeros if further

SCK falling edges are applied. Figure 5 illustrates that dur-

ing the case where SCK is held low during the acquisition

phase, only one leading zero is output. Figures 6 and 7

designed as 4 data clock periods (T

= 45.7ns) and 14

ACQ

data clock periods (T

= 160ns) respectively, yielding

CONV

a throughput time of 205.7ns.

231512fa

11

For more information www.linear.com/LTC2315-12

LTC2315-12

APPLICATIONS INFORMATION

The following table illustrates the maximum throughput

achievable for each of the three timing patterns. Note

that in order to achieve the maximum throughput rate of

5Msps, the timing pattern where SCK is held high during

the acquisition time must be used.

digital logic operating between 1.8V and 5V, including

2.5V and 3.3V systems.

Entering Nap/Sleep Mode

Pulsing CS two times and holding SCK static places the

LTC2315-12 into nap mode. Pulsing CS four times and

holding SCK static places the LTC2315-12 into sleep

mode. In sleep mode, all bias circuitry is shut down,

including the internal bandgap and reference buffer, and

only leakage currents remain (0.8µA typical). Because

the reference buffer is externally bypassed with a large

capacitor (2.2µF), the LTC2315-12 requires a significant

wait time (1.1ms) to recharge this capacitance before an

accurate conversion can be made. In contrast, nap mode

does not power down the internal bandgap or reference

bufferallowingforafastwake-upandaccurateconversion

within one conversion clock cycle. Supply current during

nap mode is nominally 1.8mA.

Table 1: Maximum Throughput vs Timing Pattern

TIMING PATTERN

MAXIMUM

THROUGHPUT

SCK high during T

5Msps

ACQ

SCK low during T

SCK continuous (t

4.86Msps

ACQ

= 18 periods)

THROUGHPUT

Serial Data Output (SDO)

The SDO output is always forced into the high impedance

state while CS is high. The falling edge of CS starts the

conversion and enables SDO. The A/D conversion result

is shifted out on the SDO pin as a serial data stream with

the MSB first. The data stream consists of either one

leading zero (SCK held low during acquisition, Fig. 5) or

two leading zeros (SCK held high during acquisition, Fig.

6) followed by 12 bits of conversion data. There is 1 cycle

of conversion latency. Subsequent falling SCK edges after

the LSB is output will output zeros on the SDO pin. The

SDO output returns to the high impedance state after the

16th falling edge of SCK.

Exiting Nap/Sleep Mode

WakinguptheLTC2315-12fromeithernaporsleepmode,

as shown in Figures 8 and 9, requires SCK to be pulsed

one time. A conversion may be started immediately fol-

lowing nap mode as shown in Figure 8. A period of time

allowing the reference voltage to recover must follow

waking up from sleep mode as shown in Figure 9. The

wait period required before initiating a conversion for the

The output swing on the SDO pin is controlled by the

OV pin voltage and supports a wide operating range

DD

recommended value of C of 2.2µF is 1.1ms.

REF

from 1.71V to 5.25V independent of the V pin voltage.

DD

Power Supply Sequencing

Power Considerations

The LTC2315-12 does not have any specific power sup-

ply sequencing requirements. Care should be taken to

observe the maximum voltage relationships described in

the Absolute Maximum Ratings section.

The LTC2315-12 provides two sets of power supply pins:

the analog 5V power supply (V ) and the digital input/

DD

output interface power supply (OV ). The flexible OV

DD

supply allows the LTC2315-12 to communicate with any

231512fa

12

For more information www.linear.com/LTC2315-12

LTC2315-12

APPLICATIONS INFORMATION

1

2

CS

NAP MODE

START t

ACQ

SCK

SDO

HOLD STATIC HIGH or LOW

HI-Z STATE

Z

0

231512 F08

Figure 8: LTC2315-12 Entering/Exiting Nap Mode

1

2

3

4

CS

V

RECOVERY

WAIT

REF

START t

ACQ

t

NAP MODE

SLEEP MODE

HI-Z STATE

SCK

SDO

HOLD STATIC HIGH or LOW

Z

0

231512 F09

Figure 9: LTC2315-12 Entering/Exiting Sleep Mode

Single-Ended Analog Input Drive

Choosing an Input Amplifier

The analog input of the LTC2315-12 is easy to drive. The

input draws only one small current spike while charging

the sample-and-hold capacitor at the end of conversion.

Duringtheconversion,theanaloginputdrawsonlyasmall

leakage current. If the source impedance of the driving

circuit is low, then the input of the LTC2315-12 can be

driven directly. As the source impedance increases, so

will the acquisition time. For minimum acquisition time

with high source impedance, a buffer amplifier should be

used. The main requirement is that the amplifier driving

the analog input must settle after the small current spike

beforethenextconversionstarts.Settlingtimemustbeless

Choosing an input amplifier is easy if a few requirements

are taken into consideration. First, to limit the magnitude

of the voltage spike seen by the amplifier from charging

the sampling capacitor, choose an amplifier that has a low

output impedance (<50Ω) at the closed-loop bandwidth

frequency. For example, if an amplifier is used in a gain

of 1 and has a unity-gain bandwidth of 100MHz, then the

output impedance at 100MHz must be less than 50Ω. The

second requirement is that the closed-loop bandwidth

must be greater than 100MHz to ensure adequate small

signal settling for full throughput rate. If slower op amps

are used, more time for settling can be provided by in-

creasing the time between conversions. The best choice

for an op amp to drive the LTC2315-12 will depend on the

application.Generally,applicationsfallintotwocategories:

AC applications where dynamic specifications are most

than t

(40ns) for full performance at the maximum

ACQ-MIN

throughput rate. While choosing an input amplifier, also

keep in mind the amount of noise and harmonic distortion

the amplifier contributes.

231512fa

13

For more information www.linear.com/LTC2315-12

LTC2315-12

APPLICATIONS INFORMATION

critical and time domain applications where DC accuracy

and settling time are most critical. The following list is a

summary of the op amps that are suitable for driving the

LTC2315-12. (More detailed information is available on

the Linear Technology website at www.linear.com.)

A simple 1-pole RC filter is sufficient for many applica-

tions. For example, Figure 10 shows a recommended

single-ended buffered drive circuit using the LT1818 in

unity gain mode. The 47pF capacitor from A to ground

IN

and 50Ω source resistor limits the input bandwidth to

68MHz. The47pFcapacitoralsoactsasachargereservoir

for the input sample-and-hold and isolates the LT1818

from sampling glitch kick-back. The 50Ω source resistor

is used to help stabilize the settling response of the drive

amplifier. When choosing values of source resistance

and shunt capacitance, the drive amplifier data sheet

should be consulted and followed for optimum settling

response. If lower input bandwidths are desired, care

should be taken to optimize the settling response of the

driver amplifier with higher values of shunt capacitance

or series resistance. High quality capacitors and resistors

should be used in the RC filter since these components

canadddistortion.NP0/C0Gandsilvermicatypedielectric

capacitors have excellent linearity. Carbon surface mount

resistors can generate distortion from self heating and

from damage that may occur during soldering. Metal film

surface mount resistors are much less susceptible to both

problems.Whenhighamplitudeunwantedsignalsareclose

in frequency to the desired signal frequency, a multiple

pole filter is required. High external source resistance,

combined with external shunt capacitance at Pin 4 and

13pF of input capacitance on the LTC2315-12 in sample

mode, will significantly reduce the internal 130MHz input

bandwidth and may increase the required acquisition time

LT6230: 215MHz GBWP, –80dBc Distortion at 1MHz,

Unity-Gain Stable, Rail-to-Rail Input and Output, 3.5mA/

Amplifier, 1.1nV/√Hz.

LT6200:165MHzGBWP,–85dBcDistortionat1MHz,Unity-

GainStable, R-RInandOut, 15mA/Amplifier, 0.95nV/√Hz.

LT1818/LT1819: 400MHz GBWP, –85dBc Distortion at

5MHz, Unity-Gain Stable, 9mA/Amplifier, Single/Dual

Voltage Mode Operational Amplifier.

Input Drive Circuits

TheanaloginputoftheLTC2315-12isdesignedtobedriven

single-ended with respect to GND. Alow impedance source

can directly drive the high impedance analog input of the

LTC2315-12 without gain error. A high impedance source

shouldbebufferedtominimizesettlingtimeduringacquisi-

tion and to optimize the distortion performance of the ADC.

For best performance, a buffer amplifier should be used

to drive the analog input of the LTC2315-12. The amplifier

provides low output impedance to allow for fast settling

of the analog signal during the acquisition phase. It also

provides isolation between the signal source and the ADC

inputswhichdrawasmallcurrentspikeduringacquisition.

beyond the minimum acquisition time (t

) of 40ns.

ACQ-MIN

Input Filtering

LTC2315-12

The noise and distortion of the buffer amplifier and other

circuitry must be considered since they add to the ADC

noiseanddistortion.Noisyinputcircuitryshouldbefiltered

prior to the analog inputs to minimize noise. A simple

1-pole RC filter is sufficient for many applications.

50Ω

+

–

A

ANALOG IN

IN

47pF

LT1818

GND

2315112 F10

Figure 10. RC Input Filter

Large filter RC time constants slow down the settling at

the analog inputs. It is important that the overall RC time

constants be short enough to allow the analog inputs to

completelysettleto>12-bitresolutionwithintheminimum

acquisition time (t

) of 40ns.

ACQ-MIN

231512fa

14

For more information www.linear.com/LTC2315-12

LTC2315-12

APPLICATIONS INFORMATION

ADC Reference

the internal reference voltage (see Table 2) and must be

less than or equal to the supply voltage (or 4.3V for the 5V

supply range). Forexample, a 3.3V externalreference may

A low noise, low temperature drift reference is critical to

achieving the full data sheet performance of the ADC. The

LTC2315-12 provides an excellent internal reference with

aguaranteed20ppm/°Cmaximumtemperaturecoefficient.

Foraddedflexibility,anexternalreferencemayalsobeused.

be used with a 3.3V V supply voltage to provide a 3.3V

DD

analog input voltage span (i.e. 3.3V > 2.048V + 50mV).

Or alternatively, a 2.5V reference may be used with a 3V

supply voltage to provide a 2.5V input voltage range (i.e.

2.5V > 2.048V + 50mV). The LTC6655-3.3, LTC6655-2.5,

available from Linear Technology, may be suitable for

many applications requiring a high performance external

reference for either 3.3V or 2.5V input spans respectively.

The high speed, low noise internal reference buffer is used

only in the internal reference configuration. The reference

buffer must be overdriven in the external reference con-

figuration with a voltage 50mV higher than the nominal

reference output voltage in the internal configuration.

Transfer Function

Using the Internal Reference

Figure11depictsthetransferfunctionoftheLTC2315-12.

The code transitions occur midway between successive

integer LSB values (i.e. 0.5LSB, 1.5LSB, 2.5LSB… FS-

0.5LSB). The output code is straight binary with 1LSB =

The internal bandgap and reference buffer are active by

default when the LTC2315-12 is not in sleep mode. The

reference voltage at the REF pin scales automatically with

the supply voltage at the V pin. The scaling of the refer-

V

/4,096.

REF

DD

ence voltage with supply is shown in the following table.

Table 2: Reference Voltage vs Supply Range

SUPPLY VOLTAGE (V

2.7V –> 3.6V

)

DD

REF VOLTAGE (V

2.048V

)

REF

111...111

111...110

4.75V –> 5.25V

4.096V

Thereferencevoltagealsodeterminesthefull-scaleanalog

input range of the LTC2315-12. For example, a 2.048V

referencevoltagewillaccommodateananaloginputrange

from0Vto2.048V.Ananaloginputvoltagethatgoesbelow

0V will be coded as all zeros and an analog input voltage

that exceeds 2.048V will be coded as all ones.

000...001

000...000

0 1LSB

FS – 1LSB

INPUT VOLTAGE (V)

ItisrecommendedthattheREFpinbebypassedtoground

with a low ESR, 2.2µF ceramic chip capacitor for optimum

performance.

231512 F11

Figure 11. LTC2315-12 Transfer Function

External Reference

DC Performance

An external reference can be used with the LTC2315-12

if better performance is required or to accommodate a

larger input voltage span. The only constraints are that

the external reference voltage must be 50mV higher than

The noise of an ADC can be evaluated in two ways: signal-to-

noise ratio (SNR) in the frequency domain and histogram in

thetimedomain.TheLTC2315-12excelsinboth.Thenoisein

the time domain histogram is the transition noise associated

231512fa

15

For more information www.linear.com/LTC2315-12

LTC2315-12

APPLICATIONS INFORMATION

with a 12-bit resolution ADC which can be measured with a

fixed DC signal applied to the input of the ADC. The resulting

outputcodesarecollectedoveralargenumberofconversions.

The shape of the distribution of codes will give an indication

of the magnitude of the transition noise. In Figure 12, the

distribution of output codes is shown for a DC input that has

been digitized 16,384 times. The distribution is Gaussian and

theRMScodetransitionnoiseis0.33LSB.Thiscorrespondsto

a noise level of 73dB relative to a full scale voltage of 4.096V.

Effective Number of Bits (ENOB)

The effective number of bits (ENOB) is a measurement of

the resolution of an ADC and is directly related to SINAD

by the equation where ENOB is the effective number of

bits of resolution and SINAD is expressed in dB:

ENOB = (SINAD – 1.76)/6.02

At the maximum sampling rate of 5MHz, the LTC2315-12

maintains an ENOB above 11.7 bits up to the Nyquist input

frequency of 2.5MHz. (Figure 14)

60000

σ = 0.33

Signal-to-Noise Ratio (SNR)

50000

40000

30000

20000

10000

0

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the first five harmonics and DC. Figure 13 shows

that the LTC2315-12 achieves a typical SNR of 73dB at a

5MHz sampling rate with a 500kHz input frequency.

Total Harmonic Distortion (THD)

2047

2049

CODE

2050

2051

2048

231512 F12

TotalHarmonicDistortion(THD)istheratiooftheRMSsum

ofallharmonicsoftheinputsignaltothefundamentalitself.

The out-of-band harmonics alias into the frequency band

between DC and half the sampling frequency (f

THD is expressed as:

Figure 12. Histogram for 16384 Conversions

/2).

SMPL

Dynamic Performance

The LTC2315-12 has excellent high speed sampling

capability. Fast Fourier Transform (FFT) techniques are

used to test the ADC’s frequency response, distortion and

noise at the rated throughput. By applying a low distortion

sine wave and analyzing the digital output using an FFT

algorithm, the ADC’s spectral content can be examined

for frequencies outside the applied fundamental. The

LTC2315-12 provides guaranteed tested limits for both

AC distortion and noise measurements.

V2²+ V3²+ V4²+ V_N²

THD=20log

V1

where V1 is the RMS amplitude of the fundamental fre-

quencyandV2throughV aretheamplitudesofthesecond

N

through Nth harmonics. THD versus Input Frequency is

shownintheTypicalPerformanceCharacteristicssection.

The LTC2315-12 has excellent distortion performance up

to the Nyquist frequency.

Signal-to-Noise and Distortion Ratio (SINAD)

The signal-to-noise and distortion ratio (SINAD) is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency and the RMS amplitude of all other frequency

components at the A/D output. The output is band-limited

tofrequenciesfromaboveDCandbelowhalfthesampling

frequency. Figure 14 shows the LTC2315-12 maintains a

SINAD above 71dB up to the Nyquist input frequency of

2.5MHz.

Intermodulation Distortion (IMD)

If the ADC input signal consists of more than one spectral

component, the ADC transfer function nonlinearity can

produce intermodulation distortion (IMD) in addition to

THD. IMD is the change in one sinusoidal input caused

by the presence of another sinusoidal input at a different

frequency.

231512fa

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LTC2315-12

APPLICATIONS INFORMATION

0

If two pure sine waves of frequencies f and f are ap-

a

b

V

= 5V

DD

SNR = 73.1dBFS

SINAD = 72.6dBFS

THD = –84dB

plied to the ADC input, nonlinearities in the ADC transfer

function can create distortion products at the sum and

–20

–40

SFDR = 87dBc

difference frequencies m • f n • f , where m and n = 0,

a

b

–60

1, 2, 3, etc. For example, the 2nd order IMD terms include

(f f ).Ifthetwoinputsinewavesareequalinmagnitude,

a

b

–80

the value (in decibels) of the 2nd order IMD products can

be expressed by the following formula:

–100

–120

–140

IMD(f f ) = 20 • log[V (f f )/V (f )]

a

b

A

a

b

A

a

500

1000

The LTC2315-12 has excellent IMD as shown in Figure 15.

0

1500

2000

2500

FREQUENCY (kHz)

231512 F13

Spurious Free Dynamic Range (SFDR)

Figure 13. 16k Point FFT of the LTC2315-12 at f_IN= 500 kHz

The spurious free dynamic range is the largest spectral

componentexcludingDC,theinputsignalandtheharmon-

icsincludedintheTHD. Thisvalueisexpressedindecibels

relative to the RMS value of a full-scale input signal.

74

73

72

71

70

69

12.0

11.8

11.7

11.5

11.3

11.2

V

= 5V

= 3V

DD

Full-Power and Full-Linear Bandwidth

The full-power bandwidth is the input frequency at which

theamplitudeofthereconstructedfundamentalisreduced

by 3dB for a full-scale input signal.

V

DD

The full-linear bandwidth is the input frequency at which

the SINAD has dropped to 68dB (11 effective bits). The

LTC2315-12 has been designed to optimize the input

bandwidth,allowingtheADCtounder-sampleinputsignals

withfrequenciesabovetheconverter’sNyquistfrequency.

The noise floor stays very low at high frequencies and

SINAD becomes dominated by distortion at frequencies

beyond Nyquist.

0

1500

2000

2500

500

1000

INPUT FREQUENCY (kHz)

231512 F14

Figure 14. LTC2315-12 ENOB/SINAD vs f_IN

0

V

= 5V

= 5Msps

f = 461.421kHz

= 541.421kHz

DD

f

S

–20

–40

a

b

f

Recommended Layout

IMD (f + f ) = –77.4dBc

2

3

b

a

IMD (2fb –f ) = –89.4dBc

–60

To obtain the best performance from the LTC2315-12 a

printed circuit board is required. Layout for the printed

circuit board (PCB) should ensure the digital and analog

signal lines are separated as much as possible. In particu-

lar, care should be taken not to run any digital clocks or

signals alongside analog signals or underneath the ADC.

ThefollowingisanexampleofarecommendedPCBlayout.

A single solid ground plane is used. Bypass capacitors to

the supplies are placed as close as possible to the supply

pins. Low impedance common returns for these bypass

capacitors are essential to the low noise operation of the

–80

–100

–120

–140

–160

0

1500

2000

2500

500

1000

INPUT FREQUENCY (kHz)

231512 F15

Figure 15. LTC2315-12 IMD Plot

231512fa

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For more information www.linear.com/LTC2315-12

LTC2315-12

APPLICATIONS INFORMATION

ADC. The analog input traces are screened by ground.

For more details and information refer to DC1563, the

evaluation kit for the LTC2315-12.

parator. The problem can be eliminated by forcing the

microprocessor into a “Wait” state during conversion or

by using three-state buffers to isolate the ADC data bus.

Bypassing Considerations

High quality tantalum and ceramic bypass capacitors

should be used at the V , OV and REF pins. For opti-

DD

mum performance, a 2.2µF ceramic chip capacitor should

be used for the V and OV pins. The recommended

DD

bypassing for the REF pin is also a low ESR, 2.2µF ceramic

capacitor. The traces connecting the pins and the bypass

capacitors must be kept as short as possible and should

be made as wide as possible avoiding the use of vias.

ThefollowingisanexampleofarecommendedPCBlayout.

All analog circuitry grounds should be terminated at the

LTC2315-12. The ground return from the LTC2315-12 to

the power supply should be low impedance for noise free

operation. Digital circuitry grounds must be connected to

the digital supply common.

In applications where the ADC data outputs and control

signals are connected to a continuously active micropro-

cessor bus, it is possible to get errors in the conversion

results. These errors are due to feed-through from the

microprocessor to the successive approximation com-

Figure 17. Layer 1 Top Layer

Figure 18. Layer 2 GND Plane

Figure 16. Top Silkscreen

231512fa

18

For more information www.linear.com/LTC2315-12

LTC2315-12

APPLICATIONS INFORMATION

Figure 19. Layer 3 PWR Plane

Figure 20. Layer 4 Bottom Layer

REF

+

C6

C7

4.7µF

OPT

U5

LT1790ACS6-2.048

9V TO 10V

V

DD

VCCIO

VCM

4

6

VI

VO

GND GND

C8

10µF

R9

1k

C9

4.7µF

C10

OPT

C11

OPT

C12

4.7µF

1

2

AC DC

JP1

COUPLING

1

2

5

HD1X3-100

U1

*

1 2

3

V

DD

REF OV

DD

8

7

6

CSL

SCK

R14

0k

R15

49.9Ω

CSL

SCK

SDO

J4

4

A

IN

A

IN

0V TO 4.096V

C18

OPT

SDO

C19

47pF

NPO

C17

1µF

GND

3

JP2

R16

33Ω

V

231512 F21

CM

3

2

1

1.024V

2.048V

HD1X3-100

R18

1k

Figure 21. Partial DC1563 Demo Board Schematic

231512fa

19

For more information www.linear.com/LTC2315-12

LTC2315-12

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

TS8 Package

8-Lead Plastic TSOT-23

(Reference LTC DWG # 05-08-1637 Rev A)

2.90 BSC

(NOTE 4)

0.40

MAX

0.65

REF

1.22 REF

1.4 MIN

1.50 – 1.75

(NOTE 4)

2.80 BSC

3.85 MAX 2.62 REF

PIN ONE ID

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

0.22 – 0.36

8 PLCS (NOTE 3)

0.65 BSC

0.80 – 0.90

0.20 BSC

DATUM ‘A’

0.01 – 0.10

1.00 MAX

0.30 – 0.50 REF

1.95 BSC

TS8 TSOT-23 0710 REV A

0.09 – 0.20

(NOTE 3)

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. JEDEC PACKAGE REFERENCE IS MO-193

231512fa

20

For more information www.linear.com/LTC2315-12

LTC2315-12

REVISION HISTORY

REV

DATE

10/13 Added pin-compatible family table

Changed T to 150°C

DESCRIPTION

PAGE NUMBER

A

1

2

JMAX

Changed SINAD condition for –3dB Input Linear Bandwidth to ≥68dB

Reordered/Renumbered Notes

3, 16

3, 4, 5

231512fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

21

For more information www.linear.com/LTC2315-12

LTC2315-12

TYPICAL APPLICATION

Low-Jitter Clock Timing with RF Sine Generator Using Clock

Squaring/Level-Shifting Circuit and Re-Timing Flip-Flop

V

CC

NC7SVU04P5X

0.1µF

1k

MASTER CLOCK

CC

V

50Ω

PRE

CLR

D

CONV

Q

>

CONTROL

LOGIC

(FPGA, CPLD,

DSP, ETC.)

NL17SZ74

CONV ENABLE

CS

SCK

LTC2315-12

NC7SVUO4P5X

SDO

33Ω

231512 TA03

RELATED PARTS

PART NUMBER

ADCs

DESCRIPTION

COMMENTS

LTC2313-12

12-Bit, 2.5Msps Serial ADC

12-Bit, 500ksps Serial ADC

12-Bit, 2.8Msps Serial ADC

3V/5V, 14mW/25mW, 20ppm/°C Max Internal Reference,

Single-Ended Input, 8-Lead TSOT-23 Package

LTC2312-12

3V/5V, 9mW/15mW, 20ppm/°C Max Internal Reference,

Single-Ended Input, 8-Lead TSOT-23 Package

LTC1403/LTC1403-1

LTC1407/LTC1407-1

3V, 14mW, Unipolar/Bipolar Inputs, MSOP Package

12-Bit, 3Msps Simultaneous Sampling ADC

3V, 2-Channel Differential, Unipolar/Bipolar Inputs, 14mW,

MSOP Package

LTC2355/LTC2356

LTC2365/LTC2366

Amplifiers

12-/14-Bit, 3.5Msps Serial ADC

3.3V Supply, Differential, Input, 18mW, MSOP Package

3.3V Supply, 8mW, TSOT-23 Package

12-Bit, 1Msps/3Msps Serial Sampling ADC

LT6236/LT6237

Single/Dual Operation Amplifier with Low

Wideband Noise

215MHz, 3.5mA/Amplifier, 1.1nV/√Hz

LT6200/LT6201

LT6230/LT6231

LT1818/LT1819

References

Single/Dual Operational Amplifiers

165MHz, 0.95nV/√Hz

215MHz, 3.5mA/Amplifier, 1.1nV/√Hz

400MHz, 9mA/Amplifier, 6nV/√Hz

LTC6655-2.5/LTC6655-3.3 Precision Low Drift Low Noise Buffered Reference 2.5V/3.3V, 5ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package

LT1461-3/LT1461-3.3V Precision Series Voltage Family 0.05% Initial Accuracy, 3ppm Drift

231512fa

LT 1013 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

22

For more information www.linear.com/LTC2315-12

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2315-12

●

 LINEAR TECHNOLOGY CORPORATION 2013


型号：	LTC2315ITS8-12#TRMPBF
厂家：	Linear
描述：	LTC2315-12 - 12-Bit, 5Msps Serial Sampling ADC in TSOT; Package: SOT; Pins: 8; Temperature Range: -40°C to 85°C 光电二极管转换器
文件：	总22页 (文件大小：689K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2315ITS8-12#TRMPBF [Linear]

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