LTC2320CUKG-12#PBF [Linear]
LTC2320-12 - Octal, 12-Bit + Sign, 1.5Msps/Ch Simultaneous Sampling ADC; Package: QFN; Pins: 52; Temperature Range: 0°C to 70°C;型号: | LTC2320CUKG-12#PBF |
厂家: | Linear |
描述: | LTC2320-12 - Octal, 12-Bit + Sign, 1.5Msps/Ch Simultaneous Sampling ADC; Package: QFN; Pins: 52; Temperature Range: 0°C to 70°C 转换器 |
文件: | 总32页 (文件大小:1632K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC2320-12
Octal, 12-Bit + Sign,
1.5Msps/Ch Simultaneous
Sampling ADC
FeaTures
DescripTion
The LTC®2320-12 is a low noise, high speed octal 12-bit
+ sign successive approximation register (SAR) ADC with
differential inputs and wide input common mode range.
Operatingfromasingle3.3Vor5Vsupply,theLTC2320-12
n
1.5Msps/Ch Throughput Rate
n
Eight Simultaneously Sampling Channels
n
Guaranteed 12-Bit, No Missing Codes
n
8V Differential Inputs with Wide Input
P-P
Common Mode Range
has an 8V differential input range, making it ideal for
P-P
n
n
n
n
n
77dB SNR (Typ) at f = 500kHz
applications which require a wide dynamic range with
high common mode rejection. The LTC2320-12 achieves
0.25LSB INL typical, no missing codes at 12 bits and
77dB SNR.
IN
IN
–90dB THD (Typ) at f = 500kHz
Guaranteed Operation to 125°C
Single 3.3V or 5V Supply
Low Drift (20ppm/°C Max) 2.048V or 4.096V
Internal Reference
TheLTC2320-12hasanonboardlowdrift(20ppm/°Cmax)
2.048V or 4.096V temperature-compensated reference.
The LTC2320-12 also has a high speed SPI-compatible
serial interface that supports CMOS or LVDS. The fast
1.5Msps per channel throughput with no latency makes
the LTC2320-12 ideally suited for a wide variety of high
speedapplications.TheLTC2320-12dissipatesonly20mW
per channel and offers nap and sleep modes to reduce the
power consumption to 26μW for further power savings
during inactive periods.
n
n
n
n
1.8V to 2.5V I/O Voltages
CMOS or LVDS SPI-Compatible Serial I/O
Power Dissipation 20mW/Ch (Typ)
Small 52-Lead (7mm × 8mm) QFN Package
applicaTions
n
High Speed Data Acquisition Systems
n
Communications
n
Remote Data Acquisition
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
n
Imaging
n
Optical Networking
n
Automotive
n
Multiphase Motor Control
10µF
1µF
Typical applicaTion
1.8V TO 2.5V
3.3V OR 5V
32k Point FFT fSMPL = 1.5Msps,
TRUE DIFFERENTIAL INPUTS
V
GND
GND OV
DD
fIN = 500kHz
DD
+
–
NO CONFIGURATION REQUIRED
A
IN1
IN1
S/H
CMOS/LVDS
SDR/DDR
REFBUFEN
A
12-BIT
+ SIGN
SAR ADC
0
–20
+
–
MUX
IN , IN
SNR = 78.4dB
+
–
A
A
IN2
IN2
S/H
THD = –90.9dB
SINAD = 78.2dB
SFDR = 95.2dB
ARBITRARY
DIFFERENTIAL
V
V
DD
0V
DD
0V
+
–
A
A
IN3
IN3
S/H
SDO1
SDO2
SDO3
SDO4
SDO5
SDO6
SDO7
SDO8
CLKOUT
SCK
12-BIT
+ SIGN
SAR ADC
–40
MUX
+
–
A
A
IN4
IN4
S/H
–60
LTC2320-12
+
–
A
A
IN5
IN5
S/H
12-BIT
+ SIGN
SAR ADC
–80
BIPOLAR
UNIPOLAR
MUX
+
–
V
V
DD
0V
DD
0V
A
A
IN6
IN6
S/H
–100
–120
–140
CNV
SAMPLE
CLOCK
+
–
A
A
IN7
IN7
S/H
12-BIT
+ SIGN
SAR ADC
MUX
+
–
A
A
IN8
IN8
S/H
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7
REF
REFOUT1 REFOUT2 REFOUT3 REFOUT4
232012 TA01a
FREQUENCY (MHz)
EIGHT SIMULTANEOUS
SAMPLING CHANNELS
1µF
10µF
232012 TA01b
10µF
10µF
10µF
232012fa
1
For more information www.linear.com/LTC2320-12
LTC2320-12
absoluTe MaxiMuM raTings
pin conFiguraTion
(Notes 1, 2)
TOP VIEW
Supply Voltage (V )..................................................6V
DD
Supply Voltage (OV )................................................3V
DD
Analog Input Voltage
52 51 50 49 48 47 46 45 44 43 42 41
–
–
+
+
–
A
A
1
2
40 SDO8/SDOD
39 SDO7/SDOD
IN6
A
, A (Note 3) ................... –0.3V to (V + 0.3V)
IN
IN DD
+
IN6
REFOUT1,2,3,4........................ .–0.3V to (V + 0.3V)
DD
DD
GND
–
GND
OV
3
38
37
CNV........................................ –0.3V to (OV + 0.3V)
A
4
IN5
DD
+
–
+
A
5
36 SDO6/SDOC
SDO5/SDOC
35
IN5
Digital Input Voltage
REFOUT3
GND
6
(Note 3).......................... (GND – 0.3V) to (OV + 0.3V)
–
DD
7
34 CLKOUTEN/CLKOUT
53
GND
+
Digital Output Voltage
REF
8
33 CLKOUT/CLKOUT
REFOUT2
–
9
32 GND
(Note 3).......................... (GND – 0.3V) to (OV + 0.3V)
DD
A
A
10
11
31 OV
DD
IN4
Operating Temperature Range
+
–
+
–
+
30 SDO4/SDOB
29 SDO3/SDOB
28 SDO2/SDOA
27 SDO1/SDOA
IN4
LTC2320C................................................ 0°C to 70°C
LTC2320I .............................................–40°C to 85°C
LTC2320H.......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
GND 12
–
A
A
13
14
IN3
+
IN3
15 16 17 18 19 20 21 22 23 24 25 26
UKG PACKAGE
52-LEAD (7mm × 8mm) PLASTIC QFN
T
JMAX
= 150°C, θ = 31°C/W
JA
EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB
http://www.linear.com/product/LTC2320-12#orderinfo
orDer inForMaTion
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
LTC2320UKG-12
LTC2320UKG-12
LTC2320UKG-12
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC2320CUKG-12#PBF
LTC2320IUKG-12#PBF
LTC2320HUKG-12#PBF
LTC2320CUKG-12#TRPBF
LTC2320IUKG-12#TRPBF
LTC2320HUKG-12#TRPBF
52-Lead (7mm × 8mm) Plastic QFN
52-Lead (7mm × 8mm) Plastic QFN
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 85°C
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
232012fa
2
For more information www.linear.com/LTC2320-12
LTC2320-12
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
+
+
–
–
l
l
l
l
l
V
V
V
V
Absolute Input Range (A to A
)
)
(Note 5)
0
V
DD
V
DD
IN
IN
IN
IN
IN
IN
–
+
+
Absolute Input Range (A to A
(Note 5)
0
V
IN
–
+
–
– V
Input Differential Voltage Range
Common Mode Input Range
V
V
= V – V
–REFOUT1,2,3,4
REFOUT1,2,3,4
V
IN
IN
IN
IN
+
–
= (V – V )/2
0
V
DD
V
CM
CM
IN
IN
I
IN
Analog Input DC Leakage Current
Analog Input Capacitance
–1
1
μA
pF
dB
V
C
IN
10
CMRR
Input Common Mode Rejection Ratio
CNV High Level Input Voltage
CNV Low Level Input Voltage
CNV Input Current
f
IN
= 500kHz
102
l
l
l
V
V
1.5
IHCNV
ILCNV
INCNV
0.5
10
V
I
–10
μA
converTer characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL PARAMETER
CONDITIONS
MIN
12
TYP
MAX
UNITS
Bits
l
l
Resolution
No Missing Codes
12
Bits
Transition Noise
0.2
0.25
0.4
0
LSB
RMS
l
l
l
INL
Integral Linearity Error
Differential Linearity Error
Bipolar Zero-Scale Error
Bipolar Zero-Scale Error Drift
Bipolar Full-Scale Error
Bipolar Full-Scale Error Drift
(Note 6)
(Note 7)
–1
1
LSB
DNL
BZE
–0.99
–1.5
0.99
1.5
LSB
LSB
0.005
0
LSB/°C
LSB
l
FSE
V
V
= 4.096V (REFBUFEN Grounded) (Note 7)
= 4.096V (REFBUFEN Grounded)
–3
3
REFOUT1,2,3,4
15
ppm/°C
REFOUT1,2,3,4
DynaMic accuracy The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dBFS (Notes 4, 8).
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
77
MAX
UNITS
dB
l
l
l
l
SINAD
Signal-to-(Noise + Distortion) Ratio f = 500kHz, V
= 4.096V, Internal Reference
= 5V, External Reference
= 4.096V, Internal Reference
= 5V, External Reference
= 4.096V, Internal Reference
= 5V, External Reference
= 4.096V, Internal Reference
= 5V, External Reference
74
IN
REFOUT1,2,3,4
REFOUT1,2,3,4
REFOUT1,2,3,4
REFOUT1,2,3,4
REFOUT1,2,3,4
REFOUT1,2,3,4
REFOUT1,2,3,4
REFOUT1,2,3,4
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
= 500kHz, V
= 500kHz, V
= 500kHz, V
= 500kHz, V
= 500kHz, V
= 500kHz, V
= 500kHz, V
77
dB
SNR
Signal-to-Noise Ratio
75
76
77
dB
77.5
–90
–91
93
dB
THD
Total Harmonic Distortion
Spurious Free Dynamic Range
–76
dB
dB
SFDR
dB
93
dB
–3dB Input Bandwidth
Aperture Delay
55
MHz
ps
500
500
1
Aperture Delay Matching
Aperture Jitter
ps
ps
RMS
Transient Response
Full-Scale Step
30
ns
232012fa
3
For more information www.linear.com/LTC2320-12
LTC2320-12
inTernal reFerence characTerisTics The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
Internal Reference Output Voltage
4.75V < V < 5.25V
4.078
2.034
4.096
2.048
4.115
2.064
V
V
REFOUT1,2,3,4
DD
3.13V < V < 3.47V
DD
l
V
Temperature Coefficient
(Note 14)
3
20
ppm/°C
Ω
REF
REFOUT1,2,3,4 Output Impedance
Line Regulation
0.25
0.3
V
4.75V < V < 5.25V
mV/V
REFOUT1,2,3,4
DD
I
External Reference Current
REFBUFEN = 0V
REFOUT1,2,3,4
REFOUT1,2,3,4 = 4.096V
REFOUT1,2,3,4 = 2.048V
(Notes 9, 10)
385
204
μA
μA
DigiTal inpuTs anD DigiTal ouTpuTs The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL PARAMETER
CONDITIONS
CMOS/LVDS = GND
MIN
0.8 • OV
–10
TYP
MAX
UNITS
CMOS Digital Inputs and Outputs
l
l
l
l
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
V
V
IH
IL
DD
0.2 • OV
DD
I
V
IN
= 0V to OV
DD
10
μA
pF
IN
C
IN
Digital Input Capacitance
5
l
l
V
V
High Level Output Voltage
Low Level Output Voltage
I = –500μA
OV – 0.2
V
V
OH
OL
O
DD
I = 500μA
O
0.2
10
l
l
l
I
I
I
Hi-Z Output Leakage Current
Output Source Current
Output Sink Current
V
OUT
V
OUT
V
OUT
= 0V to OV
DD
–10
μA
mA
mA
OZ
= 0V
= OV
–10
10
SOURCE
SINK
DD
LVDS Digital Inputs and Outputs
CMOS/LVDS = OV
DD
l
l
l
l
l
l
V
V
V
V
V
V
LVDS Differential Input Voltage
LVDS Common Mode Input Voltage
LVDS Differential Output Voltage
LVDS Common Mode Output Voltage
100Ω Differential Termination
DD
240
1
600
1.45
600
1.4
mV
V
ID
OV = 2.5V
100Ω Differential Termination
OV = 2.5V
DD
IS
100Ω Differential Termination
OV = 2.5V
DD
220
0.85
100
0.85
350
1.2
mV
V
OD
100Ω Differential Termination
OV = 2.5V
DD
OS
Low Power LVDS Differential Output Voltage 100Ω Differential Termination
200
1.2
350
1.4
mV
V
OD_LP
OS_LP
OV = 2.5V
DD
Low Power LVDS Common Mode Output Voltage 100Ω Differential Termination
OV = 2.5V
DD
232012fa
4
For more information www.linear.com/LTC2320-12
LTC2320-12
power requireMenTs The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
V
Supply Voltage
5V Operation
3.3V Operation
4.75
3.13
5.25
3.47
V
V
DD
+
–
l
IV
DD
Supply Current
1.5Msps Sample Rate (IN = IN = 0V)
31
38
mA
CMOS I/O Mode
CMOS/LVDS = GND
Supply Voltage
l
l
l
l
OV
1.71
2.63
7
V
mA
mA
µA
DD
OVDD
NAP
I
I
I
Supply Current
1.5Msps Sample Rate (C = 5pF)
4.4
5.3
20
L
Nap Mode Current
Sleep Mode Current
Power Dissipation
Conversion Done (I
)
6.2
110
VDD
Sleep Mode (I
+ I
)
OVDD
SLEEP
VDD
l
l
l
P
V
= 3.3V, 1.5Msps Sample Rate
DD
102
18
20
130
266
355
mW
mW
µW
D_3.3V
Nap Mode
Sleep Mode
l
l
l
P
D_5V
Power Dissipation
V
= 5V, 1.5Msps Sample Rate
162
27
30
208
31.2
525
mW
mW
µW
DD
Nap Mode
Sleep Mode
LVDS I/O Mode
CMOS/LVDS = OV , OV = 2.5V
DD DD
l
l
l
l
OV
Supply Voltage
Supply Current
2.37
2.63
34
V
mA
mA
µA
DD
OVDD
NAP
I
I
I
1.5Msps Sample Rate (C = 5pF, R = 100Ω)
26
5.3
20
L
L
Nap Mode Current
Sleep Mode Current
Power Dissipation
Conversion Done (I
)
6.2
VDD
Sleep Mode (I
+ I )
OVDD
110
SLEEP
VDD
l
l
l
P
V
= 3.3V, 1.5Msps Sample Rate
DD
151
52
80
196
60
355
mW
mW
µW
D_3.3V
Nap Mode
Sleep Mode
l
l
l
P
D_5V
Power Dissipation
V
= 5V, 1.5Msps Sample Rate
214
51
30
275
685
525
mW
mW
µW
DD
Nap Mode
Sleep Mode
aDc TiMing characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
CONDITIONS
MIN
0.667
30
TYP
MAX
1.5
UNITS
Msps
µs
l
l
l
l
f
t
t
t
t
t
Maximum Sampling Frequency
Time Between Conversions
Conversion Time
SMPL
(Note 11) t
= t
+ t
+ t
READOUT
1000
450
CYC
CYC
CNVH
CONV
ns
CONV
CNV High Time
ns
CNVH
Sampling Aperture
(Note 11) t
= t
– t
CONV
215
50
ns
ACQUISITION
WAKE
ACQUISITION
CYC
REFOUT1,2,3,4 Wake-Up Time
C
= 10µF
ms
REFOUT1,2,3,4
CMOS I/O Mode, SDR
CMOS/LVDS = GND, SDR/ DDR = GND
l
l
l
l
l
t
t
t
t
t
SCK Period
(Note 13)
9.1
4.1
4.1
0
ns
ns
ns
ns
ns
SCK
SCK High Time
SCKH
SCK Low Time
SCKL
SDO Data Remains Valid Delay from CLKOUT
SCK to CLKOUT Delay
C = 5pF (Note 12)
L
1.5
4.5
HSDO_SDR
DSCKCLKOUT
(Note 12)
2
232012fa
5
For more information www.linear.com/LTC2320-12
LTC2320-12
aDc TiMing characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
CONDITIONS
(Note 11)
(Note 11)
(Note 11)
MIN
TYP
MAX
UNITS
ns
l
l
l
t
t
t
Bus Relinquish Time After CNV
SDO Valid Delay from CNV
SCK Delay Time to CNV
3
3
DCNVSDOZ
DCNVSDOV
DSCKHCNVH
ns
0
ns
CMOS I/O Mode, DDR
CMOS/LVDS = GND, SDR/ DDR = OV
DD
l
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
SCK Period
18.2
8.2
8.2
0
ns
ns
ns
ns
ns
ns
ns
ns
SCK
SCK High Time
SCKH
SCK Low Time
SCKL
SDO Data Remains Valid Delay from CLKOUT
SCK to CLKOUT Delay
Bus Relinquish Time After CNV
SDO Valid Delay from CNV
SCK Delay Time to CNV
C = 5pF (Note 12)
1.5
4.5
3
HSDO_DDR
DSCKCLKOUT
DCNVSDOZ
DCNVSDOV
DSCKHCNVH
L
(Note 12)
(Note 11)
(Note 11)
(Note 11)
2
3
0
LVDS I/O Mode, SDR
CMOS/LVDS = OV , SDR/DDR = GND
DD
l
l
l
l
l
l
t
t
t
t
t
t
SCK Period
3.3
1.5
1.5
0
ns
ns
ns
ns
ns
ns
SCK
SCK High Time
SCKH
SCK Low Time
SCKL
SDO Data Remains Valid Delay from CLKOUT
SCK to CLKOUT Delay
SCK Delay Time to CNV
C = 5pF OV = 2.5V
1.5
4
HSDO_SDR
DSCKCLKOUT
DSCKHCNVH
L
DD
OV = 2.5V
DD
2
(Note 11)
0
LVDS I/O Mode, DDR
CMOS/LVDS = OV , SDR/DDR = OV
DD DD
l
l
l
l
l
l
t
t
t
t
t
t
SCK Period
6.6
3
ns
ns
ns
ns
ns
ns
SCK
SCK High Time
SCKH
SCK Low Time
3
SCKL
SDO Data Remains Valid Delay from CLKOUT
SCK to CLKOUT Delay
SCK Delay Time to CNV
C = 5pF OV = 2.5V
0
1.5
4
HSDO_DDR
DSCKCLKOUT
DSCKHCNVH
L
DD
OV = 2.5V
DD
2
(Note 11)
0
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
deviation from ideal first and last code transitions and includes the effect
of offset error.
Note 8: All specifications in dB are referred to a full-scale 4.096V input
with REF = 4.096V.
Note 2: All voltage values are with respect to ground.
Note 9: When REFOUT1,2,3,4 is overdriven, the internal reference buffer
Note 3: When these pin voltages are taken below ground, or above V or
must be turned off by setting REFBUFEN = 0V.
DD
OV , they will be clamped by internal diodes. This product can handle input
DD
Note 10: f
= 1.5MHz, I
varies proportionally with sample rate.
SMPL
REFOUT1,2,3,4
currents up to 100mA below ground, or above V or OV , without latch-up.
DD
DD
Note 11: Guaranteed by design, not subject to test.
Note 12: Parameter tested and guaranteed at OV = 1.71V and OV = 2.5V.
Note 13: t
rising edge capture.
Note 14: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 15: CNV is driven from a low jitter digital source, typically at OV
logic levels.
Note 4: V = 5V, OV = 2.5V, REFOUT1,2,3,4 = 4.096V, f = 1.5MHz.
SMPL
DD
DD
DD
DD
Note 5: Recommended operating conditions.
of 9.1ns allows a shift clock frequency up to 105MHz for
SCK
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 0 and 1111 1111
1111 1. Full-scale bipolar error is the worst-case of –FS or +FS untrimmed
DD
232012fa
6
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LTC2320-12
aDc TiMing characTerisTics
0.8 • OV
DD
t
WIDTH
0.2 • OV
DD
50%
50%
t
t
DELAY
DELAY
232012 F01
0.8 • OV
0.8 • OV
0.2 • OV
DD
DD
DD
DD
0.2 • OV
Figure 1. Voltage Levels for Timing Specifications
232012fa
7
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LTC2320-12
Typical perForMance characTerisTics
TA = 25°C, VDD = 5V, OVDD = 2.5V, REFOUT1,2,3,4
= 4.096V, fSMPL = 1.5Msps, unless otherwise noted.
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
DC Histogram
1.00
0.75
0.50
0.25
0
1.0
0.5
70000
52500
35000
17500
0
Right Click In Graph Area for Menu
Double Click In Graph Area for Data Setup
0
–0.25
–0.50
–0.75
–1.00
–0.5
–1.0
–4096
–2048
0
2048
4096
–4096
–2048
0
2048
4096
–2
–1
0
1
2
OUTPUT CODE
OUTPUT CODE
CODE
232012 G01
232012 G02
232012 G03
THD, Harmonics vs Input
Frequency (1kHz to 750kHz)
32k Point FFT, fSMPL = 1.5Msps,
fIN = 500kHz
SNR, SINAD vs Input Frequency
(1kHz to 750kHz)
80.0
79.5
79.0
78.5
78.0
77.5
77.0
76.5
76.0
75.5
75.0
–80
–84
0
–20
SNR = 78.4dB
THD = –90.9dB
SINAD = 78.2dB
SFDR = 95.2dB
–88
SNR
THD
–40
–92
–96
SINAD
–60
–100
–104
–108
–112
–116
–120
HD3
–80
HD2
–100
–120
–140
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
232012 G05
232012 G06
232012 G04
THD, Harmonics vs Input Common
Mode
SNR, SINAD vs Reference Voltage,
fIN = 500kHz
32k Point FFT, IMD, fSMPL =1.5Msps,
AIN+ = 490kHz, AIN– = 510kHz
–80
–84
0
80
78
76
74
72
70
68
66
64
THD = 87dB
f
= 500kHz
f
= 500kHz
IN
IN
SNR
V
= 20kHz, 4V
CM
P-P
–20
–40
–88
SINAD
THD
–92
–96
–60
–100
–104
–108
–112
–116
–120
HD2
HD3
–80
–100
–120
–140
1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
INPUT COMMON MODE (V)
FREQUENCY (MHz)
V
(V)
REFOUT
232012 G07
232012 G09
232012 G08
232012fa
8
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LTC2320-12
Typical perForMance characTerisTics
TA = 25°C, VDD = 5V, OVDD = 2.5V, REFOUT1,2,3,4
= 4.096V, fSMPL = 1.5Msps, unless otherwise noted.
Step Response
(Large Signal Settling)
4096
CMRR vs Input Frequency
Crosstalk vs Input Frequency
–90
–91
–92
–93
–94
–95
–96
–97
–98
–99
–100
120
115
110
105
100
95
V
= 4V
P-P
CM
3072
2048
4.096V RANGE
1024
0
IN+ = 1.5MHz SQUARE WAVE
IN– = 0V
–1024
90
0
100 200 300 400 500 600 700
–20 –10
0
10 20 30 40 50 60 70 80 90
0
500
1000
1500
FREQUENCY (kHz)
SETTLING TIME (ns)
FREQUENCY (kHz)
232012 G11
232012 G12
232012 G10
Step Response
(Fine Settling)
External Reference Supply
Current vs Sample Frequency
REF Output vs Temperature
100
80
400
350
300
250
200
150
100
50
1.00
0.50
REFBUFEN = 0V
(EXT REF BUF
V
= 3.3V
60
DD
OVERDRIVING REF BUF)
0
40
–0.50
–1.00
–1.50
–2.00
–2.50
–3.00
20
V
= 4.096V
REFOUT1,2,3,4
0
V
= 5V
DD
–20
–40
–60
–80
–100
4.096V RANGE
IN+ = 1.5MHz
SQUARE WAVE
V
= 2.048V
REFOUT1,2,3,4
IN– = 0V
0
–20 –10
0
10 20 30 40 50 60 70 80 90
0
0.3
0.6
0.9
1.2
1.5
–55 –35 –15
5
25 45 65 85 105 125
SETTLING TIME (ns)
SAMPLE FREQUENCY (Msps)
TEMPERATURE (°C)
232012 G13
232012 G14
232012 G15
Supply Current
vs Sample Frequency
OVDD Current vs SCK Frequency,
CLOAD = 10pF
Offset Error vs Temperature
0.250
0.125
0
33
31
29
27
25
23
21
19
8
7
6
5
4
3
2
1
0
32
FULL SCALE SINUSOIDAL INPUT
30
LVDS (4 LANES)
28
26
24
22
20
18
16
14
12
CMOS (2.5V, 8 LANES)
V
= 5V
DD
CMOS(1.8V, 8 LANES)
V
= 3.3V
DD
–0.125
LOW POWER LVDS (4 LANES)
–0.250
–55 –35 –15
5
25 45 65 85 105 125
0
0.3
0.6
0.9
1.2
1.5
0
50
100
150
200
250
300
TEMPERATURE (°C)
SAMPLE FREQUENCY (Msps)
SCK FREQUENCY (MHz)
232012 G16
232012 G17
232012 G18
232012fa
9
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LTC2320-12
pin FuncTions
Pins that are the same for all digital I/O modes.
V
(Pins 15, 21, 44, 52): Power Supply. Bypass V to
DD DD
GND with a 10µF ceramic capacitor and a 0.1µF ceramic
+
–
A
, A
(Pins 2, 1): Analog Differential Input Pins.
IN6
IN6
capacitorclosetothepart. TheV pinsshouldbeshorted
together and driven from the same supply.
+
–
DD
Full-scale range (A
These pins can be driven from V to GND.
– A
) is REFOUT3 voltage.
DD
IN6
IN6
+
–
A
IN2
, A
(Pins 17, 16): Analog Differential Input Pins.
IN2
GND (Pins 3, 7, 12, 18, 26, 32, 38, 46, 49): Ground.
These pins and exposed pad (Pin 53) must be tied directly
to a solid ground plane.
+
–
Full-scale range (A
– A
) is REFOUT1 voltage.
IN2
IN2
These pins can be driven from V to GND.
DD
+
–
A
IN1
, A
(Pins 20, 19): Analog Differential Input Pins.
+
–
IN1
A
IN5
, A
(Pins 5, 4): Analog Differential Input Pins.
IN5
+
–
Full-scale range (A
– A
) is REFOUT1 voltage.
+
–
IN1
IN1
Full-scale range (A
These pins can be driven from V to GND.
– A
) is REFOUT3 voltage.
IN5
IN5
These pins can be driven from V to GND.
DD
DD
REFOUT1(Pin22):ReferenceBuffer1Output.Anonboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the
pin with a 10µF (X5R, 0805 size) ceramic capacitor. The
internal buffer driving this pin may be disabled by ground-
ing the REFBUFEN pin. If the buffer is disabled, an external
reference may drive this pin in the range of 1.25V to 5V.
REFOUT3 (Pin 6): Reference Buffer 3 Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the
pin with a 10µF (X5R, 0805 size) ceramic capacitor. The
internal buffer driving this pin may be disabled by ground-
ing the REFBUFEN pin. If the buffer is disabled, an external
reference may drive this pin in the range of 1.25V to 5V.
SDR/DDR (Pin 23): Double Data Rate Input. Controls the
frequency of SCK and CLKOUT. Tie to GND for the falling
edge of SCK to shift each serial data output (Single Data
REF (Pin 8): Common 4.096V reference output. Decouple
to GND with a 1μF low ESR ceramic capacitor. May be
overdriven with a single external reference to establish a
common reference for ADC cores 1 through 4.
Rate, SDR). Tie to OV to shift serial data output on each
DD
edge of SCK (Double Data Rate, DDR). CLKOUT will be a
delayed version of SCK for both pin states.
REFOUT2 (Pin 9): Reference Buffer 2 Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the
pin with a 10µF (X5R, 0805 size) ceramic capacitor. The
internal buffer driving this pin may be disabled by ground-
ing the REFBUFEN pin. If the buffer is disabled, an external
reference may drive this pin in the range of 1.25V to 5V.
CNV (Pin 24): Convert Input. This pin, when high, defines
the acquisition phase. When this pin is driven low, the
conversion phase is initiated and output data is clocked
out. This input must be driven at OV levels with a low
DD
jitter pulse. This pin is unaffected by the CMOS/LVDS pin.
CMOS/LVDS (Pin 25): I/O Mode Select. Ground this pin
+
–
A
, A
(Pins 11, 10): Analog Differential Input Pins.
IN4
IN4
to enable CMOS mode, tie to OV to enable LVDS mode.
+
–
DD
Full-scale range (A
These pins can be driven from V to GND.
– A
) is REFOUT2 voltage.
IN4
IN4
Float this pin to enable low power LVDS mode.
DD
OV (Pins 31, 37): I/O Interface Digital Power. The range
+
–
DD
A
IN3
, A
(Pins 14, 13): Analog Differential Input Pins.
IN3
of OV is 1.71V to 2.63V. This supply is nominally set
+
–
DD
Full-scale range (A
These pins can be driven from V to GND.
– A
) is REFOUT2 voltage.
IN3
IN3
to the same supply as the host interface (CMOS: 1.8V or
DD
2.5V, LVDS: 2.5V). Bypass OV to GND (Pins 32 and 38)
DD
with 0.1µF capacitors.
232012fa
10
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LTC2320-12
pin FuncTions
REFBUFEN (Pin 43): Reference Buffer Output Enable. Tie
SDO3 (Pin 29): CMOS Serial Data Output for ADC Chan-
nel 3. The conversion result is shifted MSB first on each
falling edge of SCK in SDR mode and each SCK edge in
DDR mode. 13 SCK edges are required for 13-bit conver-
sion data to be read from SDO3 in SDR mode, 13 SCK
edges in DDR mode. Supplying more clocks will yield
data from subsequent channels (CH4, CH5, CH6, CH7,
CH8, CH1, CH2).
to V when using the internal reference. Tie to ground
DD
to disable the internal REFOUT1–4 buffers for use with
external voltage references. This pin has a 500k internal
pull-up to V .
DD
REFOUT4 (Pin45):ReferenceBuffer4Output.Anonboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the
pin with a 10µF (X5R, 0805 size) ceramic capacitor. The
internal buffer driving this pin may be disabled by ground-
ing the REFBUFEN pin. If the buffer is disabled, an external
reference may drive this pin in the range of 1.25V to 5V.
SDO4 (Pin 30): CMOS Serial Data Output for ADC Chan-
nel 4. The conversion result is shifted MSB first on each
falling edge of SCK in SDR mode and each SCK edge in
DDR mode. 13 SCK edges are required for 13-bit conver-
sion data to be read from SDO4 in SDR mode, 13 SCK
edges in DDR mode. Supplying more clocks will yield
data from subsequent channels (CH5, CH6, CH7, CH8,
CH1, CH2, CH3).
+
–
A
, A
(Pins 48, 47): Analog Differential Input Pins.
IN8
IN8
+
–
Full-scale range (A
These pins can be driven from V to GND.
– A
) is REFOUT4 voltage.
IN8
IN8
DD
+
–
A
IN7
, A
(Pins 51, 50): Analog Differential Input Pins.
IN7
CLKOUT (Pin 33): Serial Data Clock Output. CLKOUT
provides a skew-matched clock to latch the SDO output
at the receiver (FPGA). The logic level is determined by
+
–
Full-scale range (A
These pins can be driven from V to GND.
– A
) is REFOUT4 voltage.
IN7
IN7
DD
Exposed Pad (Pin 53): Ground. Solder this pad to ground.
OV . This pin echoes the input at SCK with a small delay.
DD
CLKOUTEN (Pin 34): CLKOUT can be disabled by tying
CMOS DATA OUTPUT OPTION (CMOS/LVDS = LOW)
Pin 34 to OV for a small power savings. If CLKOUT is
DD
used, ground this pin.
SDO1 (Pin 27): CMOS Serial Data Output for ADC Chan-
nel 1. The conversion result is shifted MSB first on each
falling edge of SCK in SDR mode and each SCK edge in
DDR mode. 13 SCK edges are required for 13-bit conver-
sion data to be read from SDO1 in SDR mode, 13 SCK
edges in DDR mode. Supplying more clocks will yield
data from subsequent channels (CH2, CH3, CH4, CH5,
CH6, CH7, CH8).
SDO5 (Pin 35): CMOS Serial Data Output for ADC Chan-
nel 5. The conversion result is shifted MSB first on each
falling edge of SCK in SDR mode and each SCK edge in
DDR mode. 13 SCK edges are required for 13-bit conver-
sion data to be read from SDO5 in SDR mode, 13 SCK
edges in DDR mode. Supplying more clocks will yield
data from subsequent channels (CH6, CH7, CH8, CH1,
CH2, CH3, CH4).
SDO2 (Pin 28): CMOS Serial Data Output for ADC Chan-
nel 2. The conversion result is shifted MSB first on each
falling edge of SCK in SDR mode and each SCK edge in
DDR mode. 13 SCK edges are required for 13-bit conver-
sion data to be read from SDO2 in SDR mode, 13 SCK
edges in DDR mode. Supplying more clocks will yield
data from subsequent channels (CH3, CH4, CH5, CH6,
CH7, CH8, CH1).
SDO6 (Pin 36): CMOS Serial Data Output for ADC Chan-
nel 6. The conversion result is shifted MSB first on each
falling edge of SCK in SDR mode and each SCK edge in
DDR mode. 13 SCK edges are required for 13-bit conver-
sion data to be read from SDO6 in SDR mode, 13 SCK
edges in DDR mode. Supplying more clocks will yield
data from subsequent channels (CH7, CH8, CH1, CH2,
CH3, CH4, CH5).
232012fa
11
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LTC2320-12
pin FuncTions
each SCK edge in DDR mode. 32 SCK edges are required
for 13-bit conversion data to be read from A and A
on SDOB in SDR mode, 13 SCK edges in DDR mode.
Supplying more clocks will yield data from subsequent
channels (CH5, CH6, CH7, CH8, CH1, CH2).Terminate
with a 100Ω resistor at the receiver (FPGA).
SDO7 (Pin 39): CMOS Serial Data Output for ADC Chan-
nel 7. The conversion result is shifted MSB first on each
falling edge of SCK in SDR mode and each SCK edge in
DDR mode. 13 SCK edges are required for 13-bit conver-
sion data to be read from SDO7 in SDR mode, 13 SCK
edges in DDR mode. Supplying more clocks will yield
data from subsequent channels (CH8, CH1, CH2, CH3,
CH4, CH5, CH6).
IN3
IN4
+
–
CLKOUT , CLKOUT (Pins 33, 34): Serial Data Clock
Output. CLKOUT provides a skew-matched clock to
latch the SDO output at the receiver. These pins echo the
input at SCK with a small delay. These pins must be dif-
ferentially terminated by an external 100Ω resistor at the
receiver (FPGA).
SDO8 (Pin 40): CMOS Serial Data Output for ADC Chan-
nel 8. The conversion result is shifted MSB first on each
falling edge of SCK in SDR mode and each SCK edge in
DDR mode. 13 SCK edges are required for 13-bit conver-
sion data to be read from SDO8 in SDR mode, 13 SCK
edges in DDR mode. Supplying more clocks will yield
data from subsequent channels (CH1, CH2, CH3, CH4,
CH5, CH6, CH7).
+
–
SDOC , SDOC (Pins 35, 36): LVDS Serial Data Output for
ADCchannels5and6.TheconversionresultisshiftedCH5
MSB first on each falling edge of SCK in SDR mode and
each SCK edge in DDR mode. 32 SCK edges are required
for 13-bit conversion data to be read from A and A
SCK (Pin 41): Serial Data Clock Input. The falling edge
of this clock shifts the conversion result MSB first onto
the SDO pins in SDR mode (DDR = LOW). In DDR mode
(SDR/DDR = HIGH) each edge of this clock shifts the
conversion result MSB first onto the SDO pins. The logic
IN5
IN6
on SDOA in SDR mode, 13 SCK edges in DDR mode.
Supplying more clocks will yield data from subsequent
channels (CH7, CH8, CH1, CH2, CH3, CH4).Terminate
with a 100Ω resistor at the receiver (FPGA).
level is determined by OV .
+
–
DD
SDOD , SDOD (Pins 39, 40): LVDS Serial Data Output
for ADC Channels 7 and 8. The conversion result is shifted
CH7 MSB first on each falling edge of SCK in SDR mode
and each SCK edge in DDR mode. 32 SCK edges are re-
DNC (Pin 42): In CMOS mode do not connect this pin.
LVDS DATA OUTPUT OPTION (CMOS/LVDS = HIGH OR
FLOAT)
quired for 13-bit conversion data to be read from A and
IN7
A
IN8
on SDOA in SDR mode, 13 SCK edges in DDR mode.
+
–
SDOA , SDOA (Pins 27, 28): LVDS Serial Data Output for
ADCChannels1and2.TheconversionresultisshiftedCH1
MSB first on each falling edge of SCK in SDR mode and
each SCK edge in DDR mode. 32 SCK edges are required
Supplying more clocks will yield data from subsequent
channels (CH1, CH2, CH3, CH4, CH5, CH6).Terminate
with a 100Ω resistor at the receiver (FPGA).
+
–
SCK , SCK (Pins 41, 42): Serial Data Clock Input. The
falling edge of this clock shifts the conversion result MSB
first onto the SDO pins in SDR mode (SDR/DDR = LOW).
In DDR mode (SDR/DDR = HIGH) each edge of this clock
shifts the conversion result MSB first onto the SDO pins.
Thesepinsmustbedifferentiallyterminatedbyanexternal
100Ω resistor at the receiver (ADC).
for 13-bit conversion data to be read from A and A
IN1
IN2
on SDOA in SDR mode, 13 SCK edges in DDR mode.
Supplying more clocks will yield data from subsequent
channels (CH3, CH4, CH5, CH6, CH7, CH8).Terminate
with a 100Ω resistor at the receiver (FPGA).
+
–
SDOB , SDOB (Pins 29, 30): LVDS Serial Data Output for
ADCChannels3and4.TheconversionresultisshiftedCH3
MSB first on each falling edge of SCK in SDR mode and
232012fa
12
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LTC2320-12
FuncTional block DiagraM
CMOS IO Mode
V
GND
DD
24
CNV
(15, 21, 44, 52)
(3, 7, 12, 18, 26, 32, 38, 46, 49, 53)
+
–
A
A
IN1
+
–
20
19
S/H
IN1
SDO1
27
CMOS
I/O
12-BIT + SIGN
SAR ADC
+
–
MUX
SDO2
A
A
IN2
28
+
17
16
S/H
IN2
–
REFOUT1
22
×1
REF
+
–
A
A
IN3
+
–
14
13
S/H
IN3
SDO3
29
CMOS
I/O
12-BIT + SIGN
SAR ADC
MUX
+
–
SDO4
A
A
IN4
30
+
11
10
S/H
IN4
–
REFOUT2
9
×1
REF
CLKOUT
33
SCK
41
42
CMOS
RECEIVERS
OUTPUT
CLOCK DRIVER
DNC
CLKOUTEN
34
+
SDR/DDR
23
A
A
IN5
+
5
4
–
S/H
–
IN5
SDO6
SDO6
35
36
CMOS
I/O
12-BIT + SIGN
SAR ADC
+
–
MUX
A
A
IN6
+
2
1
S/H
IN6
–
REFOUT3
×1
REF
6
+
–
A
A
IN7
+
51
50
S/H
–
IN7
SDO7
SDO8
39
40
CMOS
I/O
12-BIT + SIGN
SAR ADC
MUX
+
–
A
A
IN8
+
48
47
S/H
IN8
–
REFOUT4
×1
REF
45
250μA
OV (31, 37)
DD
REF
×1.7
×3.4
8
1.2V INT REF
REFBUFEN
43
25
CMOS/LVDS
232012 BDa
232012fa
13
For more information www.linear.com/LTC2320-12
LTC2320-12
FuncTional block DiagraM
LVDS IO Mode
V
GND
DD
24
CNV
(15, 21, 44, 52)
(3, 7, 12, 18, 26, 32, 38, 46, 49, 53)
+
–
A
A
IN1
+
–
20
19
S/H
IN1
+
–
SDOA
SDOA
27
28
LVDS
I/O
12-BIT + SIGN
SAR ADC
+
–
MUX
A
A
IN2
+
17
16
S/H
IN2
–
REFOUT1
×1
REF
22
+
–
A
A
IN3
+
–
14
13
S/H
IN3
+
SDOB
29
30
LVDS
I/O
12-BIT + SIGN
SAR ADC
–
MUX
+
–
SDOB
A
A
IN4
+
11
10
S/H
IN4
–
REFOUT2
×1
REF
9
+
+
–
CLKOUT
SCK
SCK
41
42
33
34
LVDS
RECEIVERS
OUTPUT
CLOCK DRIVER
–
CLKOUT
+
SDR/DDR
23
A
A
IN5
+
5
4
–
S/H
–
IN5
+
SDOC
35
36
LVDS
I/O
12-BIT + SIGN
SAR ADC
–
+
–
SDOC
MUX
A
A
IN6
+
2
1
S/H
IN6
–
REFOUT3
×1
REF
6
+
–
A
A
IN7
+
51
50
S/H
–
IN7
+
SDOD
39
40
LVDS
I/O
12-BIT + SIGN
SAR ADC
–
MUX
+
–
SDOD
A
A
IN8
+
48
47
S/H
IN8
–
REFOUT4
×1
REF
45
250μA
OV (31, 37)
DD
REF
×1.7
×3.4
8
1.2V INT REF
REFBUFEN
43
25
CMOS/LVDS
232012 BDb
232012fa
14
For more information www.linear.com/LTC2320-12
LTC2320-12
TiMing DiagraM
SDR Mode, CMOS (Reading 1 Channel per SDO)
SAMPLE N
SAMPLE N+1
CNV
CONVERT
ACQUIRE
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SCK
Hi-Z
Hi-Z
CLKOUT
Hi-Z
Hi-Z
SDO1
DONT CARE
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
D12
CHANNEL 1
CONVERSION N
CHANNEL 2
CONVERSION N
Hi-Z
Hi-Z
SDO8
DONT CARE
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
D12
CHANNEL 8
CONVERSION N
CHANNEL 1
CONVERSION N
232012 TD01
DDR Mode, CMOS (Reading 1 Channel per SDO)
SAMPLE N
SAMPLE N+1
CNV
CONVERT
ACQUIRE
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SCK
Hi-Z
Hi-Z
CLKOUT
SDO1
Hi-Z
Hi-Z
DONT CARE
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
D12
CHANNEL 1
CONVERSION N
CHANNEL 2
CONVERSION N
Hi-Z
Hi-Z
SDO8
DONT CARE
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
D12
CHANNEL 1
CONVERSION N
CHANNEL 8
CONVERSION N
232012 TD02
232012fa
15
For more information www.linear.com/LTC2320-12
LTC2320-12
TiMing DiagraM
SDR Mode, LVDS (Reading 2 Channels per SDO Pair)
SAMPLE N
SAMPLE N+1
CNV
CONVERT
ACQUIRE
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SCK
CLKOUT
SDOA
DONT CARE
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
D12
CHANNEL 1
CONVERSION N
CHANNEL 2
CONVERSION N
CHANNEL 3
CONVERSION N
SDOD
DONT CARE
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
D12
CHANNEL 7
CONVERSION N
CHANNEL 8
CONVERSION N
CHANNEL 1
CONVERSION N
232012 TD03
DDR Mode, LVDS (Reading 2 Channels per SDO Pair)
SAMPLE N
SAMPLE N+1
ACQUIRE
CNV
CONVERT
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SCK
CLKOUT
SDOA
DONT CARE
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
D12
CHANNEL 1
CONVERSION N
CHANNEL 2
CONVERSION N
CHANNEL 3
CONVERSION N
SDOD
DONT CARE
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
D12
CHANNEL 7
CONVERSION N
CHANNEL 8
CONVERSION N
CHANNEL 1
CONVERSION N
232012 TD04
232012fa
16
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LTC2320-12
applicaTions inForMaTion
OVERVIEW
TRANSFER FUNCTION
The LTC2320-12 digitizes the full-scale voltage of 2 •
The LTC2320-12 is a low noise, high speed 12-bit succes-
sive approximation register (SAR) ADC with differential
inputs and a wide input common mode range. Operating
from a single 3.3V or 5V supply, the LTC2320-12 has a
13
REFOUT into 2 levels, resulting in an LSꢀ size of 1mV
withREFꢀUF=4.096V.Theidealtransferfunctionisshown
in Figure 2. The output data is in 2’s complement format.
When driven by fully differential inputs, the transfer func-
4V or 8V differential input range, making it ideal for
P-P
P-P
13
tion spans 2 codes. When driven by pseudo-differential
applications which require a wide dynamic range. The
LTC2320-12 achieves 0.25LSꢀ INL typical, no missing
codes at 12 bits and 77dꢀ SNR.
12
inputs, the transfer function spans 2 codes.
0 1111 1111 1111
0 1111 1111 1110
The LTC2320-12 has an onboard reference buffer and low
drift (20ppm/°C max) 4.096V temperature-compensated
reference. The LTC2320-12 also has a high speed SPI-
compatible serial interface that supports CMOS or LVDS.
The fast 1.5Msps per channel throughput with no latency
makes the LTC2320-12 ideally suited for a wide variety of
high speed applications. The LTC2320-12 dissipates only
20mWperchannel.Napandsleepmodesarealsoprovided
to reduce the power consumption of the LTC2320-12 dur-
ing inactive periods for further power savings.
0 0000 0000 0001
0 0000 0000 0000
1 1111 1111 1111
2 • REFOUT
8192
1LSB =
1 0000 0000 0001
1 0000 0000 0000
–REFOUT
–1
LSB
0
1
LSB
REFOUT – 1LSB
INPUT VOLTAGE (V)
232012 F02
Figure 2. LTC2320-12 Transfer Function
CONVERTER OPERATION
The LTC2320-12 operates in two phases. During the ac-
quisition phase, the sample capacitor is connected to the
V
V
DD
C
IN
R
15Ω
+
–
ON
10pF
analog input pins A and A to sample the differential
IN
IN
+
A
A
IN
analoginputvoltage,asshowninFigure3.Afallingedgeon
the CNV pin initiates a conversion. During the conversion
phase,the12-bitCDACissequencedthroughasuccessive
approximationalgorithmeffectivelycomparingthesampled
input with binary-weighted fractions of the reference volt-
BIAS
VOLTAGE
DD
C
IN
R
15Ω
ON
10pF
–
232012 F03
age (e.g., V /2, V
REFOUT
/4 … V
REFOUT
/32768) using
REFOUT
IN
adifferentialcomparator. Attheendofconversion, aCDAC
output approximates the sampled analog input. The ADC
control logic then prepares the 12-bit digital output code
for serial transfer.
Figure 3. The Equivalent Circuit for the Differential
Analog Input of the LTC2320-12
Table 1. Code Ranges for the Analog Input Operational Modes
+
–
MODE
SPAN (V – V
)
MIN CODE
MAX CODE
IN
IN
Fully Differential
–REFOUT to +REFOUT
–-REFOUT/2 to +REFOUT/2
0 to REFOUT
1 0000 0000 0000
1 1000 0000 0000
0 0000 0000 0000
0 1111 1111 1111
0 0111 1111 1111
0 1111 1111 1111
Pseudo-Differential ꢀipolar
Pseudo-Differential Unipolar
232012fa
17
For more information www.linear.com/LTC2320-12
LTC2320-12
applicaTions inForMaTion
Analog Input
by the high CMRR of the ADC. The LTC2320-12 flexibility
handles both pseudo-differential unipolar and bipolar
signals,withnoconfigurationrequired.Thewidecommon
mode input range relaxes the accuracy requirements of
anysignalconditioningcircuitspriortotheanaloginputs.
The differential inputs of the LTC2320-12 provide great
flexibility to convert a wide variety of analog signals with
no configuration required. The LTC2320-12 digitizes the
+
–
difference voltage between the A and A pins while
IN
IN
supporting a wide common mode input range. The analog
Pseudo-Differential Bipolar Input Range
input signals can have an arbitrary relationship to each
The pseudo-differential bipolar configuration represents
driving one of the analog inputs at a fixed voltage, typically
other, provided that they remain between V and GND.
DD
The LTC2320-12 can also digitize more limited classes of
analog input signals such as pseudo-differential unipolar/
bipolarandfullydifferentialwithnoconfigurationrequired.
V
/2, and applying a signal to the other A pin. In this
REF
IN
case the analog input swings symmetrically around the
fixedinputyieldingbipolartwo’scomplementoutputcodes
with an ADC span of half of full-scale. This configuration
is illustrated in Figure 4, and the corresponding transfer
function in Figure 5. The fixed analog input pin need not
The analog inputs of the LTC2320-12 can be modeled
by the equivalent circuit shown in Figure 3. The back-
to-back diodes at the inputs form clamps that provide
ESD protection. In the acquisition phase, 10pF (C )
IN
be set at V /2, but at some point within the V rails
REF
DD
from the sampling capacitor in series with approximately
allowingthealternateinputtoswingsymmetricallyaround
15Ω(R )fromtheon-resistanceofthesamplingswitch
+
–
ON
thisvoltage.Iftheinputsignal(A –A )swingsbeyond
IN
IN
is connected to the input. Any unwanted signal that is
common to both inputs will be reduced by the common
mode rejection of the ADC sampler. The inputs of the
ADC core draw a small current spike while charging the
REFOUT1,2,3,4/2, valid codes will be generated by the
ADC and must be clamped by the user, if necessary.
Pseudo-Differential Unipolar Input Range
C capacitors during acquisition.
IN
The pseudo-differential unipolar configuration represents
driving one of the analog inputs at ground and applying a
Single-Ended Signals
signal to the other A pin. In this case, the analog input
IN
Single-ended signals can be directly digitized by the
LTC2320-12. These signals should be sensed pseudo-
differentially for improved common mode rejection. ꢀy
connecting the reference signal (e.g., ground sense) of
swings between ground and V yielding unipolar two’s
REF
complement output codes with an ADC span of half of
full-scale. This configuration is illustrated in Figure 6, and
thecorrespondingtransferfunctioninFigure7.Iftheinput
the main analog signal to the other A pin, any noise or
+
–
IN
signal (A – A ) swings negative, valid codes will be
IN
IN
disturbance common to the two signals will be rejected
V
V
REF
REF
LT1819
LTC2320-12
+
25Ω
25Ω
+
–
0V
0V
A
REFOUT1
IN1
10µF
1µF
V
REF
REF
220pF
10k
V
/2
REF
+
–
V
/2
REF
–
TO CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
A
SDO1
CLKOUT
SCK
IN1
10k
1µF
ONLY CHANNEL 1 SHOWN FOR CLARITY
232012 F04
Figure 4. Pseudo-Differential Bipolar Application Circuit
232012fa
18
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LTC2320-12
applicaTions inForMaTion
ADC CODE
(2’s COMPLEMENT)
4095
2047
A
IN
+
–
(A – A
)
IN
IN
–V
–V /2
REF
0
V
REF
/2
V
REF
REF
DOTTED REGIONS AVAILABLE
–2048
–4096
232012 F05
Figure 5. Pseudo-Differential Bipolar Transfer Function
V
REF
LT1818
LTC2320-12
+
V
REF
25Ω
25Ω
+
–
0V
A
REFOUT1
IN1
0V
10µF
1µF
REF
220pF
–
TO CONTROL
LOGIC
A
SDO1
CLKOUT
SCK
IN1
(FPGA, CPLD,
DSP, ETC.)
232012 F06
Figure 6. Pseudo-Differential Unipolar Application Circuit
ADC CODE
(2’s COMPLEMENT)
4095
2047
A
IN
+
–
(A – A
)
IN
IN
–V
–V /2
REF
0
V
REF
/2
V
REF
REF
DOTTED REGIONS AVAILABLE
BUT UNUSED
–2048
–4096
232012 F07
Figure 7. Pseudo-Differential Unipolar Transfer Function
232012fa
19
For more information www.linear.com/LTC2320-12
LTC2320-12
applicaTions inForMaTion
generated by the ADC and must be clamped by the user,
if necessary.
Fully-Differential Inputs
To achieve the best distortion performance of the
LTC2320-12, we recommend driving a fully-differential
signal through LT1819 amplifiers configured as two
unity-gain buffers, as shown in Figure 9. This circuit
achieves the full data sheet THD specification of –90dꢀ at
input frequencies up to 500kHz. A fully-differential input
signal can span the maximum full-scale of the ADC, up to
REFOUT1,2,3,4. The common mode input voltage can
Single-Ended-to-Differential Conversion
Whilesingle-endedsignalscanbedirectlydigitizedaspre-
viously discussed, single-ended to differential conversion
circuits may also be used when higher dynamic range is
desired. ꢀy producing a differential signal at the inputs of
the LTC2320-12, the signal swing presented to the ADC is
maximized, thus increasing the achievable SNR.
span the entire supply range up to V , limited by the
DD
input signal swing. The fully-differential configuration is
illustrated in Figure 10, with the corresponding transfer
function illustrated in Figure 11.
The LT®1819 high speed dual operational amplifier is
recommendedforperformingsingle-ended-to-differential
conversions, as shown in Figure 8. In this case, the first
amplifier is configured as a unity-gain buffer and the
single-ended input signal directly drives the high imped-
ance input of this amplifier.
V
REF
LT1819
V
V
REF
V
LT1819
REF
+
–
0V
V
REF
+
–
0V
0V
0V
V
REF
V
REF
/2
+
–
REF
0V
200Ω
V
REF
+
–
0V
0V
200Ω
232012 F08
232012 F09
Figure 8. Single-Ended to Differential Driver
Figure 9. LT1819 Buffering a Fully-Differential Signal Source
V
V
REF
REF
0V
LT1819
LTC2320-12
+
25Ω
25Ω
+
–
0V
A
A
REFOUT1
IN1
10µF
1µF
REF
220pF
V
V
REF
0V
REF
+
–
0V
–
TO CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
SDO1
CLKOUT
SCK
IN1
ONLY CHANNEL 1 SHOWN FOR CLARITY
232012 F10
Figure 10. Fully-Differential Application Circuit
232012fa
20
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LTC2320-12
applicaTions inForMaTion
ADC CODE
(2’s COMPLEMENT)
SINGLE-ENDED
INPUT SIGNAL
+
50Ω
IN
4095
2047
LTC2320
–
IN
3.3nF
SINGLE-ENDED
TO DIFFERENTIAL
232012 F12
DRIVER
BW = 1MHz
A
IN
+
–
(A
– A
)
INn
INn
–V
–V /2
REF
0
V
REF
/2
V
REF
REF
Figure 12. Input Signal Chain
–2048
–4096
Highqualitycapacitorsandresistorsshouldbeusedinthe
RCfilterssincethesecomponentscanadddistortion.NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occurduringsoldering.Metalfilmsurfacemountresistors
are much less susceptible to both problems.
232012 F11
Figure 11. Fully-Differential Transfer Function
INPUT DRIVE CIRCUITS
A low impedance source can directly drive the high im-
pedance inputs of the LTC2320-12 without gain error. A
high impedance source should be buffered to minimize
settling time during acquisition and to optimize the dis-
tortion performance of the ADC. Minimizing settling time
is important even for DC inputs, because the ADC inputs
draw a current spike when during acquisition.
ADC REFERENCE
Internal Reference
The LTC2320-12 has an on-chip, low noise, low
drift (20ppm/°C max), temperature compensated band-
gap reference. It is internally buffered and is available
at REF (Pin 8). The reference buffer gains the internal
For best performance, a buffer amplifier should be used to
drive the analog inputs of the LTC2320-12. The amplifier
provides low output impedance to minimize gain error
and allows for fast settling of the analog signal during
the acquisition phase. It also provides isolation between
the signal source and the ADC inputs, which draw a small
current spike during acquisition.
reference voltage to 4.096V for supply voltages V = 5V
DD
and to 2.048V for V = 3.3V. The REF pin also drives
DD
the four internal reference buffers with a current limited
output (250μA) so it may be easily overdriven with an
external reference in the range of 1.25V to 5V. ꢀypass
REF to GND with a 1μF (X5R, 0805 size) ceramic capacitor
to compensate the reference buffer and minimize noise.
The 1μF capacitor should be as close as possible to the
LTC2320-12 package to minimize wiring inductance. The
voltage on the REF pin must be externally buffered if used
for external circuitry.
Input Filtering
The noise and distortion of the buffer amplifier and signal
sourcemustbeconsideredsincetheyaddtotheADCnoise
and distortion. Noisy input signals should be filtered prior
to the buffer amplifier input with a low bandwidth filter to
minimizenoise.Thesimple1-poleRClowpassfiltershown
in Figure 12 is sufficient for many applications.
External Reference
The internal REFOUT1,2,3,4 buffers can also be over-
driven from 1.25V to 5V with an external reference at
REFOUT1,2,3,4 as shown in Figure 13 (c). To do so,
REFꢀUFEN must be grounded to disable the REF buffers.
A 55k internal resistance loads the REFOUT1,2,3,4 pins
when the REF buffers are disabled. To maximize the input
The sampling switch on-resistance (R ) and the sample
capacitor (C ) form a second lowpass filter that limits
the input bandwidth to the ADC core to 110MHz. A buffer
amplifier with a low noise density must be selected to
minimize the degradation of the SNR over this bandwidth.
ON
IN
232012fa
21
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LTC2320-12
applicaTions inForMaTion
Table 2. Reference Configurations and Ranges
REFOUT1,2,3,4
PIN
DIFFERENTIAL INPUT
RANGE PIN
REFERENCE CONFIGURATION
V
REFBUFEN
5V
REF PIN
4.096V
DD
Internal Reference with Internal ꢀuffers
5V
4.096V
4.096V
3.3V
5V
3.3V
5V
2.048V
2.048V
2.048V
Common External Reference with Internal ꢀuffer (REF Pin
Externally Overdriven)
1.25V to 5V
1.25V to 5V
4.096V
1.25V to 3.3V
1.25V to 3.3V
1.25V to 5V
1.25V to 3.3V
1.25V to 5V
1.25V to 3.3V
1.25V to 5V
1.25V to 3.3V
3.3V
5V
3.3V
0V
External Reference with REF ꢀuffers Disabled
3.3V
0V
2.048V
V
3.3V TO 5V
DD
V
+5V
DD
5V TO
13.2V
REFBUFEN
REF
REFBUFEN
REF
LTC6655-4.096
V
V
IN
OUT_F
V
OUT_S
1µF
LTC2320-12
SHDN
LTC2320-12
10µF
REFOUT1
REFOUT2
REFOUT3
REFOUT4
0.1µF
REFOUT1
REFOUT2
REFOUT3
10µF
10µF
10µF
10µF
10µF
10µF
REFOUT4
10µF
GND
10µF
GND
232012 F13a
232012 F13b
(13a) LTC2320-12 Internal Reference Circuit
(13b) LTC2320-12 with a Shared External Reference Circuit
V
+5V
DD
REFBUFEN
REF
1µF
5V TO 13.2V
5V TO 13.2V
5V TO 13.2V
5V TO 13.2V
LTC6655-4.096
V
V
IN
OUT_F
V
OUT_S
REFOUT1
SHDN
10µF
10µF
10µF
10µF
0.1µF
0.1µF
0.1µF
0.1µF
LTC2320-12
LTC6655-2.048
V
V
REFOUT2
REFOUT3
IN
OUT_F
V
OUT_S
SHDN
LTC6655-2.5
V
V
IN
OUT_F
SHDN
V
OUT_S
LTC6655-3
V
V
IN
OUT_F
V
OUT_S
REFOUT4
SHDN
GND
232012 F13c
(13c) LTC2320-12 with Different External Reference Voltages
Figure 13. Reference Connections
232012fa
22
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LTC2320-12
applicaTions inForMaTion
4096
3072
2048
1024
0
signal swing and corresponding SNR, the LTC6655-5 is
recommendedwhenoverdrivingREFOUT. TheLTC6655-5
offers the same small size, accuracy, drift and extended
temperature range as the LTC6655-4.096. ꢀy using a 5V
reference, a higher SNR can be achieved. We recommend
bypassing the LTC6655-5 with a 10μF ceramic capacitor
(X5R, 0805 size) close to each of the REFOUT1,2,3,4
pins. If the REF pin voltage is used as a REFOUT refer-
ence when REFꢀUFEN is connected to GND, it should be
buffered externally.
4.096V RANGE
IN+ = 1.5MHz SQUARE WAVE
IN– = 0V
10 20 30 40 50 60 70 80 90
SETTLING TIME (ns)
–1024
–20 –10
0
232012 F15
Internal Reference Buffer Transient Response
Figure 15. Transient Response of the LTC2320-12
conversion cycle. If the internal reference buffer is over-
driven,theexternalreferencemustprovideallofthischarge
DYNAMIC PERFORMANCE
Fast Fourier transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. ꢀy applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequen-
cies outside the fundamental. The LTC2320-12 provides
guaranteed tested limits for both AC distortion and noise
measurements.
with a DC current equivalent to I
= Q
/t
.
REF
CONV CYC
Thus, the DC current draw of I
depends
REFOUT1,2,3,4
on the sampling rate and output code. In applications
where a burst of samples is taken after idling for long
periods, as shown in Figure 14 , I
quickly goes from
REFꢀUF
approximately~75µAtoamaximumof500µAforREFOUT
= 5V at 1.5Msps. This step in DC current draw triggers a
transient response in the external reference that must be
considered since any deviation in the voltage at REFOUT
will affect the accuracy of the output code. If an external
reference is used to overdrive REFOUT1,2,3,4, the fast
settling LTC6655 reference is recommended.
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is bandlimited
tofrequenciesfromaboveDCandbelowhalfthesampling
frequency.Figure16 showsthattheLTC2320-12achieves
a typical SINAD of 77dꢀ at a 1.5MHz sampling rate with
a 500kHz input.
CNV
IDLE
PERIOD
232012 F14
Figure 14. CNV Waveform Showing Burst Sampling
Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 16 shows
that the LTC2320-12 achieves a typical SNR of 77dꢀ at a
1.5MHz sampling rate with a 500kHz input.
232012fa
23
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LTC2320-12
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0
supply voltage drops below 2V. Once the supply voltage
re-enters the nominal supply voltage range, the POR will
reinitialize the ADC. No conversions should be initiated
until 10ms after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
SNR = 78.4dB
THD = –90.9dB
–20
–40
SINAD = 78.2dB
SFDR = 95.2dB
–60
–80
33
31
29
–100
–120
–140
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7
V
= 5V
DD
FREQUENCY (MHz)
27
25
23
21
19
232012 F16
Figure 16. 32k Point FFT of the LTC2320-12
V
= 3.3V
DD
Total Harmonic Distortion (THD)
Totalharmonicdistortion(THD)istheratiooftheRMSsum
ofallharmonicsoftheinputsignaltothefundamentalitself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (f
THD is expressed as:
0
0.3
0.6
0.9
1.2
1.5
SAMPLE FREQUENCY (Msps)
232012 F17
/2).
SMPL
Figure 17. Power Supply Current of the LTC2320-12
Versus Sampling Rate
2
V22 +V32 +V42 + …+VN
THD=20log
TIMING AND CONTROL
V1
CNV Timing
where V1 is the RMS amplitude of the fundamental
frequency and V2 through V are the amplitudes of the
N
The LTC2320-12 sampling and conversion is controlled
by CNV. A rising edge on CNV will start sampling and the
fallingedgestartstheconversionandreadoutprocess.The
conversion process is timed by the SCK input clock. For
optimum performance, CNV should be driven by a clean
low jitter signal. The Typical Application at the back of the
data sheet illustrates a recommended implementation to
reduce the relatively large jitter from an FPGA CNV pulse
source. Note the low jitter input clock times the falling
edge of the CNV signal. The rising edge jitter of CNV is
much less critical to performance. The typical pulse width
of the CNV signal is 30ns with < 1.5ns rise and fall times
at a 1.5Msps conversion rate.
second through Nth harmonics.
POWER CONSIDERATIONS
The LTC2320-12 requires two power supplies: the 3.3V
to 5V power supply (V ), and the digital input/output
DD
interface power supply (OV ). The flexible OV supply
DD
DD
allows the LTC2320-12 to communicate with any digital
logic operating between 1.8V and 2.5V. When using LVDS
I/O, the OV supply must be set to 2.5V.
DD
Power Supply Sequencing
The LTC2320-12 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2320-12
has a power-on-reset (POR) circuit that will reset the
LTC2320-12 at initial power-up or whenever the power
SCK Serial Data Clock Input
In SDR mode (SDR/DDR Pin 23 = GND), the falling edge
of this clock shifts the conversion result MSꢀ first onto
the SDO pins. A 100MHz external clock must be applied at
232012fa
24
For more information www.linear.com/LTC2320-12
LTC2320-12
applicaTions inForMaTion
the SCK pin to achieve 1.5Msps throughput using all eight
SDO outputs. In DDR mode (SDR/DDR Pin 23 = OV ),
each input edge of SCK shifts the conversion result MSB
first onto the SDO pins. A 50MHz external clock must be
applied at the SCK pin to achieve 1.5Msps throughput
using all eight SDO1 through SDO8 outputs.
two CNV pulses must be applied. This is the case for both
CMOS and LVDS modes. The second rising edge of CNV
initiates the nap state. The nap state will persist until either
asinglerisingedgeofSCKisapplied,orfurtherCNVpulses
are applied. The SCK rising edge will put the LTC2320-12
back into the operational (full-power) state. When in nap
mode, two additional pulses will put the LTC2320-12 in
sleep mode. When configured for CMOS I/O operation, a
single rising edge of SCK can return the LTC2320-12 into
operational mode. A 10ms delay is necessary after exiting
sleep mode to allow the reference buffer to recharge the
external filter capacitor. In LVDS mode, exit sleep mode
by supplying a fifth CNV pulse. The fifth pulse will return
the LTC2320-12 to operational mode, and further SCK
pulses will keep the part from re-entering nap and sleep
modes. The fifth SCK pulse also works in CMOS mode
as a method to exit sleep. In the absence of SCK pulses,
repetitive CNV pulses will cycle the LTC2320-12 between
operational, nap and sleep modes indefinitely.
DD
CLKOUT Serial Data Clock Output
The CLKOUT output provides a skew-matched clock to
latch the SDO output at the receiver. The timing skew
of the CLKOUT and SDO outputs are matched. For high
throughput applications, using CLKOUT instead of SCK to
capture the SDO output eases timing requirements at the
receiver. For low throughput speed applications, CLKOUT
can be disabled by tying Pin 34 to OV .
DD
Nap/Sleep Modes
Nap mode is a method to save power without sacrificing
power-updelaysforsubsequentconversions. Sleepmode
has substantial power savings, but a power-up delay is
incurred to allow the reference and power systems to
become valid. To enter nap mode on the LTC2320-12,
the SCK signal must be held high or low and a series of
Refer to the timing diagrams in Figure 18, Figure 19,
Figure 20 and Figure 21 for more detailed timing informa-
tion about sleep and nap modes.
CNV
1
2
NAP MODE
FULL POWER MODE
SCK
HOLD STATIC HIGH OR LOW
Z
WAKE ON 1ST SCK EDGE
SDO1 – 8
Z
232012 F18
Figure 18. CMOS and LVDS Mode NAP and WAKE Using SCK
232012fa
25
For more information www.linear.com/LTC2320-12
LTC2320-12
applicaTions inForMaTion
REFOUT
RECOVERY
REFOUT1 – 4
4.096V
4.096V
t
WAKE
CNV
1
2
3
4
NAP MODE
SLEEP MODE
FULL POWER MODE
SCK
HOLD STATIC HIGH OR LOW
WAKE ON 1ST SCK EDGE
SDO1 – 8
Z
Z
Z
Z
232012 F19
Figure 19. CMOS Mode SLEEP and WAKE Using SCK
REFOUT
RECOVERY
REFOUT1 – 4
4.096V
4.096V
t
WAKE
WAKE ON 5TH
CNV EDGE
CNV
1
2
3
4
5
NAP MODE
SLEEP MODE
FULL POWER MODE
SCK
HOLD STATIC HIGH OR LOW
SDO1 – 8
Z
Z
Z
Z
Z
232012 F20
Figure 20. LVDS and CMOS Mode SLEEP and WAKE Using CNV
SDR MODE TIMING
DDR MODE TIMING
t
t
CYC
CYC
t
t
t
READOUT
CNVH
CONV
t
t
t
CNVH
CONV
READOUT
t
DSCKCNVH
t
DSCKCNVH
CNV
CNV
t
t
SCKH
t
SCK
SCKH
t
SCK
SCK
SCK
1
2
3
14
15
16
1
2
3
14
15
16
t
SCKL
t
SCKL
CLKOUT
CLKOUT
1
2
3
14
15
16
1
2
3
14
15
16
t
DSCKCLKOUT
t
DSCKCLKOUT
t
t
t
t
DCNVSDOV
DCNVSDOZ
DCNVSDOZ
t
t
HSDO
DCNVSDOV
HSDO
HI-Z
HI-Z
HI-Z
HI-Z
SDO
D15
D14
D13
D2
D1
D0 D15
SDO
D15
D14
D13
D2
D1
D0 D15
232012 F21
Figure 21. LTC2320-12 Timing Diagram
232012fa
26
For more information www.linear.com/LTC2320-12
LTC2320-12
applicaTions inForMaTion
DIGITAL INTERFACE
using CLKOUT instead of SCK to capture the SDO output
eases timing requirements at the receiver. In CMOS mode,
use the SDO1 – SDO8, and CLKOUT pins as outputs. Use
The LTC2320-12 features a serial digital interface that
is simple and straightforward to use. The flexible OV
DD
+
the SCK pin as an input. In LVDS mode, use the SDOA /
supply allows the LTC2320-12 to communicate with any
digital logic operating between 1.8V and 2.5V. In addi-
tion to a standard CMOS SPI interface, the LTC2320-12
provides an optional LVDS SPI interface to support low
noise digital design. The CMOS /LVDS pin is used to select
the digital interface mode. The SCK input clock shifts the
conversion result MSB first on the SDO pins. CLKOUT
provides a skew-matched clock to latch the SDO output
at the receiver. The timing skew of the CLKOUT and SDO
outputs are matched. For high throughput applications,
–
+
–
+
–
SDOA through SDOD /SDOD and CLKOUT /CLKOUT
pins as differential outputs. Each LVDS lane yields two
channels worth of data: SDOA yields CH1 and CH2 data,
SDOByieldsCH3andCH4data, SDOCyieldsCH5andCH6
data and SDOD yields CH7 and CH8 data. These pins must
bedifferentiallyterminatedbyanexternal100Ωresistorat
+
–
the receiver (FPGA). The SCK /SCK pins are differential
inputs and must be terminated differentially by an external
100Ω resistor at the receiver(ADC).
2.5V
2.5V
LTC2320-12
FPGA OR DSP
LTC2320-12
FPGA OR DSP
OV
DD
OV
DD
+
–
+
–
+
–
+
–
SCK
SCK
SCK
SCK
100Ω
100Ω
100Ω
+
–
+
–
+
–
SDOD
SDOD
SDOD
SDOD
+
–
+
–
+
–
SDOC
SDOC
SDOC
SDOC
100Ω
100Ω
100Ω
100Ω
2.5V
2.5V
CMOS/LVDS
CMOS/LVDS
+
–
+
–
+
–
+
–
CLKOUT
CLKOUT
CLKOUT
CLKOUT
100Ω
100Ω
+
–
+
–
+
–
SDOB
SDOB
SDOB
SDOB
+
–
+
–
+
–
+
–
SDOA
SDOA
SDOA
SDOA
RETIMING
FLIP-FLOP
RETIMING
FLIP-FLOP
CNV
CNV
232012 F22
232012 F23
Figure 22. LTC2320-12 Using the LVDS Interface
Figure 23. LTC2320-12 Using the LVDS Interface with One Lane
232012fa
27
For more information www.linear.com/LTC2320-12
LTC2320-12
applicaTions inForMaTion
SDR/DDR Modes
CMOS
The LTC2320-12 has an SDR (single data rate) and DDR
(double data rate) mode for reading conversion data from
theSDOpins. Inbothmodes, CLKOUTisadelayedversion
of SCK. In SDR mode, each negative edge of SCK shifts
the conversion data out the SDO pins. In DDR mode,
each edge of the SCK input shifts the conversion data
out. In DDR mode, the required SCK frequency is half of
what is required in SDR mode. Tie SDR/DDR to ground to
In CMOS mode, the number of possible data lanes range
from eight (SDO1 – SDO8), four (SDO1, SDO3, SDO5
and SDO7), two (SDO1 and SDO5) and one (SDO1). As
suggested in the CMOS Timing Diagrams, each SDO lane
outputs the conversion results for all analog input chan-
nels in a sequential circular manner. For example, the first
conversion result on SDO1 corresponds to analog input
channel 1, followed by the conversion results for chan-
nels 2 through 8. The data output on SDO1 then wraps
backtochannel1andthispatternrepeatsindefinitely.Other
SDO lanes follow a similar circular pattern except the first
conversion result presented on each lane corresponds to
its associated analog input channel.
configure for SDR mode and to OV for DDR mode. The
DD
CLKOUT signal is a delayed version of the SCK input and is
phase aligned with the SDO data. In SDR mode, the SDO
transitions on the falling edge of CLKOUT as illustrated
in Figure 21. We recommend using the rising edge of
CLKOUT to latch the SDO data into the FPGA register in
SDR mode. In DDR mode, The SDO transitions on each
input edge of SCK. We recommend using the CLKOUT ris-
ing and falling edges to latch the SDO data into the FPGA
registers in DDR mode. Since CLKOUT and SDO data is
phase aligned, the SDO signals will need to be digitally
delayed in the FPGA to provide adequate setup and hold
timing margins in DDR mode.
Applications that cannot accommodate the full eight lanes
of serial data may employ fewer lanes without reconfigur-
ing the LTC2320-12. For example, capturing the first two
conversion results (32 SCK cycles total in SDR mode and
32 SCK edges in DDR mode) from SDO1, SDO3, SDO5,
and SDO7 provides data for analog input channels 1 and
2, 3 and 4, 5 and 6, and 7 and 8, respectively, using four
output lanes. Similarly, capturing the first four conversion
results (64 SCK cycles total in SDR mode and 64 SCK
edges in DDR mode) from SDO1 and SDO5 provides data
for analog input channels 1 to 4 and 5 to 8, respectively,
using two output lanes. If only one lane can be accom-
modated, capturing the first eight conversion results
(128 SCK cycles total in SDR mode and 128 SCK edges in
DDR mode) from SDO1 provides data for all analog input
channels. Generally, the more data lanes used, the lower
the required SCK frequency. When using less than eight
lanes in CMOS mode, there is a limit on the maximum
possible conversion frequency. See Table 3 for examples
of various possibilities and the resulting SCK frequency
required.
Multiple Data Lanes
The LTC2320-12 has up to eight SDO data lanes in CMOS
mode and four SDO lanes in LVDS mode. In CMOS mode,
the number of possible data lanes range from eight
(SDO1–SDO8),four(SDO1,SDO3,SDO5andSDO7),two
(SDO1 and SDO5) and one (SDO1). Generally, the more
data lanes used, the lower the required SCK frequency.
When using less than eight lanes in CMOS mode, there
is a limit on the maximum possible conversion frequency
(see Table 3). Each SDO pin will hold the MSB of the con-
version data. In DDR mode you can use a SCK frequency
half the SDR mode. See Table 3 for examples of various
possibilities and the resulting SCK frequency required.
LVDS
Multiple Data Lanes
InLVDSmode,thenumberofpossibledatalanepairsrange
from four (SDOA – SDOD), two (SDOA and SDOC) and
one (SDOA). As suggested in the LVDS Timing Diagrams,
each SDO lane pair outputs the conversion results for all
analog input channels in a sequential circular manner.
The LTC2320-12 has up to eight serial data output data
lanes in CMOS mode and four serial data output lane pairs
in LVDS mode. The data on each lane consists of 12-bit
conversion results presented MSB first.
232012fa
28
For more information www.linear.com/LTC2320-12
LTC2320-12
applicaTions inForMaTion
For example, the first conversion result on SDOA cor-
responds to analog input channel pair 1 and 2, followed
by the conversion results for channels 3 through 8. The
data output on SDOA then wraps back to channel 1 and
this pattern repeats indefinitely. Other SDO lanes follow a
similar circular pattern except the first conversion result
presented on each lane corresponds to its associated
analog input channel pairs (SDOA: analog inputs 1 and
2, SDOB: analog inputs 3 and 4, SDOC: analog inputs 5
and 6 and SDOD: analog inputs 7 and 8).
See Table 3 for examples of various possibilities and the
resulting SCK frequency required.
BOARD LAYOUT
To obtain the best performance from the LTC2320-12,
a printed circuit board is recommended. Layout for the
printed circuit board (PCB) should ensure the digital and
analog signal lines are separated as much as possible.
In particular, care should be taken not to run any digital
clocks or signals adjacent to analog signals or underneath
the ADC.
Applications that cannot accommodate the full four lanes
of serial data may employ fewer lanes without reconfigur-
ing the LTC2320-12. For example, capturing the first four
conversion results (64 SCK cycles total in SDR mode
and 64 SCK edges in DDR mode) from SDOA and SDOC
provides data for analog input channels 1 through 4, and
5 through 8, respectively, using two output lanes. If only
one lane can be accommodated, capturing the first eight
conversion results (128 SCK cycles total in SDR mode
and 128 SCK edges in DDR mode) from SDOA provides
data for all analog input channels. Generally, the more
data lanes used, the lower the required SCK frequency.
When using less than four lanes in LVDS mode, there is
a limit on the maximum possible conversion frequency.
Supply bypass capacitors should be placed as close as
possible to the supply pins. Low impedance common
returns for these bypass capacitors are essential to the
low noise operation of the ADC. A single solid ground
plane is recommended for this purpose. When possible,
screen the analog input traces using ground.
Recommended Layout
For a detailed look at the reference design for this con-
verter, including schematics and PCB layout, please refer
to DC2395A, the evaluation kit for the LTC2320-12.
Table 3. Conversion Frequency for Various I/O Modes
CONVERSION
FREQUENCY
(Msps/CH)
CMOS/
I/O MODE LVDS PIN
SDR/
DDR PIN
SDO1 – 8
LANES
SDOA – D
LANES
SCK FREQ
(MHz)
CLKOUT FREQ
(MHz)
SCK
CYCLES
OV
DD
GND (SDR) SDO1 – SDO8
100
50
100
50
16
8
1.5
1.5
OV (DDR) SDO1 – SDO8
DD
GND
CMOS
1.8V to 2.5V
SDO1, SDO3,
SDO5, SDO7
(CMOS)
OV (DDR)
DD
50
50
16
1.25
GND (SDR)
GND (SDR)
SDO1
100
200
100
150
300
100
200
100
150
300
128
32
0.5
1.5
1.5
1.4
1.0
SDOA – SDOD
SDOA – SDOD
SDOA, SDOC
SDOA
OV (DDR)
DD
16
OV
DD
LVDS
2.5V
(LVDS)
OV (DDR)
DD
32
GND (SDR)
128
Notes: Conversion Period (SDR) = t
Conversion Period (DDR) = t
+ t
+ t
+ (128/(Lanes • f ))
+ (64/(Lanes • f ))
SCK
CNV_MIN
CONV_MAX SCK
CNV_MIN
CONV_MAX
Conversion Frequency = 1/Conversion Period
SCK Cycles (SDR) = 128/Lanes
SCK Cycles (DDR) = 64/Lanes
232012fa
29
For more information www.linear.com/LTC2320-12
LTC2320-12
package DescripTion
Please refer to http://www.linear.com/product/LTC2320-12#packaging for the most recent package drawings.
UKG Package
52-Lead Plastic QFN (7mm × 8mm)
(Reference LTC DWG # 05-08-1729 Rev Ø)
7.50 ±0.05
6.10 ±0.05
5.50 REF
(2 SIDES)
0.70 ±0.05
6.45 ±0.05
6.50 REF
(2 SIDES)
7.10 ±0.05 8.50 ±0.05
5.41 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.50 REF
(2 SIDES)
0.75 ±0.05
7.00 ±0.10
(2 SIDES)
R = 0.115
TYP
0.00 – 0.05
51
52
0.40 ±0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45°C
CHAMFER
6.45 ±0.10
8.00 ±0.10
(2 SIDES)
6.50 REF
(2 SIDES)
5.41 ±0.10
(UKG52) QFN REV
Ø 0306
R = 0.10
TYP
0.25 ±0.05
0.50 BSC
TOP VIEW
0.200 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
0.75 ±0.05
232012fa
30
For more information www.linear.com/LTC2320-12
LTC2320-12
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
02/17 Corrected text to specify no latency
17
232012fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
31
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC2320-12
Typical applicaTion
Low Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level-Shifting Circuit and Retiming Flip-Flop
V
CC
NC7SVUO4P5X
0.1µF
1k
MASTER_CLOCK
V
CC
50Ω
1k
D
PRE
NC7SV74K8X
CONV
Q
CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
CLR
CONV ENABLE
CNV
LTC2320-12
SCK
10Ω
10Ω
CLKOUT
GND
GND
CMOS/LVDS
SDR/DDR
SDO1 – 8
232012 TA02
NC7SVU04P5X (× 9)
relaTeD parTs
PART NUMBER
ADCs
DESCRIPTION
COMMENTS
LTC2310-16/LTC2310-14/ 16-/14-/12-Bit Differential Input ADC with Wide
LTC2310-12 Input Common Mode
3.3V/5V Supply, Single-Channel, 35mW, 20ppm/°C Max Internal
Reference, Flexible Inputs, 16-Lead MSOP Package
LTC2321-16/LTC2321-14/ Dual 16-/14-/12-Bit, 2Msps/Ch, Simultaneous
LTC2321-12 Sampling ADCs
3.3V/5V Supply, 33mW/Ch, 20ppm°C Max Internal Reference,
Flexible Inputs, 4mm × 5mm QFN-28 Package
LTC2324-16/LTC2324-14/ Quad 16-/14-/12-Bit 2Msps/Ch Simultaneous
LTC2324-12 Sampling ADCs
3.3V/5V Supply, Single-Channel, 40mW, 20ppm/°C Max Internal
Reference, Flexible Inputs, 52-Lead QFN Package
LTC2370-16/LTC2368-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps Serial,
LTC2367-16/LTC2364-16 Low Power ADCs
2.5V Supply, Pseudo-Differential Unipolar Input, 94dB SNR, 5V Input Range,
DGC, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2380-16/LTC2378-16/ 16-Bit, 2Msps/1Msps/500ksps/250ksps Serial,
LTC2377-16/LTC2376-16 Low Power ADCs
2.5V Supply, Differential Input, 96.2dB SNR, 5V Input Range, DGC,
Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
DACs
LTC2632
Dual 12-/10-/8-Bit, SPI V
Reference
DACs with Internal
DACs with External
2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode,
Rail-to-Rail Output, 8-Pin ThinSOT™ Package
OUT
LTC2602/LTC2612/
LTC2622
Dual 16-/14-/12-Bit SPI V
Reference
300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, 8-Lead
MSOP Package
OUT
References
LTC6655
Precision Low Drift, Low Noise Buffered Reference 5V/4.096V/3.3V/3V/2.5V/2.048V/1.25V, 2ppm/°C, 0.25ppm
Peak-to-Peak Noise, MSOP-8 Package
LTC6652
Precision Low Drift, Low Noise Buffered Reference 5V/4.096V/3.3V/3V/2.5V/2.048V/1.25V, 5ppm/°C, 2.1ppm
Peak-to-Peak Noise, MSOP-8 Package
Amplifiers
LT1818/LT1819
400MHz, 2500V/µs, 9mA Single/Dual Operational
Amplifiers
–85dBc Distortion at 5MHz, 6nV/√Hz Input Noise Voltage, 9mA Supply
Current, Unity-Gain Stable
LT1806
LT6200
325MHz, Single, Rail-to-Rail Input and Output, Low –80dBc Distortion at 5MHz, 3.5nV/√Hz Input Noise Voltage,
Distortion, Low Noise Precision Op Amps 9mA Supply Current, Unity-Gain Stable
165MHz, Rail-to-Rail Input and Output, 0.95nV/√Hz Low Noise, Low Distortion, Unity-Gain Stable
Low Noise, Op Amp Family
232012fa
LT 0217 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
32
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2320-12
●
●
LINEAR TECHNOLOGY CORPORATION 2017
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