LTC2373-18_15 [Linear]
18-Bit, 1Msps, 8-Channel SAR ADC with 100dB SNR;
| 型号： | LTC2373-18_15 |
| 厂家： | 
Linear |
| 描述： | 18-Bit, 1Msps, 8-Channel SAR ADC with 100dB SNR |
| 文件： | 总50页 (文件大小：1927K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2373-18
18-Bit, 1Msps, 8-Channel
SAR ADC with 100dB SNR
FeaTures
DescripTion
The LTC®2373-18 is a low noise, high speed, 8-channel
18-bitsuccessiveapproximationregister(SAR)ADC.Oper-
atingfromasingle5Vsupply,theLTC2373-18hasahighly
configurable, low crosstalk 8-channel input multiplexer,
supporting fully differential, pseudo-differential unipolar
and pseudo-differential bipolar analog input ranges. The
LTC2373-18 achieves 2.75LSB INL (maximum) in all
inputranges, nomissingcodesat18-bitsand100dB(fully
differential)/ 95dB (pseudo-differential) SNR (typical).
n
1Msps Throughput Rate
n
18-Bit Resolution with No Missing Codes
n
8-Channel Multiplexer with Selectable Input Range
n
Fully Differential (±±4.096V
n
Pseudo-Differential Unipolar (.6 to ±4.096V
n
Pseudo-Differential Bipolar (±ꢀ4.±86V
n
INL: ±ꢀ4ꢁ7LSB (MaxiꢂuꢂV
n
SNR: 1..dB (Fully DifferentialV/07dB (Pseudo-
DifferentialV (TypicalV at f = 1kHz
IN
IN
n
n
n
n
n
n
n
n
n
n
THD: –11.dB (TypicalV at f = 1kHz
TheLTC2373-18hasanonboardlowdrift(20ppm/°Cmax)
2.048V temperature-compensated referenceanda single-
shot capable reference buffer. The LTC2373-18 also has a
high speed SPI-compatible serial interface that supports
1.8V, 2.5V, 3.3V and 5V logic through which a sequencer
with a depth of 16 may be programmed. An internal os-
cillator sets the conversion time, easing external timing
considerations. The LTC2373-18 dissipates only 40mW
and automatically naps between conversions, leading to
reduced power dissipation that scales with the sampling
rate. A sleep mode is also provided to reduce the power
consumption of the LTC2373-18 to 300μW for further
power savings during inactive periods.
Programmable Sequencer
Selectable Digital Gain Compression
Single 5V Supply with 1.8V to 5V I/O Voltages
SPI-Compatible Serial I/O
Onboard 2.048V Reference and Reference Buffer
No Pipeline Delay, No Cycle Latency
Power Dissipation 40mW (Typical)
Guaranteed Operation to 125°C
32-Lead 5mm × 5mm QFN Package
applicaTions
n
Programmable Logic Controllers
n
Industrial Process Control
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 7705765, 7961132, 8319673.
n
High Speed Data Acquisition
n
Portable or Compact Instrumentation
n
ATE
Integral Nonlinearity
Typical applicaTion
vs Output Code
5V
2.0
4.096V
1.8V TO 5V
FULLY DIFFERENTIAL
BIPOLAR
UNIPOLAR
0V
1.5
1.0
10µF
2.2µF
0.1µF
0V
10Ω
V
V
OV
DD
DD
DDLBYP
0.5
4.096V
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
RESET
RDL
+
LTC2373-18
1200pF
1200pF
0V
4.096V
0V
0
+
–
MUX
18-BIT
SAMPLING ADC
SDO
SCK
SDI
BUSY
CNV
10Ω
–0.5
–1.0
–1.5
–2.0
–
SAMPLE
CLOCK
4.096V
0V
REFBUF REFIN
47µF 0.1µF
GND
237318 TA01a
0
65536
131072
OUTPUT CODE
196608
262144
2.048V
2373 TA01b
237318f
1
For more information www.linear.com/LTC2373-18
LTC2373-18
absoluTe MaxiMuM raTings
pin conFiguraTion
(Notes 1, ꢀV
Supply Voltage (V )................................................. 6V
TOP VIEW
DD
Supply Voltage (OV )............................................... 6V
DD
Analog Input Voltage (Note 3)
CH0 to CH7, COM ........ (GND – 0.3V) to (V + 0.3V)
DD
32 31 30 29 28 27 26 25
REFBUF ....................... (GND – 0.3V) to (V + 0.3V)
DD
CH2
1
2
3
4
5
6
7
8
24 RESET
23 GND
REFIN...................................................................... 2.8V
CH3
+
Digital Input Voltage
MUXOUT
SDO
SCK
22
21
+
–
–
ADCIN
ADCIN
(Note 3)...........................(GND –0.3V) to (OV + 0.3V)
DD
33
20 SDI
Digital Output Voltage
MUXOUT
BUSY
19
(Note 3)...........................(GND –0.3V) to (OV + 0.3V)
DD
CH4
CH5
18 RDL
17 GND
Power Dissipation.............................................. 500mW
Operating Temperature Range
9
10 11 12 13 14 15 16
LTC2373C................................................0°C to 70°C
LTC2373I .............................................–40°C to 85°C
LTC2373H..........................................–40°C to 125°C
Storage Temperature Range ..................–65°C to 150°C
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
T
JMAX
= 125°C, θ = 44°C/W
JA
EXPOSED PAD IS GND (PIN 33) MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
32-Lead (5mm × 5mm) Plastic QFN
TEMPERATURE RANGE
0°C to 70°C
LTC2373CUH-18#PBF
LTC2373IUH-18#PBF
LTC2373HUH-18#PBF
LTC2373CUH-18#TRPBF 237318
LTC2373IUH-18#TRPBF 237318
LTC2373HUH-18#TRPBF 237318
32-Lead (5mm × 5mm) Plastic QFN
32-Lead (5mm × 5mm) Plastic QFN
–40°C to 85°C
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
237318f
2
For more information www.linear.com/LTC2373-18
LTC2373-18
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
teꢂperature range, otherwise specifications are at TA = ꢀ7°C4 (Note ±V
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
l
V
V
Absolute Input Range (CH0 to CH7) (Note 5)
–0.1
V
V
+ 0.1
V
IN
IN
REFBUF
–
+
l
l
l
Absolute Input Range
(CH0 to CH7, COM)
Fully Differential (Note 5)
Pseudo-Differential Unipolar (Note 5)
Pseudo-Differential Bipolar (Note 5)
–0.1
–0.1
+ 0.1
V
V
V
REFBUF
0
0.1
V
/2 – 0.1
REFBUF
V
/2
V /2 + 0.1
REFBUF
REFBUF
–
l
l
l
V
V
– V
Input Differential Voltage Range
Common Mode Input Range
Fully Differential
–V
V
V
V
V
V
V
IN
IN
REFBUF
0
REFBUF
REFBUF
/2
REFBUF
Pseudo-Differential Unipolar
Pseudo-Differential Bipolar
–V
/2
REFBUF
Pseudo-Differential Bipolar and
Fully Differential (Note 6)
CM
IN
l
l
–V
/2 – 0.1
REFBUF
V
/2
V
/2 + 0.1
REFBUF
V
REFBUF
I
IN
Analog Input Leakage Current
Analog Input Capacitance
–1
1
µA
C
Sample Mode
Hold Mode
75
5
pF
pF
CMRR
Input Common Mode Rejection Ratio Fully Differential, f = 500kHz
67
66
66
dB
dB
dB
IN
Pseudo-Differential Unipolar, f = 500kHz
IN
Pseudo-Differential Bipolar, f = 500kHz
IN
converTer characTerisTics The l denotes the specifications which apply over the full operating
teꢂperature range, otherwise specifications are at TA = ꢀ7°C4 (Note ±V
SYMBOL PARAMETER
CONDITIONS
MIN
18
TYP
MAX
UNITS
Bits
l
l
Resolution
No Missing Codes
18
Bits
Transition Noise
Fully Differential
Pseudo-Differential Unipolar
Pseudo-Differential Bipolar
0.85
1.5
1.5
LSB
LSB
LSB
RMS
RMS
RMS
l
l
l
INL
Integral Linearity Error
Differential Linearity Error
Zero-Scale Error
Fully Differential (Note 7)
–2
0.5
0.8
0.8
2
LSB
LSB
LSB
Pseudo-Differential Unipolar (Note 7)
Pseudo-Differential Bipolar (Note 7)
–2.75
–2.75
2.75
2.75
l
l
l
DNL
ZSE
Fully Differential (Note 6)
Pseudo-Differential Unipolar (Note 6)
Pseudo-Differential Bipolar (Note 6)
–0.9
–0.9
–0.9
0.25
0.25
0.25
0.9
0.9
0.9
LSB
LSB
LSB
l
l
l
Fully Differential (Note 8)
Pseudo-Differential Unipolar (Note 8)
Pseudo-Differential Bipolar (Note 8)
–15
–30
–30
2
2
2
15
30
30
LSB
LSB
LSB
Zero-Scale Error Drift
Zero-Scale Error Match
Full-Scale Error
Fully Differential
20
30
30
mLSB/°C
mLSB/°C
mLSB/°C
Pseudo-Differential Unipolar
Pseudo-Differential Bipolar
l
l
l
Fully Differential
Pseudo-Differential Unipolar
Pseudo-Differential Bipolar
–18
–24
–28
2
4
4
18
24
28
LSB
LSB
LSB
FSE
Fully Differential
l
l
REFBUF = 4.096V (REFBUF Overdriven) (Notes 8, 9)
REFIN = 2.048V (REFIN Overdriven) (Note 8)
Pseudo-Differential Unipolar
–50
–100
7
11
50
100
LSB
LSB
l
l
REFBUF = 4.096V (REFBUF Overdriven) (Notes 8, 9)
REFIN = 2.048V (REFIN Overdriven) (Note 8)
Pseudo-Differential Bipolar
REFBUF = 4.096V (REFBUF Overdriven) (Notes 8, 9)
REFIN = 2.048V (REFIN Overdriven) (Note 8)
–75
–200
5
14
75
200
LSB
LSB
l
l
–50
–120
8
12
50
120
LSB
LSB
237318f
3
For more information www.linear.com/LTC2373-18
LTC2373-18
converTer characTerisTics The l denotes the specifications which apply over the full operating
teꢂperature range, otherwise specifications are at TA = ꢀ7°C4 (Note ±V
SYMBOL PARAMETER
Full-Scale Error Drift
CONDITIONS
MIN
TYP
MAX
UNITS
Fully Differential
REFBUF = 4.096V (REFBUF Overdriven) (Note 9)
Pseudo-Differential Unipolar
0.2
0.2
0.2
ppm/°C
ppm/°C
ppm/°C
REFBUF = 4.096V (REFBUF Overdriven) (Note 9)
Pseudo-Differential Bipolar
REFBUF = 4.096V (REFBUF Overdriven) (Note 9)
Full-Scale Error Match
Fully Differential
l
l
l
REFBUF = 4.096V (REFBUF Overdriven) (Note 9)
Pseudo-Differential Unipolar
–18
–24
–28
2
4
4
18
24
28
LSB
LSB
LSB
REFBUF = 4.096V (REFBUF Overdriven) (Note 9)
Pseudo-Differential Bipolar
REFBUF = 4.096V (REFBUF Overdriven) (Note 9)
The l denotes the specifications which apply over the full operating teꢂperature range,
DynaMic accuracy
otherwise specifications are at TA = ꢀ7°C and AIN = –1dBFS4 (Notes ±, 1.V
SYMBOL PARAMETER
SINAD Signal-to-(Noise + Distortion) Ratio Fully Differential
= 1kHz, REFIN = 2.048V (REFIN Overdriven)
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
f
IN
96
99.5
94.8
94.8
dB
dB
dB
Pseudo-Differential Unipolar
= 1kHz, REFIN = 2.048V (REFIN Overdriven)
f
90.5
90.5
IN
Pseudo-Differential Bipolar
= 1kHz, REFIN = 2.048V (REFIN Overdriven)
f
IN
Fully Differential
= 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
f
101.4
96.6
96.6
dB
dB
dB
IN
Pseudo-Differential Unipolar
= 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
f
IN
Pseudo-Differential Bipolar
= 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
f
IN
Fully Differential
= 1kHz, REFIN = 2.048V (REFIN Overdriven), SEL = 1
f
98.4
93.3
dB
dB
IN
Pseudo-Differential Bipolar
= 1kHz, REFIN = 2.048V (REFIN Overdriven), SEL = 1
f
IN
SNR
Signal-to-Noise Ratio
Fully Differential
= 1kHz, REFIN = 2.048V (REFIN Overdriven)
l
l
l
f
96.5
91
100
95.0
95.0
dB
dB
dB
IN
Pseudo-Differential Unipolar
= 1kHz, REFIN = 2.048V (REFIN Overdriven)
f
IN
Pseudo-Differential Bipolar
= 1kHz, REFIN = 2.048V (REFIN Overdriven)
f
IN
91
Fully Differential
= 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
f
102
96.8
96.8
dB
dB
dB
IN
Pseudo-Differential Unipolar
= 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
f
IN
Pseudo-Differential Bipolar
= 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
f
IN
Fully Differential
= 1kHz, REFIN = 2.048V (REFIN Overdriven), SEL = 1
f
98.5
93.4
dB
dB
IN
Pseudo-Differential Bipolar
= 1kHz, REFIN = 2.048V (REFIN Overdriven), SEL = 1
f
IN
237318f
4
For more information www.linear.com/LTC2373-18
LTC2373-18
The l denotes the specifications which apply over the full operating teꢂperature range,
DynaMic accuracy
otherwise specifications are at TA = ꢀ7°C and AIN = –1dBFS4 (Notes ±, 1.V
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
THD
Total Harmonic Distortion
Fully Differential
IN
l
l
l
f
= 1kHz, REFIN = 2.048V (REFIN Overdriven)
–104
–99
–114
–110
–110
dB
dB
dB
Pseudo-Differential Unipolar
= 1kHz, REFIN = 2.048V (REFIN Overdriven)
f
IN
Pseudo-Differential Bipolar
= 1kHz, REFIN = 2.048V (REFIN Overdriven)
f
IN
–99
Fully Differential
= 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
f
–111
–110
–110
dB
dB
dB
IN
Pseudo-Differential Unipolar
= 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
f
IN
Pseudo-Differential Bipolar
= 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
f
IN
Fully Differential
= 1kHz, REFIN = 2.048V (REFIN Overdriven), SEL = 1
f
–113
–110
dB
dB
IN
Pseudo-Differential Bipolar
= 1kHz, REFIN = 2.048V (REFIN Overdriven), SEL = 1
f
IN
SFDR
Spurious Free Dynamic Range
Fully Differential
= 1kHz, REFIN = 2.048V (REFIN Overdriven)
l
l
l
f
104
99
114
110
110
dB
dB
dB
IN
Pseudo-Differential Unipolar
= 1kHz, REFIN = 2.048V (REFIN Overdriven)
f
IN
Pseudo-Differential Bipolar
= 1kHz, REFIN = 2.048V (REFIN Overdriven)
f
IN
99
Fully Differential
= 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
f
112
112
112
dB
dB
dB
IN
Pseudo-Differential Unipolar
= 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
f
IN
Pseudo-Differential Bipolar
= 1kHz, REFBUF = 5V (REFBUF Overdriven) (Note 9)
f
IN
Fully Differential
= 1kHz, REFIN = 2.048V (REFIN Overdriven), SEL = 1
f
112.5
dB
IN
Pseudo-Differential Bipolar
f
f
= 1kHz, REFIN = 2.048V (REFIN Overdriven), SEL = 1
= 100kHz, Signal Applied to an OFF Channel
113.5
–107
22
dB
dB
IN
Channel-to-Channel Crosstalk
–3dB Input Linear Bandwidth
Aperture Delay
IN
MHz
ps
500
4
Aperture Jitter
ps
RMS
Transient Response
Full-Scale Step
460
ns
inTernal reFerence characTerisTics The l denotes the specifications which apply over the
full operating teꢂperature range, otherwise specifications are at TA = ꢀ7°C4 (Note ±V
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
2.048
4
MAX
2.053
20
UNITS
V
V
Internal Reference Output Voltage
2.043
REFIN
l
V
REFIN
Temperature Coefficient
(Note 11)
ppm/°C
kΩ
REFIN Output Impedance
Line Regulation
15
V
REFIN
V
= 4.75V to 5.25V
DD
0.06
mV/V
V
REFIN Input Voltage Range
(REFIN Overdriven) (Note 5)
1.25
2.4
237318f
5
For more information www.linear.com/LTC2373-18
LTC2373-18
reFerence buFFer characTerisTics The l denotes the specifications which apply over the full
operating teꢂperature range, otherwise specifications are at TA = ꢀ7°C4 (Note ±V
SYMBOL PARAMETER
CONDITIONS
= 2.048V
MIN
4.088
2.5
TYP
MAX
4.104
5
UNITS
l
l
V
Reference Buffer Output Voltage
REFBUF Input Voltage Range
REFBUF Output Impedance
REFBUF Load Current
V
4.096
V
V
REFBUF
REFIN
(REFBUF Overdriven) (Notes 5, 9)
V
= 0V (Buffer Disabled)
13
kΩ
REFIN
l
I
V
V
= 5V (REFBUF Overdriven) (Notes 9, 12)
= 5V, Nap Mode (REFBUF Overdriven) (Note 9)
1.1
0.38
1.5
mA
mA
REFBUF
REFBUF
REFBUF
DigiTal inpuTs anD DigiTal ouTpuTs The l denotes the specifications which apply over the
full operating teꢂperature range, otherwise specifications are at TA = ꢀ7°C4 (Note ±V
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
l
l
l
V
IH
V
IL
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
0.8 • OV
DD
0.2 • OV
V
DD
I
V
IN
= 0V to OV
DD
–10
10
μA
pF
IN
C
V
V
Digital Input Capacitance
High Level Output Voltage
Low Level Output Voltage
Hi-Z Output Leakage Current
Output Source Current
Output Sink Current
5
IN
l
l
l
I = –500µA
O
OV – 0.2
DD
V
OH
OL
I = 500µA
O
0.2
10
V
I
I
I
V
OUT
V
OUT
V
OUT
= 0V to OV
DD
–10
µA
mA
mA
OZ
= 0V
= OV
–10
10
SOURCE
SINK
DD
power requireMenTs The l denotes the specifications which apply over the full operating teꢂperature
range, otherwise specifications are at TA = ꢀ7°C4 (Note ±V
SYMBOL
PARAMETER
Supply Voltage
Supply Voltage
CONDITIONS
MIN
4.75
1.71
TYP
MAX
5.25
5.25
11
UNITS
l
l
V
5
V
V
DD
OV
DD
l
l
l
l
I
I
I
I
Supply Current
1Msps Sample Rate
8.0
0.7
1.25
60
mA
mA
mA
μA
VDD
OVDD
NAP
Supply Current
1Msps Sample Rate (C = 20pF)
L
Nap Mode Current
Sleep Mode Current
Conversion Done (I
+ I
)
1.5
120
VDD
OVDD
Sleep Mode (I
+ I )
OVDD
SLEEP
VDD
P
Power Dissipation
Nap Mode
Sleep Mode
1Msps Sample Rate
Conversion Done (I
40
6.25
300
55
7.5
600
mW
mW
µW
D
+ I
)
VDD
OVDD
Sleep Mode (I
+ I
)
OVDD
VDD
aDc TiMing characTerisTics
The l denotes the specifications which apply over the full operating
teꢂperature range, otherwise specifications are at TA = ꢀ7°C4 (Note ±V
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
1
UNITS
Msps
ns
l
l
l
l
l
l
l
l
l
f
t
t
t
t
t
t
t
t
Maximum Sampling Frequency
Conversion Time
SMPL
CONV
ACQ
460
460
1
527
Acquisition Time
t
= t
– t
– t (Note 6)
BUSYLH
ns
ACQ
CYC
CONV
Time Between Conversions
CNV High Time
µs
CYC
20
ns
CNVH
CNVL
BUSYLH
RESETH
QUIET
Minimum Low Time for CNV
CNV↑ to BUSY↑ Delay
RESET Pulse Width
(Note 14)
20
ns
C = 20pF
L
13
ns
200
20
ns
(Note 6)
ns
SCK, SDI and RDL Quiet Time from CNV↑
237318f
6
For more information www.linear.com/LTC2373-18
LTC2373-18
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
teꢂperature range, otherwise specifications are at TA = ꢀ7°C4 (Note ±V
l
t
t
t
t
t
t
SCK Period
(Notes 13, 14)
10
4
ns
ns
ns
ns
ns
SCK
l
l
l
l
SCK High Time
SCKH
SCK Low Time
4
SCKL
(Note 13)
4
SDI Setup Time From SCK↑
SDI Hold Time From SCK↑
SDO Data Valid Delay from SCK↑
SSDISCK
HSDISCK
DSDO
(Note 13)
1
l
l
l
C = 20pF, OV = 5.25V
7.5
8
9.5
ns
ns
ns
L
DD
C = 20pF, OV = 2.5V
L
DD
C = 20pF, OV = 1.71V
L
DD
l
l
l
l
t
t
t
t
t
t
t
t
C = 20pF (Note 6)
1
ns
ns
ns
ns
ms
ns
ns
ns
SDO Data Remains Valid Delay from SCK↑
SDO Data Valid Delay from BUSY↓
Bus Enable Time After RDL↓
Bus Relinquish Time After RDL↑
REFBUF Wake-Up Time
HSDO
L
C = 20pF (Note 6)
L
5
DSDOBUSYL
EN
(Note 13)
(Note 13)
16
13
DIS
C
= 47μF, C = 0.1µF
REFIN
200
WAKE
REFBUF
l
l
l
38
36
40
CNV↑ to MUX Starts Resetting Delay
MUX Reset Time During Conversion
CNVMRST
MRST1
VLDMRST
8th SCK↑ to MUX Starts Resetting Delay After
Programming 1st Valid Configuration Word
l
t
MUX Reset Time During Acquisition After
Programming 1st Valid Configuration Word
42
ns
MRST2
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
0.5LSB when the output code flickers between 00 0000 0000 0000 0000
and 00 0000 0000 0000 0001. Bipolar zero-scale error is the offset volt-
age measured from –0.5LSB when the output code flickers between 00
0000 0000 0000 0000 and 11 1111 1111 1111 1111. Fully differential full-
scale error is the worst-case deviation of the first and last code transitions
from ideal and includes the effect of offset error. Unipolar full-scale error
is the deviation of the last code transition from the ideal and includes the
effect of offset error. Bipolar full-scale error is the worst-case deviation
of the first and last code transitions from ideal and includes the effect of
offset error.
Note ꢀ: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above V or
DD
OV , they will be clamped by internal diodes. This product can handle
DD
input currents up to 100mA below ground or above V or OV without
DD
DD
latchup.
Note ±: V = 5V, OV = 2.5V, f
= 1MHz, REFIN = 2.048V unless
DD
DD
SMPL
Note 0: When REFBUF is overdriven, the internal reference buffer must be
turned off by setting REFIN=0V.
otherwise noted.
Note 7: Recommended operating conditions.
Note 9: Guaranteed by design, not subject to test.
Note ꢁ: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Fully differential zero-scale error is the offset voltage measured
from –0.5LSB when the output code flickers between 01 1111 1111 1111
1111 and 10 0000 0000 0000 0000 in straight binary format and 00 0000
0000 0000 0000 and 11 1111 1111 1111 1111 in two’s complement
format. Unipolar zero-scale error is the offset voltage measured from
Note 1.: All specifications in dB are referred to a full-scale
differential), 0V to V (pseudo-differential unipolar), or
V
(fully
REFBUF
V
/2
REFBUF
REFBUF
(pseudo-differential bipolar) input.
Note 11: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 1ꢀ: f
= 1MHz, I
varies proportionally with sample rate.
SMPL
REFBUF
Note 13: Parameter tested and guaranteed at OV = 1.71V, OV = 2.5V
DD
DD
and OV = 5.25V.
DD
Note 1±: t
of 10ns maximum allows a shift clock frequency up to
SCK
100MHz for rising edge capture.
0.8 • OV
DD
t
WIDTH
0.2 • OV
DD
50%
50%
t
t
DELAY
DELAY
237318 F01
0.8 • OV
0.8 • OV
0.2 • OV
DD
DD
DD
DD
0.2 • OV
Figure 14 6oltage Levels for Tiꢂing Specifications
237318f
7
For more information www.linear.com/LTC2373-18
LTC2373-18
TA = ꢀ7°C, 6DD = 76, O6DD = ꢀ476, REFIN = ꢀ4.±86,
Typical perForMance characTerisTics
Fully Differential Range, 6CM = ꢀ4.±86, fSMPL = 1Msps, unless otherwise noted4
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
DC Histograꢂ (Zero-ScaleV
2.0
1.5
1.0
0.8
140000
σ = 0.85
120000
0.6
1.0
100000
80000
60000
40000
20000
0
0.4
0.5
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
0
65536
131072
196608
262144
0
65536
131072
196608
262144
–4 –3 –2 –1
0
1
2
3
4
OUTPUT CODE
OUTPUT CODE
CODE
237318 G01
237318 G02
237318 G03
3ꢀk Point FFT fSMPL = 1Msps,
fIN = 1kHz
3ꢀk Point FFT fSMPL = 1Msps,
fIN = 1kHz, REFBUF = 76
DC Histograꢂ (Near Full-ScaleV
120000
100000
80000
60000
40000
20000
0
0
–20
0
–20
SNR = 100.7dB
THD = –114dB
SINAD = 100.5dB
SFDR = 115.3dB
SNR = 102.3dB
THD = –111.5dB
SINAD = 101.8dB
SFDR = 111.9dB
σ = 1.00
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
–180
–180
131052 131054 131056 131058 131060
0
100
200
300
400
500
0
100
200
300
400
500
CODE
FREQUENCY (kHz)
FREQUENCY (kHz)
237318 G04
237318 G05
237318 G06
SNR, SINAD vs Input Level,
fIN = 1kHz
THD, Harꢂonics vs REFBUF,
fIN = 1kHz
SNR, SINAD vs REFBUF, fIN = 1kHz
103
102
–105
–110
101.0
100.5
100.0
SNR
SNR
101
100
99
SINAD
SINAD
–115
–120
–125
–130
THD
3RD
98
99.5
99.0
97
2ND
96
2.5
3
3.5
4
4.5
5
4.5
–20
–10
2.5
3
3.5
4
5
–40
–30
0
REFBUF VOLTAGE (V)
REFBUF VOLTAGE (V)
INPUT LEVEL (dB)
237318 G07
237318 G08
237318 G09
237318f
8
For more information www.linear.com/LTC2373-18
LTC2373-18
TA = ꢀ7°C, 6DD = 76, O6DD = ꢀ476, REFIN = ꢀ4.±86,
Typical perForMance characTerisTics
Fully Differential Range, 6CM = ꢀ4.±86, fSMPL = 1Msps, unless otherwise noted4
THD, Harꢂonics vs Input
Frequency
SNR, SINAD vs Input Frequency
CMRR vs Input Frequency
105
100
95
–70
–80
80
75
70
65
60
SNR
–90
90
SINAD
–100
–110
–120
–130
85
80
THD
2ND
3RD
55
50
75
70
0
25 50 75 100 125 150 175 200
FREQUENCY (kHz)
0
25 50 75 100 125 150 175 200
FREQUENCY (kHz)
0
100
200
300
400
500
FREQUENCY (kHz)
237318 G10
237318 G11
237318 G12
SNR, SINAD vs Teꢂperature,
fIN = 1kHz
THD, Harꢂonics vs Teꢂperature,
fIN = 1kHz
PSRR vs Frequency
102
101
100
99
–110
–115
95
90
85
80
75
70
65
60
55
50
45
THD
SNR
3RD
SINAD
–120
–125
–130
2ND
98
97
96
–40 –25 –10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
–40 –25 –10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
1
100
10
FREQUENCY (kHz)
1k
237318 G14
237318 G15
237318 G13
Full-Scale Error vs Teꢂperature
REFBUF = ±4.096
INL vs Teꢂperature
Zero-Scale Error vs Teꢂperature
2
1
4
3
2
2.0
1.5
1.0
–FS
MAX INL
MIN INL
1
0
0.5
0
+FS
0
–1
–2
–1
–2
–3
–4
–0.5
–1.0
–1.5
–2.0
–40 –25 –10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
–40 –25 –10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
–40 –25 –10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
237318 G16
237318 G17
237318 G18
237318f
9
For more information www.linear.com/LTC2373-18
LTC2373-18
TA = ꢀ7°C, 6DD = 76, O6DD = ꢀ476, REFIN = ꢀ4.±86,
DC Histograꢂ (Zero-ScaleV
Typical perForMance characTerisTics
Pseudo-Differential Unipolar Range, fSMPL = 1Msps, unless otherwise noted4
Integral Nonlinearity vs Output
Code
Differential Nonlinearity vs
Output Code
2.0
1.5
1.0
0.8
80000
σ = 1.54
0.6
60000
40000
20000
0
1.0
0.4
0.5
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
0
65536
131072
196608
262144
0
65536
131072
196608
262144
4
6
8
10 12 14 16 18 20
OUTPUT CODE
OUTPUT CODE
CODE
237318 G19
237318 G20
237318 G21
3ꢀk Point FFT fSMPL = 1Msps,
fIN = 1kHz, REFBUF = 76
3ꢀk Point FFT fSMPL = 1Msps,
fIN = 1kHz
DC Histograꢂ (Near Full-ScaleV
60000
40000
20000
0
0
–20
0
–20
SNR = 95.1dB
THD = –110dB
SINAD = 94.9dB
SFDR = 113.3dB
SNR = 96.9dB
THD = –111dB
SINAD = 96.7dB
SFDR = 112.8dB
σ = 1.89
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
–180
–180
262122
262128
262134 262140
0
100
200
300
400
500
0
100
200
300
400
500
CODE
FREQUENCY (kHz)
FREQUENCY (kHz)
237318 G22
237318 G23
237318 G24
THD, Harꢂonics vs REFBUF,
fIN = 1kHz
SNR, SINAD vs Input Level,
IN = 1kHz
SNR, SINAD vs REFBUF, fIN = 1kHz
f
98
97
–105
–110
96.0
95.5
95.0
94.5
94.0
THD
2ND
SNR
96
95
94
93
92
91
90
SINAD
–115
–120
–125
–130
SNR
–10
3RD
SINAD
2.5
3
3.5
4
4.5
5
2.5
3
3.5
4
4.5
5
–40
–30
–20
0
REFBUF VOLTAGE (V)
REFBUF VOLTAGE (V)
INPUT LEVEL (dB)
237318 G25
237318 G26
237318 G27
237318f
10
For more information www.linear.com/LTC2373-18
LTC2373-18
TA = ꢀ7°C, 6DD = 76, O6DD = ꢀ476, REFIN = ꢀ4.±86,
Typical perForMance characTerisTics
Pseudo-Differential Unipolar Range, fSMPL = 1Msps, unless otherwise noted4
THD, Harꢂonics vs Input
Frequency
SNR, SINAD vs Input Frequency
CMRR vs Input Frequency
100
95
–60
–70
80
75
70
65
60
SNR
90
85
80
75
70
65
–80
–90
–100
–110
–120
–130
SINAD
THD
2ND
3RD
55
50
0
25 50 75 100 125 150 175 200
FREQUENCY (kHz)
0
25 50 75 100 125 150 175 200
FREQUENCY (kHz)
0
100
200
300
400
500
FREQUENCY (kHz)
237318 G28
237318 G29
237318 G30
SNR, SINAD vs Teꢂperature,
fIN = 1kHz
THD, Harꢂonics vs Teꢂperature,
fIN = 1kHz
PSRR vs Frequency
95
90
85
80
75
70
65
60
55
50
45
97
96
95
94
–100
–105
–110
–115
SNR
THD
SINAD
3RD
2ND
93
92
–120
–125
1
100
FREQUENCY (kHz)
1k
–40 –25 –10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
–40 –25 –10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
10
237318 G31
237318 G32
237318 G33
Full-Scale Error vs Teꢂperature
REFBUF = ±4.096
INL vs Teꢂperature
Zero-Scale Error vs Teꢂperature
2
1
0
5
4
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
MAX INL
3
2
1
MIN INL
0
–1
–2
–1
–0.5
–2
–1.0
–40 –25 –10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
–40 –25 –10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
–40 –25 –10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
237318 G34
237318 G35
237318 G36
237318f
11
For more information www.linear.com/LTC2373-18
LTC2373-18
TA = ꢀ7°C, 6DD = 76, O6DD = ꢀ476, REFIN = ꢀ4.±86,
DC Histograꢂ (Zero-ScaleV
Typical perForMance characTerisTics
Pseudo-Differential Bipolar Range, fSMPL = 1Msps, unless otherwise noted4
Integral Nonlinearity vs Output
Code
Differential Nonlinearity vs
Output Code
2.0
1.5
1.0
0.8
80000
σ = 1.55
0.6
1.0
60000
40000
20000
0
0.4
0.5
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
0
65536
131072
196608
262144
0
65536
131072
196608
262144
–7
–5 –3
–1
1
3
5
7
OUTPUT CODE
OUTPUT CODE
CODE
237318 G37
237318 G38
237318 G39
3ꢀk Point FFT fSMPL = 1Msps,
fIN = 1kHz, REFBUF = 76
3ꢀk Point FFT fSMPL = 1Msps,
fIN = 1kHz
DC Histograꢂ (Near Full-ScaleV
80000
60000
40000
20000
0
0
–20
0
–20
SNR = 95.6dB
σ = 1.65
SNR = 97.2dB
THD = –109.8dB
SINAD = 95.5dB
SFDR = 111.6dB
THD = –109.2dB
SINAD = 96.9dB
SFDR = 112.2dB
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
–180
–180
131055 131058 131061 131063 131066 131069
0
100
200
300
400
500
0
100
200
300
400
500
CODE
FREQUENCY (kHz)
FREQUENCY (kHz)
237318 G41
237318 G40
237318 G42
THD, Harꢂonics vs REFBUF,
fIN = 1kHz
SNR, SINAD vs Input Level,
fIN = 1kHz
SNR, SINAD vs REFBUF, fIN = 1kHz
98
96.0
95.5
95.0
94.5
94.0
–105
–110
THD
2ND
97
96
95
94
93
92
91
90
SNR
SINAD
SNR
SINAD
–115
–120
–125
–130
3RD
2.5
3
3.5
4
4.5
5
–40
–30
–20
–10
0
2.5
3
3.5
4
4.5
5
REFBUF VOLTAGE (V)
INPUT LEVEL (dB)
REFBUF VOLTAGE (V)
237318 G43
237318 G45
237318 G44
237318f
12
For more information www.linear.com/LTC2373-18
LTC2373-18
TA = ꢀ7°C, 6DD = 76, O6DD = ꢀ476, REFIN = ꢀ4.±86,
Typical perForMance characTerisTics
Pseudo-Differential Bipolar Range, fSMPL = 1Msps, unless otherwise noted4
THD, Harꢂonics vs Input
Frequency
SNR, SINAD vs Input Frequency
CMRR vs Input Frequency
100
95
90
85
80
75
70
65
–60
–70
80
75
70
65
60
SNR
–80
–90
SINAD
–100
–110
–120
–130
THD
2ND
3RD
55
50
0
25 50 75 100 125 150 175 200
FREQUENCY (kHz)
0
25 50 75 100 125 150 175 200
FREQUENCY (kHz)
0
100
200
300
400
500
FREQUENCY (kHz)
237318 G46
237318 G47
237318 G48
SNR, SINAD vs Teꢂperature,
THD, Harꢂonics vs Teꢂperature,
fIN = 1kHz
PSRR vs Frequency
f
IN = 1kHz
95
90
85
80
75
70
65
60
55
50
45
97
96
95
94
93
–100
–105
–110
–115
–120
SNR
THD
3RD
SINAD
2ND
92
–125
1
100
10
FREQUENCY (kHz)
1k
–40 –25 –10
5
20 35 50 65 80 95 110 125
–40 –25 –10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
237318 G49
237318 G50
237318 G51
Full-Scale Error vs Teꢂperature
REFBUF = ±4.096
INL vs Teꢂperature
Zero-Scale Error vs Teꢂperature
2
1
3
2
2.0
1.5
+FS
–FS
MAX INL
1.0
1
0.5
0
0
0
MIN INL
–0.5
–1.0
–1.5
–2.0
–1
–2
–3
–1
–2
–40 –25 –10
5
20 35 50 65 80 95 110 125
–40 –25 –10
5
20 35 50 65 80 95 110 125
–40 –25 –10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
237318 G52
237318 G53
237318 G54
237318f
13
For more information www.linear.com/LTC2373-18
LTC2373-18
TA = ꢀ7°C, 6DD = 76, O6DD = ꢀ476, REFIN = ꢀ4.±86,
Typical perForMance characTerisTics
fSMPL = 1Msps, unless otherwise noted4
Input Leakage Current vs Teꢂperature
(MUXOUT± Shorted to ADCIN±V
Supply Current vs Teꢂperature
Sleep Current vs Teꢂperature
10
8
100
80
200
ON CHANNEL, V(CHx,COM) = 5V
OFF CHANNEL, V(CHx,COM) = 5V
ON CHANNEL, V(CHx,COM) = 0V
OFF CHANNEL, V(CHx,COM) = 0V
100
60
I
VDD
6
4
2
0
60
40
20
0
–100
I
OVDD
–200
–40 –25 –10
5
20 35 50 65 80 95 110 125
–40 –25 –10
5
20 35 50 65 80 95 110 125
–40 –25 –10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
237318 G55
237318 G56
237318 G57
Internal Reference Output vs
Teꢂperature
Internal Reference Output
Teꢂperature Coefficient Distribution
Supply Current vs Saꢂpling Rate
40
35
30
25
20
15
10
5
2.052
2.051
10
8
2.050
2.049
2.048
2.047
2.046
2.045
2.044
I
VDD
6
4
2
0
I
OVDD
0
–12 –10 –8 –6 –4 –2
0 2 4 6 8 10 12
–40 –25 –10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
0
100 200 300 400 500 600 700 800 900 1000
SAMPLING FREQUENCY (kHz)
DRIFT (ppm/°C)
237318 G59
237318 G58
237318 G60
Crosstalk FFT (AC Crosstalk-
Channel Adjacent to MUXOUTV
Crosstalk FFT (AC Crosstalk-
Channel NOT Adjacent to MUXOUTV
0
–20
–40
–60
–80
0
–20
SFDR = 107.3dB
SFDR = 130dB
f
IN
= 100kHz
f
IN
= 100kHz
–40
–60
–80
–100
–120
–140
–100
–120
–140
–160
–180
–160
–180
0
100
200
300
400
500
0
100
200
300
400
500
FREQUENCY (kHz)
FREQUENCY (kHz)
237318 G61
237318 G62
237318f
14
For more information www.linear.com/LTC2373-18
LTC2373-18
pin FuncTions
CH. to CHꢁ (Pins 1, ꢀ, ꢁ, 8, 0, 1., 31 and 3ꢀV: Analog
Inputs. CH0 to CH7 can be configured as single-ended
inputs relative to COM, or as pairs of differential input
channels. See the Analog Input Multiplexer section.
UnusedanaloginputsshouldbetiedtoaDCvoltagewithin
the analog input voltage range of (GND – 0.3V) to (V
0.3V) as specified in Absolute Maximum Ratings.
SDI (Pin ꢀ.V: Serial Data Input. Data provided on this pin
in synchrony with SCK can be used to program the MUX
channel configuration, converter input range and digital
gain compression setting via the sequencer. Input data on
SDI is latched on rising edges of SCK when the serial data
+
I/O bus is enabled. Logic levels are determined by OV .
DD
DD
SCK (Pin ꢀ1V: Serial Data Clock Input. When the serial
data I/O bus is enabled, the conversion result followed
by configuration information is shifted out at SDO on
the rising edges of this clock MSB first. Serial input data
is latched on the rising edges of this clock at SDI. Logic
+
–
MUXOUT , MUXOUT (Pin 3, Pin 9V: Analog Output Pins
of MUX.
+
–
ADCIN , ADCIN (Pin ±, Pin 7V: Analog Input Pins of
ADC Core.
levels are determined by OV .
DD
GND (Pins 11, 1±, 17, 1ꢁ, ꢀ3, ꢀ9, ꢀꢁ and Exposed Pad
Pin 33V: Ground.
SDO (Pin ꢀꢀV: Serial Data Output. The conversion result
followed by configuration information is output on this
pin on each rising edge of SCK MSB first when the serial
data I/O bus is enabled. The output data format is de-
termined by the converter operating mode. Logic levels
REFBUF (Pin 1ꢀV: Reference Buffer Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the
pin with a 47μF ceramic capacitor. The internal buffer
driving this pin may be disabled by grounding its input
at REFIN. Once the buffer is disabled, an external refer-
ence may overdrive this pin in the range of 2.5V to 5V.
A resistive load greater than 500k can be placed on the
reference buffer output.
are determined by OV .
DD
RESET(Pinꢀ±V:ResetInput.Whenthispinisbroughthigh,
the LTC2373-18 is reset. If this occurs during a conver-
sion, the conversion is halted and the data bus becomes
Hi-Z. Logic levels are determined by OV .
DD
O6 (Pin ꢀ7V: I/O Interface Digital Power. The range of
DD
REFIN (Pin 13V: Reference Output/Reference Buffer In-
put. An onboard bandgap reference nominally outputs
2.048V at this pin. Bypass this pin with a 0.1μF ceramic
capacitor to GND to limit the reference output noise. If
more accuracy is desired, this pin may be overdriven by
an external reference in the range of 1.25V to 2.4V.
OV is 1.71V to 5.25V. This supply is nominally set to
DD
the same supply as the host interface (1.8V, 2.5V, 3.3V,
or 5V). Bypass OV to GND with a 0.1μF capacitor.
DD
6
(Pin ꢀ8V: 2.5V Supply Bypass Pin. The voltage on
DDLBYP
this pin is generated via an onboard regulator off of V .
DD
This pin must be bypassed with a 2.2μF ceramic capacitor
to GND. Applying an external voltage to this pin can cause
damage to the IC or improper operation.
CN6 (Pin 19V: Convert Input. A rising edge on this input
powers up the part and initiates a new conversion. Logic
levels are determined by OV .
DD
6
(Pin ꢀ0V: 5V Power Supply. The range of V is 4.75V
DD
DD
RDL(Pin18V:ReadLowInput.WhenRDLislow,theserial
data I/O bus is enabled. When RDL is high, the serial data
I/O bus becomes Hi-Z. RDL also gates the external shift
to5.25V.BypassV toGNDwitha10µFceramiccapacitor.
DD
COM (Pin 3.V: Common Input. This is the reference point
for all single-ended inputs. It must be free of noise and
connectedtoGNDforunipolarconversionsandREFBUF/2
for bipolar conversions. If unused, this input should be
tied to a DC voltage within the analog input voltage range
clock. Logic levels are determined by OV .
DD
BUSY (Pin 10V: BUSY Indicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished. Logic levels are determined by OV .
DD
of (GND – 0.3V) to (V + 0.3V) as specified in Absolute
DD
Maximum Ratings.
237318f
15
For more information www.linear.com/LTC2373-18
LTC2373-18
FuncTional block DiagraM
OV = 1.8V
DD
TO 5V
V
= 5V
V
= 2.5V
DDLBYP
DD
LTC2373-18
LDO
CNV
BUSY
RESET
CONTROL LOGIC
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
SEQUENCER
SPI
PORT
RDL
SDO
SDI
+
18-BIT SAMPLING ADC
SCK
–
15k
2.048V
REFERENCE
2x REFERENCE
BUFFER
GND
237318 BD01
–
–
MUXOUT
ADCIN REFBUF = 2.5V REFIN = 1.25V
+
+
MUXOUT ADCIN
TO 5V
TO 2.4V
TiMing DiagraM
Typical Conversion and Serial Interface Tiꢂing
RESET = 0
CNV
N
N + 1
CONVERT
NAP
BUSY
SCK
RDL
SDO
SDI
Hi-Z
Hi-Z
D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SOS A3 A2 A1 A0 R1 R0 SEL
DATA FROM CONVERSION N
CONFIGURATION WORD
FROM CONVERSION N
C7 C6 C5 C4 C3 C2 C1 C0
237318 TD01
CONFIGURATION WORD
FOR CONVERSION N + 1
237318f
16
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LTC2373-18
applicaTions inForMaTion
O6ER6IEW
TRANSFER FUNCTION
The LTC2373-18 is a low noise, high speed, highly con-
figurable 8-channel 18-bit successive approximation
register (SAR) ADC. The LTC2373-18 features a low
crosstalk 8-channel input multiplexer (MUX) and a high
performance 18-bit accurate ADC core that can be con-
figured to accept fully-differential, pseudo-differential
unipolarand pseudo-differentialbipolarinputsignals. The
input range of the ADC core can be set independently of
the MUX input channel configuration. The outputs of the
MUX and inputs of the ADC core are pinned out, allowing
flexibility in how the MUX is connected to the ADC core.
The MUX may be wired directly to the ADC core or signal
conditioning circuitry may be inserted between the MUX
andADCcore,dependingontheapplication.TheLTC2373-
18 also has a selectable digital gain compression (DGC)
feature. The LTC2373-18 has a programmable sequencer
that can be programmed with configuration words
ranging from a depth of one up to a maximum depth of
16 configuration words.
The LTC2373-18 digitizes the full-scale voltage of 2 ×
REFBUF in fully differential mode and REFBUF in pseudo-
18
differential mode into 2 levels. With REFBUF = 4.096V,
the resulting LSB sizes in fully differential and pseudo-
differentialmodesare31.25μVand15.625μV,respectively.
The binary format of the conversion result depends on the
converter input range as described in Table 6. The ideal
two’s complement transfer function is shown in Figure 2,
whiletheidealstraightbinarytransferfunctionisshownin
Figure 3. The ideal straight binary transfer function can be
obtained from the two’s complement transfer function by
invertingthemostsignificantbit(MSB)ofeachoutputcode.
011...111
BIPOLAR
ZERO
011...110
000...001
000...000
111...111
111...110
The LTC2373-18 has an onboard low drift reference and
a single-shot capable reference buffer. The LTC2373-18
also has a high speed SPI-compatible serial interface that
supports 1.8V, 2.5V, 3.3V and 5V logic. The LTC2373-
18 automatically naps between conversions, leading to
reduced power dissipation that scales with the sampling
rate. A sleep mode is also provided for further power
savings during inactive periods.
100...001
100...000
FSR = +FS – –FS
1LSB = FSR/262144
–1 0V
1
LSB
–FSR/2
FSR/2 – 1LSB
LSB
INPUT VOLTAGE (V)
237318 F02
Figure ꢀ4 LTCꢀ3ꢁ3-18 Two’s Coꢂpleꢂent Transfer Function4
Straight Binary Transfer Function Can Be Obtained by Inverting
the Most Significant Bit (MSBV of Each Output Code
CON6ERTER OPERATION
The LTC2373-18 operates in two phases. During the ac-
111...111
111...110
+ –
/
+ –
/
quisition phase when MUXOUT is wired to ADCIN
,
the charge redistribution capacitor D/A converter (CDAC)
is connected through the MUX to the selected MUX
analog input pins. A rising edge on the CNV pin initiates
a conversion. During the conversion phase, the 18-bit
CDAC is sequenced through a successive approximation
algorithm, effectively comparing the sampled input with
binary-weighted fractions of the reference voltage (e.g.
100...001
100...000
UNIPOLAR
011...111
ZERO
011...110
000...001
FSR = +FS
000...000
1LSB = FSR/262144
V
/2, V
/4 … V
/262144) using a dif-
REFBUF
REFBUF
REFBUF
ferential comparator. At the end of conversion, the CDAC
output approximates the sampled analog input. The ADC
control logic then prepares the 18-bit digital output code
for serial transfer.
0V
FSR – 1LSB
INPUT VOLTAGE (V)
237318 F03
Figure 34 LTCꢀ3ꢁ3-18 Straight Binary Transfer Function
237318f
17
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LTC2373-18
applicaTions inForMaTion
ANALOG INPUTS
ground, C , at the output summing node of the MUX.
PAR
PAR
C
is a lumped capacitance on the order of 20pF formed
The LTC2373-18 can be configured to accept one of
three voltage ranges: fully differential ( 4.096V), pseudo-
differentialunipolar(0Vto4.096V),andpseudo-differential
bipolar( 2.048V).Inallthreeranges,theADCsamplesand
digitizes the voltage difference between the two ADC core
primarily by pin parasitics and diode junctions. Parasitic
capacitances from the PCB will also contribute to C
.
PAR
Thiscapacitanceisdischargedthroughaswitchtoground
everyconversioncycleorwhenafirstnewconfigurationis
programmed to minimize crosstalk due to charge sharing
between channels.
+
−
analog input pins (ADCIN − ADCIN ), and any unwanted
signal that is common to both inputs is reduced by the
common mode rejection ratio (CMRR) of the ADC. The
MUXoutputsthevoltagesoftheselectedMUXanaloginput
During acquisition, each active MUX analog input sees a
cascade of two first order lowpass filters formed by R
,
SW
+ –
/
+ –
/
channels to MUXOUT , according to the MUX configu-
C
and the ADC sampling network when MUXOUT is
PAR
+ –
/
+ –
+ –
/
+ –
/
/
ration. MUXOUT may be wired directly to ADCIN or
connected through a buffer. Refer to the Configuring the
LTC2373-18sectionfordetailsonhowtoselecttheanalog
input range and MUX channel configuration.
wired directly to ADCIN . If a buffer is inserted between
+ –
/
MUXOUT and ADCIN , then each active MUX analog
input only sees a first order lowpass filter formed by R
SW
and C
that is loaded with the input impedance of the
PAR
buffer.
Independentoftheselectedrangeorchannelconfiguration,
the MUX analog inputs can be modeled by the equivalent
circuit shown in Figure 4. CHx and CHy are distinct input
pins selected from the CH0 to CH7 MUX analog inputs,
depending on the MUX configuration. Each pin has ESD
BothC andC drawcurrentspikeswhilebeingcharged
IN
PAR
+ –
/
during acquisition. If MUXOUT is wired directly to
+ –
/
ADCIN , the current spikes from the charging of both
capacitors are drawn from the active MUX analog inputs.
+ –
+ –
/
+ –
/
/
protection diodes. The ADC core analog inputs, ADCIN
,
A buffer inserted between MUXOUT and ADCIN will
each see a sampling network consisting of approximately
absorbthecurrentspikefromC ,leavingthecurrentspike
IN
50pF (C ) from the sampling CDAC in series with 40Ω
from C to be drawn from the active MUX analog inputs.
IN
PAR
(R ) from the on-resistance of the sampling switch.
During conversion and sleep, the MUX analog inputs and
ADC core analog inputs draw only a small leakage current.
ON
The MUX is modeled by a 40Ω resistor representing the
MUX switch on-resistance (R ) and a capacitance to
SW
V
V
DD
DD
V
DD
C
50pF
IN
R
40Ω
R
ON
40Ω
SW
OR
+
+
CH
MUXOUT
ADCIN
X
C
20pF
PAR
BIAS
VOLTAGE
V
V
DD
DD
V
DD
C
50pF
IN
R
40Ω
R
ON
40Ω
SW
OR
–
–
CH , COM
Y
MUXOUT
ADCIN
C
20pF
PAR
237318 F04
ADC CORE
MUX
Figure ±4 Equivalent Circuit for the Differential Analog Inputs of the LTCꢀ3ꢁ3-18
237318f
18
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LTC2373-18
applicaTions inForMaTion
Fully Differential Input Range
INPUT DRI6E CIRCUITS
+ −
+ −
/
/
Whether MUXOUT is wired directly to ADCIN or
through a buffer with high input impedance, the MUX
analog inputs of the LTC2373-18 are high impedance. In
either case, a low impedance source can directly drive the
MUX analog inputs without gain error. A high impedance
source should be buffered in both cases to minimize set-
tlingtimeduringacquisitionandtooptimizeADClinearity.
The fully differential input range provides the widest
input signal swing, configuring the ADC to digitize the
+
differentialanaloginputvoltagetotheADCcore(ADCIN −
−
ADCIN )providedthroughtheselectedMUXanaloginputs
+
over a span of V
. In this range, the ADCIN and
REFBUF
−
ADCIN pins should be driven 180 degrees out-of-phase
with respect to each other, centered around a common
+
−
mode voltage (ADCIN + ADCIN )/2 that is restricted to
For best performance, a buffer amplifier should be used
to drive the MUX analog inputs of the LTC2373-18 with
+
−
(V
/2 0.1V). Both the ADCIN and ADCIN pins are
REFBUF
allowed to swing from (GND − 0.1V) to (V
+ 0.1V).
+ −
/
+ −
/
REFBUF
MUXOUT wired directly to ADCIN . The amplifier
provides low output impedance, which produces fast
settling of the analog signal during the acquisition phase.
It also provides isolation between the signal source and
the current spikes drawn by the MUX analog inputs when
entering acquisition.
Unwanted signals common to both inputs are reduced
by the CMRR of the ADC. The output data format may be
selected as straight binary or two’s complement.
Pseudo-Differential Unipolar Input Range
In the pseudo-differential unipolar input range, the ADC
digitizes the differential analog input voltage to the ADC
Noise and Distortion
+
−
core (ADCIN − ADCIN ) provided through the selected
Thenoiseanddistortionofthebufferamplifiersandsignal
sources must be considered since they add to the ADC
noise and distortion. Noisyinput signalsshould be filtered
prior to the inputs of the buffers driving the MUX analog
inputs with an appropriate filter to minimize noise. The
simple 1-pole RC lowpass filter (LPF1) shown in Figure 5
is sufficient for many applications.
MUX analog inputs over a span of (0V to V
). In this
REFBUF
range, a single-ended unipolar input signal, driven on the
+
ADCIN pin, ismeasured with respecttothesignal ground
−
+
reference level, driven on the ADCIN pin. The ADCIN
pin is allowed to swing from (GND − 0.1V) to (V
+
REFBUF
−
0.1V), while the ADCIN pin is restricted to (GND 0.1V).
Unwanted signals common to both inputs are reduced by
the CMRR of the ADC. The output data format is straight
binary.
Buffer amplifiers with low noise density must be selected
to minimize SNR degradation. Coupling filter networks
(LPF2) should be placed between the buffer outputs and
MUX analog inputs to both minimize the noise contribu-
tion of the buffers and reduce disturbances reflected into
the buffer from MUX analog input sampling transients.
Pseudo-Differential Bipolar Input Range
In the pseudo-differential bipolar input range, the ADC
digitizes the differential analog input voltage to the ADC
+ −
/
If a buffer amplifier is used between MUXOUT and
+
−
core (ADCIN − ADCIN ) provided through the selected
+ −
/
ADCIN , a coupling filter network (LPF3) should be
placed between the buffer output and ADC core analog
inputs to both minimize the noise contribution of the buf-
fer and reduce disturbances reflected into the buffer from
the ADC core analog input sampling transients. Long RC
time constants at the MUX or ADC core analog inputs will
slow down the settling of those inputs. Therefore, LPF2
and LPF3 typically require wider bandwidths than LPF1.
MUX analog inputs over a span of ( V
/2). In this
REFBUF
range, a single-ended bipolar input signal, driven on the
+
ADCIN pin, is measured with respect to the signal mid-
−
+
scalereferencelevel,drivenontheADCIN pin.TheADCIN
pin is allowed to swing from (GND − 0.1V) to (V
REFBUF
−
+ 0.1V), while the ADCIN pin is restricted to (V
/2
REFBUF
0.1V). Unwanted signals common to both inputs are
reduced by the CMRR of the ADC. The output data format
is two’s complement.
237318f
19
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LTC2373-18
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Table 1 lists typical recommended values for the R and C
of each LPF mentioned.
coupling filters that are used to both filter noise and re-
duce sampling transients due to the current spikes.
Table 14 Recoꢂꢂended R and C 6alues for Each Lowpass Filter
The MUX and ADC core analog inputs may be modeled
as a switched capacitor load on the drive circuit. A drive
circuitmayrelypartiallyonattenuatingswitched-capacitor
Rx(ΩV
Cx(pFV
BANDWIDTH
LPF1
LPF2
LPF3
50
10
25
100000
1200
31.8kHz
13MHz
2.4MHz
current spikes with small filter capacitors C
placed
FILT
directlyattheADCinputsandpartiallyonthedriveramplifier
having sufficient bandwidth to recover from the residual
disturbance.AmplifiersoptimizedforDCperformancemay
not have sufficient bandwidth to fully recover at the ADC’s
maximumconversionrate,whichcanproducenonlinearity
and other errors. Coupling filter circuits may be classified
in three broad categories:
2700
Highqualitycapacitorsandresistorsshouldbeusedinthe
RCfilterssincethesecomponentscanadddistortion.NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occurduringsoldering.Metalfilmsurfacemountresistors
are much less susceptible to both problems.
Fully Settled: This case is characterized by filter time
constants and an overall settling time that are consider-
ably shorter than the sample period. When acquisition
begins, the coupling filter is disturbed. For a typical first
order RC filter, the disturbance will look like an initial step
with an exponential decay. The amplifier will have its own
response to the disturbance, which may include ringing. If
the input settles completely (to within the accuracy of the
LTC2373-18),thedisturbancewillnotcontributeanyerror.
Input Currents
One of the biggest challenges in coupling an amplifier to
the LTC2373-18 is in dealing with current spikes drawn
by the MUX and ADC core analog inputs at the start of
each acquisition phase. LPF2 and LPF3 are examples of
LTC2373-18
CH0
LPF1
LPF1
LPF2
LPF2
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
SIGNAL
SOURCES
+
LPF1
LPF2
18-BIT ADC CORE
–
LPF1
LPF2
1/2 LPF1
1/2 LPF2
237318 F05
+ –
/
+ –
/
MUXOUT
ADCIN
BANDLIMITING
SIGNAL SOURCE
NOISE
BANDLIMITING
BUFFER NOISE
AND REDUCING
SAMPLING TRANSIENTS
LPF3
R
X
C
C
X
BANDLIMITING
BUFFER NOISE
AND REDUCING
LPFx
R
X
X
SAMPLING TRANSIENTS
Figure 74 Input Signal Chain
237318f
20
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LTC2373-18
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Partially Settled: In this case, the beginning of acquisition
causes a disturbance of the coupling filter, which then
begins to settle out towards the nominal input voltage.
However, acquisition ends (and the conversion begins)
before the input settles to its final value. This generally
produces a gain error, but as long as the settling is linear,
no distortion is produced. The coupling filter’s response
is affected by the amplifier’s output impedance and other
parameters. A linear settling response to fast switched-
capacitor current spikes can NOT always be assumed for
precision, low bandwidth amplifiers. The coupling filter
serves to attenuate the current spikes’ high frequency
energy before it reaches the amplifier.
The first form of crosstalk is often referred to as static
crosstalk. In static crosstalk, a signal applied to an OFF
channel, V
, couples capacitively into the input
INTERFERER
signal path, thus corrupting the input signal of the ON
channel,V .Figure7showsanRCmodeloftwoMUX
SIGNAL
input channels and the associated parasitic capacitances.
Capacitive coupling from an OFF channel into the input
signal path can occur through C of an OFF switch to
SW
+ –
/
the MUXOUT output pins or through C to an adja-
PIN
+ –
+ –
/
/
cent input pin or the MUXOUT output pins. Coupling
through C
to the MUXOUT pins is the dominant
PIN
coupling mechanism that limits the crosstalk to –107dB
with a 100kHz input signal applied to an OFF CH3 or CH4.
+
–
These pins sit adjacent to the MUXOUT and MUXOUT
+ –
/
Fully Averaged: Consider the case where MUXOUT is
pins, respectively.
+ –
/
directly wired to ADCIN . If the coupling filter’s capaci-
tors (C ) at the MUX analog inputs are much larger than
The second form of crosstalk is referred to as adjacent
channel crosstalk, which has to do with memory from the
inputofonechannelaffectingthesampledvalueofanother
FILT
the sum of the ADC’s sample capacitors (50pF) and the
MUX’soutputsummingnodecapacitances(20pF),thenthe
samplingglitchisgreatlyattenuated. Thedrivingamplifier
effectively only sees the average sampling current, which
is quite small. At 1Msps, the equivalent input resistance is
approximately 14k (as shown in Figure 6), a benign resis-
tive load for most precision amplifiers. However, resistive
voltage division will occur between the coupling filter’s
DC resistance and MUX’s equivalent (switched-capacitor)
input resistance, thus producing a gain error.
channel. In this case, C
at the output summing nodes
PAR
+ –
/
of the MUX, MUXOUT , can act as memory storage
elements if not dealt with properly. The potential cross-
talk mechanism here is through charge sharing. C
is
PAR
charged approximately to the voltage of each channel that
is sampled. If that charge is not cleared when switching
fromonechanneltothenext,thenchargesharingbetween
the charge on the filter capacitor (C ) of one channel
FILT
will occur with the charge from another channel stored on
LTC2373-18
C
.TheunwantedchargefromC cantakealongtime
R
CH
X
EQ
PAR
PAR
to settle out depending on the input filter bandwidth. C
PAR
C
C
>> C
TOT
FILT
FILT
BIAS
VOLTAGE
is discharged through a low impedance switch to ground
every conversion cycle or when a first new configuration
is programmed to mitigate this effect.
R
EQ
CH , COM
Y
>> C
TOT
237318 F06
+ –
/
1
MUXOUT
R
EQ
=
C
= C + C = 70pF
IN PAR
TOT
f
• C
TOT
SMPL
C
PAR
Figure 94 Equivalent Circuit for the MUX Analog Inputs of the
LTCꢀ3ꢁ3-18 at 1Msps
C
C
PIN
PIN
R
R
SW
CH3/CH4
V
INTERFERER
Crosstalk
OFF CHANNEL
C
SW
C
FILT
Crosstalk is a typical concern in systems that employ
multiplexers. The LTC2373-18 features a low crosstalk
8-channel MUX. There are two forms of crosstalk in the
LTC2373-18 that potentially allow the signal from one
channel to corrupt the signal from another channel being
sampled.
SW
CH2/CH5
V
SIGNAL
ON CHANNEL
C
SW
C
FILT
237318 F07
Figure ꢁ4 RC Equivalent Circuit for Two MUX Analog
Input Channels
237318f
21
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LTC2373-18
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Driving the MUX Analog Inputs
sity, enabling it to achieve the full ADC data sheet SNR
and THD specifications for all input ranges, as shown in
the FFT plots in Figures 8b, 8c and 8d. The RC filter time
constant is chosen to allow for sufficient transient settling
of the LTC2373-18 MUX analog inputs during acquisition.
With a maximum supply current of 7.8mA, the LT6237
is a perfect complement to the low power LTC2373-18.
The LTC2373-18 can be programmed to accept fully
differential or pseudo-differential input signals. In most
applications, it is recommended that the LTC2373-18 be
driven using the LT6237 ADC driver configured as two
unity-gain buffers regardless of the input range, as shown
in Figure 8a. The LT6237 combines fast settling and good
DC linearity with a 1.1nV/√Hz input-referred noise den-
+
4.096V
V
0V
8
MUX CHANNELS
CH0 AND CH1
SELECTED
0V
2
3
–
+
LTC2373-18
10Ω
10Ω
CH0
1
7
4.096V
0V
CH1
1200pF
CH2
CH3
CH4
CH5
CH6
CH7
COM
LT6237
4.096V
0V
5
6
+
–
1200pF
+
–
18-BIT ADC CORE
4.096V
0V
4
–
V
2.048V
237318 F08a
+ –
/
MUXOUT
SHORTED TO
+ –
/
ADCIN
Figure 8a4 LT9ꢀ3ꢁ Buffering a Fully Differential or Pseudo-Differential Signal Source
0
–20
0
–20
0
–20
SNR = 100dB
SNR = 94.8dB
SNR = 94.8dB
THD = –113dB
SINAD = 99.7dB
SFDR = 113.8dB
THD = –106.1dB
SINAD = 94.6dB
SFDR = 107.1dB
THD = –105.5dB
SINAD = 94.6dB
SFDR = 107.1dB
–40
–40
–40
–60
–60
–60
–80
–80
–80
–100
–120
–140
–100
–120
–140
–100
–120
–140
–160
–180
–160
–180
–160
–180
0
100
200
300
400
500
0
100
200
300
400
500
0
100
200
300
400
500
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
237318 F08b
237318 F08c
237318 F08d
Figure 8b4 3ꢀk Point FFT fSMPL
=
Figure 8c4 3ꢀk Point FFT fSMPL
=
Figure 8d4 3ꢀk Point FFT fSMPL =
1Msps, fIN = 1kHz for Circuit Shown
in Figure 8a; Driven with Fully
Differential Inputs
1Msps, fIN = 1kHz for Circuit Shown
in Figure 8a; Driven with Unipolar
Inputs
1Msps, fIN = 1kHz for Circuit Shown
in Figure 8a; Driven with Bipolar
Inputs
237318f
22
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LTC2373-18
applicaTions inForMaTion
Maximizing SNR with a Single-Ended to Differential
Conversion
0
–20
SNR = 100dB
THD = –106.2dB
SINAD = 99.4dB
SFDR = 108.1dB
–40
A single-ended input signal may be converted to a fully
differential signal prior to driving the MUX analog inputs
of the LTC2373-18 to take advantage of the higher SNR
of the LTC2373-18 in the fully differential input range.
The LT6350 ADC driver shown in Figure 9a can be used
to convert a 0V to 4.096V input signal to a fully differential
4.096V output signal. The RC time constant is larger in
this case to limit the high frequency noise contribution
of the LT6350. This topology provides a 5dB increase in
SNR over single-ended operation and achieves the full
data sheet SNR performance of the fully differential input
range of 100dB as shown in the FFT plot in Figure 9b. The
maximum supply current of 10.4mA makes the LT6350 a
good companion to the low power LTC2373-18.
–60
–80
–100
–120
–140
–160
–180
0
100
200
300
400
500
FREQUENCY (kHz)
237318 F09b
Figure 9b. 32k Point FFT fSMPL = 1Msps,
fIN = 1kHz for Circuit Shown in Figure 9a
Maximizing SNR for Eight Single-Ended Inputs Using
a Shared Amplifier Between MUXOUT and ADCIN
+ –
/
+ –
/
While converting a single-ended signal to a fully differ-
ential signal offers the benefit of higher SNR, two input
channels are required per single-ended input, leading to
a reduced number of single-ended input signals that can
be interfaced to the LTC2373-18. Performing the sin-
gle-ended to differential conversion using the LT6237
4.096V
+
V
3
OUT1
0V
MUX CHANNELS
CH0 AND CH1
SELECTED
LT6350
LTC2373-18
10Ω
10Ω
CH0
CH1
4
5
4.096V
0V
3300pF
3300pF
8
1
+
–
R
R
INT
INT
CH2
CH3
CH4
CH5
CH6
CH7
COM
3300pF
–
+
+
–
2
18-BIT ADC CORE
6
4.096V
0V
+
–
V
CM
= 2.048V
–
OUT2
V
237318 F09a
+ –
/
MUXOUT
SHORTED TO
+ –
/
ADCIN
Figure 9a. LT6350 Converting a 0V to 4 .096V Single-Ended Signal to a ±4 .096V Fully Differential Signal
237318f
23
For more information www.linear.com/LTC2373-18
LTC2373-18
applicaTions inForMaTion
+/–
+/–
betweenMUXOUT andADCIN asshowninFigure10a
provides the SNR benefits of the fully differential range
without sacrificing additional MUX inputs to do so. Using
the MUX configurations where CH0 to CH7 is output to
inputs achieve an SNR of 99dB with this circuit as shown
in Figure 10b, which is a 4dB improvement in SNR over
single-ended operation.
0
+
–
SNR = 99dB
MUXOUT and COM to MUXOUT enables eight single-
ended inputs to be converted with the fully differential
input range. The COM MUX input channel is used in the
feedback connection of the buffer amplifier connected
in a follower configuration to improve the distortion
performance of the circuit. THD degradation would oth-
erwise occur due to the non-linear voltage drop across
the MUX switch from the input current of the buffer and
the non-linear on-resistance of the MUX switch. The 1k
–20
–40
THD = –108dB
SINAD = 98.4dB
SFDR = 107.7dB
–60
–80
–100
–120
–140
–160
–180
0
100
200
300
400
500
FREQUENCY (kHz)
–
237318 F10b
resistor between COM and MUXOUT maintains negative
Figure 10b. 32k Point FFT fSMPL = 1Msps,
fIN = 1kHz for Circuit Shown in Figure 10a
feedback around the buffer when the MUX turns OFF, so
that the buffer output does not rail. Eight single-ended
+
V
MUX CHANNELS
CH0 AND COM
SELECTED
6
3
4
+
–
4.096V
0V
LTC2373-18
10Ω
CH0
LT6236
1
1200pF
CH1
CH2
CH3
CH4
CH5
CH6
2
5
–
V
+
18-BIT ADC CORE
–
CH7
COM
237318 F10a
–
+
+
–
MUXOUT
MUXOUT
ADCIN
ADCIN
+
V
1k
8
7
6
5
–
+
24.9Ω
100pF
499Ω
100pF
2700pF
2700pF
499Ω
–
2
3
24.9Ω
LT6237
1
+
4
+
= 2.048V
–
V
CM
–
V
Figure 10a. LT6236 Buffering a Single-Ended 0V to 4 .096V Input Signal and the LT6237 Configured to Perform a
Single-Ended to Differential Conversion to the ±4 .096V Fully Differential Input Range
237318f
24
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LTC2373-18
applicaTions inForMaTion
Using Digital Gain Compression for Single Supply
Operation
ADC driver results in additional power savings for the
entire system versus conventional systems that have a
negative supply for the ADC driver.
The LTC2373-18 offers a digital gain compression (DGC)
feature which defines the full-scale input swing to be be-
With DGC enabled, the LTC2373-18 can be driven by the
low power LTC6362 differential driver which is powered
fromasingle5Vsupply.Figure11bshowshowtoconfigure
the LTC6362 to accept a 3.28V true bipolar single-ended
input signal and level shift the signal to the reduced input
range of the LTC2373-18 when digital gain compression
is enabled. Using the LT6236 to buffer the resistor divider
tween 10% and 90% of the V
analog input range.
REFBUF
This feature allows the ADC driver to be powered off of a
single positive supply since each input swings between
0.41V and 3.69V with V
= 4.096V as in Figure 11a.
REFBUF
Needing only a positive supply and ground to power the
that creates V , the entire signal chain solution can be
V
= 4.096V
3.69V
REFBUF
CM
powered from a single 5V supply, minimizing power
consumption and reducing complexity. The reduced input
signal swing of this single 5V supply solution limits the
achievableSNRto98dB,asshownintheFFT ofFigure11c.
To enable DGC, set SEL=1 in the configuration word.
0.41V
0V
237318 F11a
Figure 11a. Input Swing of the LTC2373-18 with Digital Gain
Compression Enabled and V REFBUF = 4 .096V
5V
6
0.1µF
+
–
3
4
4.096V
1
LT6236
2
47µF
10µF
5
0.1µF
1k
MUX CHANNELS
CH0 AND CH1
SELECTED
3.69V
0.41V
V
CM
1k
2
3
5
10µF
1k
+
V
V
REFBUF
LTC2373-18
DD
35.7Ω
35.7Ω
CH0
CH1
150Ω
850Ω
850Ω
1500pF
8
1
+
0.22µF
0.22µF
3.28V
0V
–3.28V
CH2
CH3
CH4
CH5
CH6
CH7
COM
LTC6362
100Ω
–
1500pF
R
= 50Ω
4
6
SOURCE
+
–
3.69V
0.41V
V
18-BIT ADC CORE
V
SOURCE
1k
–
DIGITAL GAIN COMPRESSION ENABLED BY SETTING
SEL = 1 IN THE CONFIGURATION WORD
237318 F11b
+ –
/
MUXOUT
SHORTED TO
+ –
/
ADCIN
Figure 11b. LTC6362 Configured to Accept a ±3.28V Input Signal While Running from a Single 5V Supply When
Digital Gain Compression is Enabled in the LTC2373-18
237318f
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LTC2373-18
applicaTions inForMaTion
0
Internal Reference with Internal Buffer
SNR = 98dB
THD = –106.1dB
SINAD = 97.5dB
SFDR = 110dB
–20
–40
The LTC2373-18 has an on-chip, low noise, low drift
(20ppm/°C), temperature compensated bandgap refer-
ence that is factory trimmed to 2.048V. It is internally
connected to a reference buffer as shown in Figure 12a
and is available at REFIN (Pin 13). REFIN should be by-
passedto GND with a 0.1μFceramiccapacitorto minimize
noise. The reference buffer gains the REFIN voltage by 2
to 4.096V at REFBUF (Pin 12). Bypass REFBUF to GND
withatleast47μFceramiccapacitor(X7R, 10V, 1210size)
to compensate the reference buffer and minimize noise.
–60
–80
–100
–120
–140
–160
–180
0
100
200
300
400
500
FREQUENCY (kHz)
237318 F11c
Figure 11c. 32k Point FFT fSMPL = 1Msps, fIN = 1kHz for
Circuit Shown in Figure 11b
LTC2373-18
15k
REFIN
BANDGAP
REFERENCE
ADC REFERENCE
0.1µF
There are three ways of providing the ADC reference. The
first is to use both the internal reference and reference
buffer. The second is to externally overdrive the internal
reference and use the internal reference buffer. The third
is to disable the internal reference buffer and overdrive
the REFBUF pin from an external source. The following
tables give examples of these cases and the resulting fully
differential, unipolar and bipolar input ranges.
REFBUF
REFERENCE
BUFFER
6.5k
47µF
6.5k
GND
237318 F12a
Figure 12a. LTC2373-18 Internal Reference Circuit
Table 2. Internal Reference with Internal Buffer
FULLY
External Reference with Internal Buffer
DIFFERENTIAL UNIPOLAR
BIPOLAR
REFIN
REFBUF INPUT RANGE INPUT RANGE INPUT RANGE
If more accuracy and/or lower drift is desired, REFIN
can be easily overdriven by an external reference since a
15k resistor is in series with the reference as shown in
Figure 12b. REFIN can be overdriven in the range from
1.25V to 2.4V. The resulting voltage at REFBUF will be
2 × REFIN. Linear Technology offers a portfolio of high
performance references designed to meet the needs of
2.048V
4.096V
4.096V
0V to 4.096V
2.048V
Table 3. External Reference with Internal Buffer
FULLY
REFIN
DIFFERENTIAL UNIPOLAR
BIPOLAR
(OV ERDRIV E) REFBUF INPUT RANGE INPUT RANGE INPUT RANGE
1.25 (Min)
2.048V
2.5V
4.096V
4.8V
2.5V
4.096V
4.8V
0V to 2.5V
0V to 4.096V
0V to 4.8V
1.25V
2.048V
2.4V
2.4V (Max)
LTC2373-18
15k
REFIN
BANDGAP
REFERENCE
Table 4 . External Reference Unbuffered
FULLY
2.7µF
REFBUF
REFERENCE
BUFFER
DIFFERENTIAL UNIPOLAR
BIPOLAR
REFIN
REFBUF INPUT RANGE INPUT RANGE INPUT RANGE
6.5k
2.5V
LTC6655-2.048
47µF
0V
2.5V
5V
0V to 2.5V
0V to 5V
1.25V
2.5V
(Min)
6.5k
5V
(Max)
GND
0V
237318 F12b
Figure 12b. Using the LTC6655-2.04 8 as an External Reference
237318f
26
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LTC2373-18
applicaTions inForMaTion
manyapplications.Withitssmallsize,lowpower,andhigh
accuracy, the LTC6655-2.048 is well suited for use with
the LTC2373-18 when overdriving the internal reference.
The LTC6655-2.048 offers 0.025% (max) initial accuracy
and 2ppm/°C (max) temperature coefficient for high pre-
cision applications. The LTC6655-2.048 is fully specified
over the H-grade temperature range and complements
the extended temperature range of the LTC2373-18 up to
125°C.BypassingtheLTC6655-2.048witha2.7μFto100μF
ceramiccapacitorclosetotheREFINpinisrecommended.
external reference must provide all of this charge with a
DC current equivalent to I
= Q
/t . Thus, the
REFBUF
CONV CYC
DC current draw of REFBUF depends on the sampling rate
and output code. In applications where a burst of samples
istakenafteridlingforlongperiods,asshowninFigure13,
I
quicklygoesfromapproximately380µAtoamaxi-
REFBUF
mum of 1.5mA for REFBUF = 5V at 1Msps. This step in DC
current draw triggers a transient response in the external
reference that must be considered since any deviation in
thevoltageatREFBUFwillaffecttheaccuracyoftheoutput
code. IfanexternalreferenceisusedtooverdriveREFBUF,
the fast settling LTC6655-5 reference is recommended.
External Reference Unbuffered
The internal reference buffer can also be overdriven from
2.5V to 5V with an external reference at REFBUF as shown
inFigure12c.To doso,REFINmustbegroundedtodisable
the reference buffer. A 13k resistor loads the REFBUF pin
whenthereferencebufferisdisabled.To maximizetheinput
signal swing and corresponding SNR, the LTC6655-5 is
recommendedwhenoverdrivingREFBUF.TheLTC6655-5
offers the same small size, accuracy, drift and extended
temperature range as the LTC6655-2.048. By using a 5V
reference, an SNR of 102dB can be achieved. Bypassing
the LTC6655-5 with a 47μF ceramic capacitor (X5R, 0805
size) close to the REFBUF pin is recommended.
Internal Reference Buffer Transient Response
Foroptimumtransientperformance,theinternalreference
buffer should be used. The internal reference buffer uses a
proprietarydesignthatresultsinanoutputvoltagechange
atREFBUFoflessthan1LSBwhenrespondingtoasudden
burst of conversions. This makes the internal reference
buffer of the LTC2373-18 truly single-shot capable since
the first sample taken after idling will yield the same re-
sult as a sample taken after the transient response of the
internal reference buffer has settled. Figures 14a, 14b,
and 14c show the transient responses of the LTC2373-
18 with the internal reference buffer and with the internal
reference buffer overdriven by the LTC6655-5, both with
a bypass capacitance of 47μF in fully differential, pseudo-
differential unipolar, and pseudo-differential bipolar input
ranges, respectively.
LTC2373-18
15k
REFIN
BANDGAP
REFERENCE
REFBUF
REFERENCE
BUFFER
6.5k
DYNAMIC PERFORMANCE
LTC6655-5
47µF
6.5k
Fast fourier transform (FFT) techniques are used to test the
ADC’s frequency response, distortion and noise at the rated
throughput. By applying a low distortion sine wave and ana-
lyzing the digital output using an FFT algorithm, the ADC’s
spectralcontentcanbeexaminedforfrequenciesoutsidethe
fundamental. The LTC2373-18 provides guaranteed tested
limits for both AC distortion and noise measurements.
GND
237318 F12c
Figure 12c. Overdriving REFBUF Using the LTC6655-5
TheREFBUFpinoftheLTC2373-18drawsacharge(Q
fromtheexternalbypasscapacitorduringeachconversion
cycle. If the internal reference buffer is overdriven, the
)
CONV
CNV
237318 F13
IDLE
PERIOD
IDLE
PERIOD
Figure 13. CNV Waveform Showing Burst Sampling
237318f
27
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LTC2373-18
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8
components at the A/D output. The output is band limited
tofrequenciesfromaboveDCandbelowhalfthesampling
frequency. Figure15showsthattheLTC2373-18achieves
a typical SINAD of 100dB (fully differential) at a 1MHz
sampling rate with a 1kHz input.
INTERNAL REFERENCE BUFFER
EXTERNAL SOURCE ON REFBUF
6
4
2
0
0
SNR = 100.7dB
–20
–40
THD = –114dB
SINAD = 100.5dB
SFDR = 115.3dB
–2
0
100 200 300 400 500 600 700 800 900 1000
TIME (µs)
–60
237318 F11c
–80
Figure 14 a. Transient Response of the LTC2373-18 in the
Fully Differential Input Range
–100
–120
–140
–160
8
INTERNAL REFERENCE BUFFER
EXTERNAL SOURCE ON REFBUF
6
4
–180
0
100
200
300
400
500
FREQUENCY (kHz)
237318 F15
2
Figure 15. 32k Point FFT fSMPL = 1Msps, fIN = 1kHz
0
Signal-to-Noise Ratio (SNR)
–2
0
100 200 300 400 500 600 700 800 900 1000
TIME (µs)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 15 shows
thattheLTC2373-18achievesatypicalSNRof100dB(fully
differential) at a 1MHz sampling rate with a 1kHz input.
237318 F14b
Figure 14 b. Transient Response of the LTC2373-18 in the
Pseudo-Differential Unipolar Input Range
2
0
Total Harmonic Distortion (THD)
Totalharmonicdistortion(THD)istheratiooftheRMSsum
ofallharmonicsoftheinputsignaltothefundamentalitself.
The out-of-band harmonics alias into the frequency band
–2
–4
between DC and half the sampling frequency (f
THD is expressed as:
/2).
SMPL
INTERNAL REFERENCE BUFFER
EXTERNAL SOURCE ON REFBUF
–6
0
100 200 300 400 500 600 700 800 900 1000
TIME (µs)
2
237318 F14c
V22 +V32 +V42 +…+VN
THD=20log
V1
Figure 14 c. Transient Response of the LTC2373-18 in the
Pseudo-Differential Bipolar Input Range
where V1 is the RMS amplitude of the fundamental
Signal-to-Noise and Distortion Ratio (SINAD)
frequency and V2 through V are the amplitudes of the
N
second through Nth harmonics. Figure 15 shows that
the LTC2373-18 achieves a typical THD of –114dB (fully
differential) at a 1MHz sampling rate with a 1kHz input.
The signal-to-noise and distortion ratio (SINAD) is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency and the RMS amplitude of all other frequency
237318f
28
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POWER CONSIDERATIONS
mum acquisition time of 460ns, throughput performance
of 1Msps is guaranteed without any external adjustments.
The LTC2373-18 provides two power supply pins: the 5V
power supply (V ), and the digital input/output interface
DD
Auto Nap Mode
power supply (OV ). The flexible OV supply allows the
DD
DD
The LTC2373-18 automatically enters nap mode after a
conversion has been completed and completely powers
up once a new conversion is initiated on the rising edge of
CNV. During nap mode, only the ADC core powers down
and all other circuits remain active. During nap, data from
thelastconversioncanbeclockedout. Theautonapmode
featurewillreducethepowerdissipationoftheLTC2373-18
as the sampling frequency is reduced. Since full power is
consumed only during a conversion, the ADC core of the
LTC2373-18remainspowereddownforalargerfractionof
LTC2373-18tocommunicatewithanydigitallogicoperating
between 1.8V and 5V, including 2.5V and 3.3V systems.
Power Supply Sequencing
The LTC2373-18 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2373-18
has a power-on-reset (POR) circuit that will reset the
LTC2373-18 at initial power-up or whenever the power
supply voltage drops below 2V. Once the supply voltage
re-enters the nominal supply voltage range, the POR will
reinitialize the ADC. No conversions should be initiated
until 100ms after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
the conversion cycle (t ) at lower sample rates, thereby
CYC
reducing the average power dissipation which scales with
the sampling rate as shown in Figure 16.
10
8
I
VDD
6
4
2
0
TIMING AND CONTROL
CNV Timing
The LTC2373-18 conversion is controlled by CNV. A ris-
ing edge on CNV will start a conversion and power up the
LTC2373-18.Onceaconversionhasbeeninitiated,itcannot
berestarteduntiltheconversioniscomplete.Foroptimum
performance, CNV should be driven by a clean low jitter
signal. Converter status is indicated by the BUSY output
which remains high while the conversion is in progress.
To ensure that no errors occur in the digitized results, any
additional transitions on CNV should occur within 40ns
from the start of the conversion or after the conversion
has been completed. Once the conversion has completed,
the LTC2373-18 powers down and begins acquiring the
input signal. It is not necessary to clock out all of the data
and configuration bits before starting a new conversion.
I
OVDD
0
100 200 300 400 500 600 700 800 900 1000
SAMPLING FREQUENCY (kHz)
237318 F16
Figure 16. Power Supply Current of the LTC2373-18 vs
Sampling Rate
Sleep Mode
Theautonapmodefeatureprovideslimitedpowersavings
since only the ADC core powers down. To obtain greater
power savings, the LTC2373-18 provides a sleep mode.
During sleep mode, the entire part is powered down
except for a small standby current resulting in a power
dissipation of 300μW. To enter sleep mode, toggle CNV
twice with no intervening rising edge on SCK. The part
will enter sleep mode on the falling edge of BUSY from
the last conversion initiated. Once in sleep mode, a rising
Internal Conversion Clock
The LTC2373-18 has an internal clock that is trimmed to
achieveamaximumconversiontimeof527ns.Withamini-
237318f
29
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edge on SCK will wake the part up. Upon emerging from
Configuring the LTC2373-18
sleep mode, wait t
ms before initiating a conversion
WAKE
The various modes of operation of the LTC2373-18 are
programmedbysevenbitsofan8-bitcontrolword,C[7:0].
The control word is shifted in at SDI on the rising edges
of SCK, MSB first. The control word is defined as follows:
to allow the reference and reference buffer to wake-up
and charge the bypass capacitors at REFIN and REFBUF.
(Refer to the Timing Diagrams section for more detailed
timing information about sleep mode.)
C[7]
X
C[6]
A[3]
C[5]
A[2]
C[4]
A[1]
C[3]
A[0]
C[2]
R[1]
C[1]
R[0]
C[0]
SEL
DIGITAL INTERFACE
The LTC2373-18 has a serial digital interface. The flexible
The MSB of the control word, C[7], is used during the
programming of the sequencer and does not control
the operating mode or configuration of the MUX or ADC
(see Programming the Sequencer section). Referring to
Table 6, bits A[3:0] (C[6:3]) control the analog input MUX
channel configuration. Bits R[1:0] (C[2:1]) control the
input range configuration of the ADC and the SEL (C[0])
bit enables/disables the digital gain compression feature
(see Using Digital Gain Compression for Single Supply
Operation section).
OV supplyallowstheLTC2373-18tocommunicatewith
DD
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
The serial data I/O bus is enabled when RDL is low. Serial
output data is clocked out on the SDO pin and serial input
configurationdataisclockedinattheSDIpinwhenanexternal
clock is applied to the SCK pin if the serial data I/O bus is
enabled.SerialoutputdatatransitionsonrisingedgesofSCK
and serial input data is latched on rising edges of SCK. D17
remains valid till the first rising edge of SCK. After the 18 bits
of the conversion result are shifted out, a start-of-sequence
(SOS) bit followed by the 7-bit control word corresponding
to the conversion result is shifted out. SDO will remain low
after 26 SCK rising edges have been issued. Clocking out the
data and configuration information after the conversion will
yield the best performance. Table 5 lists the minimum shift
clock frequency needed to achieve 1Msps throughput when
shifting out a different number of bits.
Table 6. Description of Decoded Configuration Bits
BITS
NAME
BEHAV IOR
[A3:A0] MUX Channel
Configuration Bits
See Table 7
[R1:R0] Input Range
Selection Bits
00 – Pseudo-Differential Unipolar Input
(Straight Binary Output Data Format)
01 – Pseudo-Differential Bipolar Input
(Two’s-Complement Output Data
Format)
10 – Fully Differential Input
(Straight Binary Output Data Format)
11 – Fully Differential Input
(Two’s-Complement Output Data
Format)
Table 5. Minimum Shift Clock Frequency vs Number of Bits for 1Msps
NUMBER OF BITS
f (MHz)
SCK
Conversion Result
18
19
26
41
44
60
SEL
Digital Gain
Compression Bit
0 – Digital Gain Compression Disabled
1 – Digital Gain Compression Enabled
Conversion Result + SOS Bit
Conversion Result + SOS Bit +
Configuration Data
Note: Digital gain compression feature always disabled for the pseudo-
differential unipolar input range.
The configuration of the LTC2373-18 is programmed via
a sequencer through the serial interface. The following
sectionsdescribethevariouswaystheLTC2373-18canbe
programmed, the operation of the sequencer and general
use of the LTC2373-18.
Analog Input Multiplexer
The analog input MUX is programmed by the A[3:0]
(C[6:3]) bits of the input control word. Table 7 lists the
MUX configurations for all combinations of the configu-
ration bits. The selected positive (+) channel is output
+
to MUXOUT and the selected negative (−) channel is
−
output to MUXOUT . Figure 17 shows an example of the
MUX configuration being updated on successive conver-
sions. Note how the voltages of the selected positive (+)
237318f
30
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CONVERSION #1
CONVERSION #2
V(CH2)
(+)
(–)
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
(+)
(–)
V(CH0)
V(CH1)
+
–
+
+
–
+
–
MUXOUT
MUXOUT
MUXOUT
ADCIN
ADCIN
18-BIT
ADC CORE
18-BIT
ADC CORE
V(COM)
–
ADCIN
MUXOUT
ADCIN
COM
COM
R[1:0] = 10
FULLY DIFFERENTIAL
STRAIGHT BINARY
R[1:0] = 00
MUX
MUX
PSEUDO-DIFFERENTIAL
A[3:0] = 0000
A[3:0] = 1010
UNIPOLAR
237318 F17
Figure 17. Changing the Configuration of the LTC2373-18 on Successive Conversions
+
and negative (−) channels are output at MUXOUT and
An internal memory pointer determines which of the up
to 16 programmed control words is currently controlling
the converter. The pointer is reset to point to the first pro-
grammedcontrolwordeachtimethesequencermemoryis
programmed.Uponreachingthefinalprogrammedcontrol
word stored in memory, the pointer is automatically reset
to the firstmemorylocationandthe sequenceisrestarted.
Atpower-uporafterresettingtheLTC2373-18,theinternal
sequencer memory programming defaults to a depth of 1
withcontrolwordC0[6:0]=0000000(CH0 /CH1 ,unipolar
input range, digital gain compression disabled). Figure
18b shows the sequencer memory programmed with 8
configurations along with the memory pointer location for
conversions run after programming.
−
MUXOUT , respectively.
Table 7. Channel Configuration
MUX CONFIGURATION
BITS
MULTIPLEXER CONFIGURATION
A[3] A[2] A[1] A[0] CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
+
–
+
–
+
–
–
+
+
–
–
+
+
–
+
–
–
+
+
–
–
–
–
–
–
–
–
Start of Sequence
+
The start of sequence (SOS) bit is output to SDO on the
19th SCK cycle during all SPI transactions and indicates
whether the configuration for the conversion just per-
formed corresponds to the control word stored in the
first memory location of the sequencer memory. When
SOS=1, the current configuration corresponds to the first
memory location of the sequencer. The SOS bit can be
used to align the conversion data with the corresponding
control word when truncated SPI transactions are used
to maximize throughput. Only one extra bit needs to be
shifted out to maintain alignment of the configuration
with the conversion data. This results in needing 19 SCK
cycles instead of 26, which allows a higher throughput
to be achieved while being able to keep the configuration
information properly aligned with the conversion data.
+
+
+
+
+
+
Sequencer
The LTC2373-18 features a sequencer that can store up
to 16 7-bit control words in internal memory. The 7-bit
controlwordisdefinedintheConfiguringtheLTC2373-18
section. The sequencer repeatedly cycles through the
control words stored in sequencer memory on succes-
sive conversions if no new valid control words are input
to the part in a given transaction. The sequencer memory
is shown in Figure 18a.
237318f
31
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LTC2373-18
applicaTions inForMaTion
SEQUENCER MEMORY
SEQUENCER PROGRAMMED
7-BITS WIDE
WITH EIGHT CONTROL WORDS
C0[6:0]
C1[6:0]
C2[6:0]
C3[6:0]
C4[6:0]
C5[6:0]
C6[6:0]
C7[6:0]
C0[6:0]
C1[6:0]
C2[6:0]
C3[6:0]
C4[6:0]
C5[6:0]
C6[6:0]
C7[6:0]
1ST CONVERSION
9TH CONVERSION
10TH CONVERSION
11TH CONVERSION
12TH CONVERSION
13TH CONVERSION
14TH CONVERSION
15TH CONVERSION
16TH CONVERSION
....
2ND CONVERSION
3RD CONVERSION
4TH CONVERSION
5TH CONVERSION
6TH CONVERSION
7TH CONVERSION
8TH CONVERSION
MEMORY POINTER
LOCATION
16
CONTROL
WORDS
C8[6:0]
C9[6:0]
X
X
X
X
X
X
X
X
C10[6:0]
C11[6:0]
C12[6:0]
C13[6:0]
C14[6:0]
C15[6:0]
237318 F18a
237318 F18b
Figure 18a. Internal Sequencer Memory
Figure 18b. Sequencer Programmed with Eight Control Words and the
Memory Pointer Location for Conversions Run After Programming
Programming the Sequencer
Transaction Window
for their specific application after power-up or resetting
the part, and then drive the SDI pin to GND. This will force
the control word bits to all zeros and the converter will
automaticallysequencethroughtheconfigurationsstored
in sequencer memory. The following sections provide
further details on programming the sequencer.
A transaction window opens at power-up, after resetting
the LTC2373-18, and every conversion cycle at the falling
edge of BUSY, allowing the sequencer to be programmed.
Once the transaction window opens, the state machine
controlling the programming of the sequencer memory is
in a reset state, waiting for control words to be shifted in
at SDI. The transaction window closes at the start of the
next conversion when BUSY transitions from low to high,
as shown in Figure 19. Serial input data at SDI is ignored
by the sequencer state machine when BUSY is high.
The sequencer memory may be programmed by inputting
oneormorevalidcontrolwordsatSDI.Eachcontrolwordis
an8-bitwordasdescribedintheConfiguringtheLTC2373-
18section.AvalidinputcontrolwordisonewhereC[7]=1
and the remaining lower 7-bits, C[6:0], have been shifted
in before the transaction window closes as shown in
Figure 20a. When the 1st control word is successfully en-
teredonthe8thrisingedgeofSCK,thesequencermemory
is cleared, the new configuration, C[6:0], is written into
the first memory location and is applied to the converter.
At this point, a new acquisition window begins since the
Input Control Word
The input control word is used to determine whether or
not the sequencer is being programmed. In many cases
the user will simply need to configure the converter once
CNV
BUSY
237318 F19
TRANSACTION WINDOW
Figure 19. Sequencer Programming Transaction Window
237318f
32
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LTC2373-18
applicaTions inForMaTion
new configuration may result in a different channel being
acquired. Additional valid input control words are written
into subsequent memory locations. The sequencer only
storesvalidinputcontrolwordsanddiscardscontrolwords
that are partially written or have C[7] = 0. If C[7] = 0 at any
point during sequencer programming, the LTC2373-18
closes the input transaction window until the completion
of the next conversion as shown in Figure 20b. Figure 21
shows a truncated programming transaction where the
firstpartialinputcontrolwordisdiscardedandthesecond
completeinputcontrolwordissuccessfullyprogrammed.
The transaction window also closes after 16 successive
valid input control words have been written, since the
sequencer memory has been filled.
CNV
BUSY
RDL
SCK
SDI
1
2
3
4
5
6
7
8
DON’T CARE
Hi-Z
C[7]
D17
C[6]
C[5]
C[4]
C[3]
C[2]
C[1]
C[0]
SDO
D16
D15
D14
D13
D12
D11
D10
D9
START OF NEW
TRANSACTION
WINDOW
1ST VALID CONTROL WORD ENTERED
SEQUENCER MEMORY CLEARED AND UPDATED
NEW CONFIGURATION APPLIED
NEW ACQUISITION PERIOD BEGINS
237318 F20a
Figure 20a. V alid Control Word Successfully Programmed, C[7] = 1
CNV
BUSY
RDL
SCK
SDI
1
2
3
4
5
6
7
8
DON’T CARE
Hi-Z
DON’T CARE
C[7]
D17
SDO
D16
D15
D14
D13
D12
D11
D10
D9
237318 F20b
START OF NEW
TRANSACTION WINDOW CLOSED
TRANSACTION
WINDOW
Figure 20b. Invalid Control Word Entered, C[7] = 0
237318f
33
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LTC2373-18
applicaTions inForMaTion
CNV
BUSY
RDL
SCK
SDI
1
2
3
4
5
6
1
2
3
4
5
6
7
8
DON’T CARE
DON’T CARE
C[7]
A[3] A[2] A[1] A[0] R[1]
C[7] A[3] A[2] A[1] A[0]
R[1]
R[0] SEL
PARTIAL CONTROL
WORD DISCARDED
VALID CONTROL
WORD ACCEPTED
Hi-Z
Hi-Z
Hi-Z
SDO
D17 D16 D15 D14
D13 D12
TRANSACTION
D17 D16 D15 D14 D13 D12 D11 D10
START OF NEW
TRANSACTION
WINDOW
START OF NEW
TRANSACTION
WINDOW
1ST VALID CONTROL WORD ENTERED
SEQUENCER MEMORY CLEARED AND UPDATED
NEW CONFIGURATION APPLIED
WINDOW CLOSED
NEW ACQUISITION PERIOD BEGINS
PARTIAL CONTROL
WORD DISCARDED
237318 F21
Figure 21. Truncated Programming Transaction Followed by the Successful Programming of One Configuration
237318f
34
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LTC2373-18
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Programming the Sequencer with Two Configurations
ing and after the programming process. The first stored
configuration will instruct the converter to sample a fully
Figure 22 illustrates the sequencer memory being pro-
grammed while reading out a conversion result. C[7] of
the first two input control words is 1, so these control
words are valid and are written to sequencer memory
in succession. C[7] of the third control word is 0, so the
input transaction is terminated at this point. Since there
were only two valid control words entered, the sequencer
memory is programmed with a depth of two. Figure 23
shows the state of the sequencer memory before, dur-
+
–
differential signal on the CH7 /CH6 pair with digital gain
compression disabled, and the second stored configura-
tion will instruct the converter to sample a unipolar signal
on the CH3/COM pair with digital gain compression dis-
abled. The converter will then alternate between the two
programmed configurations on successive conversions.
Note that configurations stored in sequencer memory are
retained until the power is cycled, the part is reset, or a
newseriesofconfigurationprogrammingwordsareinput.
CNV
BUSY
RDL
SCK
SDI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DON’T CARE
DON’T CARE
C[7]
A[3] A[2] A[1] A[0] R[1] R[0] SEL C[7] A[3] A[2] A[1] A[0]
R[1] R[0] SEL C[7]
CONTROL WORD #1
CONTROL WORD #2
Hi-Z
Hi-Z
D0
SDO
D17 D16 D15 D14
D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
START OF NEW
TRANSACTION
WINDOW
1ST VALID CONTROL WORD ENTERED
SEQUENCER MEMORY CLEARED AND UPDATED
NEW CONFIGURATION APPLIED
TRANSACTION
WINDOW CLOSED
NEW ACQUISITION PERIOD BEGINS
2ND VALID CONTROL WORD ENTERED
237318 F22
SEQUENCER MEMORY UPDATED
Figure 22. Sequencer Programmed with Two Control Words
SEQUENCER MEMORY
FROM PREVIOUS
PROGRAMMING
SEQUENCER MEMORY
AFTER PROGRAMMING
1ST CONTROL WORD
SEQUENCER MEMORY
AFTER PROGRAMMING
2ND CONTROL WORD
....
C0[6:0]
C1[6:0]
C2[6:0]
C3[6:0]
C4[6:0]
C5[6:0]
C6[6:0]
C7[6:0]
C8[6:0]
C9[6:0]
C10[6:0]
C11[6:0]
C12[6:0]
C13[6:0]
C14[6:0]
C15[6:0]
C0[6:0] = 0111100
C0[6:0] = 0111100
C1[6:0] = 1011000
1ST CONVERSION
2ND CONVERSION
3RD CONVERSION
4TH CONVERSION
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MEMORY POINTER
LOCATION
X
237318 F23
Figure 23. Sequencer Memory Before, During and After Programming
237318f
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LTC2373-18
TiMing DiagraMs
MUX Reset Timing
The MUX turns OFF and begins resetting t
ns
CNVMRST
after a conversion is initiated by the rising edge of CNV.
The parasitic capacitances (C ) on the output summing
PAR
After t
ns, the MUX turns ON to the next channel
+ –
/
MRST1
nodes of the MUX, MUXOUT , are discharged to ground
every conversion cycle and when a first new valid con-
figuration word is programmed into the sequencer. This
is done to avoid crosstalk between input channels due to
programmed in the sequencer.
TheMUXalsoturnsOFFandresetsaftert
nswhen
VLDMRST
afirstnewvalidconfigurationwordisprogrammedintothe
sequencer on the 8th rising edge of SCK. This is because
the MUX may need to switch channels based on the newly
input configuration, so memory of the previous channel
needstobecleared. Anewacquisitionperiodbeginswhen
charge sharing from C . The bottom most waveform in
PAR
Figure24representsthevoltagesoftheMUXoutputnodes.
+ –
/
The MUX is being reset when V(MUXOUT ) sits at 0V.
the MUX is reconnected after t
ns.
MRST2
t
CNVMRST
t
ACQ
CNV
BUSY
SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SDI
C[7] C[6] C[5] C[4] C[3] C[2] C[1] C[0]
SDO
D17 D16 D15 D14 D13 D12 D11 D10 D9
D8
t
D7
D6
D5
D4
D3
D2
D1
D0
SOS
t
t
VLDMRST
MRST1
MRST2
+ –
/
V(MUXOUT
)
237318 F24
0V
Figure 24 . MUX Reset Timing
237318f
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LTC2373-18
TiMing DiagraMs
Single Device, Sequencer Not Programmed
availableatthefallingedgeofBUSY.Thestart-of-sequence
(SOS) bit followed by the current configuration is shifted
out after the conversion data.
RDL enables or disables the serial data I/O bus. If RDL is
high, the serial data I/O bus is disabled and the serial shift
clock SCK is ignored. If RDL is low, SDO is driven and
serial input data may be shifted in at SDI. Figure 25 shows
a single LTC2373-18 operated with RDL and RESET tied
to ground. With RDL grounded, the serial data I/O bus is
enabled and the MSB(D17) of the new conversion data is
Bringing SDI low during data readback as shown closes
the sequencer programming window at the first rising
edge of SCK after the falling edge of BUSY since C[7] = 0.
As a result, the sequencer is not programmed.
CONVERT
DIGITAL HOST
CNV
RDL
BUSY
IRQ
LTC2373-18
RESET
SDO
SDI
DATA IN
SDI
SCK
CLK
NAP AND
ACQUIRE
CONVERT
NAP AND ACQUIRE
CONVERT
t
CYC
RDL = 0
RESET = 0
t
CNVL
CNV
BUSY
SCK
t
CNVH
– t
BUSYLH
t
= t
ACQ CYC CONV
– t
t
ACQ
t
CONV
t
t
SCK
BUSYLH
t
t
SCKH
QUIET
1
2
3
17
18
19
20
21
22
23
24
25
26
t
SCKL
t
HSDO
SDI
t
DSDO
t
DSDOBUSYL
SDO
D17 D16 D15
D0
SOS A[3] A[2] A[1] A[0] R[1] R[0] SEL
237318 F25
Figure 25. Using a Single LTC2373-18 without Programming the Sequencer
237318f
37
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LTC2373-18
TiMing DiagraMs
Single Device, Sequencer Programmed
open, a valid input configuration is detected on the 8th
rising edge of SCK. At this point, the MUX turns OFF and
resets and sequencer memory is reset and updated with
the new configuration. The new channel configuration is
applied when the MUX turns ON, marking the beginning
of a new acquisition period.
Figure 26 shows the timing for a single device being
operated with RDL and RESET tied to ground. With RDL
grounded, the serial data I/O bus is enabled and the
MSB(D17) of the new conversion data is available at the
falling edge of BUSY. The start-of-sequence (SOS) bit
followed by the configuration used for the conversion just
performed is shifted out after the new conversion data.
‘On the Fly’ Device Programming
The sequencer may be programmed with one control
word as shown in Figure 26 every conversion cycle to
achieve complete flexibility in the multiplexer configura-
tion, input range and digital gain compression setting on
each conversion.
When SDI is high at the first rising edge of SCK after
the falling edge of BUSY as shown, the sequencer pro-
gramming window stays open, allowing the sequencer to
beprogrammed.Withthesequencerprogrammingwindow
CONVERT
NAP
NAP
CONVERT
RDL = 0
RESET = 0
t
CNVL
CNV
BUSY
SCK
t
CNVH
+ t
ACQ
t
+ t
VLDMRST MRST2
t
CONV
t
SCK
t
BUSYLH
t
t
SCKH
QUIET
1
2
3
4
5
6
7
8
9
23
24
25
26
t
t
SCKL
SSDISCK
HSDISCK
t
t
HSDO
t
DSDO
SDI
C[7] C[6] C[5] C[4] C[3] C[2] C[1] C[0]
t
DSDOBUSYL
SDO
D17 D16 D15 D14 D13 D12 D11 D10 D9
R[1] R[0] SEL
237318 F26
Figure 26. Using a Single LTC2373-18 Programming the Sequencer
237318f
38
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LTC2373-18
TiMing DiagraMs
Multiple Devices
avoid bus conflicts. RDL must also be used to selectively
program each ADC through the shared SDI input line. The
RDLinputsidlehighandareindividuallybroughtlowtoread
data out of and selectively program each device between
conversions. When RDL is brought low, the MSB(D17)
of the selected device is output onto SDO.
Figure 27 shows the multiple LTC2373-18 devices operat-
ing and sharing CNV, SDI, SCK and SDO. By sharing CNV,
SDI, SCK and SDO, the number of signals required to
operate multiple ADCs in parallel is reduced. Since SDO is
shared, the RDL input of each ADC must be used to allow
only one LTC2373-18 to drive SDO at a time in order to
RDL
RDL
B
A
CONVERT
DIGITAL HOST
IRQ
CNV
CNV
RDL
BUSY
SDI
RDL
BUSY
SDI
LTC2373-18
B
LTC2373-18
A
RESET
RESET
SCK
SDO
SCK
SDO
SDI
DATA IN
CLK
CONVERT
NAP
NAP
RESET = 0
CONVERT
t
CNVL
CNV
t
CNVH
BUSY
t
CONV
t
BUSYLH
RDL
RDL
A
B
t
SCK
t
t
QUIET
SCKH
SCK
SDI
1
2
3
16
17
18
19
20
21
34
35
36
t
SSDISCK
HSDISCK
t
SCKL
t
DON’T CARE
Hi-Z
C [7] C [6] C [5]
C [7] C [6] C [5]
B B B
A
A
A
t
HSDO
t
t
t
EN
DIS
DSDO
Hi-Z
Hi-Z
SDO
D17
D16
D15
D1
A
D0
D17
D16 D15
D1
B
D0
B
A
A
A
A
B
B
B
237318 F27
Figure 27. Multiple Devices Sharing CNV , SCK and SDO
237318f
39
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LTC2373-18
TiMing DiagraMs
Sleep Mode
partwillentersleepmodeonthefallingedgeofBUSYfrom
the last conversion initiated. Once in sleep mode, a rising
edge on SCK will wake the part up. Upon emerging from
The LTC2373-18 automatically naps and starts acquiring
the input once a conversion has completed. Only the ADC
core powers down in nap mode. As a result, the auto nap
feature provides limited power savings. To obtain greater
power savings, the LTC2373-18 provides a sleep mode.
Duringsleepmode,theentirepartispowereddownexcept
for a small standby current resulting in a 300μW power
dissipation. To entersleepmode, toggleCNVtwicewithno
intervening rising edge on SCK as shown in Figure 28. The
sleep mode, wait t
ms before initiating a conversion
WAKE
to allow the reference and reference buffer to wake-up and
charge the bypass capacitors at REFIN and REFBUF. The
serial data I/O bus is enabled or disabled by RDL during
sleep mode. Sleep mode does not affect the state of the
sequencer memory or memory pointer.
CONVERT
CNVH
NAP
CONVERT
SLEEP
NAP
RDL = DON’T CARE
SDI = DON’T CARE
CONVERT
t
t
WAKE
CNV
BUSY
t
t
CONV
CONV
t
BUSYLH
SCK
CONVERT
SLEEP
NAP
RDL = DON’T CARE
SDI = DON’T CARE
CONVERT
t
CNVH
t
WAKE
CNV
BUSY
t
CONV
t
BUSYLH
SCK
237318 F28
Figure 28. Sleep Mode Timing Diagram
237318f
40
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LTC2373-18
TiMing DiagraMs
RESET Timing
is immediately halted. During reset, requests for new
conversions are ignored. Once RESET returns low, the
LTC2373-18 is ready to start a new conversion after the
acquisition time has been met.
When the RESET pin is high, the LTC2373-18 is reset and
the serial I/O data bus is put into a high impedance mode,
as shown in Figure 29. The serial data output register and
sequencermemoryarealsoclearedandsettotheirdefault
states. If this occurs during a conversion, the conversion
t
RESETH
RESET
CNV
t
ACQ
Hi-Z
SDO
237318 F29
Figure 29. RESET Pin Timing
boarD layouT
To obtain the best performance from the LTC2373-18
a printed circuit board is recommended. Layout for the
printed circuit board (PCB) should ensure the digital and
analog signal lines are separated as much as possible.
In particular, care should be taken not to run any digital
clocks or signals alongside analog signals or underneath
the ADC.
Recommended Layout
ThefollowingisanexampleofarecommendedPCBlayout.
A single solid ground plane is used. Bypass capacitors to
the supplies are placed as close as possible to the supply
pins. Low impedance common returns for these bypass
capacitors are essential to the low noise operation of the
ADC. The analog input traces are screened by ground.
For more details and information refer to DC2071, the
evaluation kit for the LTC2373-18.
237318f
41
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LTC2373-18
boarD layouT
Figure 30. Top Silkscreen
237318f
42
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LTC2373-18
boarD layouT
Figure 31. Layer 1 Component Side
237318f
43
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LTC2373-18
boarD layouT
Figure 32. Layer 2 Ground Plane
237318f
44
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LTC2373-18
boarD layouT
Figure 33. Layer 3 Power Plane
237318f
45
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LTC2373-18
boarD layouT
Figure 34 . Layer 4 Bottom Layer
237318f
46
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LTC2373-18
scheMaTics
5
3
5
3
G N D
V C
4
1
D
Q
Q
2
1
5
3
P C
2
C
5
3
N I E F R
3 1
D
D
G N
G N
3 3
3 2
F
B U E F R
2 1
5 2
8 2
9 2
D
O G N
6 2
D D O V
Y P B L D V D
D
D
D
D
D
G N
G N
G N
G N
G N
1 1
4 1
5 1
7 1
7 2
D
V D
+ N I
A D C
- N I
A D C
5
4
3
+ T U X O U M
- T U X O U M
6
X U M C 8 H -
8
4
8
4
6
2
5
237318f
47
For more information www.linear.com/LTC2373-18
LTC2373-18
scheMaTics
S H D N
7
3
V +
V -
6
N
+ V
H S D
M
V O C
7
3
2
- V
6
1
2
3
9
8
4
8
4
4
8
8
4
1
2
3
1
2
3
237318f
48
For more information www.linear.com/LTC2373-18
LTC2373-18
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.45 ±0.05
3.50 REF
(4 SIDES)
3.45 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
R = 0.05
TYP
0.00 – 0.05
R = 0.115
TYP
0.75 ±0.05
5.00 ±0.10
(4 SIDES)
31 32
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.45 ±0.10
3.50 REF
(4-SIDES)
3.45 ±0.10
(UH32) QFN 0406 REV D
0.200 REF
0.25 ±0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
237318f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
49
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC2373-18
Typical applicaTion
LTC6362 Configured to Accept a ±10V Input Signal Using a Single 5V Supply with Digital
Gain Compression Enabled on the LTC2373-18
5V
6
3
4
+
–
4.096V
1
LT6236
2
10µF
10µF
5
1k
1k
V
CM
47µF
MUX CHANNELS
CH0 AND CH1
SELECTED
3.69V
0.41V
333Ω
10µF
2
3
5
+
V
REFBUF
V
DD
35.7Ω
CH0
150Ω
100Ω
850Ω
CH1
8
1
LTC2373-18
1500pF
+
0.22µF
0.22µF
CH2
CH3
CH4
CH5
CH6
CH7
COM
10V
0V
LTC6362
–
1500pF
–10V
35.7Ω
850Ω
4
6
+
–
R
= 50Ω
SOURCE
–
V
3.69V
0.41V
18-BIT ADC CORE
V
SOURCE
333Ω
DIGITAL GAIN COMPRESSION ENABLED BY SETTING
SEL = 1 IN THE CONFIGURATION WORD
237318 TA02
+ –
+ –
/
/
MUXOUT SHORTED TO ADCIN
relaTeD parTs
PART NUMBER
ADCs
DESCRIPTION
COMMENTS
LTC2378-20/LTC2377-20 20-Bit, 1Msps/500ksps/250ksps, 0.5ppm 2.5V Supply, 5V Fully Differential Input, 104dB SNR, MSOP-16 and
LTC2376-20
INL Serial, Low Power ADC
4mm × 3mm DFN-16 Packages
LTC2379-18/LTC2378-18 18-Bit, 1.6Msps/1Msps/500ksps/250ksps
LTC2377-18/LTC2376-18 Serial, Low Power ADC
2.5V Supply, Differential Input, 101.2dB SNR, 5V Input Range, DGC,
Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2380-16/LTC2378-16 16-Bit, 2Msps/1Msps/500ksps/250ksps
LTC2377-16/LTC2376-16 Serial, Low Power ADC
2.5V Supply, Differential Input, 96.2dB SNR, 5V Input Range, DGC,
Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2369-18/LTC2368-18 18-Bit, 1.6Msps/1Msps/500ksps/250ksps
LTC2367-18/LTC2364-18 Serial, Low Power ADC
2.5V Supply, Pseudo-Differential Unipolar Input, 96.5dB SNR, 0V to 5V Input
Range, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2370-16/LTC2368-16 16-Bit, 2Msps/1Msps/500ksps/250ksps
LTC2367-16/LTC2364-16 Serial, Low Power ADC
2.5V Supply, Pseudo-Differential Unipolar Input, 94dB SNR, 0V to 5V Input
Range, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
DACs
LTC2756
18-Bit, Serial I
SoftSpan™ DAC
1LSB INL/DNL, Software-Selectable Ranges, SSOP-28 Package
OUT
LTC2641
LTC2630
References
LTC6655
16-Bit/14-Bit/12-Bit Single Serial V
DAC
1LSB INL/DNL, MSOP-8 Package, 0V to 5V Output
SC70 6-Pin Package, Internal Reference, 1LSB INL (12 Bits)
OUT
12-Bit/10-Bit/8-Bit Single V
DACs
OUT
Precision Low Drift Low Noise Buffered
Reference
Precision Low Drift Low Noise Buffered
Reference
5V/2.5V/2.048V/1.2V, 5ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package
5V/2.5V/2.048V/1.2V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package
LTC6652
Amplifiers
LT6237/LT6236
LT6350
Dual/Single Rail-to-Rail Output ADC Driver
Low Noise Single-Ended-to-Differential ADC Rail-to-Rail Inputs and Outputs, 240ns, 0.01% Settling Time
Driver
215MHz GBW, 1.1nV/√Hz, 3.5mA Supply Current
LTC6362
Low Power, Fully Differential Input/Output
Amplifier/Driver
Single 2.8V to 5.25V Supply, 1mA Supply Current, MSOP-8 and 3mm × 3mm
DFN-8 Packages
237318f
LT 0115 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
50
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2373-18
●
●
LINEAR TECHNOLOGY CORPORATION 2015
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