LTC2376-18_技术文档

LTC6362

Precision, Low Power

Rail-to-Rail Input/Output

Differential Op Amp/SAR

ADC Driver

FEATURES

DESCRIPTION

The LTC^®6362 is a low power, low noise differential op

amp with rail-to-rail input and output swing that has been

optimized to drive low power SAR ADCs. The LTC6362

draws only 1mA of supply current in active operation, and

features a shutdown mode in which the current consump-

tion is reduced to 70μA.

n

1mA Supply Current

n

Single 2.8V to 5.25V supply

n

Fully Differential Input and Output

n

200μV Max Offset Voltage

n

260nA Max Input Bias Current

n

Fast Settling: 550ns to 18-Bit, 8V Output

P-P

n

Low Distortion: –116dBc at 1kHz, 8V

Rail-to-Rail Inputs and Outputs

3.9nV/√Hz Input-Referred Noise

180MHz Gain-Bandwidth Product

34MHz –3dB Bandwidth

P-P

The amplifier may be configured to convert a single-

ended input signal to a differential output signal, and is

capable of being operated in an inverting or noninverting

configuration.

n

Low offset voltage, low input bias current, and a stable

high impedance configuration make this amplifier suit-

able for use not only as an ADC driver but also earlier in

the signal chain, to convert a precision sensor signal to

a balanced (differential) signal for processing in noisy

industrial environments.

Low Power Shutdown: 70µA

8-Lead MSOP and 3mm × 3mm 8-Lead DFN Packages

APPLICATIONS

n

16-Bit and 18-Bit SAR ADC Drivers

n

Single-Ended-to-Differential Conversion

n

Low Power Pipeline ADC Driver

The LTC6362 is available in an 8-lead MSOP package and

also in a compact 3mm × 3mm 8-pin leadless DFN pack-

age, and operates with guaranteed specifications over a

–40°C to 125°C temperature range.

n

Differential Line Drivers

n

Battery-Powered Instrumentation

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

TYPICAL APPLICATION

LTC6362 Driving LTC2379-18

f_IN= 2kHz, –1dBFS, 16384-Point FFT

0

–10

–20

–30

–40

–50

–60

–70

–80

DC-Coupled Interface from a Ground-Referenced

Single-Ended Input to an LTC2379-18 SAR ADC

V

= 5V, 0V

S

OUTDIFF

= 8.9V

P-P

HD2 = –116.0dBc

HD3 = –114.9dBc

SFDR = 110.1dB

THD = –108.0dB

SNR = 101.2dB

SINAD = 99.9dB

1k

5V

2.5V

5V

3.9nF

V

DD

35.7Ω

REF

1k

+

–

A

18-BIT

+

–

IN

V

OCM

LTC2379-18

SAR ADC

–90

V

IN

3.9nF

LTC6362

0.1µF

SHDN

–100

–110

–120

–130

–140

–150

+

1.6Msps

–

IN

GND

1k

6362 TA01a

0

100 200 300 400 500 600 700 800

FREQUENCY (kHz)

6362 TA01b

6362fa

1

LTC6362

ABSOLUTE MAXIMUM RATINGS ^{(Note 1)}

+

–

Total Supply Voltage (V – V ).................................5.5V

Specified Temperature Range (Note 5)

Input Current (+IN, –IN, V , SHDN) (Note 2) ... 10mA

LTC6362C ................................................ 0°C to 70°C

LTC6362I .............................................–40°C to 85°C

LTC6362H.......................................... –40°C to 125°C

Maximum Junction Temperature .......................... 150°C

Storage Temperature Range .................. –65°C to 150°C

OCM

Output Short-Circuit Duration (Note 3) ............ Indefinite

Operating Temperature Range (Note 4)

LTC6362C/LTC6362I............................–40°C to 85°C

LTC6362H.......................................... –40°C to 125°C

PIN CONFIGURATION

TOP VIEW

–IN

1

2

3

4

8

7

6

5

+IN

–IN

1

2

3

4

8 +IN

V

SHDN

OCM

V

7 SHDN

OCM

+

–

+

V

6 V

V

5 –OUT

+OUT

9

+OUT

–OUT

–

V

MS8 PACKAGE

8-LEAD PLASTIC MSOP

= 150°C, θ = 273°C/W, θ = 45°C/W

DD PACKAGE

8-LEAD (3mm × 3mm) PLASTIC DFN

T

JMAX

JA

JC

T

= 150°C, θ = 39.7°C/W, θ = 45°C/W

JA JC

JMAX

–

EXPOSED PAD (PIN 9) IS V , MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH

LTC6362CMS8#PBF

LTC6362IMS8#PBF

LTC6362HMS8#PBF

LTC6362CDD#PBF

LTC6362IDD#PBF

LTC6362HDD#PBF

TAPE AND REEL

PART MARKING*

LTGCN

PACKAGE DESCRIPTION

SPECIFIED TEMPERATURE RANGE

LTC6362CMS8#TRPBF

LTC6362IMS8#TRPBF

LTC6362HMS8#TRPBF

LTC6362CDD#TRPBF

LTC6362IDD#TRPBF

LTC6362HDD#TRPBF

8-Lead Plastic MSOP

0°C to 70°C

LTGCN

8-Lead Plastic MSOP

–40°C to 85°C

–40°C to 125°C

0°C to 70°C

LTGCN

8-Lead Plastic MSOP

LGCM

8-Lead (3mm × 3mm) Plastic DFN

LGCM

–40°C to 85°C

–40°C to 125°C

LGCM

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

6362fa

2

LTC6362

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V⁺= 5V, V^–= 0V, V_CM= V_OCM= V_ICM= 2.5V, V_SHDN= open. V_Sis defined

as (V⁺– V^–). V_OUTCMis defined as (V_+OUT+ V_–OUT)/2. V_ICMis defined as (V_+IN+ V_–IN)/2. V_OUTDIFFis defined as (V_+OUT– V_–OUT).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

(Note 6)

Differential Offset Voltage (Input Referred)

V = 3V

S

OSDIFF

V

=1.5V

50

65

200

350

250

600

µV

ICM

l

V

= 2.75V

ICM

V = 5V

S

V

= 2.5V

50

75

200

350

260

600

µV

ICM

l

V

= 4.5V

ICM

l

Differential Offset Voltage Drift (Input Referred) V = 3V

0.9

2.5

µV/°C

∆V

/∆T (Note 7)

OSDIFF

S

V = 5V

S

I (Note 8)

B

Input Bias Current

V = 3V

S

V

=1.5V

100

75

350

500

350

850

nA

ICM

l

V

= 2.5V

ICM

V = 5V

S

V

= 2.5V

75

260

460

350

850

nA

ICM

l

V

= 4.5V

ICM

l

Input Bias Current Drift

Input Offset Current

V = 3V

S

1.1

0.9

nA/°C

∆I /∆T

S

B

V = 5V

I

(Note 8)

V = 3V

S

OS

V

=1.5V

75

325

650

nA

ICM

l

V

= 2.5V

125

425

ICM

1200

V = 5V

S

V

=2.5V

75

325

500

nA

ICM

l

V

= 4.5V

125

425

ICM

1200

R

Input Resistance

Common Mode

Differential Mode

14

32

MΩ

kΩ

IN

C

Input Capacitance

Differential Mode

2

pF

nV/√Hz

pA/√Hz

nV/√Hz

IN

e

Differential Input Noise Voltage Density

Input Noise Current Density

Common Mode Noise Voltage Density

Input Common Mode Range

f = 100kHz, Not Including R /R Noise

3.9

0.8

14.3

n

I

F

i

n

f = 100kHz, Not Including R /R Noise

I F

e

f = 100kHz

V = 3V

nvocm

l

V

(Note 9)

0

3

5

V

ICMR

S

V = 5V

S

l

CMRRI (Note 10)

CMRRIO (Note 10)

PSRR (Note 11)

Input Common Mode Rejection Ratio

V = 3V, V

S

from 0V to 3V

70

73

95

98

dB

S

ICM

(Input Referred) ∆V /∆V

V = 5V, V

from 0V to 5V

ICM

OSDIFF

l

Output Common Mode Rejection Ratio

(Input Referred) ∆V /∆V

V = 3V, V

from 0.5V to 2.5V

from 0.5V to 4.5V

75

55

100

90

dB

S

OCM

V = 5V, V

OCM

OSDIFF

S

l

Differential Power Supply Rejection

(∆V /∆V

V = 2.8V to 5.25V

S

80

105

dB

)

OSDIFF

S

l

PSRRCM (Note 11)

Output Common Mode Power Supply Rejection V = 2.8V to 5.25V

S

58

72

dB

(∆V /∆V

)

S

OSCM

6362fa

3

LTC6362

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V⁺= 5V, V^–= 0V, V_CM= V_OCM= V_ICM= 2.5V, V_SHDN= open. V_Sis defined

as (V⁺– V^–). V_OUTCMis defined as (V_+OUT+ V_–OUT)/2. V_ICMis defined as (V_+IN+ V_–IN)/2. V_OUTDIFFis defined as (V_+OUT– V_–OUT).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

GCM

V = 3V, V

S

from 0.5V to 2.5V

from 0.5V to 4.5V

1

V/V

Common Mode Gain (∆V

/∆V

)

S

OCM

OUTCM

OCM

V = 5V, V

l

Common Mode Gain Error 100 • (GCM – 1)

Output Balance (∆V /∆V

V = 3V, V

S

from 0.5V to 2.5V

from 0.5V to 4.5V

0.07

0.16

0.4

%

∆GCM

S

OCM

V = 5V, V

BAL

)

∆V

OUTDIFF

= 2V

OUTCM

OUTDIFF

l

–57

–35

dB

Single-Ended Input

Differential Input

A

V

Open-Loop Voltage Gain

Common Mode Offset Voltage

(V – V

95

dB

VOL

l

V = 3V

6

30

mV

OSCM

S

)

V = 5V

S

OUTCM

OCM

l

Common Mode Offset Voltage Drift

Output Signal Common Mode Range

(Voltage Range for the V Pin)

45

μV/°C

∆V

/∆T

(Note 9)

OSCM

l

V

OCM

V

OCM

Driven Externally, V = 3V

0.5

2.5

4.5

V

OUTCMR

S

Driven Externally, V = 5V

OCM

S

l

V

Self-Biased Voltage at the V

V

OCM

V

OCM

Not Connected, V = 3V

1.475

2.475

1.5

2.5

1.525

2.525

V

OCM

S

Not Connected, V = 5V

S

l

R

Input Resistance, V

110

170

230

kΩ

INVOCM

OCM

l

V

Output Voltage, High, Either Output Pin

Output Voltage, Low , Either Output Pin

I = 0mA, V = 3V

2.85

2.75

2.93

2.85

V

OUT

L

S

I = –5mA, V = 3V

L

S

l

I = 0mA, V = 5V

4.8

4.7

4.93

4.85

V

L

S

I = –5mA, V = 5V

L

S

l

I = 0mA, V = 3V

0.05

0.13

0.15

0.3

V

L

S

I = 5mA, V = 3V

L

S

l

I = 0mA, V = 5V

0.05

0.13

0.2

0.4

V

L

S

I = 5mA, V = 5V

L

S

l

I

Output Short-Circuit Current, Either Output Pin V = 3V

13

15

25

35

mA

SC

S

V = 5V

S

SR

Slew Rate

Differential 8V Output

45

V/μs

P-P

GBWP

Gain-Bandwidth Product

f

= 200kHz

145

90

180

MHz

TEST

l

f

–3dB Bandwidth

R = R = 1k

34

MHz

–3dB

I

F

HD2/HD3

2nd/3rd Order Harmonic Distortion

Single-Ended Input

f = 1kHz, V

= 8V

–120/–116

–106/–103

–84/–76

dBc

OUT

P-P

f = 10kHz, V

= 8V

P-P

OUT

f = 100kHz, V

= 8V

P-P

OUT

t

Settling Time to a 2V Output Step

0.1%

160

180

230

440

ns

s

P-P

0.01%

0.0015% (16-Bit)

4ppm (18-Bit)

Settling Time to a 8V Output Step

0.1%

230

300

460

550

ns

P-P

0.01%

0.0015% (16-Bit)

4ppm (18-Bit)

l

V (Note 12)

Supply Voltage Range

Supply Current

2.8

5.25

V

S

I

V = 3V, Active

0.9

0.96

1.05

mA

S

l

V = 3V, Shutdown

S

55

1

130

µA

V = 5V, Active

S

1.06

1.18

mA

l

V = 5V, Shutdown

S

70

140

µA

6362fa

4

LTC6362

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V⁺= 5V, V^–= 0V, V_CM= V_OCM= V_ICM= 2.5V, V_SHDN= open. V_Sis defined

as (V⁺– V^–). V_OUTCMis defined as (V_+OUT+ V_–OUT)/2. V_ICMis defined as (V_+IN+ V_–IN)/2. V_OUTDIFFis defined as (V_+OUT– V_–OUT).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

SHDN Input Logic Low

SHDN Input Logic High

Turn-On Time

0.8

V

IL

IH

2

t

2

μs

ON

OFF

Turn-Off Time

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 9: Input common mode range is tested by verifying that at the limits

stated in the Electrical Characteristics table, the differential offset (V

)

OSDIFF

and common mode offset (V

) have not deviated by more than 1mV

OSCM

and 35mV respectively compared to the V

= 2.5V (at V = 5V) and

ICM

S

V

ICM

= 1.5V (at V = 3V) cases.

S

Note 2: Input pins (+IN, –IN, V

and SHDN) are protected by steering

OCM

diodes to either supply. If the inputs should exceed either supply voltage,

the input current should be limited to less than 10mA. In addition, the

inputs +IN, –IN are protected by a pair of back-to-back diodes. If the

differential input voltage exceeds 1.4V, the input current should be limited

to less than 10mA.

Output common mode range is tested by verifying that at the limits stated

in the Electrical Characteristics table, the common mode offset (V

)

OSCM

has not deviated by more than 15mV compared to the V

= 2.5V

OCM

(at V = 5V) and V

= 1.5V (at V = 3V) cases.

S

OCM

S

Note 10: Input CMRR is defined as the ratio of the change in the input

Note 3: A heat sink may be required to keep the junction temperature

below the absolute maximum rating when the output is shorted

indefinitely.

common mode voltage at the pins +IN or –IN to the change in differential

input referred offset voltage. Output CMRR is defined as the ratio of

the change in the voltage at the V

pin to the change in differential

OCM

input referred offset voltage. This specification is strongly dependent on

feedback ratio matching between the two outputs and their respective

inputs and it is difficult to measure actual amplifier performance (see

Effects of Resistor Pair Mismatch in the Applications Information section

of this data sheet). For a better indicator of actual amplifier performance

independent of feedback component matching, refer to the PSRR

specification.

Note 11: Differential power supply rejection (PSRR) is defined as the

ratio of the change in supply voltage to the change in differential input

referred offset voltage. Common mode power supply rejection (PSRRCM)

is defined as the ratio of the change in supply voltage to the change in the

common mode offset voltage.

Note 4: The LTC6362C and LTC6362I are guaranteed functional over

the operating temperature range of –40°C to 85°C. The LTC6362H is

guaranteed functional over the operating temperature range of –40°C to

125°C.

Note 5: The LTC6362C is guaranteed to meet specified performance from

0°C to 70°C.The LTC6362I is guaranteed to meet specified performance

from –40°C to 85°C. The LTC6362C is designed, characterized and

expected to meet specified performance from –40°C to 85°C, but is not

tested or QA sampled at these temperatures. The LTC6362H is guaranteed

to meet specified performance from –40°C to 125°C.

Note 6: Differential input referred offset voltage includes offset due to

input offset current across 1k source resistance.

Note 7: Maximum differential input referred offset voltage drift is

determined by a large sampling of typical parts. Drift is not guaranteed by

test or QA sampled at this value.

Note 12: Supply voltage range is guaranteed by power supply rejection

ratio test.

Note 8: Input bias current is defined as the maximum of the input currents

flowing into either of the input pins (–IN and +IN). Input Offset current is

+

–

defined as the difference between the input currents (I = I – I ).

OS

B

6362fa

5

LTC6362

TYPICAL PERFORMANCE CHARACTERISTICS

Differential Input Offset Voltage

vs Temperature

Input Offset Current

vs Temperature

Differential Input Offset Voltage

vs Input Common Mode Voltage

300

250

200

150

100

50

100

300

250

200

150

100

50

V

= 5V, 0V

= 2.5V

V

=

ICM

OCM

2ꢀ5V

= 0V

V

=

ICM

OCM

2ꢀ5V

= 0V

S

OCM

S

75

50

TYPICAL UNIT

FIVE TYPICAL UNITS

25

0

–25

–50

–75

–50

–100

–150

–200

–50

–100

–150

–200

T

= 125°C

= 25°C

= –40°C

A

–100

–25

0

50

75 100 125

1

3

–50

0

25

50

75 100 125

–50

25

0

2

4

5

–25

TEMPERATURE (°C)

INPUT COMMON MODE VOLTAGE (V)

6362 G02

6362 G03

6362 G01

Common Mode Offset Voltage

vs Temperature

Input Bias Current vs Input

Common Mode Voltage

Supply Current vs Temperature

800

600

15

1.2

1.1

1.0

0.9

0.8

0.7

V

= 5V

S

V

=

ICM

OCM

2ꢀ5V

= 0V

S

400

10

5

FIVE TYPICAL UNITS

200

V

= 5V

= 3V

S

0

–200

–400

–600

–800

–1000

–1200

–1400

–1600

0

–5

–10

–15

0

1

2

3

4

5

50

75 100 125

–50

0

25

50

75 100 125

–50

0

25

–25

TEMPERATURE (°C)

INPUT COMMON MODE VOLTAGE (V)

TEMPERATURE (°C)

6362 G05

6362 G04

6362 G06

Supply Current

vs Supply Voltage

Shutdown Supply Current

vs Supply Voltage

Supply Current vs SHDN Voltage

1.2

1.0

0.8

0.6

0.4

0.2

0

1.2

1.0

0.8

0.6

0.4

0.2

0

90

80

70

60

50

40

30

20

10

0

–

V

= 5V

S

V

= V

SHDN

T

= 125°C

= 25°C

T

= 125°C

= 25°C

A

T

= 125°C

= 25°C

A

= –40°C

0

1

2

3

4

5

0

1

2

3

4

5

0

1

2

5

3

4

SUPPLY VOLTAGE (V)

SHDN VOLTAGE (V)

SUPPLY VOLTAGE (V)

6362 G07

6362 G08

6362 G09

6362fa

6

LTC6362

TYPICAL PERFORMANCE CHARACTERISTICS

Turn-On and Turn-Off

Transient Response

Differential Output Impedance

vs Frequency

Input Noise Density vs Frequency

1000

100

10

100

10

1

100

10

1

V

=

ICM

2.ꢀV

= V

V

=

2ꢀ.V

F

S

I

= 0V

R = R = 1k

OCM

V

SHDN

V

OUTDIFF

e

n

i

n

1

100k

0.1

10

100

1k

10k 100k

1M

10M

1M

10M

100M

1G

5µs/DIV

6362 G10

FREQUENCY (Hz)

6362 G11

6362 G12

Common Mode Rejection Ratio

vs Frequency

Differential Power Supply

Rejection Ratio vs Frequency

Slew Rate vs Temperature

100

90

80

70

60

50

40

30

120

110

100

90

80

70

60

50

40

30

20

10

0

60

55

V

= 2ꢀ5V

V

=

2ꢀ5V

V

=

2ꢀ5V

S

I

+

R = R = 1k

PSRR

F

–

V

= 8V

P-P

OUTDIFF

DIFFERENTIAL INPUT

SLEW MEASURED 10% TO 90%

FALLING

50

45

40

RISING

50

–25

0

75 100 125

1k

10k 100k

1M

10M 100M 1G

1k

10k 100k

1M

10M 100M 1G

–50

25

FREQUENCY (Hz)

TEMPERATURE (°C)

6362 G13

6362 G14

6362 G15

Overdriven Output Transient

Response

Small-Signal Step Response

Large-Signal Step Response

V

INDIFF

V

+OUT

V

+OUT

V

–OUT

V

–OUT

V

OUTDIFF

6362 G17

6362 G16

636± G18

100ns/DIV

P-P

V

= ±±2.V

1µs/DIV

V

= 2ꢀ5V

V

=

2ꢀ.V

= 200mV

S

= 13V

= 1k

= 8V

= 1k

INDIFF

LOAD

P-P

INDIFF

LOAD

P-P

INDIFF

R = R = 1k

LOAD

R

I

F

R

= 1k

6362fa

7

LTC6362

TYPICAL PERFORMANCE CHARACTERISTICS

Frequency Response

vs Closed-Loop Gain

60

Frequency Peaking

vs Load Capacitance

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

V

=

2ꢀ5V

= V

V

=

ICM

OCM

R = R = 1k

2.5V

= 0V

S

= 0V

ICM

LOAD

OCM

= 1k

50

40

R

I

F

R

= 1k

LOAD

A

V

A

V

A

V

A

V

A

V

A

V

= 1, R = 1k, R = 1k

I F

30

= 2, R = 500Ω, R = 1k

I

F

= 5, R = 400Ω, R = 2k

20

= 10, R = 200Ω, R = 2k

I

F

= 20, R = 100Ω, R = 2k

I

F

10

= 100, R = 20Ω, R = 2k

I

F

0

CAPACITOR VALUES ARE

FROM EACH OUTPUT TO

GROUND THROUGH 35Ω

SERIES RESISTANCE

–10

–20

100k

1M

10M

FREQUENCY (Hz)

100M

1G

10

100

1000

10000

CAPACITIVE LOAD (pF)

6362 G19

6362 G20

Settling Time to 8V_P-P

Output Step

Settling Time vs Output Step

DC Linearity

700

600

500

400

300

200

100

0

100

80

5

4

150

120

90

V

= 5V, 0V

F

V

= 5V, 0V

F

S

I

S

I

R = R = 1k

18-BIT

60

3

40

2

60

16-BIT

20

1

30

ERROR

0

–20

–40

–60

–80

–100

–1

–2

–3

–4

–5

–30

–60

–90

V

=

ICM

R = R = 1k

2ꢀ5V

= V

F

S

= 0V

OCM

I

V

OUTDIFF

NO LOAD

LINEAR FIT FOR –4V < V

–120

–150

< 4V

INDIFF

6362 G22

2

3

4

5

6

7

8

–5 –4 –3

1

2

3

4

5

–2 –1

V

0

0.5µs/DIV

DIFFERENTIAL OUTPUT STEP (V

)

(V)

P-P

INDIFF

6362 G21

6362 G23

Harmonic Distortion vs Input

Common Mode Voltage

Harmonic Distortion vs Output

Amplitude

Harmonic Distortion vs Frequency

–70

–80

–90

–70

–80

–90

V

= 5V, 0V

= 2.5V

V

= 5V, 0V

= 2.5V

V

= 5V, 0V

= 2.5V

OCM

S

OCM

S

OCM

S

R = R = 1k

I

F

I

F

I

F

V

= 8V

V

IN

= 8V

f

= 2kHz

OUTDIFF

P-P

OUTDIFF

P-P

IN

SINGLE-ENDED INPUT,

GROUND REFERENCED

f

= 2kHz

SINGLE-ENDED INPUT,

GROUND REFERENCED

–90

DIFFERENTIAL INPUTS

–100

–110

–120

–130

–100

–110

–120

–130

–140

HD3

–100

–110

–120

–130

HD2

HD3

1

10

FREQUENCY (kHz)

100

0

1

2

3

4

5

0

2

4

6

8

10

INPUT COMMON MODE VOLTAGE (V)

V

(V

)

OUTDIFF P-P

6362 G24

6362 G25

6362 G26

6362fa

8

LTC6362

PIN FUNCTIONS

–

–IN (Pin 1): Inverting Input of Amplifier. Valid input range

V (Pin 6/Exposed Pad Pin 9): Negative Power Supply,

–

+

is from V to V .

Typically 0V. Negative supply can be negative as long as

2.8V ≤ (V – V ) ≤ 5.25V still holds.

+

–

V

(Pin 2): Output Common Mode Reference Voltage.

OCM

The voltage on this pin sets the output common mode

voltage level. If left floating, an internal resistor divider

develops a default voltage of 2.5V with a 5V supply.

SHDN (Pin 7): When SHDN is floating or directly tied to

+

V the LTC6362 is in the normal (active) operating mode.

–

WhentheSHDNpinisconnectedtoV , thepartisdisabled

and draws approximately 70µA of supply current.

+

V (Pin 3): Positive Power Supply. Operational supply

–

range is 2.8V to 5.25V when V = 0V.

+IN (Pin 8): Noninverting Input of Amplifier. Valid input

range is from V to V .

–

+

+OUT (Pin 4): Positive Output Pin. Output capable of

swinging rail-to-rail.

–OUT (Pin 5): Negative Output Pin. Output capable of

swinging rail-to-rail.

BLOCK DIAGRAM

8

7

6

5

–

+IN

SHDN

V

–OUT

–

+

–

+

–

+

V

+

V

+

–

V

340k

+

–

V

+

OCM

–

V

–

+

–

+

V

+

–IN

+OUT

V

OCM

1

2

3

4

6362 BD

6362fa

9

LTC6362

APPLICATIONS INFORMATION

Functional Description

General Amplifier Applications

The LTC6362 is a low power, low noise, high DC accuracy

fully differential operational amplifier/ADC driver. The

amplifier is optimized to convert a fully differential or

single-ended signal to a low impedance, balanced differ-

ential output suitable for driving high performance, low

powerdifferentialsuccessiveapproximationregister(SAR)

ADCs. The balanced differential nature of the amplifier

also provides even-order harmonic distortion cancella-

tion, and low susceptibility to common mode noise (like

power supply noise).

In Figure 1, the gain to V

given by:

from V and V

is

INM

OUTDIFF

INP





R_F

R

V_OUTDIFF= V_+OUT− V_–OUT

≈

• V_INP– V

(

)

INM







_I

Note from the previous equation, the differential output

voltage (V – V ) is completely independent of

input and output common mode voltages, or the voltage

at the common mode pin. This makes the LTC6362 ideally

suited for pre-amplification, level shifting and conversion

of single-ended signals to differential output signals for

driving differential input ADCs.

+OUT

–OUT

The outputs of the LTC6362 are capable of swinging rail-

to-rail and can source or sink up to 35mA of current. The

LTC6362 is optimized for high bandwidth and low power

applications. Load capacitances above 10pF to ground or

5pF differentially should be decoupled with 10Ω to 100Ω

of series resistance from each output to prevent oscilla-

tion or ringing. Feedback should be taken directly from

the amplifier output. Higher voltage gain configurations

tend to have better capacitive drive capability than lower

gain configurations due to lower closed-loop bandwidth.

Output Common Mode and V

OCM

The output common mode voltage is defined as the aver-

age of the two outputs:

V_+OUT+ V



_–OUT

V_OUTCM= V_OCM

=









2

As the equation shows, the output common mode voltage

is independent of the input common mode voltage, and

Input Pin Protection

is instead determined by the voltage on the V

pin, by

The LTC6362 input stage is protected against differential

input voltages which exceed 1.4V by two pairs of series

diodes connected back-to-back between +IN and –IN.

Moreover, all pins have clamping diodes to both power

supplies. If any pin is driven to voltages which exceed

either supply, the current should be limited to under 10mA

to prevent damage to the IC.

OCM

means of an internal common mode feedback loop.

If the V pin is left open, an internal resistor divider

OCM

develops a default voltage of 2.5V with a 5V supply. The

V

pin can be overdriven to another voltage if desired.

OCM

For example, when driving an ADC, if the ADC makes a

reference available for setting the common mode volt-

age, it can be directly tied to the V

pin, as long as

OCM

SHDN Pin

the ADC is capable of driving the 170k input resistance

presented by the V pin. The Electrical Characteristics

The LTC6362 has a SHDN pin which when driven to within

0.8V above the negative rail, will shut down amplifier op-

eration such that only 70µA is drawn from the supplies.

Pull-down circuitry should be capable of sinking at least

4µA to guarantee complete shutdown across all condi-

tions. For normal operation, the SHDN pin should be left

floating or tied to the positive rail.

OCM

table specifies the valid range that can be applied to the

pin (V ).

V

OCM

OUTCMR

6362fa

10

LTC6362

APPLICATIONS INFORMATION

Input Common Mode Voltage Range

current follows ∆I /∆V = 75nA/V, with I at V = 2.5V

B

ICM

B

ICM

typically below 75nA on a 5V supply. For common mode

voltages ranging from 1.1V below the positive supply to

0.2V below the positive supply, input bias current follows

The LTC6362’s input common mode voltage (V ) is

ICM

defined as the average of the two input pins, V and

+IN

V

. The inputs of the LTC6362 are capable of swinging

–IN

∆I /∆V = 25nA/V, with I at V = 4.5V typically below

B

ICM

B

ICM

rail-to-rail and as such the valid range that can be used for

75nAona5Vsupply. Operatingwithintheserangesallows

the amplifier to be used in applications with high source

resistances where errors due to voltage drops must be

–

+

V

ICM

is V to V . However, due to external resistive divider

action of the gain and feedback resistors, the effective

range of signals that can be processed is even wider. The

input common mode range at the op amp inputs depends

minimized. For applications where V

is within 0.2V of

ICM

either rail, input bias current may reach values over 1µA.

on the circuit configuration (gain), V

and V (refer to

OCM

CM

Figure 1). For fully differential input applications, where

Input Impedance and Loading Effects

V

INP

= –V , the common mode input is approximately:

INM

The low frequency input impedance looking into the V

INP

V_+IN+ V_–IN

R_I

R_I+R_F

R_F

R_I+R_F

or V

input of Figure 1 depends on how the inputs are

V

=

≈ V_OCM

•

+ V_CM•

INM

ICM

2

driven. For fully differential input sources (V = –V ),

INP

INM

the input impedance seen at either input is simply:

With single-ended inputs, there is an input signal compo-

nent to the input common mode voltage. Applying only

R

INP

= R = R

INM I

V

(setting V

to zero), the input common voltage is

INP

INM

For single-ended inputs, because of the signal imbalance

at the input, the input impedance actually increases over

thebalanceddifferentialcase.Theinputimpedancelooking

into either input is:

approximately:

V_+IN+ V_–IN

V

=

ICM

2

R_I

R_I+R_F

R_F

R_I+R_F

V

R_F

R_I+R_F

INP

2

R_INP=R_INM

=

≈ V_OCM

•

+ V_CM

•

+

•





_F

R_F

R +R

1

 

2

 

1–

•

 







I

This means that if, for example, the input signal (V

)

INP

is a sine, an attenuated version of that sine signal also

appears at the op amp inputs.

Inputsignalsourceswithnon-zerooutputimpedancescan

alsocausefeedbackimbalancebetweenthepairoffeedback

networks. For the best performance, it is recommended

that the input source output impedance be compensated.

If input impedance matching is required by the source, a

termination resistor R1 should be chosen (see Figure 2)

such that:

R

F

I

V

+IN

V

–OUT

+

–

V

INP

+

V

OCM

+

V

CM

–

+

–

V

INM

R_INM•R_S

R1=

R

I

R

F

V

–IN

V

+OUT

6362 F01

R_INM–R_S

Figure 1. Definitions and Terminology

According to Figure 2, the input impedance looking into

thedifferentialamp(R )reflectsthesingle-endedsource

INM

Input Bias Current

case, given above. Also, R2 is chosen as:

Input bias current varies according to V . For common

ICM

R1•R_S

R2=R1||R_S=

R1+R_S

mode voltages ranging from 0.2V above the negative

supply to 1.1V below the positive supply, input bias

6362fa

11

LTC6362

APPLICATIONS INFORMATION

R

INM

R

I2

R

F2

V

+IN

V

–OUT

R

F

S

I

+

–

V

INP

+

R1

V

S

V

VOCM

OCM

–

+

–

+

V

CM

–

+

–

V

INM

R1 CHOSEN SO THAT R1 || R

R2 CHOSEN TO BALANCE R1 || R

= R

S

+

INM

S

R

I1

R

V

F1

–IN

V

+OUT

6362 F03

R

F

I

6405 F04

Figure 3. Real-World Application with

Feedback Resistor Pair Mismatch

R2 = R || R1

S

Figure 2. Optimal Compensation for Signal Source Impedance

When the feedback ratios mismatch (Δβ), common mode

to differential conversion occurs. Setting the differential

Effects of Resistor Pair Mismatch

input to zero (V

= 0), the degree of common mode

INDIFF

to differential conversion is given by the equation:

Figure 3 shows a circuit diagram which takes into consid-

eration that real world resistors will not match perfectly.

Assuming infinite open-loop gain, the differential output

relationship is given by the equation:

V

≈ (V – V ) • ∆β/β

OUTDIFF

CM

OCM

AVG

In general, the degree of feedback pair mismatch is a

source of common mode to differential conversion of

both signals and noise. Using 0.1% resistors or better will

mitigate most problems. A low impedance ground plane

should be used as a reference for both the input signal

V

= V

– V

OUT(DIFF)

+OUT

–OUT

R

∆β

β

AVG

F

≈ V

•

+ V

•

– V

•

INDIFF

CM

OCM

R

β

source and the V

pin.

I

AVG

OCM

where R is the average of R and R , and R is the

Noise

F

F1

F2

I

average of R and R .

I1

I2

TheLTC6362’sdifferentialinputreferredvoltageandcurrent

noisedensitiesare3.9nV/√Hzand0.8pA/√Hz,respectively.

In addition to the noise generated by the amplifier, the

surrounding feedback resistors also contribute noise. A

simplified noise model is shown in Figure 4. The output

noise generated by both the amplifier and the feedback

components is given by the equation:

β

is defined as the average feedback factor from the

AVG

outputs to their respective inputs:





R_I1

R_I2

R_I2+R

1

β_AVG= •

2

+





R +R



_F2

I1

F1

ꢀ

∆β is defined as the difference in the feedback factors:

R_I2R_I1

R_I2+R_F2R_I1+R_F1

Here, V and V are defined as the average and





²







R_F

R_I

2

∆β =

–

e • 1+

+2• i •R

(

)

ni

n

F

















e_no=

²

R_{I }

CM

INDIFF



R

2

^F

the difference of the two input voltages V and V

respectively:

,

+ 2• e

•

+2•e_nRF

INP

INM



nRI



V

_INP+ V

For example, if R = R = 1k, the output noise of the circuit

no

F

I

INM

V_CM

=

e

= 12nV/√Hz.

2

If the circuits surrounding the amplifier are well balanced,

common mode noise (e ) does not appear in the dif-

V

INDIFF

= V – V

INP INM

nvocm

ferential output noise equation given above.

6362fa

12

LTC6362

APPLICATIONS INFORMATION

2

speed of the amplifier as well as the feedback factor. Since

the LTC6362 is designed to be stable in a differential signal

gain of 1 (where R = R or β = 1/2), the maximum f

e

nRI

e

nRF

R

I

R

F

2

i

n+

I

F

–3dB

is obtained and measured in this gain setting, as reported

in the Electrical Characteristics table.

+

–

2

In most amplifiers, the open-loop gain response exhibitsa

conventionalsingle-poleroll-offformostofthefrequencies

beforetheunity-gaincrossoverfrequency,andtheGBWand

unity-gain frequency are close to each other. However, the

LTC6362 is intentionally compensated in such a way that

e

no

2

i

n–

e

2

ni

2

e

nRI

e

nRF

R

I

R

F

its GBW is significantly larger than its f

. This means

–3dB

6362 F04

that at lower frequencies where the amplifier inputs gen-

erally operate, the amplifier’s gain and thus the feedback

loop gain is larger. This has the important advantage of

further linearizing the amplifier and improving distortion

at those frequencies.

Figure 4. Simplified Noise Model

TheLTC6362’sinputreferredvoltagenoisecontributesthe

equivalent noise of a 920Ω resistor. When the feedback

network is comprised of resistors whose values are larger

than this, the output noise is resistor noise and amplifier

currentnoisedominant.Forfeedbacknetworksconsisting

of resistors with values smaller than 920Ω, the output

noise is voltage noise dominant.

Feedback Capacitors

In cases where the LTC6362 is connected such that the

combinationofparasiticcapacitances(device+PCB)atthe

inverting input forms a pole whose frequency lies within

the closed-loop bandwidth of the amplifier, a capacitor

Lower resistor values always result in lower noise at the

penalty of increased distortion due to increased loading of

thefeedbacknetworkontheoutput.Higherresistorvalues

will result in higher output noise, but typically improved

distortion due to less loading on the output. For this rea-

son, when LTC6362 is configured in a differential gain of

1, using feedback resistors of at least 1k is recommended.

(C ) can be added in parallel with the feedback resistor

F

(R ) to cancel the degradation on stability. C should be

F

chosen such that it generates a zero at a frequency close

to the frequency of the pole.

In general, a larger value for C reduces the peaking (over-

F

shoot)oftheamplifierinbothfrequencyandtimedomains,

but also decreases the closed-loop bandwidth (f

).

–3dB

GBW vs f

–3dB

Board Layout and Bypass Capacitors

Gain-bandwidth product (GBW) and –3dB frequency

(f )havebeenspecifiedintheElectricalCharacteristics

For single supply applications, it is recommended that

high quality 0.1µF ceramic bypass capacitors be placed

–3dB

tableastwodifferentmetricsforthespeedoftheLTC6362.

+

–

GBW is obtained by measuring the open-loop gain of the

directly between the V and the V pin with short con-

–

amplifier at a specific frequency (f

), then calculating

nections. The V pins (including the exposed pad in the

TEST

gain • f

. GBW is a parameter that depends only on the

DD8 package) should be tied directly to a low impedance

ground plane with minimal routing. For dual (split) power

supplies, it is recommended that additional high quality

TEST

internal design and compensation of the amplifier and is

a suitable metric to specify the inherent speed capability

of the amplifier.

+

0.1µF ceramic capacitors be used to bypass V to ground

–

and V to ground, again with minimal routing. Small

f

, on the other hand, is a parameter of more practical

–3dB

geometry (e.g., 0603) surface mount ceramic capacitors

have a much higher self-resonant frequency than leaded

capacitors, and perform best with LTC6362.

6362fa

interest in different applications and is by definition the

frequency at which the closed-loop gain is 3dB lower than

its low frequency value. The value of f

depends on the

–3dB

13

LTC6362

APPLICATIONS INFORMATION

To prevent degradation in stability response, it is highly

recommendedthatanystraycapacitanceattheinputpins,

+IN and –IN, be kept to an absolute minimum by keeping

printed circuit connections as short as possible.

Theselectionofanappropriatefilterdependsonthespecific

ADC, however the following procedure is suggested for

choosing filter component values. Begin by selecting an

appropriate RC time constant for the input signal. Gener-

ally, longer time constants improve SNR at the expense of

settling time. Output transient settling to 18-bit accuracy

will typically require over twelve RC time constants. To

select the resistor value, remember the resistors in the

decoupling network should be at least 10Ω. Keep in mind

that these resistors also serve to decouple the LTC6362

outputs from load capacitance. Too large of a resistor will

leave insufficient settling time. Too small of a resistor will

not properly dampen the load transient of the sampling

process, prolonging the time required for settling. For

lowest distortion, choose capacitors with low dielectric

absorption(suchasaC0Gmultilayerceramiccapacitor).In

general,largecapacitorvaluesattenuatethefixednonlinear

charge kickback, however very large capacitor values will

detrimentallyloadthedriveratthedesiredinputfrequency

and thus cause driver distortion. Smaller input swings will

in general allow for larger filter capacitor values due to

decreased loading demands on the driver. This property

however may be limited by the particular input amplitude

dependence of differential nonlinear charge kickback for

the specific ADC used.

Attheoutput,alwayskeepinmindthedifferentialnatureof

theLTC6362,becauseitiscriticalthattheloadimpedances

seen by both outputs (stray or intended), be as balanced

and symmetric as possible. This will help preserve the

balanced operation of the LTC6362 that minimizes the

generation of even-order harmonics and maximizes the

rejection of common mode signals and noise.

TheV

pinshouldbebypassedtothegroundplanewith

OCM

a high quality 0.1µF ceramic capacitor. This will prevent

common mode signals and noise on this pin from being

inadvertently converted to differential signals and noise

by impedance mismatches both externally and internally

to the IC.

Interfacing to ADCs

WhendrivinganADC,anadditionalpassivefiltershouldbe

used between the outputs of the LTC6362 and the inputs

of the ADC. Depending on the application, a single-pole

RC filter will often be sufficient. The sampling process

of ADCs creates a charge transient that is caused by the

switching in of the ADC sampling capacitor. This mo-

mentarily “shorts” the output of the amplifier as charge

is transferred between amplifier and sampling capacitor.

The amplifier must recover and settle from this load

transient before the acquisition period has ended, for a

valid representation of the input signal. The RC network

between the outputs of the driver and the inputs of the

ADC decouples the sampling transient of the ADC (see

Figure 5). The capacitance serves to provide the bulk

of the charge during the sampling process, while the

two resistors at the outputs of the LTC6362 are used to

dampen and attenuate any charge injected by the ADC.

The RC filter gives the additional benefit of band limiting

broadband output noise.

In some applications, placingseries resistorsatthe inputs

of the ADC may further improve distortion performance.

These series resistors function with the ADC sampling

capacitor to filter potential ground bounce or other high

speed sampling disturbances. Additionally the resistors

limit the rise time of residual filter glitches that manage to

propagatetothedriveroutputs.Restrictingpossibleglitch

propagation rise time to within the small signal bandwidth

of the driver enables less disturbed output settling.

For the specific application of LTC6362 driving the

LTC2379-18 SAR ADC in a gain of A = –1 configuration,

V

the recommended component values of the RC filter for

varying filter bandwidths are provided in Figure 5. These

component values are chosen for optimal distortion per-

formance. Broadband output noise will vary with filter

bandwidth.

6362fa

14

LTC6362

APPLICATIONS INFORMATION

5V

R

FILT

1k

C

CM

8

7

6

5

–

+IN

SHDN

V

–OUT

LTC6362

5V

2.5V

+

V

+

V

R

V

DD

S

REF

+

–

340k

+

–

A

IN

LTC2379-18

SAR ADC

V

OCM

C

DIFF

A

R

S

GND

–

V

–

V

FILTER BW

(Hz)

R

C

CM DIFF

R

S

+

FILT

V

–IN

V

+OUT

R

OCM

(Ω) (pF) (pF) (Ω)

1

2

3

4

110k

380k

1.1M

3.0M

10M

29M

125 3900 3900

35.7 3900 3900

100 470 470

175 100 100

75

100 18

0

1k

FILT

0.1µF

C

CM

V

IN

68

18

0.1µF

6362 F05

5V

Figure 5. Recommended Interface Solutions for Driving the LTC2379-18 SAR ADC

TYPICAL APPLICATIONS

Single-Ended-to-Differential Conversion of a 20V_P-PGround-Referenced Input with Gain of A_V= –0.4 to Drive an ADC

4.5V

V

+OUT

10V

806Ω

0.5V

5V

2.5V

V

IN

3.9nF

0Ω

5V

–10V

V

DD

35.7Ω

REF

2k

+

–

A

+

–

IN

V

OCM

LTC2379-18

SAR ADC

V

LTC6362

3.9nF

IN

0.1µF

SHDN

0Ω

+

–

IN

3.9nF

GND

2k

806Ω

6362 TA02

4.5V

V

–OUT

0.5V

6362fa

15

LTC6362

TYPICAL APPLICATIONS

Single-Ended-to-Differential Conversion of a 5V_P-P, 2.5V Referenced Input with Gain of A_V= –1.6 to Drive an ADC

4.5V

V

+OUT

1k

0.5V

5V

2.5V

3.9nF

0Ω

5V

V

DD

35.7Ω

REF

619Ω

0.1µF

+

–

5V

A

+

–

IN

V

OCM

LTC2379-18

SAR ADC

V

IN

3.9nF

LTC6362

SHDN

0Ω

0V

+

–

IN

3.9nF

GND

619Ω

1k

6362 TA03

4.5V

V

+

CM

–

2.5V

V

–OUT

0.5V

Differentially Driving an ADC with ∆V_IN= 8V_P-Pand Gain of A_V= 1

4.5V

V

+OUT

1k

0.5V

5V

2.5V

3.9nF

0Ω

5V

V

35.7Ω

REF

DD

1k

+

–

4.5V

A

+

–

IN

V

OCM

LTC2379-18

SAR ADC

V

INM

LTC6362

3.9nF

0.1µF

SHDN

0Ω

0.5V

+

–

IN

3.9nF

GND

1k

6362 TA04

4.5V

V

INP

V

–OUT

0.5V

Single-Ended-to-Differential Conversion of a 4V_P-PInput with Gain of A_V= 2 to Drive an ADC for Applications Where

the Importance of High Input Impedance Justifies Some Degradation in Distortion, Noise, and DC Accuracy. Input Is

True High Impedance, However Common Mode Noise and Offset Are Present on the Output. Additionally, When the

Input Signal Exceeds 2.8V_P-P, a Step in Input Offset Will Occur That Will Degrade Distortion Performance

4.5V

V

+OUT

0.5V

5V

2.5V

3.9nF

0Ω

5V

V

35.7Ω

REF

DD

+

–

A

+

–

IN

V

OCM

LTC2379-18

SAR ADC

LTC6362

3.9nF

0.1µF

SHDN

4.5V

0Ω

35.7Ω

+

–

IN

3.9nF

GND

6362 TA05

V

IN

4.5V

0.5V

V

–OUT

0.5V

6362fa

16

LTC6362

TYPICAL APPLICATIONS

Differentially Driving a Pipeline ADC with A_V= 1

100Ω

V

CM

= 0.9V

0.1µF

V

+OUT

1k

1.8V

1.5nF

5Ω

3.3V

V

CM

30Ω

DD

1k

+

–

A

16 BIT

+

–

IN

V

OCM

LTC2160

PIPELINE ADC

LTC6362

1.5nF

SHDN

5Ω

0.1µF

INPUT BW = 1.2MHz

+

25Msps

–

IN

FULL SCALE = 2V

P-P

1.5nF

GND

1k

6362 TA08

V

IN

V

–OUT

MEASURED PERFORMANCE FOR LTC6362 DRIVING LTC2160:

INPUT: f = 2kHz, –1dBFS

IN

SNR: 77.0dB

HD2: –98.9dBc

HD3: –102.3dBc

THD: –96.3dB

Differential Line Driver Connected in Gain of A_V= –1

3V

V

+OUT

1V

1k

2V

V

IN

5V

–1V

49.9Ω

1k

+

–

V

OCM

V

IN

LTC6362

100Ω

0.1µF

SHDN

+

–

6362 TA06

1k

3V

V

–OUT

2V

6362fa

17

LTC6362

TYPICAL APPLICATIONS

LTC6362 Used as Lowpass Filter/Driver with 10V_P-PSingled-Ended Input, Driving a SAR ADC

1.8nF

2k

1.8nF

0.1µF

4.5V

4-POLE FILTER

= 50kHz

5V

2.5V

f

–3dB

0.5V

100Ω

V

REF

DD

1.27k 1.27k 1.27k

1.8nF

5V

–5V

+

–

A

16 BIT

2Msps

V

+

–

LTC6362

IN

CM

IN

1.8nF

LTC2380-16

SAR ADC

1.8nF

100Ω

4.5V

0.1µF

+

–

IN

1.8nF

GND

1.8nF

1.27k 1.27k

1.27k

2k

6362 TA09

V

CM

0.5V

1.8nF

Differential A_V= 1 Configuration Using an LT^®5400 Quad-Matched Resistor Network

5V

LT5400

4.5V

R1

R2

R3

R4

1

2

3

4

8

7

6

5

V

–

+

+OUT

–OUT

+

V

OCM

0.5V V

INM

INP

0.5V

4.5V

LTC6362

0.1µF

SHDN

V

4.5V

–

0.5V

6362 TA10a

CMRR Comparison Using the LT5400 and 1% 0402 Resistors

100

90

80

70

60

50

40

30

20

10

0

V

= 5V, 0V

S

USING LT5400 MATCHED RESISTORS

USING 1% 0402 RESISTORS

10

100

1k

10k

100k

FREQUENCY (Hz)

6362 TA10b

6362fa

18

LTC6362

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

MS8 Package

8-Lead Plastic MSOP

(Reference LTC DWG # 05-08-ꢀꢂꢂ0 Rev F)

0.889 0.ꢀꢁ7

(.035 .005)

5.ꢁ3

3.ꢁ0 – 3.45

(.ꢁ0ꢂ)

(.ꢀꢁꢂ – .ꢀ3ꢂ)

MIN

3.00 0.ꢀ0ꢁ

(.ꢀꢀ8 .004)

(NOTE 3)

0.5ꢁ

(.0ꢁ05)

REF

0.ꢂ5

(.0ꢁ5ꢂ)

BSC

0.4ꢁ 0.038

(.0ꢀꢂ5 .00ꢀ5)

TYP

8

7 ꢂ 5

RECOMMENDED SOLDER PAD LAYOUT

3.00 0.ꢀ0ꢁ

(.ꢀꢀ8 .004)

(NOTE 4)

4.90 0.ꢀ5ꢁ

(.ꢀ93 .00ꢂ)

DETAIL “A”

0.ꢁ54

(.0ꢀ0)

0° – ꢂ° TYP

GAUGE PLANE

ꢀ

ꢁ

3

4

0.53 0.ꢀ5ꢁ

(.0ꢁꢀ .00ꢂ)

ꢀ.ꢀ0

(.043)

MAX

0.8ꢂ

(.034)

REF

DETAIL “A”

0.ꢀ8

(.007)

SEATING

PLANE

0.ꢁꢁ – 0.38

0.ꢀ0ꢀꢂ 0.0508

(.009 – .0ꢀ5)

(.004 .00ꢁ)

0.ꢂ5

(.0ꢁ5ꢂ)

BSC

TYP

MSOP (MS8) 0307 REV F

NOTE:

ꢀ. DIMENSIONS IN MILLIMETER/(INCH)

ꢁ. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.ꢀ5ꢁmm (.00ꢂ") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.ꢀ5ꢁmm (.00ꢂ") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.ꢀ0ꢁmm (.004") MAX

6362fa

19

LTC6362

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

DD Package

8-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1698 Rev C)

0.70 ±0.05

3.5 ±0.05

2.10 ±0.05 (2 SIDES)

1.65 ±0.05

PACKAGE

OUTLINE

0.25 ±0.05

0.50

BSC

2.38 ±0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

R = 0.125

0.40 ±0.10

TYP

5

8

3.00 ±0.10

(4 SIDES)

1.65 ±0.10

(2 SIDES)

PIN 1

TOP MARK

(NOTE 6)

(DD8) DFN 0509 REV C

4

1

0.25 ±0.05

0.75 ±0.05

0.200 REF

0.50 BSC

2.38 ±0.10

BOTTOM VIEW—EXPOSED PAD

0.00 – 0.05

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON TOP AND BOTTOM OF PACKAGE

6362fa

20

LTC6362

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

1, 2, 9, 13, 20

4

A

05/12 Added DFN package

Added typical spec for 2V

t

P-P

S

6362fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

21

LTC6362

TYPICAL APPLICATION

Single-Ended-to-Differential Conversion of a 10V_P-PGround-Referenced Input with Gain of A_V= –0.8

to Drive a 5V Reference SAR ADC

4.5V

V

+OUT

5V

1k

0.5V

5V

2.5V

V

IN

3.9nF

0Ω

5V

–5V

V

35.7Ω

REF

DD

1.24k

0.1µF

+

–

A

18 BIT

+

–

IN

V

OCM

LTC2379-18

SAR ADC

V

LTC6362

3.9nF

IN

SHDN

0Ω

+

1.6Msps

–

IN

3.9nF

GND

1.24k

1k

6362 TA07

4.5V

V

–OUT

0.5V

RELATED PARTS

PART NUMBER

Operational Amplifiers

LT6350

DESCRIPTION

COMMENTS

Low Noise, Single-Ended to Differential Converter/

ADC Driver

4.8mA, –97dBc Distortion at 100kHz, 4V

Output

P–P

LTC6246/LTC6247/

LTC6248

Single/Dual/Quad 180MHz Rail-to-Rail Low Power

Op Amps

1mA/Amplifier, 4.2nV/√Hz

LTC6360

1GHz Very Low Noise Single-Ended SAR ADC Driver 13.6mA, HD2/HD3 = –103dBc/–109dBc at 40kHz, 4V Output

P-P

with True Zero Output

LTC1992/LTC1992-X

LT1994

3MHz to 4MHz Fully Differential Input/Output

Amplifiers

Internal Feedback Resistors Available (G =1, 2, 5,10)

70MHz Low Noise, Low Distortion Fully Differential 13mA, –94dBc Distortion at 1MHz, 2V Output

Input/Output Amplifier/Driver

P-P

ADCs

LTC2379-18/LTC2378-18 18-Bit, 1.6Msps/1Msps/500ksps/250ksps Serial,

LTC2377-18/LTC2376-18 Low Power ADC

2.5V Supply, Differential Input, 101.2dB SNR, 5V Input Range, DGC,

Pin Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

LTC2380-16/LTC2378-16 16-Bit, 2Msps/1Msps/500ksps/250ksps Serial,

LTC2377-16/LTC2376-16 Low Power ADC

2.5V Supply, Differential Input, 96.2dB SNR, 5V Input Range, DGC,

Pin Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

LTC2383-16/LTC2382-16/ 16-Bit, 1Msps/500ksps/250ksps Serial, Low

2.5V Supply, Differential Input, 92dB SNR, 2.5V Input Range, Pin

Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages

LTC2381-16

Power ADC

LTC2393-16/LTC2392-16/ 16-Bit, 1Msps/500ksps/250ksps Parallel/Serial ADC 5V Supply, Differential Input, 94dB SNR, 4.096V Input Range, Pin

LTC2391-16

Compatible Family in 7mm × 7mm LQFP-48 and QFN-48 Packages

3.3V Supply, 1-Channel, Unipolar/Bipolar, 18mW, MSOP-10 Package

2.35V to 3.6V Supply 6- and 8-Lead TSOT-23 Packages

LTC2355-14/LTC2356-14 14-Bit, 3.5Msps Serial ADC

LTC2366

12-Bit, 3Msps Serial ADC

LTC2162/LTC2161/

LTC2160

16-Bit, 65/40/25Msps Low Power ADC

1.8V Supply, Differential Input, 77dB SNR, 2V Input Range, Pipeline

P-P

Converter in 7mm × 7mm QFN-48 Package

6362fa

LT 0612 REV A • PRINTED IN USA

22 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

ꢀLINEAR TECHNOLOGY CORPORATION 2012

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC2376-18
厂家：	Linear
描述：	Precision, Low Power Rail-to-Rail Input/Output 高精度，低功耗，轨到轨输入/输出
文件：	总22页 (文件大小：358K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2376-18 [Linear]

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