LTC2383IMS-16PBF_技术文档

LTC2383-16

16-Bit, 1Msps, Low Power

SAR ADC with Serial Interface

FEATURES

DESCRIPTION

The LTC^®2383-16 is a low noise, low power, high speed

16-bit successive approximation register (SAR) ADC.

Operating from a 2.5V supply, the LTC2383-16 has a

2.5V fully differential input range. The LTC2383-16

consumes only 13mW and achieves 2LSꢀ ꢁIL max, no

missing codes at 16-bits and 92dꢀ SIR.

n

1Msps Throughput Rate

n

2ꢀSꢁ INꢀ ꢂMaꢃx

n

Guaranteed 16-ꢁit No Missing Codes

n

ꢀow Power: 13mW at 1Msps, 13μW at 1ksps

n

92dꢁ SNR ꢂtypx at f = 20kHz

IN

n

Guaranteed Operation to 125°C

n

2.5V Supply

The LTC2383-16 has a high speed SPꢁ-compatible serial

interface that supports 1.8V, 2.5V, 3.3V and 5V logic

while also featuring a daisychain mode. The fast 1Msps

throughput with no cycle latency makes the LTC2383-16

ideally suited for a wide variety of high speed applica-

tions. An internal oscillator sets the conversion time,

easing external timing considerations. The LTC2383-16

automatically powers down between conversions, lead-

ing to reduced power dissipation that scales with the

sampling rate.

n

Fully Differential ꢁnput Range 2.5V

n

External 2.5V Reference ꢁnput

n

Io Pipeline Delay, Io Cycle Latency

n

1.8V to 5V ꢁ/O Voltages

n

SPꢁ-Compatible Serial ꢁ/O with Daisy-Chain Mode

n

ꢁnternal Conversion Clock

n

16-pin MSOP and 4mm × 3mm DFI Packages

APPLICATIONS

n

Medical ꢁmaging

ꢀTC238X-16 SAR ADC Family

n

High Speed Data Acquisition

PART NUMꢁER

LTC2383-16

LTC2382-16

LTC2381-16

RESOꢀUTION

SPEED

1Msps

POWER

13mW

n

Portable or Compact ꢁnstrumentation

ꢁndustrial Process Control

Low Power ꢀattery-Operated ꢁnstrumentation

ATE

16

n

500ksps

250ksps

6.5mW

3.25mW

n

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

TYPICAL APPLICATION

32k Point FFT f_S= 1Msps, f_IN= 20kHz

0

2.5V 1.8V TO 5V

SIR = 92.2dꢀ

–20

–40

THD = –106.2dꢀ

SꢁIAD = 92dꢀ

SFDR = 110.4dꢀ

10μF

0.1μF

AIALOG ꢁIPUT

0V TO 2.5V

–60

V

OV

DD

50Ω

100Ω

3300pF

100Ω

CHAꢁI

RDL/SDꢁ

SDO

DD

+

–

ꢁI

–80

LT6350

LTC2383-16

–100

–120

–140

–160

–180

SCK

ꢀUSY

CIV

ꢁI

SAMPLE CLOCK

REF

GID

23816 TA01

2.5V

SꢁIGLE-EIDED-

TO-DꢁFFEREITꢁAL

DRꢁVER

47μF

(X5R, 0805 SꢁZE)

0

100

200

300

400

500

FREQUEICY (kHz)

238316 TA02

238316f

1

LTC2383-16

ABSOLUTE MAXIMUM RATINGS

ꢂNotes 1, 2x

Digital Output Voltage

Supply Voltage (V )...............................................2.8V

DD

(Iote 3)........................... (GID –0.3V) to (OV + 0.3V)

DD

Supply Voltage (OV )................................................6V

DD

Power Dissipation.............................................. 500mW

Operating Temperature Range

LTC2383C................................................ 0°C to 70°C

LTC2383ꢁ .............................................–40°C to 85°C

LTC2383H.......................................... –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

Reference ꢁnput (REF)..............................................2.8V

Analog ꢁnput Voltage (Iote 3)

+

–

ꢁI , ꢁI ......................... (GID –0.3V) to (REF + 0.3V)

Digital ꢁnput Voltage

(Iote 3)........................... (GID –0.3V) to (OV + 0.3V)

DD

PIN CONFIGURATION

TOP VꢁEW

CHAꢁI

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GID

OV

TOP VꢁEW

V

DD

CHAꢁI 1

16 GID

GID

SDO

V

2

15 OV

DD

+

GID 3

14 SDO

13 SCK

17

GID

ꢁI

SCK

+

–

ꢁI

4

5

–

ꢁI

RDL/SDꢁ

ꢀUSY

GID

12 RDL/SDꢁ

11 ꢀUSY

10 GID

GID

REF

GID 6

REF 7

REF 8

9

CIV

MS PACKAGE

16-LEAD (4mm s 5mm) PLASTꢁC MSOP

DE PACKAGE

16-LEAD (4mm s 3mm) PLASTꢁC DFI

T

= 150°C, θ = 110°C/W

JA

JMAX

T

= 150°C, θ = 43°C/W

JA

JMAX

EXPOSED PAD (PꢁI 17) ꢁS GID, MUST ꢀE SOLDERED TO PCꢀ

ORDER INFORMATION

ꢀEAD FREE FINISH

LTC2383CMS-16#PꢀF

LTC2383ꢁMS-16#PꢀF

LTC2383HMS-16#PꢀF

LTC2383CDE-16#PꢀF

LTC2383ꢁDE-16#PꢀF

TAPE AND REEꢀ

PART MARKING

PACKAGE DESCRIPTION

16-Lead Plastic MSOP

TEMPERATURE RANGE

0°C to 70°C

LTC2383CMS-16#TRPꢀF 238316

LTC2383ꢁMS-16#TRPꢀF 238316

LTC2383HMS-16#TRPꢀF 238316

LTC2383CDE-16#TRPꢀF 23836

–40°C to 85°C

–40°C to 125°C

0°C to 70°C

16-Lead (4mm × 3mm) Plastic DFI

LTC2383ꢁDE-16#TRPꢀF

23836

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

238316f

2

LTC2383-16

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. ꢂNote 4x

SYMꢁOꢀ

V +

PARAMETER

CONDITIONS

(Iote 5)

MIN

–0.05

TYP

MAX

UNITS

+

l

Absolute ꢁnput Range (ꢁI )

V

ꢁI

REF

–

V

ꢁI

–

Absolute ꢁnput Range (ꢁI )

(Iote 5)

V + – V – ꢁnput Differential Voltage range

V

= V + – V –

–V

+V

REF

ꢁI

REF

V

CM

Common-Mode ꢁnput Range

V

/2–

V /2

REF

V

/2+

REF

0.05

REF

0.05

l

ꢁ

Analog ꢁnput Leakage Current

Analog ꢁnput Capacitance

1

μA

ꢁI

C

Sample Mode

Hold Mode

45

5

pF

ꢁI

CMRR

ꢁnput Common Mode Rejection Ratio

70

dꢀ

CONVERTER CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. ꢂNote 4x

SYMꢁOꢀ PARAMETER

CONDITIONS

MIN

16

TYP

MAX

UNITS

ꢀits

l

Resolution

Io Missing Codes

16

ꢀits

Transition Ioise

0.6

0.8

0.4

0.25

3

LSꢀ

RMS

l

ꢁIL

ꢁntegral Linearity Error

Differential Linearity Error

ꢀipolar Zero-Scale Error

ꢀipolar Zero-Scale Error Drift

ꢀipolar Full-Scale Error

ꢀipolar Full-Scale Error Drift

(Iote 6)

(Iote 7)

–2

–1

–6

2

1

6

LSꢀ

DIL

ꢀZE

LSꢀ

mLSꢀ/°C

LSꢀ

l

FSE

–14

3

14

0.1

ppm/°C

DYNAMIC ACCURACY ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C and A_IN= –1dꢁFS. ꢂNotes 4, 8x

SYMꢁOꢀ PARAMETER

CONDITIONS

MIN

88.5

89

TYP

92

MAX

UNITS

dꢀ

l

SꢁIAD

SIR

Signal-to-(Ioise + Distortion) Ratio

f

ꢁI

f

ꢁI

f

ꢁI

f

ꢁI

= 20kHz

Signal-to-Ioise Ratio

Total Harmonic Distortion

Spurious Free Dynamic Range

–3dꢀ ꢁnput ꢀandwidth

Aperture Delay

= 20kHz

92

dꢀ

THD

= 20kHz, First 5 Harmonics

= 20kHz

–106

108

30

–99

dꢀ

SFDR

dꢀ

MHz

ns

2

Aperture Jitter

30

ps

Transient Response

Full-Scale Step

250

ns

238316f

3

LTC2383-16

REFERENCE INPUT ^Thel denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T_A= 25°C. ꢂNote 4x

SYMꢁOꢀ

PARAMETER

CONDITIONS

(Iote 5)

MIN

TYP

MAX

2.6

UNITS

V

l

V

Reference Voltage

Load Current

2.4

REF

ꢁ

(Iote 9)

910

μA

DIGITAL INPUTS AND DIGITAL OUTPUTS ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C. ꢂNote 4x

SYMꢁOꢀ PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

l

V

High Level ꢁnput Voltage

Low Level ꢁnput Voltage

Digital ꢁnput Current

0.8 • OV

ꢁH

ꢁL

DD

0.2 • OV

10

V

DD

ꢁ

V

ꢁI

= 0V to OV

DD

–10

μA

pF

ꢁI

C

V

Digital ꢁnput Capacitance

High Level Output Voltage

Low Level Output Voltage

Hi-Z Output Leakage Current

Output Source Current

Output Sink Current

5

ꢁI

l

ꢁ = –500 μA

O

OV – 0.2

DD

V

OH

OL

ꢁ = 500 μA

O

0.2

10

V

ꢁ

V

OUT

V

OUT

V

OUT

= 0V to OV

DD

–10

μA

mA

OZ

= 0V

= OV

–10

10

SOURCE

SꢁIK

DD

POWER REQUIREMENTS ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. ꢂNote 4x

SYMꢁOꢀ

PARAMETER

Supply Voltage

CONDITIONS

MIN

2.375

1.71

TYP

MAX

2.625

5.25

UNITS

l

V

2.5

V

DD

OV

DD

l

ꢁ

Supply Current

Power Down Mode

1Msps Sample Rate

Conversion Done

Conversion Done (H-Grade)

5.2

0.5

6.5

40

110

mA

μA

DD

P

Power Dissipation

Power Down Mode

1Msps Sample Rate

Conversion Done

Conversion Done (H-Grade)

13

1.25

16.25

100

275

mW

μW

D

ADC TIMING CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. ꢂNote 4x

SYMꢁOꢀ

PARAMETER

CONDITIONS

MIN

TYP

MAX

1

UNITS

Msps

ns

l

f

t

Maximum Sampling Frequency

Conversion Time

SMPL

COIV

ACQ

610

250

1

730

Acquisition Time

t

= t

–t

– t (Iote 10)

ꢀUSYLH

ns

ACQ

CYC COIV

Time ꢀetween Conversions

CIV High Time

us

CYC

20

ns

CIVH

ꢀUSYLH

CIVL

SCK

C = 20pF (Iote 11)

L

20

ns

CIV ↑ to ꢀUSY Delay

Minimum Low Time for CIV

SCK Period

(Iote 11)

200

10

4

ns

(Iotes 11, 12)

ns

SCK High Time

ns

SCKH

238316f

4

LTC2383-16

ADC TIMING CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. ꢂNote 4x

SYMꢁOꢀ

PARAMETER

CONDITIONS

MIN

4

TYP

MAX

UNITS

ns

l

t

SCK Low Time

SCKL

(Iote 11)

4

ns

SDꢁ Setup Time From SCK ↑

SDꢁ Hold Time From SCK ↑

SCK Period in Chain Mode

SSDꢁSCK

HSDꢁSCK

SCKCH

DSDO

1

ns

t

= t

+ t (Iote 11)

DSDO

13.5

ns

SCKCH

SSDꢁSCK

C = 20pF (Iote 11)

L

9.5

ns

SDO Data Valid Delay from SCK ↑

SDO Data Remains Valid Delay from SCK ↑

SDO Data Valid Delay from ꢀUSY ↓

ꢀus Enable Time After RDL ↓

ꢀus Relinquish Time After RDL ↑

SCK Setup Time from RDL/SDꢁ ↓

SCK Hold Time from RDL/SDꢁ ↓

C = 20pF (Iote 10)

L

1

ns

HSDO

C = 20pF (Iote 10)

L

5

ns

DSDOꢀUSYL

EI

(Iote 11)

(Iote 10)

16

13

ns

DꢁS

1

ns

SSCKRDL

HSCKRDL

16

ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may effect device

reliability and lifetime.

Note 7: ꢀipolar zero-scale error is the offset voltage measured from

–0.5LSꢀ when the output code flickers between 0000 0000 0000 0000

and 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of

–FS or +FS untrimmed deviation from ideal first and last code transitions

and includes the effect of offset error.

Note 2: All voltage values are with respect to ground.

Note 8: All specifications in dꢀ are referred to a full-scale 2.5V input with

a 2.5V reference voltage.

Note 3: When these pin voltages are taken below ground or above REFor

OV , they will be clamped by internal diodes. This product can handle

DD

input currents up to 100mA below ground or above REFor OV without

Note 9: f

= 1MHz, ꢁ varies proportionately with sample rate.

SMPL REF

DD

latch-up.

Note 10: Guaranteed by design, not subject to test.

Note 11: Parameter tested and guaranteed at OV = 1.71V, OV = 2.5V

Note 4: V = 2.5V, OV = 2.5V, REF = 2.5V, f = 1MHz.

SMPL

DD

Note 5: Recommended operating conditions.

and OV = 5.25V.

DD

Note 6: ꢁntegral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 12: t

100MHz for rising capture.

of 10ns maximum allows a shift clock frequency up to

SCK

0.8*OV

DD

t

WꢁDTH

0.2*OV

DD

50%

t

DELAY

238316F01

0.8*OV

0.2*OV

DD

0.2*OV

DD

Figure 1. Voltage ꢀevels for Timing Specifications

238316f

5

LTC2383-16

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, V}_DD= 2.5V, OV_DD= 2.5V, REF = 2.5V,

f_SMPꢀ= 1Msps, unless otherwise noted.

Integral Nonlinearity

vs Output Code

Differential Nonlinearity

vs Output Code

DC Histogram

2.0

1.5

1.0

0.5

0.0

1600000

1400000

1200000

1000000

1.0

0.5

0.0

800000

600000

400000

200000

0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

0

16384

32768

49152

65536

0

16384

32768

49152

65536

32766

32767

32768

CODE

32769

32770

OUTPUT CODE

238316 G01

238316 G02

238316 G03

32k Point FFT f_S= 1Msps,

f_IN= 20kHz

THD, Harmonics

SNR, SINAD vs Input Frequency

vs Input Frequency

0

–20

93

92

91

90

89

88

87

86

85

–80

–85

SIR = 92.2dꢀ

THD = –106.2dꢀ

SꢁIAD = 92dꢀ

–90

–40

SFDR = 110.4dꢀ

SIR

–95

–60

–100

–105

–110

–115

SꢁIAD

THD

–80

–100

–120

–140

–160

–180

2ID

–120 3RD

–125

–130

0

100

200

300

400

500

0

25 50 75 100 125 150 175 200

0

25 50 75 100 125 150 175 200

FREQUEICY (kHz)

238316 G05

238316 G06

238316 G04

SNR, SINAD vs Input level,

f_IN= 20kHz

SNR, SINAD vs Temperature

THD, Harmonics vs Temperature

94.00

93.50

93.00

92.50

92.00

91.50

91.00

93.0

92.5

92.0

91.5

91.0

–100.00

–105.00

–110.00

–115.00

–120.00

SIR

THD

2ID

SꢁIAD

SIR

SꢁIAD

3RD

–55 –35 –15

5

25 45 65 85 105 125

–40

–30

–20

–10

0

–55 –35 –15

5

25 45 65 85 105 125

TEMPERATURE (ºC)

ꢁIPUT LEVEL (dꢀ)

TEMPERATURE (ºC)

238316 G08

238316 G07

3653 G03

238316f

6

LTC2383-16

TYPICAL PERFORMANCE CHARACTERISTICS ^T_A^{= 25°C, V}_DD= 2.5V, OV_DD= 2.5V, REF = 2.5V,

f_SMPꢀ= 1Msps, unless otherwise noted.

INꢀ/DNꢀ vs Temperature

Full-Scale Error vs Temperature

Offset Error vs Temperature

0.3

0.2

0.1

0

1

0.5

0

2.5

2.0

1.5

1.0

0.5

0

MAX ꢁIL

MAX DIL

–FS

+FS

MꢁI DIL

MꢁI ꢁIL

–0.5

–0.1

–1

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

TEMPERATURE (°C)

238316 G12

238316 G10

238316 G11

Supply Current vs Temperature

Shutdown Current vs Temperature

Supply Current vs Sampling Rate

6

5

4

3

2

1

0

30

25

20

15

10

5

6

5

4

3

2

1

0

ꢁ

+ ꢁ

VDD OVDD REF

ꢁ

VDD

ꢁ

REF

ꢁ

OVDD

0

200

400

600

800

1000

–55 –35 –15

5

25 45 65 85 105 125

–55 –35 –15

5

25 45 65 85 105 125

TEMPERATURE (°C)

SAMPLꢁIG RATE (kHz)

238316 G13

238316 G14

238316 G15

238316f

7

LTC2383-16

PIN FUNCTIONS

CHAIN ꢂPin 1x: Chain Mode Selector Pin. When low, the

LTC2383-16 operates in Iormal Mode and the RDL/SDꢁ

input pin functions to enable or disable SDO. When high,

the LTC2383-16 operates in Chain Mode and the RDL/SDꢁ

pin functions as SDꢁ, the daisychain serial data input.

RDꢀ/SDIꢂPin12x:WhenCHAꢁIislow,thepartisinIormal

Mode and the pin is treated as a bus enabling input. When

CHAꢁI is high, the part is in chain mode and the pin is

treated as a serial data input pin where data from another

ADC in the daisychain is input.

V

ꢂPin 2x: 2.5V Digital Power Supply. The range of

SCKꢂPin13x:SerialDataClockꢁnput.WhenSDOisenabled,

theconversionresultordaisychaindatafromanotherADC

is shifted out on the rising edges of this clock MSꢀ first.

DD

V

is 2.375V to 2.625V. ꢀypass V to GID with a 10μF

DD

ceramic capacitor.

GND ꢂPins 3, 6, 10 and 16x: Ground.

SDOꢂPin14x:SerialDataOutput. Theconversionresultor

daisychain data is output on this pin on each rising edge

of SCK MSꢀ first. The output data is in 2’s complement

format.

+

–

IN , IN ꢂPins 4, 5x: Positive and Iegative Differential

Analog ꢁnputs.

REF ꢂPins 7, 8x: Reference ꢁnput. The range of REF is 2.4V

to 2.6V. This pin is referred to the GID pin and should be

decoupledcloselytothepinwitha47μFceramiccapacitor

(X5R, 0805 size).

OV ꢂPin 15x: ꢁ/O ꢁnterface Digital Power. The range of

DD

OV is 1.71V to 5.25V. This supply is nominally set to

DD

the same supply as the host interface (1.8V, 2.5V, 3.3V,

or 5V). ꢀypass OV to GID with a 0.1μF capacitor.

DD

CNV ꢂPin 9x: Convert ꢁnput. A rising edge on this input

initiates a new conversion. When the conversion is done,

the part powers down as long as CIV is held high. When

CIV is returned low, the part powers up in preparation

for the next conversion.

GND ꢂEꢃposed Pad Pin 17 – DFN Package Onlyx: Ground.

Exposed pad must be soldered directly to the ground

plane.

ꢁUSY ꢂPin 11x: ꢀUSY indicator. Goes high at the start of

a new conversion and returns low when the conversion

has finished.

FUNCTIONAL BLOCK DIAGRAM

V

= 2.5V

DD

OV = 1.8V to 5V

DD

REF = 2.5V

LTC2383-16

+

CHAꢁI

SDO

RDL/SDꢁ

SCK

+

–

ꢁI

SPꢁ

PORT

16-ꢀꢁT SAMPLꢁIG ADC

–

ꢁI

CIV

COITROL LOGꢁC

ꢀUSY

GID

238316 ꢀD01

238316f

8

LTC2383-16

TIMING DIAGRAM

Conversion Timing Using the Serial Interface

CHAꢁI, RDL/SDꢁ = 0

CIV

POWER-UP

POWER-DOWI

ACQUꢁRE

COIVERT

ꢀUSY

SCK

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SDO

238316 TD02

238316f

9

LTC2383-16

APPLICATIONS INFORMATION

OVERVIEW

011...111

011...110

BIPOLAR

ZERO

TheLTC2383-16isalownoise,lowpower,highspeed16-bit

successive approximation register (SAR) ADC. Operating

from a single 2.5V supply, the LTC2383-16 supports a

large 2.5V fully differential input range, making it ideal

for high performance applications which require a wide

dynamicrange.TheLTC2383-16achieves 2LSꢀꢁILmax,

no missing codes at 16-bits and 92dꢀ SIR.

000...001

000...000

111...111

111...110

100...001

100...000

FSR = +FS – –FS

1LSB = FSR/65536

Fast 1Msps throughput with no cycle latency makes the

LTC2383-16 ideally suited for a wide variety of high speed

applications.Aninternaloscillatorsetstheconversiontime,

easing external timing considerations. The LTC2383-16

dissipatesonly13mWat1Msps,whileanautopower-down

feature is provided to further reduce power dissipation

during inactive periods.

–1 0V

LSB

INPUT VOLTAGE (V)

1

LSB

–FSR/2

FSR/2 – 1LSB

238316 F02

Figure 2. ꢀTC2383-16 Transfer Function

circuit shown in Figure 3. The diodes at the input provide

ESD protection. ꢁn the acquisition phase, each input sees

approximately45pF(C )fromthesamplingCDACinseries

with 40ꢂ (R ) from the on-resistance of the sampling

switch. Any unwanted signal that is common to both

inputs will be reduced by the common mode rejection of

the ADC. The inputs draw a current spike while charging

the C capacitors during acquisition. During conversion,

the analog inputs draw only a small leakage current.

ꢁI

CONVERTER OPERATION

OI

The LTC2383-16 operates in two phases. During the

acquisition phase, the charge redistribution capacitor D/A

+

–

converter (CDAC) is connected to the ꢁI and ꢁI pins

to sample the differential analog input voltage. A rising

edge on the CIV pin initiates a conversion. During the

conversionphase,the16-bitCDACissequencedthrougha

successiveapproximationalgorithm,effectivelycomparing

the sampled input with binary-weighted fractions of the

referencevoltage(e.g.V /2,V /4…V /65536)using

ꢁI

REF

C

ꢁI

R

OI

+

REF

ꢁI

the differential comparator. At the end of conversion, the

CDAC output approximates the sampled analog input. The

ADC control logic then prepares the 16-bit digital output

code for serial transfer.

ꢀꢁAS

VOLTAGE

REF

OI

–

TRANSFER FUNCTION

238316 F03

The LTC2383-16 digitizes the full-scale voltage of 2 × REF

Figure 3. The Equivalent Circuit for the

16

into 2 levels, resulting in an LSꢀ size of 76μV with

Differential Analog Input of the ꢀTC2383-16

REF=2.5V.TheidealtransferfunctionisshowninFigure2.

The output data is in 2’s complement format.

INPUT DRIVE CIRCUITS

A low impedance source can directly drive the high

impedance inputs of the LTC2383-16 without gain error.

A high impedance source should be buffered to minimize

settling time during acquisition and to optimize the

distortion performance of the ADC. Minimizing settling

238316f

ANAꢀOG INPUT

The analog inputs of the LTC2383-16 are fully differential

in order to maximize the signal swing that can be digitized.

The analog inputs can be modeled by the equivalent

10

LTC2383-16

APPLICATIONS INFORMATION

time is important even for DC inputs, because the ADC

inputs draw a current spike when entering acquisition.

Single-Ended-to-Differential Conversion

Forsingle-endedinputsignals,asingle-endedtodifferential

conversion circuit must be used to produce a differential

signal at the inputs of the LTC2383-16. The LT6350 ADC

driver is recommended for performing single-ended-to-

differential conversions.The LT6350 is flexible and may

be configured to convert single-ended signals of various

amplitudes to the 2.5V differential input range of the

LTC2383-16. The LT6350 is also available in H-grade to

complement the extended temperature operation of the

LTC2383-16 up to 125°C.

For best performance, a buffer amplifier should be used to

drive the analog inputs of the LTC2383-16. The amplifier

provides low output impedance, which produces fast

settling of the analog signal during the acquisition phase.

ꢁt also provides isolation between the signal source and

the current spike the ADC inputs draw.

Input Filtering

The noise and distortion of the buffer amplifier and signal

sourcemustbeconsideredsincetheyaddtotheADCnoise

and distortion. Ioisy input signals should be filtered prior

to the buffer amplifier input with an appropriate filter to

minimizenoise.Thesimple1-poleRClowpassfilter(LPF1)

shown in Figure 4 is sufficient for many applications.

Figure 5 shows the LT6350 being used to convert a 0V

to 2.5V single-ended input signal. ꢁn this case, the first

amplifierisconfiguredasaunitygainbufferandthesingle-

ended input signal directly drives the high-impedance

input of the amplifier. As shown in the FFT of Figure 5a,

the LT6350 drives the LTC2383-16 to full datasheet

performance without degrading the SIR or THD .

AnotherfilternetworkconsistingofLPF2andthe100Ωseries

input resistors should be used between the buffer and ADC

inputs to both minimize the noise contribution of the buffer

and to help minimize disturbances reflected into the buffer

from sampling transients. Long RC time constants at the

analoginputswillslowdownthesettlingoftheanaloginputs.

Therefore, LPF2 requires a wider bandwidth than LPF1. A

bufferamplifierwithalownoisedensitymustbeselectedto

minimizedegradationoftheSIR. Withthe482kHzlowpass

filter shown in Figure 4, the LT6350 provides the full data

sheet performance of the LTC2383-16.

LT6350

OUT1

0V to

2.5V

4

R

ꢁIT

8

1

+

–

ꢁIT

0V to 2.5V

–

OUT2

2.5V to

0V

5

2

+

–

V

CM

= V /2

REF

238316 F05

Figure 5. ꢀT6350 Converting a 0V-2.5V Single-Ended Signal

to a 2.5V Differential Input Signal

Highqualitycapacitorsandresistorsshouldbeusedinthe

RCfilterssincethesecomponentscanadddistortion.IPO

and silver mica type dielectric capacitors have excellent

linearity. Carbon surface mount resistors can generate

distortion from self heating and from damage that may

occurduringsoldering.Metalfilmsurfacemountresistors

are much less susceptible to both problems.

0

SIR = 92.2dꢀ

–20

–40

THD = –106.2dꢀ

SꢁIAD = 92dꢀ

SFDR = 110.4dꢀ

–60

–80

LPF2

50Ω

–100

–120

–140

–160

–180

SꢁIGLE-EIDED-

ꢁIPUT SꢁGIAL

100Ω

LPF1

+

–

ꢁI

500Ω

3300pF

LTC2383-16

LT6350

6600pF

50Ω

ꢀW = 482kHz

100Ω

238316 F04

SꢁIGLE-EIDED-

TO-DꢁFFEREITꢁAL

DRꢁVER

0

100

200

300

400

500

ꢀW = 48kHz

FREQUEICY (kHz)

238316 F05a

Figure 4. Input Signal Chain

Figure 5a. 32k Point FFT Plot for Circuit Shown in Figure 5

238316f

11

LTC2383-16

APPLICATIONS INFORMATION

The LT6350 can also be used to buffer and convert single-

endedsignalslargerthantheinputrangeoftheLTC2383-16

in order to maximize the signal swing that can be digitized.

Figure6showstheLT6350convertinga0V-5Vsingle-ended

input signal to the 2.5V differential input range of the

LTC2383-16. ꢁn this case, the first amplifier in the LT6350

is configured as an inverting amplifier stage, which acts to

attenuate the input signal down to the 0V-2.5V input range

of the LTC2383-16. ꢁn the inverting amplifier configuration,

the single-ended input signal source no longer directly

drives a high impedance input of the first amplifier. The

resulting SIR and THD for several values of R , R1, R2

ꢁI

and R3 in this configuration. Figure 6a shows the resulting

FFT when using the LT6350 as shown in Figure 6.

The LT6350 can also be used to buffer and convert large,

truebipolarsignalswhichswingbelowgroundtothe 2.5V

differential input range of the LTC2383-16. Figure 7 shows

theLT6350beingusedtoconverta 10Vtruebipolarsignal

for use by the LTC2383-16. The input impedance is again

set by resistor R . Table 2 shows the resulting SIR and

ꢁI

THDforseveralvaluesofR .Figure7ashowstheresulting

ꢁI

FFT when using the LT6350 as shown in Figure 7.

input impedance is instead set by resistor R . R must

ꢁI ꢁI

Table 1. SNR, THD vs R_INfor 0-5V Single-Ended Input Signal.

be chosen carefully based on the source impedance of the

R

R1

ꢂΩx

R2

ꢂΩx

R3

ꢂΩx

R4

ꢂΩx

SNR

ꢂdꢁx

THD

ꢂdꢁx

signal source. Higher values of R tend to degrade both

IN

ꢁI

ꢂΩx

the noise and distortion of the LT6350 and LTC2383-16 as a

2k

1k

5k

1k

5k

2k

665

3.3k

16k

92

91

–101

–100

–94

system. R1, R2andR3mustbeselectedinrelationtoR to

ꢁI

10k

100k

10k

achieve the desired attenuation and to maintain a balanced

50k

100k

input impedance in the first amplifier. Table 1 shows the

V

REF

CM

R2 = 1.24k

200pF

R2 = 1k

150pF

LT6350

OUT1

2.5V to

0V

4

5

OUT1

OUT2

2.5V to

0V

4

5

R

V

8

+

–

ꢁIT

R

8

+

–

ꢁIT

10μF

R4 = 1.1k

R3 = 10k

10

μF R4 = 665Ω

R3 = 2k

–

+

–

+

0V to

2.5V

OUT2

0V to

2.5V

1

2

R

= 2k

R

= 10k

R1 = 1k

R1 = 1.24k

ꢁI

+

–

+

–

V

= V /2

REF

= V /2

REF

CM

0V to 5V

10V

75pF

220pF

238316 F06

238316 F07

Figure 6. ꢀT6350 Converting a 0V-5V Single-Ended Signal to

a 2.5V Differential Input Signal

Figure 7. ꢀT6350 Converting a 10V Single-Ended Signal to

a 2.5V Differential Input Signal

0

SIR = 92dꢀ

–20

–40

THD = –101dꢀ

SꢁIAD = 91.4dꢀ

SFDR = 103dꢀ

–20

–40

THD = –97dꢀ

SꢁIAD = 91.2dꢀ

SFDR = 99.7dꢀ

–60

–80

–100

–120

–140

–160

–180

–100

–120

–140

–160

–180

0

100

200

300

400

500

0

100

200

300

400

500

FREQUEICY (kHz)

238316 F06a

238316 F07a

Figure 6a. 32k Point FFT Plot for Circuit Shown in Figure 6

Figure 7a. 32k Point FFT Plot for Circuit Shown in Figure 7

238316f

12

LTC2383-16

APPLICATIONS INFORMATION

Table 2. SNR, THD vs R_INfor 10V Single-Ended Input Signal.

When idling, the REF pin on the LTC2383-16 draws only a

smallleakagecurrent(<1μA).ꢁnapplicationswhereaburst

of samples is taken after idling for long periods as shown

R

R1

ꢂΩx

R2

ꢂΩx

R3

ꢂΩx

R4

ꢂΩx

SNR

ꢂdꢁx

THD

ꢂdꢁx

IN

ꢂΩx

10k

1.24k

6.19k

12.4k

1.24k

6.19k

12.4k

10k

50k

1.1k

5.49k

11k

92

91

–96

in Figure 8, ꢁ quickly goes from approximately 0μA to

REF

a maximum of 910μA at 1Msps. This step in DC current

draw triggers a transient response in the reference that

must be considered since any deviation in the reference

outputvoltagewillaffecttheaccuracyoftheoutputcode.ꢁn

applications where the transient response of the reference

is important, the fast settling LTC6655-2.5 reference

is recommended. ꢁnserting a 1Ω resistor between the

47μF bypass capacitor and reference output as shown in

Figure 9 helps to improve the transient settling time and

minimize the reference voltage deviation.

50k

100k

ADC REFERENCE

TheLTC2383-16requiresanexternalreferencetodefineits

input range. A low noise, low temperature drift reference

is critical to achieving the full datasheet performance

of the ADC. Linear Technology offers a portfolio of high

performance references designed to meet the needs of

manyapplications. Withitssmallsize, lowpowerandhigh

accuracy, the LTC6652-2.5 is particularly well suited for

use with the LTC2383-16. The LTC6652-2.5 offers 0.05%

(max) initial accuracy and 5ppm/°C (max) temperature

coefficientforhighprecisionapplications.TheLTC6652-2.5

is fully specified over the H-grade temperature range and

complements the extended temperature operation of the

LTC2383-16 up to 125°C. We recommend bypassing the

LTC6652-2.5 with a 47μF ceramic capacitor (X5R, 0805

size) close to the REF pin. All performance curves shown

in this datasheet were obtained using the LTC6652-2.5.

V

OUT_S

LTC6655-2.5

V

OUT_F

1Ω

47μF

LTC2383-16

238316 F09

Figure 9. ꢀTC6655-2.5 Driving REF of ꢀTC2381-16

The REF pin of the LTC2383-16 draws charge (Q

from the 47μF bypass capacitor during each conversion

cycle. The reference replenishes this charge with a DC

)

COIV

DYNAMIC PERFORMANCE

Fast Fourier Transform (FFT) techniques are used to test

the ADC’s frequency response, distortion and noise at the

rated throughput. ꢀy applying a low distortion sine wave

andanalyzingthedigitaloutputusinganFFTalgorithm,the

ADC’s spectral content can be examined for frequencies

outside the fundamental. The LTC2383-16 provides

guaranteed tested limits for both AC distortion and noise

measurements.

current, ꢁ

= Q

/t . The DC current draw of the

REF

COIV CYC

REF pin, ꢁ , depends on the sampling rate and output

REF

code. ꢁf the LTC2383-16 is used to continuously sample

a signal at a constant rate, the LTC6652-2.5 will keep the

deviation of the reference voltage over the entire code

span to less than 0.5LSꢀs.

CIV

ꢁDLE

PERꢁOD

ꢁDLE

PERꢁOD

238316 F08

Figure 8. CNV Waveform Showing ꢁurst Sampling

238316f

13

LTC2383-16

APPLICATIONS INFORMATION

Signal-to-Noise and Distortion Ratio ꢂSINADx

where V1 is the RMS amplitude of the fundamental fre-

quency and V2 through V are the amplitudes of the

I

The signal-to-noise and distortion ratio (SꢁIAD) is the

ratiobetweentheRMSamplitudeofthefundamentalinput

frequency and the RMS amplitude of all other frequency

components at the A/D output. The output is band-limited

tofrequenciesfromaboveDCandbelowhalfthesampling

frequency. Figure 10 shows that the LTC2383-16 achieves

a typical SꢁIAD of 92dꢀ at a 1MHz sampling rate with a

20kHz input.

second through Ith harmonics.

POWER CONSIDERATIONS

The LTC2383-16 provides two power supply pins: the

2.5V power supply (V ), and the digital input/output

DD

interface power supply (OV ). The flexible OV supply

DD

allows the LTC2383-16 to communicate with any digital

logic operating between 1.8V and 5V, including 2.5V and

3.3V systems.

0

SIR = 92.2dꢀ

–20

–40

THD = –106.2dꢀ

SꢁIAD = 92dꢀ

SFDR = 110.4dꢀ

Power Supply Sequencing

–60

The LTC2383-16 does not have any specific power supply

sequencing requirements. Care should be taken to adhere

to the maximum voltage relationships described in the

Absolute Maximum Ratings section. The LTC2383-16

has a power-on-reset (POR) circuit that will reset the

LTC2383-16 at initial power-up or whenever the power

supply voltage drops below 1V. Once the supply voltage

reenters the nominal supply voltage range, the POR will

reinitialize the ADC. Io conversions should be initiated

until 20μs after a POR event to ensure the reinitialization

period has ended. Any conversions initiated before this

time will produce invalid results.

–80

–100

–120

–140

–160

–180

0

100

200

300

400

500

FREQUEICY (kHz)

238316 F10

Figure 10. 32k Point FFT of the ꢀTC2383-16

Signal-to-Noise Ratio ꢂSNRx

The signal-to-noise ratio (SIR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the first five harmonics and DC. Figure 10 shows

that the LTC2383-16 achieves a typical SIR of 92dꢀ at a

1MHz sampling rate with a 20kHz input.

TIMING AND CONTROꢀ

CNV Timing

The LTC2383-16 conversion is controlled by CIV. A rising

edgeonCIVwillstartaconversion.Onceaconversionhas

been initiated, it cannot be restarted until the conversion

is complete. For optimum performance, CIV should be

driven by a clean low jitter signal. Converter status is

indicated by the ꢀUSY output which remains high while

the conversion is in progress. To ensure that no errors

occur in the digitized results, any additional transitions

on CIV should occur within 40ns from the start of the

conversion or after the conversion has been completed.

Once the conversion has completed, the LTC2383-16

begins acquiring the input signal.

Total Harmonic Distortion ꢂTHDx

TotalHarmonicDistortion(THD)istheratiooftheRMSsum

ofallharmonicsoftheinputsignaltothefundamentalitself.

The out-of-band harmonics alias into the frequency band

between DC and half the sampling frequency (f

THD is expressed as:

/2).

SMPL

2

V2²+ V3²+ V4²+…+ V_I

THD=20log

V1

238316f

14

LTC2383-16

APPLICATIONS INFORMATION

Internal Conversion Clock

DIGITAꢀ INTERFACE

The LTC2383-16 has an internal clock that is trimmed to

achieveamaximumconversiontimeof730ns.Withamin-

imum acquisition time of 250ns, throughput performance

of 1Msps is guaranteed without any external

adjustments.

The LTC2383-16 has a serial digital interface. The flexible

OV supply allows the LTC2383-16 to communicate with

DD

any digital logic operating between 1.8V and 5V, including

2.5V and 3.3V systems.

The serial output data is clocked out on the SDO pin

when an external clock is applied to the SCK pin if SDO

is enabled. Clocking out the data after the conversion will

yield the best performance. With a shift clock frequency

of at least 60MHz, a 1Msps throughput is still achieved.

The serial output data changes state on the rising edge

of SCK and can be captured on the falling edge or next

rising edge of SCK. D15 remains valid till the first rising

edge of SCK.

Auto Power-Down

The LTC2383-16 automatically powers down after a

conversion has been completed as long as CIV remains

high.Duringpowerdown,thedatafromthelastconversion

can be clocked out. To minimize power dissipation during

power down, disable SDO and turn off SCK. To power up

the part, bring CIV low at least 200ns (t

) before the

COIVL

initiation of the next conversion. The auto power-down

feature will reduce the power dissipation of the LTC2383-

16 as the sampling frequency is reduced. Since the time

required to power up the part does not change at lower

sample rates, the LTC2383-16 can remain powered-down

The serial interface on the LTC2383-16 is simple and

straightforwardtouse.Thefollowingsectionsdescribethe

operation of the LTC2383-16. Several modes are provided

depending on whether a single or multiple ADCs share the

SPꢁ bus or are daisy-chained.

for a larger fraction of the conversion cycle (t ), thereby

CYC

reducing the average power dissipation which scales

linearly with sampling rate as shown in Figure 11.

6

5

4

3

2

1

0

200

400

600

800

1000

SAMPLꢁIG RATE (kHz)

238316 F11

Figure 11. Power Supply Current of the ꢀTC2383-16

Versus Sampling Rate

238316f

15

LTC2383-16

TIMING DIAGRAM

Normal Mode, Single Device

Figure 12 shows a single LTC2383-16 operated in Iormal

Mode with CHAꢁI and RDL/SDꢁ tied to ground. With RDL/

SDꢁ grounded, SDO is enabled and the MSꢀ(D15) of the

newconversiondataisavailableatthefallingedgeofꢀUSY.

This is the simplest way to operate the LTC2383-16.

When CHAꢁI = 0, the LTC2383-16 operates in Iormal

mode. ꢁn Iormal mode, RDL/SDꢁ enables or disables the

serial data output pin SDO. ꢁf RDL/SDꢁ is high, SDO is in

high-impedance. ꢁf RDL/SDꢁ is low, SDO is driven.

COIVERT

DꢁGꢁTAL HOST

ꢁRQ

CIV

CHAꢁI

ꢀUSY

LTC2383-16

SCK

RDL/SDꢁ

SDO

DATA ꢁI

CLK

238316 F12a

ACQUꢁRE

COIVERT

ACQUꢁRE

COIVERT

POWER-DOWI

POWER-UP

CHAꢁI = 0

t

CYC

t

CIVH

t

CIV

CIVL

t

= t

– t

ACQ CYC COIV ꢀUSYLH

t

COIV

ACQ

ꢀUSY

SCK

t

SCK

t

ꢀUSYLH

t

SCKH

1

2

3

14

15

16

t

SCKL

HSDO

t

DSDO

DSDOꢀUSYL

D15

D14

D13

D1

D0

SDO

238316 F12

(RDL/SDꢁ = 0)

Figure 12. Using a Single ꢀTC2383-16 in Normal Mode

238316f

16

LTC2383-16

TIMING DIAGRAM

Normal Mode, Multiple Devices

timeinordertoavoidbusconflicts. AsshowninFigure13,

the RDL/SDꢁ inputs idle high and are individually brought

low to read data out of each device between conversions.

When RDL/SDꢁ is brought low, the MSꢀ of the selected

device is output onto SDO. To ensure the MSꢀ is properly

output and captured, SCK must be held low at least 1ns

before and 16ns after bringing RDL/SDꢁ low.

Figure 13 shows multiple LTC2383-16 devices operating

in Iormal Mode(CHAꢁI = 0) sharing CIV, SCK and SDO.

ꢀy sharing CIV, SCK and SDO, the number of required

signals to operate multiple ADCs in parallel is reduced.

Since SDO is shared, the RDL/SDꢁ input of each ADC must

be used to allow only one LTC2383-16 to drive SDO at a

RDL2

RDL1

COIVERT

CIV

CHAꢁI

ꢀUSY

SDO

ꢁRQ

CHAꢁI

LTC2383-16

ꢀ

LTC2383-16

A

DꢁGꢁTAL HOST

SDO

RDL/SDꢁ

SCK

DATA ꢁI

CLK

238316 F13

ACQUꢁRE

COIVERT

ACQUꢁRE

COIVERT

POWER-DOWI

POWER-UP

CHAꢁI = 0

CIV

t

CIVL

t

COIV

ꢀUSY

t

ꢀUSYLH

RDL/SDꢁ

A

ꢀ

RDL/SDꢁ

t

SCK

t

SCKH

HSCKRDL

SCK

SDO

1

2

3

14

15

16

17

18

19

30

31

32

t

SSCKRDL

Hi-Z

t

SCKL

HSDO

t

DꢁS

DSDO

t

EI

Hi-Z

D15

D14

D13

D1

D0

D15

D14

D13

D1

ꢀ

D0

ꢀ

A

ꢀ

238316 F13

Figure 13. Normal Mode With Multiple Devices Sharing CNV, SCK and SDO

238316f

17

LTC2383-16

TIMING DIAGRAM

When CHAꢁI = OV , the LTC2383-16 operates in Chain

This is useful for applications where hardware constraints

maylimitthenumberoflinesneededtointerfacetoalarge

number of converters. Figure 14 shows an example with

two daisy chained devices. The MSꢀ of converter A will

appear at SDO of converter ꢀ after 16 SCK cycles. The

MSꢀ of converter A is clocked in at the SDꢁ/RDL pin of

converter ꢀ on the rising edge of the first SCK.

DD

Mode. ꢁnChainMode,SDOisalwaysenabledandRDL/SDꢁ

serves as the serial data input pin (SDꢁ) where daisychain

data output from another ADC can be input.

COIVERT

OV

DD

CIV

CHAꢁI

DꢁGꢁTAL HOST

LTC2383-16

RDL/SDꢁ

SDO

RDL/SDꢁ

ꢀUSY

SDO

ꢁRQ

A

ꢀ

DATA ꢁI

SCK

CLK

238316 F14a

COIVERT

POWER-DOWI

POWER-UP

COIVERT

ACQUꢁRE

CHAꢁI = OV

ACQUꢁRE

DD

RDL/SDꢁ = 0

A

t

CYC

t

CIVL

CIV

ꢀUSY

t

COIV

t

ꢀUSYLH

SCK

t

SCKCH

t

SCKH

1

2

3

14

15

16

17

18

30

31

32

t

SCKL

t

HSDO

SSDꢁSCK

t

DSDO

HSDꢁSCK

SDO = RDL/SDꢁ

A

ꢀ

D15

D14

D13

D1

D0

A

ꢀ

A

ꢀ

A

t

DSDOꢀUSYL

D15

D13

D1

D15

D14

D1

A

D0

A

SDO

ꢀ

A

ꢀ

238316 F14

Figure 14. Chain Mode Timing Diagram

238316f

18

LTC2383-16

BOARD LAYOUT

To obtain the best performance from the LTC2383-16

a printed circuit board is recommended. Layout for the

printed circuit board (PCꢀ) should ensure the digital and

analog signal lines are separated as much as possible.

ꢁn particular, care should be taken not to run any digital

clocks or signals alongside analog signals or underneath

the ADC.

Recommended ꢀayout

ThefollowingisanexampleofarecommendedPCꢀlayout.

A single solid ground plane is used. ꢀypass capacitors to

the supplies are placed as close as possible to the supply

pins. Low impedance common returns for these bypass

capacitors are essential to the low noise operation of the

ADC. The analog input traces are screened by ground.

For more details and information refer to DC1571A, the

evaluation kit for the LTC2383-16.

Partial Top Silkscreen

238316 ꢀL01

238316f

19

LTC2383-16

BOARD LAYOUT

Partial ꢀayer 1 Component Side

238316 ꢀL02

Partial ꢀayer 2 Ground Plane

238316 ꢀL03

238316f

20

LTC2383-16

BOARD LAYOUT

Partial ꢀayer 3 PWR Plane

238316 ꢀL04

Partial ꢀayer 4 ꢁottom ꢀayer

238316 ꢀL05

238316f

21

LTC2383-16

BOARD LAYOUT

Partial Schematic of Demoboard

R E F 1

8

R E F

1

G I D

7

D D

G I D 1 6

O V

1 5

G I D

1 0

D D

V

2

G I D

6

3

2

1

3

2

1

238316f

22

LTC2383-16

PACKAGE DESCRIPTION

DE Package

16-ꢀead Plastic DFN ꢂ4mm × 3mmx

(Reference LTC DWG # 05-08-1732 Rev Ø)

R = 0.115

0.40 0.10

4.00 0.10

(2 SꢁDES)

TYP

16

9

0.70 0.05

R = 0.05

TYP

3.30 0.05

1.70 0.05

3.30 0.10

3.60 0.05

2.20 0.05

3.00 0.10

(2 SꢁDES)

PACKAGE

OUTLꢁIE

1.70 0.10

PꢁI 1 IOTCH

R = 0.20 OR

0.35 s 45°

PꢁI 1

TOP MARK

(SEE IOTE 6)

CHAMFER

(DE16) DFI 0806 REV Ø

8

1

0.23 0.05

0.45 ꢀSC

0.75 0.05

0.200 REF

0.25 0.05

0.45 ꢀSC

3.15 REF

ꢀOTTOM VꢁEW—EXPOSED PAD

3.15 REF

0.00 – 0.05

RECOMMEIDED SOLDER PAD PꢁTCH AID DꢁMEISꢁOIS

APPLY SOLDER MASK TO AREAS THAT ARE IOT SOLDERED

IOTE:

1. DRAWꢁIG PROPOSED TO ꢀE MADE VARꢁATꢁOI OF VERSꢁOI (WGED-3) ꢁI JEDEC

PACKAGE OUTLꢁIE MO-229

2. DRAWꢁIG IOT TO SCALE

3. ALL DꢁMEISꢁOIS ARE ꢁI MꢁLLꢁMETERS

4. DꢁMEISꢁOIS OF EXPOSED PAD OI ꢀOTTOM OF PACKAGE DO IOT ꢁICLUDE

MOLD FLASH. MOLD FLASH, ꢁF PRESEIT, SHALL IOT EXCEED 0.15mm OI AIY SꢁDE

5. EXPOSED PAD SHALL ꢀE SOLDER PLATED

6. SHADED AREA ꢁS OILY A REFEREICE FOR PꢁI 1 LOCATꢁOI OI THE

TOP AID ꢀOTTOM OF PACKAGE

MS Package

16-ꢀead Plastic MSOP

(Reference LTC DWG # 05-08-1669 Rev Ø)

4.039 p 0.102

(.159 p .004)

(IOTE 3)

0.889 p 0.127

(.035 p .005)

0.280 p 0.076

(.011 p .003)

REF

16151413121110

9

3.00 p 0.102

(.118 p .004)

(IOTE 4)

DETAꢁL “A”

0o – 6o TYP

5.23

4.90 p 0.152

(.193 p .006)

3.20 – 3.45

(.206)

0.254

(.010)

(.126 – .136)

MꢁI

GAUGE PLAIE

0.53 p 0.152

(.021 p .006)

1 2 3 4 5 6 7 8

0.50

(.0197)

ꢀSC

0.305 p 0.038

(.0120 p .0015)

TYP

0.86

(.034)

REF

1.10

(.043)

MAX

DETAꢁL “A”

0.18

(.007)

RECOMMEIDED SOLDER PAD LAYOUT

SEATꢁIG

PLAIE

IOTE:

0.17 – 0.27

(.007 – .011)

TYP

1. DꢁMEISꢁOIS ꢁI MꢁLLꢁMETER/(ꢁICH)

2. DRAWꢁIG IOT TO SCALE

0.1016 p 0.0508

(.004 p .002)

MSOP (MS16) 1107 REV Ø

0.50

(.0197)

ꢀSC

3. DꢁMEISꢁOI DOES IOT ꢁICLUDE MOLD FLASH, PROTRUSꢁOIS OR GATE ꢀURRS.

MOLD FLASH, PROTRUSꢁOIS OR GATE ꢀURRS SHALL IOT EXCEED 0.152mm (.006") PER SꢁDE

4. DꢁMEISꢁOI DOES IOT ꢁICLUDE ꢁITERLEAD FLASH OR PROTRUSꢁOIS.

ꢁITERLEAD FLASH OR PROTRUSꢁOIS SHALL IOT EXCEED 0.152mm (.006") PER SꢁDE

5. LEAD COPLAIARꢁTY (ꢀOTTOM OF LEADS AFTER FORMꢁIG) SHALL ꢀE 0.102mm (.004") MAX

238316f

ꢁnformation furnished by Linear Technology Corporation is believed to be accurate and reliable.

However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresentation

that the interconnection of its circuits as described herein will not infringe on existing patent rights.

23

LTC2383-16

TYPICAL APPLICATION

ADC Driver: Single-Ended Input to Differential Output with Filter

0

–20

SIR = 92.2dꢀ

THD = –106.2dꢀ

SꢁIAD = 92dꢀ

SFDR = 110.4dꢀ

LPF2

50Ω

SꢁIGLE-EIDED

ꢁIPUT SꢁGIAL

–40

LT6350

LPF1

500Ω

100Ω

+

–

4

5

ꢁI

–60

R

ꢁIT

3300pF

8

1

+

–

ꢁIT

LTC2383-16

–80

6600pF

ꢁI

–100

–120

–140

–160

–180

50Ω

ꢀW = 482kHz

+

–

238316 TA03

2

ꢀW = 48kHz

+

–

V

= V /2

REF

CM

0

100

200

300

400

500

FREQUEICY (kHz)

238316 TA04

RELATED PARTS

PART NUMꢁER

ADCs

DESCRIPTION

COMMENTS

LTC2393-16

16-ꢀit, 1Msps Parallel/Serial ADC

16-ꢀit, 500Ksps Parallel/Serial ADC

16-ꢀit, 250Ksps Parallel/Serial ADC

5V Supply, Differential ꢁnput, 94dꢀ SIR, 4.096V ꢁnput Range, 48-Pin LQFP

Package, Pin Compatible with the LTC2392-16, LTC2391-16

LTC2392-16

LTC2391-16

5V Supply, Differential ꢁnput, 94dꢀ SIR, 4.096V ꢁnput Range, 48-Pin LQFP

Package, Pin Compatible with the LTC2393-16, LTC2391-16

5V Supply, Differential ꢁnput, 94dꢀ SIR, 4.096V ꢁnput Range, 48-Pin LQFP

Package, Pin Compatible with the LTC2393-16, LTC2392-16

LTC1864/LTC1864L

LTC1865/LTC1865L

LTC2302/LTC2306

16-bit, 250ksps/150ksps 1-Channel μPower ADC 5V/3V Supply, 1-Channel, 4.3mW/1.3mW, MSOP-8 Package

16-bit, 250ksps/150ksps 2-Channel μPower ADC 5V/3V Supply, 2-Channel, 4.3mW/1.3mW, MSOP-8 Package

12-ꢀit, 500ksps, 1-/2-Channel, Low Ioise, ADC

5V Supply, 14mW at 500ksps, 10-Pin DFI Package

LTC2355-14/LTC2356-14 14-ꢀit, 3.5Msps Serial ADC

3.3V Supply, 1-Channel, Unipolar/ꢀipolar, 18mW, MSOP-10 Package

DACs

LTC2641

16-ꢀit Single Serial V

DACs

1LSꢀ ꢁIL, 1LSꢀ DIL, MSOP-8 Package, 0V to 5V Output

SC70 6-Pin Package, ꢁnternal Reference, 1LSꢀ ꢁIL (12ꢀits)

OUT

LTC2630

12-/10-/8-ꢀit Single V

OUT

REFERENCES

LTC6652

Precision Low Drift Low Ioise ꢀuffered Reference 2.5V, 5ppm/°C Max Tempco, 2.1ppm Peak-to-Peak Ioise, MSOP-8 Package

Precision Low Drift Low Ioise ꢀuffered Reference 2.5V, 5ppm/°C Max Tempco, 0.25ppm Peak-to-Peak Ioise, MSOP-8 Package

LTC6655

AMPꢀIFIERS

LT6350

Low Ioise Single-Ended-To-Differential ADC Driver Rail-to-Rail ꢁnput and Outputs, 240ns 0.01% Settling Time, DFI-8 or

MSOP-8 Packages

LT6200/LT6200-5/

LT6200-10

165MHz/800MHz/1.6GHz Op Amp with Unity

Gain/AV = 5/AV = 10

Low Ioise Voltage: 0.95nV/√Hz (100kHz), Low Distortion: –80dꢀ at 1MHz,

TSOT23-6 Package

LT6202/LT6203

Single/Dual 100MHz Rail-to-Rail ꢁnput/Output

Ioise Low Power Amplifiers

1.9nV√Hz, 3mA Maximum, 100MHz Gain ꢀandwidth

LTC1992

Low Power, Fully Differential ꢁnput/Output

Amplifier/Driver Family

1mA Supply Current

238316f

LT 0810 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy ꢀlvd., Milpitas, CA 95035-7417

24

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC2383IMS-16PBF
厂家：	Linear
描述：	16-Bit, 1Msps, Low Power SAR ADC with Serial Interface 16位， 1Msps的，低功耗SAR ADC ，具有串行接口
文件：	总24页 (文件大小：1082K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2383IMS-16PBF [Linear]

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