LTC2391IUK-16PBF [Linear]
16-Bit, 250ksps SAR ADC with 94dB SNR; 16位, 250ksps的SAR型ADC的SNR 94分贝型号: | LTC2391IUK-16PBF |
厂家: | Linear |
描述: | 16-Bit, 250ksps SAR ADC with 94dB SNR |
文件: | 总24页 (文件大小:285K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC2391-16
16-Bit, 250ksps SAR ADC
with 94dB SNR
FeATures
DesCrIPTION
The LTC®2391-16 is a low noise, high speed 16-bit suc-
cessive approximation register (SAR) ADC. Operating
from a single 5V supply, the LTC2391-16 supports a large
±±.ꢀ96V fully differential input range, making it ideal for
high performance applications which require maximum
dynamicrange.TheLTC2391-16achieves±2LSBINLmax,
no missing codes at 16-bits and 9±dB SNR (typ).
n
250ksps Throughput Rate
n
2ꢀLS ꢁIꢀ ꢂ(aꢃx
n
Guaranteed 16-Sit Io (issing Codes
n
94dS LIR ꢂTypx at f = 20kHz
ꢁI
n
Guaranteed Operation to 125/C
n
Single 5V Supply
n
1.8V to 5V IꢁO Voltages
n
95mW Power Dissipation
The LTC2391-16 includes a precision internal reference
with a guaranteed ꢀ.5% initial accuracy and a ±2ꢀppmꢁ/C
(max) temperature coefficient. Fast 25ꢀksps throughput
with no cycle latency in both parallel and serial interface
modes makes the LTC2391-16 ideally suited for a wide
variety of high speed applications. An internal oscillator
setstheconversiontime,easingexternaltimingconsider-
ations.TheLTC2391-16dissipatesonly95mWat25ꢀksps,
whilebothnapandsleeppower-downmodesareprovided
to further reduce power during inactive periods.
n
±±.ꢀ96V Differential Input Range
n
Internal Reference (2ꢀppmꢁ/C Max)
n
No Pipeline Delay, No Cycle Latency
n
Parallel and Serial Interface
Internal Conversion Clock
n
n
±8-Pin 7mm × 7mm LQFP and QFN Packages
APPLICATIONs
n
Medical Imaging
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
n
High Speed Data Acquisition
n
Digital Signal Processing
Industrial Process Control
Instrumentation
ATE
n
n
n
TYPICAL APPLICATION
16k Point FFT fL = 250ksps,
fꢁI = 20kHz
5V
5V
0.1µF
1.8V TO 5V
4.7µF
0
–20
SNR = 94dB
10µF
0.1µF
10µF
THD ꢀ –103dB
SINAD = 93.5dB
SFDR = 104dB
–40
ANALOG INPUT
0V TO 4.096V
AVP
DVP
OVP
PARALLEL
OR
SERIAL
INTERFACE
–60
249Ω
16 BIT
+
IN
–80
–100
–120
–140
–160
2200pF
249Ω
LTC2391-16
LT6350
SER/PAR
BYTESWAP
OB/2C
CS
–
IN
RD
SINGLE-ENDED-
TO-DIFFERENTIAL
DRIVER
BUSY
VCM REFIN REFOUT CNVST PD RESET GND OGND
10µF 1µF
–180
239116 TA01
0
100
125
25
50
75
SAMPLE CLOCK
FREQUENCY (kHz)
239116 G08
239116f
ꢀ
LTC2391-16
AbsOLuTe mAxImum rATINgs ꢂIotes 1, 2x
Supply Voltage (V , V , V ) ..........................6.ꢀV
Operating Temperature Range
AVP DVP OVP
Analog Input Voltage (Note 3)
LTC2391C ................................................ ꢀ/C to 7ꢀ/C
LTC2391I.............................................. –±ꢀ/C to 85/C
LTC2391H .......................................... –±ꢀ/C to 125/C
Storage Temperature Range................... –65/C to 15ꢀ/C
+
–
IN , IN , REFIN, CNVST .. (GND – ꢀ.3V) to (V
+ ꢀ.3V)
+ ꢀ.3V)
+ ꢀ.3V)
AVP
OVP
OVP
Digital Input Voltage........(GND – ꢀ.3V) to (V
Digital Output Voltage .....(GND – ꢀ.3V) to (V
Power Dissipation...............................................5ꢀꢀmW
PIN CONFIgurATION
TOP VIEW
TOP VIEW
GND 1
AVP 2
DVP 3
36 VCM
35 GND
34 CNVST
33 PD
32 RESET
31 CS
GND
AVP
1
2
3
4
5
6
7
8
9
36 VCM
35 GND
34 CNVST
33 PD
32 RESET
31 CS
30 RD
29 BUSY
28 D15
27 D14
26 D13
25 D12
DVP
SER/PAR 4
GND 5
OB/2C 6
GND 7
BYTESWAP 8
D0 9
SER/PAR
GND
OB/2C
GND
BYTESWAP
D0
49
GND
30 RD
29 BUSY
28 D15
27 D14
26 D13
25 D12
D1 10
D2 11
D3 12
D1 10
D2 11
D3 12
UK PACKAGE
48-LEAD (7mm s 7mm) PLASTIC QFN
LX PACKAGE
T
JMAX
= 125/C, θ = 29/CꢁW
JA
48-LEAD (7mm s 7mm) PLASTIC LQFP
EXPOSED PAD (PIN ±9) IS GND, MUST BE SOLDERED TO PCB
T
= 125/C, θ = 55/CꢁW
JA
JMAX
OrDer INFOrmATION
ꢀEAD FREE FꢁIꢁLH
LTC2391CUK-16#PBF
LTC2391IUK-16#PBF
ꢀEAD FREE FꢁIꢁLH
LTC2391CLX-16#PBF
LTC2391ILX-16#PBF
LTC2391HLX-16#PBF
TAPE AID REEꢀ
PART (ARKꢁIG*
PACKAGE DELCRꢁPTꢁOI
TE(PERATURE RAIGE
ꢀ/C to 7ꢀ/C
LTC2391CUK-16#TRPBF LTC2391UK-16
±8-Lead 7mm × 7mm Plastic QFN
±8-Lead 7mm × 7mm Plastic QFN
PACKAGE DELCRꢁPTꢁOI
LTC2391IUK-16#TRPBF
TRAY
LTC2391UK-16
PART (ARKꢁIG*
LTC2391LX-16
LTC2391LX-16
LTC2391LX-16
–±ꢀ/C to 85/C
TE(PERATURE RAIGE
ꢀ/C to 7ꢀ/C
LTC2391CLX-16#PBF
LTC2391ILX-16#PBF
LTC2391HLX-16#PBF
±8-Lead 7mm × 7mm Plastic LQFP
±8-Lead 7mm × 7mm Plastic LQFP
±8-Lead 7mm × 7mm Plastic LQFP
–±ꢀ/C to 85/C
–±ꢀ/C to 125/C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http:ꢁꢁwww.linear.comꢁleadfreeꢁ
For more information on tape and reel specifications, go to: http:ꢁꢁwww.linear.comꢁtapeandreelꢁ
239116f
ꢁ
LTC2391-16
ANALOg INPuT The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. ꢂIote 4x
LY(SOꢀ
PARA(ETER
COIDꢁTꢁOIL
(ꢁI
–ꢀ.ꢀ5
–ꢀ.ꢀ5
TYP
(AX
AVP
AVP
UIꢁTL
+
+
l
l
l
l
l
V
V
V
V
Absolute Input Range (IN )
(Note 5)
V
V
IN
IN
IN
–
+
–
Absolute Input Range (IN )
(Note 5)
–
+
–
– V
Input Differential Voltage Range
Common Mode Input Range
Analog Input Leakage Current
Analog Input Capacitance
V
= V – V
–V
V
REF
V
IN
IN
IN
IN
REF
V
ꢁ2 – ꢀ.ꢀ5
REF
V
ꢁ2
REF
V
ꢁ2 + ꢀ.ꢀ5
±1
V
CM
REF
I
IN
µA
C
IN
Sample Mode
Hold Mode
±5
5
pF
pF
CMRR
Input Common Mode Rejection Ratio
7ꢀ
dB
CONverTer ChArACTerIsTICs The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. ꢂIote 4x
LY(SOꢀ
PARA(ETER
COIDꢁTꢁOIL
(ꢁI
16
TYP
(AX
UIꢁTL
Bits
l
l
Resolution
No Missing Codes
Transition Noise
16
Bits
ꢀ.3
±1
LSB
RMS
l
l
l
INL
Integral Linearity Error
Differential Linearity Error
Bipolar Zero Error
Bipolar Zero Error Drift
Bipolar Full-Scale Error
(Note 6)
(Note 7)
–2
–1
–7
2
1
7
LSB
DNL
BZE
LSB
LSB
1
ppmꢁ/C
l
FSE
External Reference
Internal Reference (Note 7)
ꢀ.1±
ꢀ.1
%
%
Bipolar Full-Scale Error Drift
±1ꢀ
ppmꢁ/C
DYNAmIC ACCurACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AꢁI = –1dSFL ꢂIotes 4, 8x
LY(SOꢀ
SINAD
SNR
PARA(ETER
COIDꢁTꢁOIL
(ꢁI
9ꢀ.5
91
TYP
93.5
9±
(AX
UIꢁTL
dB
l
l
l
Signal-to-(Noise + Distortion) Ratio
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
–3dB Input Bandwidth
Aperture Delay
f
f
f
f
= 2ꢀkHz
IN
IN
IN
IN
= 2ꢀkHz
dB
THD
= 2ꢀkHz, First 5 Harmonics
= 2ꢀkHz
–1ꢀ3
1ꢀ±
5ꢀ
–9±
dB
SFDR
dB
MHz
ns
ꢀ.5
7
Aperture Jitter
ps
RMS
Transient Response
Full-Scale Step
6ꢀ
ns
239116f
ꢂ
LTC2391-16
INTerNAL reFereNCe ChArACTerIsTICs The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. ꢂIote 4x
PARA(ETER
COIDꢁTꢁOIL
(ꢁI
TYP
±.ꢀ96
±1ꢀ
2.6
(AX
±.116
±2ꢀ
UIꢁTL
V
V
REF
V
REF
V
REF
Output Voltage
Output Tempco
Output Impedance
I
I
= ꢀ
±.ꢀ76
OUT
OUT
l
= ꢀ (I-, H-Grades) (Note 11)
ppmꢁ/C
kΩ
–ꢀ.1mA ≤ I
≤ ꢀ.1mA
OUT
External Reference Voltage
REFIN Input Impedance
2.5
±.ꢀ96
85
AVP – ꢀ.5
V
kΩ
V
Line Regulation
AVP = ±.75V to 5.25V
= ꢀ
ꢀ.3
mVꢁV
V
REF
VCM Output Voltage
I
2.ꢀ8
OUT
DIgITAL INPuTs AND DIgITAL OuTPuTs The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. ꢂIote 4x
LY(SOꢀ
PARA(ETER
COIDꢁTꢁOIL
(ꢁI
TYP
(AX
UIꢁTL
V
l
l
l
V
V
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
ꢀ.8 • OVP
IH
IL
ꢀ.5
1ꢀ
V
I
IN
V
= ꢀV to OVP
IN
–1ꢀ
OVP – ꢀ.2
–1ꢀ
µA
pF
C
V
V
Digital Input Capacitance
High Level Output Voltage
Low Level Output Voltage
Hi-Z Output Leakage Current
Output Source Current
Output Sink Current
5
IN
l
l
l
I = –5ꢀꢀµA
O
V
OH
OL
I = 5ꢀꢀµA
O
ꢀ.2
1ꢀ
V
I
I
I
V
V
V
= ꢀV to OVP
= ꢀV
µA
mA
mA
OZ
OUT
OUT
OUT
–1ꢀ
1ꢀ
SOURCE
SINK
= OVP
POwer requIremeNTs The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. ꢂIote 4x
LY(SOꢀ
, V
PARA(ETER
Supply Voltage
Supply Voltage
COIDꢁTꢁOIL
(ꢁI
±.75
1.71
TYP
(AX
5.25
5.25
UIꢁTL
l
V
5
V
V
AVP DVP
V
OVP
l
l
I
DD
Supply Current
Power Down Mode
25ꢀksps Sample Rate with Nap Mode
Conversion Done and All Digital Inputs Tied to OVP
19
35
25
25ꢀ
mA
µA
P
D
Power Dissipation
Power Down Mode
25ꢀksps Sample Rate with Nap Mode
Conversion Done and All Digital Inputs Tied to OVP
95
175
125
125ꢀ
mW
µW
239116f
ꢃ
LTC2391-16
TImINg ChArACTerIsTICs The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. ꢂIote 4x
LY(SOꢀ
PARA(ETER
COIDꢁTꢁOIL
(ꢁI
TYP
(AX
25ꢀ
UIꢁTL
ksps
ns
l
l
l
l
l
l
l
l
l
l
f
t
t
t
t
t
t
t
t
t
Sampling Frequency
Conversion Time
SMPL
25ꢀꢀ
1±85
CONV
Acquisition Time
ns
ACQ
±
CNVST Low Time
2ꢀ
ns
CNVST High Time
25ꢀ
ns
5
C = 15pF
L
15
ns
CNVST↓ to BUSY Delay
RESET Pulse Width
SCLK Period
6
5
12.5
±
ns
7
(Note 9)
ns
8
SCLK High Time
ns
9
SCLK Low Time
±
ns
1ꢀ
t , t
SCLK Rise and Fall Times
SDIN Setup Time
(Note 1ꢀ)
1
µs
r
f
l
l
l
l
l
l
l
l
t
11
t
12
t
13
t
1±
t
15
t
16
t
17
t
18
2
1
2
ns
SDIN Hold Time
ns
C = 15pF
L
8
8
ns
SDOUT Delay After SCLK↑
SDOUT Delay After CS↓
CS↓ to SCLK Setup Time
Data Valid to BUSY↓
Data Access Time after RD↓ or BYTESWAP↑
Bus Relinquish Time
ns
2ꢀ
1
ns
ns
1ꢀ
ns
1ꢀ
ns
Iote 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Iote 7: Bipolar zero error is the offset voltage measured from –ꢀ.5LSB
when the output code flickers between ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ and 1111
1111 1111 1111. Bipolar full-scale error is the worst-case of –FS or +FS
untrimmed deviation from ideal first and last code transitions and includes
the effect of offset error.
Iote 2: All voltage values are with respect to ground.
Iote 8: All specifications in dB are referred to a full-scale ±±.ꢀ96V input
with a ±.ꢀ96V reference voltage.
Iote 3: When these pin voltages are taken below ground or above
AVP, DVP or OVP, they will be clamped by internal diodes. This product can
handle input currents up to 1ꢀꢀmA below ground or above AVP, DVP or
OVP without latchup.
Iote 9: t of 8ns maximum allows a shift clock frequency up to
13
2 • (t + t
) for falling edge capture with 5ꢀ% duty cycle and up to
SETUP
13
8ꢀMHz for rising capture. t
is the set-up time of the receiving logic.
SETUP
Iote 4: AVP = DVP = OVP = 5V, f
= 25ꢀksps, external reference equal
SMPL
to ±.ꢀ96V unless otherwise noted.
Iote 10: Guaranteed by design.
Iote 5: Recommended operating conditions.
Iote 11: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Iote 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
4V
t
WIDTH
0.5V
50%
50%
t
t
DELAY
DELAY
239116F01
4V
4V
0.5V
0.5V
Figure 1. Voltage ꢀevels for Timing Lpecifications
239116f
ꢄ
LTC2391-16
TYPICAL PerFOrmANCe ChArACTerIsTICs TA = 25°C, fL(Pꢀ = 250ksps, unless otherwise noted.
ꢁntegral Ionlinearity
vs Output Code
Differential Ionlinearity
vs Output Code
DC Histogram
ꢂEꢃternal Referencex
1.5
1.0
2000000
1800000
1600000
1400000
1200000
1000000
800000
600000
400000
200000
0
2.0
1.5
1.0
0.5
0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.5
–1.0
–1.5
32764
32766 32768 32770 32772
CODE
0
16384
32768
49152
65536
32768
0
16384
49152
65536
OUTPUT CODE
OUTPUT CODE
239116 G02
239116 G03
239116 G01
DC Histogram
ꢂꢁnternal Referencex
ꢁnternal Reference Output
vs Temperature
Offset Error vs Temperature
2000000
1800000
1600000
1400000
1200000
1000000
800000
600000
400000
200000
0
4.0975
4.0970
4.0965
4.0960
4.0955
4.0950
4.0945
4.0940
4.0935
4.0930
4.0925
1.0
0.8
TC = 4ppm/°C
0.6
0.4
0.2
0
32764 32766 32768 32770 32772
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
CODE
TEMPERATURE (°C)
239116 G04
239116 G06
239116 G05
16k Point FFT fL = 250ksps,
fꢁI = 20kHz
16k Point FFT fL = 250ksps,
fꢁI = 100kHz
Full-Lcale Error vs Temperature
10
8
0
–20
0
–20
SNR = 93.4dB
SNR = 94dB
THD ꢀ –98.7dB
SINAD = 92.3dB
SFDR = 106.6dB
THD ꢀ –103dB
SINAD = 93.5dB
SFDR = 104dB
6
–40
–40
4
–60
–60
2
–80
–80
0
–100
–120
–140
–160
–100
–120
–140
–160
–2
–4
–6
–8
–10
–180
–180
–55 –35 –15
5
25 45 65 85 105 125
0
100
125
0
100
125
25
50
75
25
50
75
TEMPERATURE (°C)
FREQUENCY (kHz)
FREQUENCY (kHz)
239116 G07
239116 G09
239116 G08
239116f
ꢅ
LTC2391-16
TYPICAL PerFOrmANCe ChArACTerIsTICs TA = 25°C, fL(Pꢀ = 250ksps, unless otherwise noted.
THD, Harmonics
LIR, LꢁIAD at fꢁI = 20kHz
vs Temperature
LIR, LꢁIAD vs ꢁnput Frequency
vs ꢁnput Frequency
96
94
92
90
88
86
84
82
80
–70
–75
96
95
94
93
92
SNR
–80
SINAD
–85
SNR
–90
–95
THD
SINAD
–100
–105
–110
–115
–120
3RD
2ND
0
25
50
75
100
0
50
25
INPUT FREQUENCY (kHz)
100
75
–55 –35 –15
5
25 45 65 85 105 125
INPUT FREQUENCY (kHz)
TEMPERATURE (°C)
239116 G10
239116 G11
239116 G12
THD, Harmonics at fꢁI = 20kHz
vs Temperature
Lupply Current vs Lampling
Frequency
LIR, LꢁIAD vs ꢁnput ꢀevel
30
95.0
94.5
94.0
93.5
93.0
–95
–100
–105
–110
–115
–120
SNR
25
20
THD
3RD
SINAD
15
10
2ND
5
0
0.1
1
10
100
1000
–20
–10
–40
0
–30
–55 –35 –15
5
25 45 65 85 105 125
SAMPLING FREQUENCY (kHz)
TEMPERATURE (°C)
INPUT LEVEL (dB)
239116 G15
239116 G14
239116 G13
Power-Down Current
vs Temperature
Lupply Current vs Temperature
18
16
14
12
10
8
90
80
70
60
50
40
30
20
10
0
AVP
6
DVP
0VP
DVP
4
AVP
0VP
2
0
–55 –35 –15
5
25 45 65 85 105 125
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE (°C)
TEMPERATURE (°C)
239116 G16
239116 G17
239116f
ꢆ
LTC2391-16
PIN FuNCTIONs
GID ꢂPins 1, 5, 7, 20, 35, 41, 44, 48, Eꢃposed Pad Pin
49x: Ground. All GND pins must be connected to a solid
ground plane.
D7 ꢂPin 16x: Data Bit 7. When SERꢁPAR = ꢀ this pin is
Bit 7 of the parallel port data output bus.
OGID ꢂPin 17x: Digital Ground for the InputꢁOutput
Interface.
AVP ꢂPins 2, 40, 45, 46, 47x: 5V Analog Power Supply.
The range of AVP is ±.75V to 5.25V. Bypass AVP to GND
with a good quality ꢀ.1µF and a 1ꢀµF ceramic capacitor
in parallel.
OVP ꢂPin 18x: Digital Power Supply for the InputꢁOutput
Interface. The range for OVP is 1.8V to 5V. Bypass OVP
to OGND with a good quality ±.7µF ceramic capacitor
close to the pin.
DVP ꢂPins 3, 19x: 5V Digital Power Supply. The range of
DVP is ±.75V to 5.25V. Bypass DVP to GND with a good
quality ꢀ.1µF and a 1ꢀµF ceramic capacitor in parallel.
D8 ꢂPin 21x: Data Bit 8. When SERꢁPAR = ꢀ this pin is
Bit 8 of the parallel port data output bus.
LER/PAR ꢂPin 4x: SerialꢁParallel Selection Input. This pin
controls the digital interface. A logic high on this pin se-
lects the serial interface and a logic low selects the parallel
interface. In the serial mode the non-active digital outputs
are high impedance.
D9/LDꢁI ꢂPin 22x: Data Bit 9ꢁSerial Data Input. When
SERꢁPAR = ꢀ this pin is Bit 9 of the parallel port data
output bus. When SERꢁPAR = 1, (serial mode) this is
the serial data input. SDIN can be used as a data input to
daisy-chain two or more conversion results into a single
SDOUT line. The digital data level on SDIN is output on
SDOUT with a delay of 16 SCLK periods after the start of
the read sequence.
OS/2C ꢂPin 6x: Offset BinaryꢁTwo’s Complement Input.
When OBꢁ2C is high, the digital output is offset binary.
When low, the MSB is inverted resulting in two’s comple-
ment output.
D10/LDOUTꢂPin23x:DataBit1ꢀꢁSerialDataOuput.When
SERꢁPAR = ꢀ this pin is Bit 1ꢀ of the parallel port data
output bus. When SERꢁPAR = 1, (serial mode) this is the
serial data output. The conversion result can be clocked
out serially on this pin synchronized to SCLK. The data
is clocked out MSB first on the rising edge of SCLK and
is valid on the falling edge of SCLK. The data format is
determined by the logic level of OBꢁ2C.
SYTELWAP ꢂPin 8x: BYTESWAP Input. With BYTESWAP
low, data will be output with Pin 28 (D15) being the
MSB and Pin 9 (Dꢀ) being the LSB. With BYTESWAP
high, the upper eight bits and the lower eight bits will
be switched. The MSB is output on Pin 16 and Bit 8 is
output on Pin 9. Bit 7 is output on Pin 28 and the LSB is
output on Pin 21.
D0 ꢂPin 9x: Data Bit ꢀ. When SERꢁPAR = ꢀ this pin is Bit ꢀ
D11/LCꢀK ꢂPin 24x: Data Bit 11ꢁSerial Clock Input. When
SERꢁPAR = ꢀ this pin is Bit 11 of the parallel port data
output bus. When SERꢁPAR = 1, (serial mode) this is the
serial clock input.
of the parallel port data output bus.
D1 ꢂPin 10x: Data Bit 1. When SERꢁPAR = ꢀ this pin is
Bit 1 of the parallel port data output bus.
D12 ꢂPin 25x: Data Bit 12. When SERꢁPAR = ꢀ this pin is
Bit 12 of the parallel port data output bus.
D2 ꢂPin 11x: Data Bit 2. When SERꢁPAR = ꢀ this pin is
Bit 2 of the parallel port data output bus.
D13 ꢂPin 26x: Data Bit 13. When SERꢁPAR = ꢀ this pin is
Bit 13 of the parallel port data output bus.
D3 ꢂPin 12x: Data Bit 3. When SERꢁPAR = ꢀ this pin is
Bit 3 of the parallel port data output bus.
D14 ꢂPin 27x: Data Bit 1±. When SERꢁPAR = ꢀ this pin is
Bit 1± of the parallel port data output bus.
D4 ꢂPin 13x: Data Bit ±. When SERꢁPAR = ꢀ this pin is
Bit ± of the parallel port data output bus.
D15 ꢂPin 28x: Data Bit 15. When SERꢁPAR = ꢀ this pin is
Bit 15 of the parallel port data output bus. The data format
is determined by the logic level of OBꢁ2C.
D5 ꢂPin 14x: Data Bit 5. When SERꢁPAR = ꢀ this pin is
Bit 5 of the parallel port data output bus.
D6 ꢂPin 15x: Data Bit 6. When SERꢁPAR = ꢀ this pin is
Bit 6 of the parallel port data output bus.
239116f
ꢇ
LTC2391-16
PIN FuNCTIONs
SULY ꢂPin 29x: Busy Output. A low-to-high transition oc-
curs when a conversion is started. It stays high until the
conversion is complete. The falling edge of BUSY can be
used as the data-ready clock signal.
VC( ꢂPin 36x: Common Mode Analog Output. Typically
the output voltage is 2.ꢀ±8V. Bypass to GND with a 1ꢀµF
capacitor.
REFOUT ꢂPin 37x: Internal Reference Output. Nominal
output voltage is ±.ꢀ96V. Connect this pin to REFIN if us-
ing the internal reference. If an external reference is used
connect REFOUT to ground.
RD ꢂPin 30x: Read Data Input. When CS and RD are both
low, the parallel and serial output bus is enabled.
CS ꢂPin 31x: Chip Select. When CS and RD are both low,
the parallel and serial output bus is enabled. CS is also
used to gate the external shift clock.
REFꢁI ꢂPin 38x: Reference Input. An external reference
can be applied to REFIN if a more accurate reference is
required. If an external reference is used tie REFOUT to
ground.
RELET ꢂPin 32x: Reset Input. When high the LTC2391-16
isreset, andifthisoccursduringaconversion, theconver-
sion is halted and the data bus is put into Hi-Z mode.
REFLEILE ꢂPin 39x: Reference Input Sense. Leave
REFSENSE open when using the internal reference. If
an external reference is used connect REFSENSE to the
ground pin of the external reference.
PD ꢂPin 33x: Power-Down Input. When high, the
LTC2391-16ispowereddownandsubsequentconversion
requests are ignored. Before entering power shutdown,
the digital output data should be read.
–
+
+
ꢁI , ꢁI ꢂPin 42, Pin 43x: Differential Analog Inputs.
–
IN – (IN ) can range up to ±V
.
REF
CNVST ꢂPin 34x: Conversion Start Input. A falling edge
on CNVST puts the internal sample-and-hold into the hold
mode and starts a conversion. CNVST is independent of
CS.
239116f
ꢈ
LTC2391-16
FuNCTIONAL bLOCk DIAgrAm
AVP DVP OVP
LTC2391-16
16-BIT OR
TWO BYTE
SDIN
SDOUT
SCLK
+
IN
PARALLEL/
SERIAL
INTERFACE
16-BIT SAMPLING ADC
16-BIT
–
IN
CS
1x BUFFER
RD
REFIN
SER/PAR
BYTESWAP
OB/2C
REFOUT
VCM
4.096V
BUSY
CONTROL LOGIC
CNVST PD
REFERENCE
REFSENSE
RESET
GND OGND
239116BD
TImINg DIAgrAms
Conversion Timing Using the Parallel ꢁnterface
CS, RD = 0
CNVST
ACQUIRE
BUSY
CONVERT
D[15:0]
PREVIOUS CONVERSION
CURRENT CONVERSION
239116 TD01
Conversion Timing Using the Lerial ꢁnterface
CS, RD = 0
CNVST
ACQUIRE
BUSY
CONVERT
SCLK
D14 D12 D10 D8 D6 D4 D2 D0
D15 D13 D11 D9 D7 D5 D3 D1
SDOUT
239116 TD02
239116f
ꢀ0
LTC2391-16
APPLICATIONs INFOrmATION
OVERVꢁEW
011...111
011...110
BIPOLAR
ZERO
The LTC2391-16 is a low noise, high speed 16-bit suc-
cessive approximation register (SAR) ADC. Operating
from a single 5V supply, the LTC2391-16 supports a
large ±±.ꢀ96V fully differential input range, making it ideal
for high performance applications which require a wide
dynamicrange.TheLTC2391-16achieves±2LSBINLmax,
no missing codes at 16 bits and 9±dB SNR (typ).
000...001
000...000
111...111
111...110
100...001
100...000
FSR = +FS – –FS
1LSB = FSR/65536
TheLTC2391-16includesaprecisioninternalreferencewith
aguaranteedꢀ.5%initialaccuracyanda±2ꢀppmꢁ/C(max)
temperature coefficient. Fast 25ꢀksps throughput with no
cycle latency in both parallel and serial interface modes
makes the LTC2391-16 ideally suited for a wide variety
of high speed applications. An internal oscillator sets the
conversion time, easing external timing considerations.
The LTC2391-16 dissipates only 95mW at 25ꢀksps, while
both nap and sleep power-down modes are provided to
further reduce power during inactive periods.
–1 0V
LSB
INPUT VOLTAGE (V)
1
LSB
–FSR/2
FSR/2 – 1LSB
239116 F02
Figure 2. ꢀTC2391-16 Two’s Complement Transfer Function
AIAꢀOG ꢁIPUT
The analog inputs of the LTC2391-16 are fully differential
in order to maximize the signal swing that can be digitized.
Theanaloginputscanbemodeledbytheequivalentcircuit
showninFigure3.ThediodesattheinputprovideESDpro-
tection. The analog inputs should not exceed the supply or
gobelowground.Intheacquisitionphase,eachinputsees
approximately±ꢀpF(C )fromthesamplingCDACinseries
with 5ꢀΩ (R ) from the on-resistance of the sampling
switch. Any unwanted signal that is common to both
inputs will be reduced by the common mode rejection of
the ADC. The inputs draw only one small current spike
COIVERTER OPERATꢁOI
The LTC2391-16 operates in two phases. During the ac-
quisition phase, the charge redistribution capacitor DꢁA
IN
+
–
IN
converter (CDAC) is connected to the IN and IN pins
to sample the differential analog input voltage. A falling
edge on the CNVST pin initiates a conversion. During the
conversionphase,the16-bitCDACissequencedthrougha
successiveapproximationalgorithm,effectivelycomparing
the sampled input with binary-weighted fractions of the
while charging the C capacitors during acquisition.
During conversion, the analog inputs draw only a small
IN
leakage current.
reference voltage (e.g., V ꢁ2, V ꢁ± … V ꢁ65536)
REF
REF
REF
usingthedifferentialcomparator.Attheendofconversion,
the CDAC output approximates the sampled analog input.
The ADC control logic then prepares the 16-bit digital
output code for parallel or serial transfer.
AVP
C
IN
R
R
IN
IN
+
–
IN
IN
BIAS
AVP
VOLTAGE
C
IN
TRAILFER FUICTꢁOI
239116 F03
The LTC2391-16 digitizes the full-scale voltage of 2 • V
REF
REF
16
into2 levels,resultinginanLSBsizeof125µVwhenV
=±.ꢀ96V. Theidealtransferfunctionfortwo’scomplement
is shown in Figure 2. The OBꢁ2C pin selects either offset
binary or two’s complement format.
Figure 3. The Equivalent Circuit for the
Differential Analog ꢁnput of the ꢀTC2391-16
239116f
ꢀꢀ
LTC2391-16
APPLICATIONs INFOrmATION
ꢁIPUT DRꢁVE CꢁRCUꢁTL
distortion from self heating and from damage that may
occurduringsoldering.Metalfilmsurfacemountresistors
are much less susceptible to both problems.
Alowimpedancesourcecandirectlydrivethehighimped-
ance inputs of the LTC2391-16 without gain error. A high
impedance source should be buffered to minimize settling
time during acquisition and to optimize the distortion
performance of the ADC.
Lingle-to-Differential Conversion
For single-ended input signals, a single-ended-to-differ-
ential conversion circuit must be used to produce a dif-
ferentialsignalattheADCinputs.TheLT635ꢀADCdriveris
recommendedforperformingasingle-ended-to-differential
conversion, as shown in Figure ±a. Its low noise and good
DC linearity allows the LTC2391-16 to meet full data sheet
specifications. An alternative solution using two op amps
is shown in Figure ±b. Using two LT®18ꢀ6 op amps, the
circuit achieves 9±dB signal-to-noise ratio (SNR). For a
2ꢀkHz input signal, the input of the LTC2391-16 has been
bandwidth limited to about 25kHz.
For best performance, a buffer amplifier should be used
to drive the analog inputs of the LTC2391-16. The am-
plifier provides low output impedance to allow for fast
settling of the analog signal during the acquisition phase.
It also provides isolation between the signal source and
the ADC inputs which draw a small current spike during
acquisition.
ꢁnput Filtering
The noise and distortion of the buffer amplifier and other
circuitry must be considered since they add to the ADC
noiseanddistortion.Noisyinputcircuitryshouldbefiltered
prior to the analog inputs to minimize noise. A simple
1-pole RC filter is sufficient for many applications.
ADC REFEREICE
A low noise, low temperature drift reference is critical to
achieving the full data sheet performance of the ADC. The
LTC2391-16 provides an excellent internal reference with
a ±2ꢀppmꢁ/C (max) temperature coefficient. For better
accuracy, an external reference can be used.
Large filter RC time constants slow down the settling at
the analog inputs. It is important that the overall RC time
constants be short enough to allow the analog inputs to
completely settle to 16-bit resolution within the acquisi-
The high speed, low noise internal reference buffer is used
for both internal and external reference applications. It
cannot be bypassed.
tion time (t ).
ACQ
Highqualitycapacitorsandresistorsshouldbeusedinthe
RC filter since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
ANALOG
INPUT
+
0V TO 4.096V
LT1806
–
249Ω
+
IN
301Ω
0.013µF
249Ω
LTC2391-16
+
IN
301Ω
249Ω
–
IN
ANALOG INPUT
0V TO 4.096V
2200pF
LT6350
LTC2391-16
239116 F04b
249Ω
–
–
+
IN
LT1806
239116 F04a
COMMON
MODE
VOLTAGE
SINGLE-ENDED-
TO-DIFFERENTIAL
DRIVER
Figure 4a. Recommended Lingle-Ended-to-Differential
Conversion Circuit Using the ꢀT6350 ADC Driver
Figure 4b. Alternative Lingle-Ended-to-Differential
Conversion Circuit Using Two ꢀT1806 Op Amps
239116f
ꢀꢁ
LTC2391-16
APPLICATIONs INFOrmATION
ꢁnternal Reference
DYIA(ꢁC PERFOR(AICE
To use the internal reference, simply tie the REFOUT and
REFIN pins together. This connects the ±.ꢀ96V output of
the internal reference to the input of the internal reference
buffer. The output impedance of the internal reference is
approximately 2.6kΩ and the input impedance of the in-
ternal reference buffer is about 85kΩ. It is recommended
that this node be bypassed to ground with a 1µF or larger
capacitortofiltertheoutputnoiseoftheinternalreference.
The REFSENSE pin should be left floating when using the
internal reference.
Fast fourier transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequen-
cies outside the fundamental. The LTC2391-16 provides
guaranteed tested limits for both AC distortion and noise
measurements.
Lignal-to-Ioise and Distortion Ratio ꢂLꢁIADx
The signal-to-noise and distortion ratio (SINAD) is the
ratiobetweentheRMSamplitudeofthefundamentalinput
frequency and the RMS amplitude of all other frequency
components at the AꢁD output. The output is band-limited
tofrequenciesfromaboveDCandbelowhalfthesampling
frequency. Figure 5 shows that the LTC2391-16 achieves
a typical SINAD of 93.5dB at a 25ꢀksps sampling rate
with a 2ꢀkHz input.
Eꢃternal Reference
An external reference can be used with the LTC2391-16
when even higher performance is required. The
LT179ꢀ-±.ꢀ96 offers ꢀ.ꢀ5% (max) initial accuracy and
1ꢀppmꢁ/C (max) temperature coefficient. When using an
external reference, connect the reference output to the
REFIN pin and connect the REFOUT pin to ground. The
REFSENSE pin should be connected to the ground of the
external reference.
0
–20
SNR = 94dB
THD ꢀ –103dB
SINAD = 93.5dB
SFDR = 104dB
–40
–60
–80
–100
–120
–140
–160
–180
0
100
125
25
50
75
FREQUENCY (kHz)
239116 G08
Figure 5. 16k Point FFT of the ꢀTC2391-16, fL = 250ksps, fꢁI = 20kHz
239116f
ꢀꢂ
LTC2391-16
APPLICATIONs INFOrmATION
Lignal-to-Ioise Ratio ꢂLIRx
Power Lupply Lequencing
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 5 shows
that the LTC2391-16 achieves a typical SNR of 9±dB at a
25ꢀkHz sampling rate with a 2ꢀkHz input.
The LTC2391-16 does not have any specific power sup-
ply sequencing requirements. Care should be taken to
observe the maximum voltage relationships described in
the Absolute Maximum Ratings section. The LTC2391-16
has a power-on reset (POR) circuit. With the POR, the
result of the first conversion is valid after power has
been applied to the ADC. The LTC2391-16 will reset itself
if the power supply voltage drops below 2.5V. Once the
supply voltage is brought back to its nominal value, the
POR will reinitialize the ADC and it will be ready to start
a new conversion.
Total Harmonic Distortion ꢂTHDx
Totalharmonicdistortion(THD)istheratiooftheRMSsum
ofallharmonicsoftheinputsignaltothefundamentalitself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (f
THD is expressed as:
ꢁ2).
Iap (ode
SMPL
The LTC2391-16 can be put into the nap mode after a
conversion has been completed to reduce the power
consumption between conversions. In this mode some
of the circuitry on the device is turned off. Nap mode is
enabledbykeepingCNVSTlowbetweenconversions.When
the next conversion is requested, bring CNVST high and
hold for at least 25ꢀns, then start the next conversion by
bringing CNVST low. See Figure 6.
V22 + V32 + V42...VN2
THD= 20log
V1
where V is the RMS amplitude of the fundamental fre-
1
quencyandV throughV aretheamplitudesofthesecond
2
N
through Nth harmonics.
POWER COILꢁDERATꢁOIL
Power Lhutdown (ode
The LTC2391-16 provides three sets of power supply
pins: the analog 5V power supply (AVP), the digital 5V
power supply (DVP) and the digital inputꢁoutput interface
power supply (OVP). The flexible OVP supply allows the
LTC2391-16tocommunicatewithanydigitallogicoperating
between 1.8V and 5V, including 2.5V and 3.3V systems.
When PD is tied high, the LTC2391-16 enters power shut-
downandsubsequentrequestsforconversionareignored.
Before entering power shutdown, the digital output data
needstoberead.However,ifarequestforpowershutdown
(PD = high) occurs during a conversion, the conversion
will finish and then the device will power down. The data
t
5
CNVST
BUSY
NAP
t
t
ACQ
CONV
NAP MODE
239116 F06
Figure 6. Iap (ode Timing for the ꢀTC2391-16
239116f
ꢀꢃ
LTC2391-16
APPLICATIONs INFOrmATION
from that conversion can be read after PD = low is ap-
plied. In this mode, power consumption drops to a typical
value of 175µW from 95mW. This mode can be used if the
LTC2391-16 is inactive for a long period of time and the
user wants to minimize the power dissipation.
Tꢁ(ꢁIG AID COITROꢀ
The LTC2391-16 conversion is controlled by CNVST. A
falling edge on CNVST will start a conversion. CS and RD
control the digital interface on the LTC2391-16. When
either CS or RD is high, the digital outputs are high
impedance.
Recovery from Power Lhutdown (ode
Once the PD pin is returned to a low level, ending the
power shutdown request, the internal circuitry will begin
to power up. If the internal reference is used, the 2.6kΩ
output impedance with the 1µF bypass capacitor on the
REFINꢁREFOUT pins will be the main time constant for
the power-on recovery time. If an external reference is
used, typically allow 5ms for recovery before initiating a
new conversion.
CNVST Timing
The LTC2391-16 conversion is controlled by CNVST. A
falling edge on CNVST will start a conversion. Once a
conversion has been initiated, it cannot be restarted until
the conversion is complete. For optimum performance
CNVSTshouldbeacleanlowjittersignal. Converterstatus
is indicated by the BUSY output which remains high while
the conversion is in progress. To ensure no errors occur
in the digitized results return the rising edge either within
±ꢀns from the start of the conversion or wait until after
the conversion has been completed. The CNVST timing
needed to take advantage of the reduced power mode of
operation is described in the Nap Mode section.
Power Dissipation vs Lampling Frequency
The power dissipation of the LTC2391-16 will decrease
as the sampling frequency is reduced when nap mode
is activated. See Figure 7. In nap mode, a portion of the
circuitryontheLTC2391-16isturnedoffafteraconversion
has been completed. Increasing the time allowed between
conversions lowers the average power.
ꢁnternal Conversion Clock
The LTC2391-16 has an internal clock that is trimmed
to achieve a maximum conversion time of 25ꢀꢀns. No
external adjustments are required and with a maximum
acquisition time of 1±85ns, a throughput performance of
25ꢀksps is guaranteed.
30
25
20
DꢁGꢁTAꢀ ꢁITERFACE
15
10
The LTC2391-16 allows both parallel and serial digital
interfaces. TheflexibleOVPsupplyallowstheLTC2391-16
to communicate with any digital logic operating between
1.8V and 5V, including 2.5V and 3.3V systems.
5
0
0.1
1
10
100
1000
SAMPLING FREQUENCY (kHz)
239116 G15
Figure 7. Power Dissipation of the ꢀTC2391-16
Decreases with Decreasing Lampling Frequency
239116f
ꢀꢄ
LTC2391-16
APPLICATIONs INFOrmATION
Parallel (odes
The SDIN input pin is used to daisy-chain multiple con-
verters. This is useful for applications where hardware
constraints may limit the number of lines needed to
interface to a large number of converters. For example,
if two devices are cascaded, the MSB of the first device
will appear at the output after 17 SCLK cycles. The first
MSB is clocked in on the falling edge of the first SCLK.
See Figure 12.
The parallel output data interface is active when the
SERꢁPAR pin is tied low and when both CS and RD are low.
The output data can be read as a 16-bit word as shown
in Figures 8, 9 and 1ꢀ or it can be read as two 8-bit bytes
by using the BYTESWAP pin. As shown in Figure 11, with
the BYTESWAP pin low, the first eight MSBs are output on
the D15 to D8 pins and the eight LSBs are output on the
D7 to DO pins. When BYTESWAP is taken high, the eight
LSBs now are output on the D15 to D8 pins and the eight
MSBs are output on the D7 to Dꢀ pins.
Data Format
When OBꢁ2C is high, the digital output is offset binary.
When low, the MSB is inverted resulting in two’s comple-
ment output. This pin is active in both the parallel and
serial modes of operation.
Lerial (odes
The serial output data interface is active when the
SERꢁPAR pin is tied high and when both CS and RD are
low. The serial output data will be clocked out on the
SDOUT pin when an external clock is applied to the SCLK
pin. Clocking out the data after the conversion will yield
the best performance. With a shift clock frequency of at
least15MHz, a25ꢀkspsthroughputisachieved. Theserial
output data changes state on the rising edge of SCLK and
can be captured on the falling edge of SCLK. D15 remains
valid till the first rising edge of shift clock after the first
falling edge of shift clock. The non-active digital outputs
are high impedance when operating in the serial mode.
Reset
When the RESET pin is high, the LTC2391-16 is reset, and
ifthisoccursduringaconversion, theconversionishalted
and the data bus is put into Hi-Z mode. In reset, requests
fornewconversionsareignored.OnceRESETreturnslow,
the LTC2391-16 is ready to start a new conversion after
the acquisition time has been met. See Figure 13.
CS = RD = 0
t
4
CNVST
BUSY
t
CONV
t
t
16
6
PREVIOUS CONVERSION
NEW
DATA BUS D[15:0]
239116 F08
Figure 8. Read the Parallel Data Continuously.
The Data Sus is Always Driven and Can’t Se Lhared
239116f
ꢀꢅ
LTC2391-16
APPLICATIONs INFOrmATION
CS
RD
BUSY
Hi-Z
Hi-Z
CURRENT
CONVERSION
DATA BUS D[15:0]
239116 F09
t
t
18
17
Figure 9. Read the Parallel Data After the Conversion
CS = 0
t
4
CNVST, RD
BUSY
t
CONV
t
6
Hi-Z
Hi-Z
PREVIOUS
CONVERSION
DATA BUS D[15:0]
239116 F09
t
17
t
18
Figure 10. Read the Parallel Data During the Conversion
8-BIT INTERFACE
CS, RD
BYTESWAP
D[15:8]
Hi-Z
Hi-Z
HIGH BYTE
LOW BYTE
239116 F11
t
17
t
17
t
18
Figure 11. 8-Sit Parallel ꢁnterface Using the SYTELWAP Pin
239116f
ꢀꢆ
LTC2391-16
APPLICATIONs INFOrmATION
RD = 0
SCLK STARTS LOW
t
15
CS
BUSY
t
8
t
10
t
9
SCLK
1
2
3
4
15
16
17
18
t
13
Hi-Z
SDOUT
(ADC 2)
D15
D14
D13
D1
D0
X15
X14
t
t
12
14
t
11
SDIN
(ADC 2)
X15
X14
X13
X1
X0
RD = 0
SCLK STARTS HIGH
CS
BUSY
t
8
t
10
t
9
SCLK
1
2
3
4
15
16
17
18
t
13
Hi-Z
SDOUT
(ADC 2)
D15
D14
D13
D1
D0
X15
X14
t
12
t
14
t
11
SDIN
(ADC 2)
X15
X14
X13
X1
X0
CNVST IN
CS IN
RD IN
SCLK IN
LTC2391-16
LTC2391-16
CNVST
CNVST
CS
CS
RD
SCLK
SDIN SDOUT
RD
SCLK
SDIN SDOUT
DATA OUT
239116 F12
ADC 1
ADC 2
Figure 12. Lerial ꢁnterface with Eꢃternal Clock. Read After
the Conversion. Daisy-Chain (ultiple Converters
239116f
ꢀꢇ
LTC2391-16
APPLICATIONs INFOrmATION
t
7
RESET
t
ACQ
CVNST
Hi-Z
DATA BUS D[15:0]
239116 F13
Figure 13. RELET Pin Timing
239116f
ꢀꢈ
LTC2391-16
APPLICATIONs INFOrmATION
SOARD ꢀAYOUT
Recommended ꢀayout
To obtain the best performance from the LTC2391-16, a
printed circuit board (PCB) is recommended. Layout for
the printed circuit board should ensure the digital and
analog signal lines are separated as much as possible.
In particular, care should be taken not to run any digital
clocks or signals alongside analog signals or underneath
the ADC.
ThefollowingisanexampleofarecommendedPCBlayout.
A single solid ground plane is used. Bypass capacitors to
the supplies are placed as close as possible to the supply
pins. Low impedance common returns for these bypass
capacitors are essential to the low noise operation of the
ADC. The analog input traces are screened by ground.
For more details and information refer to DC15ꢀꢀA, the
evaluation kit for the LTC2391-16
Partial Lchematic of Demoboard
C36
1µF
CNVST
34
39
38
37
CNVST
REFSENSE
REFIN
REFOUT
R2
249Ω
1%
29
28
27
26
25
24
23
22
21
16
15
14
13
12
11
10
9
BUSY
D15
D14
D13
D12
BUSY
D15
43
D14
+
IN
D13
D12
C54
OPT
D11/SCLK
D11/SCLK
D10/SDOUT
D9/SDIN
D8
D10/SDOUT
D9/SDIN
D8
C2
D7
D7
LTC2391-16
2200pF
1206 NPO
D6
D6
D5
D5
D4
D4
R3
249Ω
1%
D3
D3
D2
D1
D2
D1
44
–
IN
D0
D0
8
C55
OPT
BYTESWAP
GND
7
VCM OB/2C GND SER/PAR RESET PD CS RD
36
6
5
4
32 33
31 30
C53
10µF
C31
0.1µF
C30
10µF
C29
0.1µF
C28
10µF
R24
1.0Ω
3.3V
5V
C40
4.7µF
47
46 45 40
2
19
3
18
AVP/AVL AVP AVP AVP AVP
DVP DVP/DVL OVP
LTC2391-16
GND GND GND GND GND GND OGND
48 44 41 35 20 17
239116 TA02
1
239116f
ꢁ0
LTC2391-16
APPLICATIONs INFOrmATION
Partial Top Lilkscreen
Partial ꢀayer 1 Component Lide
Partial ꢀayer 2 Ground Plane
239116f
ꢁꢀ
LTC2391-16
PACkAge DesCrIPTION
UK Package
48-ꢀead Plastic QFI ꢂ7mm × 7mmx
(Reference LTC DWG # ꢀ5-ꢀ8-17ꢀ±)
0.70 p0.05
5.15 p 0.05
5.50 REF
6.10 p0.05 7.50 p0.05
(4 SIDES)
5.15 p 0.05
PACKAGE OUTLINE
0.25 p0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 p 0.05
R = 0.115
TYP
7.00 p 0.10
(4 SIDES)
R = 0.10
TYP
47 48
0.40 p 0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1
CHAMFER
C = 0.35
5.15 p 0.10
5.50 REF
(4-SIDES)
5.15 p 0.10
(UK48) QFN 0406 REV C
0.200 REF
0.25 p 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
239116f
ꢁꢁ
LTC2391-16
PACkAge DesCrIPTION
ꢀX Package
48-ꢀead Plastic ꢀQFP ꢂ7mm × 7mmx
(Reference LTC DWG # ꢀ5-ꢀ8-176ꢀ Rev Ø)
7.15 – 7.25
5.50 REF
9.00 BSC
7.00 BSC
48
48
1
2
SEE NOTE: 4
1
2
0.50 BSC
9.00 BSC
7.00 BSC
5.50 REF
7.15 – 7.25
0.20 – 0.30
A
A
PACKAGE OUTLINE
C0.30 – 0.50
1.30 MIN
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
1.60
11° – 13°
1.35 – 1.45 MAX
R0.08 – 0.20
GAUGE PLANE
0.25
0° – 7°
11° – 13°
1.00 REF
0.50
BSC
0.09 – 0.20
0.17 – 0.27
0.05 – 0.15
LX48 LQFP 0907 REVØ
0.45 – 0.75
SECTION A – A
NOTE:
1. PACKAGE DIMENSIONS CONFORM TO JEDEC #MS-026 PACKAGE OUTLINE
2. DIMENSIONS ARE IN MILLIMETERS
4. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER
5. DRAWING IS NOT TO SCALE
3. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT
239116f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ꢁꢂ
LTC2391-16
TYPICAL APPLICATION
ADC Driver: Lingle-Ended ꢁnput to Differential Output
5V
249Ω
0.1µF
V
IN
+
5V
+
+
0V to 4V –
IN1
+
–
SHDN
V
OUT2
–
A
IN
2200pF
LTC2391-16
+
–
+
LT6350
A
IN
–
+
–
V
OUT1
249Ω
IN2
IN1
239116 TA03
0.1µF
–5V
0.1µF
499Ω
2V
reLATeD PArTs
PART IU(SER
DELCRꢁPTꢁOI
CO((EITL
LTC1±11
1±-Bit 2.5Msps Parallel ADC
5V Supply, 1-Channel, 8ꢀdB SNR, ±1.8V Input Range,
SSOP-36 Package
LTC16ꢀ9
16-Bit 2ꢀꢀksps Serial ADC
5V Supply, 1-Channel, 87dB SNR, Resistor-Selectable Inputs:
±1ꢀV, ±5V, ±3.3V, ꢀV to ±V, ꢀV to 5V, ꢀV to 1ꢀV
LTC186±
LTC186±L
LTC1865
LTC1865L
LTC1867
16-Bit 25ꢀksps Serial ADC
16-Bit 15ꢀksps Serial ADC
16-Bit 25ꢀksps Serial ADC
16-Bit 15ꢀksps Serial ADC
5V Supply, 1-Channel, ±.3mW, MSOP-8 Package
3V Supply, 1-Channel, 1.3mW, MSOP-8 Package
5V Supply, 2-Channel, ±.3mW, MSOP-8 Package
3V Supply, 2-Channel, 1.3mW, MSOP-8 Package
16-Bit, 2ꢀꢀksps 8-Channel ADC
5V Supply, 6.5mW, SSOP-16 Package, Pin Compatible with
LTC1863, LTC1867L
LTC2355-1±ꢁLTC2356-1±
LTC2392-16
1±-Bit, 3.5Msps Serial ADCs
3.3V Supply, 1-Channel, 18mW, MSOP-1ꢀ Package
16-Bit, 5ꢀꢀksps ParallelꢁSerial ADC
16-Bit, 1Msps ParallelꢁSerial ADC
5V Supply, Differential Input, 9±dB SNR, ±±.ꢀ96V Input Range,
Pin Compatible with the LTC2393-16, LTC2391-16
LTC2393-16
5V Supply, Differential Input, 9±dB SNR, ±±.ꢀ96V Input Range,
Pin Compatible with the LTC2392-16, LTC2391-16
DACs
LTC26±1
LTC263ꢀ
References
LT1236
16-Bit Single Serial V
DACs
DACs
±1LSB INL, ±1LSB DNL, MSOP-8 Package, ꢀV to 5V Output
SC7ꢀ 6-Pin Package, Internal Reference, ±1LSB INL (12 Bits)
OUT
12-ꢁ1ꢀ-ꢁ8-Bit Single V
OUT
Precision Reference in SO-8 Package
ꢀ.25ppm Noise, Low Drift Precision Reference
5V, 1ꢀV; ꢀ.ꢀ5% Initial Accuracy (Max); 5ppm Tempco (Max)
ꢀ.ꢀ25% Initial Accuracy (Max), 2ppm Tempco (Max),
LTC6655
P-P
ꢀ.25ppm Noise (ꢀ.1Hz to 1ꢀHz) in MSOP-8 Package
P-P
Amplifiers
LT1±69
125mV (Max) Input Offset Voltage, Low Distortion: –96.5dB at
Dual 9ꢀMHz, 22Vꢁµs Dual Op Amps in ±mm × ±mm
DFN-12 Package
1ꢀꢀkHz, 1ꢀV , Settling Time: 9ꢀꢀns
P-P
LT18ꢀ6ꢁLT18ꢀ7
325MHz, SingleꢁDual Precision Op Amps in TSOT23-6,
MSOP-8 Packages
Rail-to-Rail Input and Output, Low Distortion, –8ꢀdBc at 5MHz,
Low Voltage Noise: 3.5nVꢁ√Hz
LTC62ꢀꢀꢁLTC62ꢀꢀ-5ꢁ
LTC62ꢀꢀ-1ꢀ
165MHzꢁ8ꢀꢀMHzꢁ1.6GHz Op Amps with
Unity GainꢁAV = 5ꢁAV = 1ꢀ
Low Noise Voltage: ꢀ.95nVꢁ√Hz (1ꢀꢀkHz), Low Distortion:
–8ꢀdB at 1MHz, TSOT23-6 Package
LT635ꢀ
Low Noise Single-Ended-to-Differential ADC Driver
Rail-to-Rail Input and Outputs, 2±ꢀns ꢀ.ꢀ1% Settling Time
239116f
LT 0210 • PRINTED IN USA
Linear Technology Corporation
163ꢀ McCarthy Blvd., Milpitas, CA 95ꢀ35-7±17
ꢁꢃ
●
●
LINEAR TECHNOLOGY CORPORATION 2010
(±ꢀ8) ±32-19ꢀꢀ FAX: (±ꢀ8) ±3±-ꢀ5ꢀ7 www.linear.com
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