LTC2413IGN_技术文档

LTC2413

24-Bit No Latency ∆Σ^TMADC,

with Simultaneous 50Hz/60Hz Rejection

U

DESCRIPTIO

FEATURES

The LTC^®2413 is a 2.7V to 5.5V simultaneous 50Hz/60Hz

rejection micropower 24-bit differential ∆Σ analog to

digital converter with an integrated oscillator, 2ppm INL

and 0.16ppm RMS noise. It uses delta-sigma technology

and provides single cycle settling time for multiplexed

applications. Through a single pin, the LTC2413 can be

configured for better than 87dB input differential mode

rejection over the range of 49Hz to 61.2Hz (50Hz and

60Hz ±2% simultaneously), or it can be driven by an

external oscillator for a user defined rejection frequency.

The internal oscillator requires no external frequency

setting components.

■

Simultaneous 50Hz/60Hz Rejection

(87dB Minimum)

Differential Input and Differential Reference with

GND to V_CCCommon Mode Range

2ppm INL and No Missing Codes at 24 Bits

0.1ppm Offset and 2.5ppm Full-Scale Error

0.16ppm Noise

No Latency: Digital Filter Settles in a Single Cycle.

Internal Oscillator—No External Components

Required

24-Bit ADC in Narrow SSOP-16 Package

(SO-8 Footprint)

■

Single Supply 2.7V to 5.5V Operation

Low Supply Current (200µA) and Auto Shutdown

Pin Compatible with LTC2410

The converter accepts any external differential reference

voltage from 0.1V to V_CCfor flexible ratiometric and

remote sensing measurement configurations. The full-

U

scale differential input range is from –0.5V_REFto 0.5V_REF

.

APPLICATIO S

The reference common mode voltage, V_REFCM, and the

input common mode voltage, V_INCM, may be indepen-

dently set anywhere within the GND to V_CCrange of the

LTC2413. The DC common mode input rejection is better

than 140dB.

■

Direct Sensor Digitizer

■

Weight Scales

■

Direct Temperature Measurement

Gas Analyzers

Strain-Gauge Transducers

■

The LTC2413 communicates through a flexible 3-wire

digital interface which is compatible with SPI and

MICROWIRE^TMprotocols.

■

Instrumentation

Data Acquisition

Industrial Process Control

6-Digit DVMs

■

, LTC and LT are registered trademarks of Linear Technology Corporation.

No Latency ∆Σ is a trademark of Linear Technology Corporation.

MICROWIRE is a trademark of National Semiconductor Corporation.

■

Products for International Markets

U

TYPICAL APPLICATIO

Measured Noise Rejection from 48Hz to 62.5Hz

–80

MEASURED DATA

CALCULATED DATA

–85

–90

2.7V TO 5.5V

V

= 5V

1µF

CC

+

REF = 5V

REF = GND

= EXTERNAL CLOCK SOURCE

= INTERNAL OSC/

2

14

13

–

V

F

O

CC

LTC2413

–95

SIMULTANEOUS 50Hz/60Hz REJECTION

V

= 2.5V

INCM

–100

–105

–110

–115

–120

= 5V

IN(P-P)

3

4

T = 25°C

A

+

REFERENCE

VOLTAGE

REF

SCK

–

0.1V TO V

CC

3-WIRE

SPI INTERFACE

5

6

12

11

+

ANALOG INPUT RANGE

–0.5V TO 0.5V

IN

SDO

CS

REF

–

IN

1, 7, 8, 9, 10, 15, 16

GND

48

50

52

54

56

58

60

62

2413 TA01

INPUT FREQUENCY (Hz)

2413 TA02

sn2413 2413fs

1

LTC2413

W W U W

U

W

U

ABSOLUTE AXI U RATI GS

PACKAGE/ORDER I FOR ATIO

(Notes 1, 2)

TOP VIEW

ORDER PART NUMBER

Supply Voltage (V_CC) to GND.......................–0.3V to 7V

Analog Input Pins Voltage

to GND.................................... –0.3V to (V_CC+ 0.3V)

Reference Input Pins Voltage

to GND.................................... –0.3V to (V_CC+ 0.3V)

Digital Input Voltage to GND........ –0.3V to (V_CC+ 0.3V)

Digital Output Voltage to GND ..... –0.3V to (V_CC+ 0.3V)

Operating Temperature Range

LTC2413C ............................................... 0°C to 70°C

LTC2413I............................................ –40°C to 85°C

Storage Temperature Range ................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec).................. 300°C

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GND

V

CC

LTC2413CGN

LTC2413IGN

+

F

O

REF

–

SCK

SDO

CS

REF

+

IN

GN PART MARKING

–

IN

GND

2413

2413I

GN PACKAGE

16-LEAD PLASTIC SSOP

T_JMAX= 125°C, θ_JA= 95°C/W

Consult factory for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Notes 3, 4)

PARAMETER

CONDITIONS

≤ V , –0.5 • V ≤ V ≤ 0.5 • V , (Note 5)

MIN

TYP

MAX

UNITS

Resolution (No Missing Codes) 0.1V ≤ V

●

24

Bits

REF

CC

REF

IN

REF

+

–

Integral Nonlinearity

4.5V ≤ V ≤ 5.5V, REF = 2.5V, REF = GND, V

= 1.25V, (Note 6)

= 2.5V, (Note 6)

1

2

5

ppm of V

CC

INCM

REF

+

–

5V ≤ V ≤ 5.5V, REF = 5V, REF = GND, V

REF = 2.5V, REF = GND, V

14

CC

INCM

+

–

= 1.25V, (Note 6)

INCM

+

–

Offset Error

2.5V ≤ REF ≤ V , REF = GND,

0.5

2.5

µV

CC

+

–

GND ≤ IN = IN ≤ V , (Note 13)

CC

+

–

Offset Error Drift

2.5V ≤ REF ≤ V , REF = GND,

10

nV/°C

ppm of V

CC

+

–

GND ≤ IN = IN ≤ V

CC

+

–

Positive Full-Scale Error

Positive Full-Scale Error Drift

Negative Full-Scale Error

Negative Full-Scale Error Drift

Total Unadjusted Error

2.5V ≤ REF ≤ V , REF = GND,

●

2.5

12

CC

REF

+

–

+

IN = 0.75 • REF , IN = 0.25 • REF

+

–

2.5V ≤ REF ≤ V , REF = GND,

0.03

2.5

ppm of V /°C

REF

CC

+

–

+

IN = 0.75 • REF , IN = 0.25 • REF

+

–

2.5V ≤ REF ≤ V , REF = GND,

ppm of V

REF

CC

+

–

IN = 0.25 • REF , IN = 0.75 • REF

+

–

2.5V ≤ REF ≤ V , REF = GND,

0.03

ppm of V /°C

REF

CC

+

–

IN = 0.25 • REF , IN = 0.75 • REF

+

–

4.5V ≤ V ≤ 5.5V, REF = 2.5V, REF = GND, V

5V ≤ V ≤ 5.5V, REF = 5V, REF = GND, V

REF = 2.5V, REF = GND, V

= 1.25V

= 2.5V

3

4

ppm of V

CC

INCM

REF

+

–

CC

INCM

+

–

= 1.25V

INCM

+

Output Noise

5V ≤ V ≤ 5.5V, REF = 5V, V – = GND,

0.8

µV

RMS

CC

REF

–

+

GND ≤ IN = IN ≤ 5V, (Note 12)

sn2413 2413fs

2

LTC2413

U

CO VERTER CHARACTERISTICS

The ● denotes specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Notes 3, 4)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

–

Input Common Mode Rejection DC 2.5V ≤ REF ≤ V , REF = GND,

●

130

140

dB

CC

–

+

GND ≤ IN = IN ≤ V

CC

+

–

Input Common Mode Rejection

49Hz to 61.2Hz

2.5V ≤ REF ≤ V , REF = GND,

140

87

dB

CC

–

+

GND ≤ IN = IN ≤ V , (Note 7)

CC

Input Normal Mode Rejection

49Hz to 61.2Hz

(Note 7)

Input Normal Mode Rejection

External Oscillator

87

External Clock f

/2560 ±14%

EOSC

Input Normal Mode Rejection

External Clock f /2560 ±4%

110

130

140

EOSC

+

–

Reference Common Mode

Rejection DC

2.5V ≤ REF ≤ V , GND ≤ REF ≤ 2.5V,

CC

–

+

V

= 2.5V, IN = IN = GND

REF

+

–

+

Power Supply Rejection, DC

REF = 2.5V, REF = GND, IN = IN = GND

120

dB

+

–

Power Supply Rejection

Simultaneous 50Hz/60Hz ±2%

REF = 2.5V, REF = GND,

–

+

IN = IN = GND, (Note 7)

U

A ALOG I PUT A D REFERE CE _{The ● denotes specifications which apply over the full operating}

temperature range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

IN

Absolute/Common Mode IN Voltage

●

GND – 0.3V

V

+ 0.3V

V

CC

–

IN

Absolute/Common Mode IN Voltage

+ 0.3V

/2

V

Input Differential Voltage Range

–V /2

REF

V

IN

REF

+

–

(IN – IN )

+

–

+

REF

Absolute/Common Mode REF Voltage

●

0.1

GND

0.1

V

CC

–

Absolute/Common Mode REF Voltage

V

– 0.1V

CC

V

Reference Differential Voltage Range

V

CC

REF

+

–

(REF – REF )

+

C (IN )

IN Sampling Capacitance

18

1

pF

nA

S

–

C (IN )

IN Sampling Capacitance

S

+

C (REF )

REF Sampling Capacitance

S

–

C (REF )

REF Sampling Capacitance

S

+

I

(IN )

IN DC Leakage Current

CS = V , IN = GND

●

–10

10

DC_LEAK

CC

–

(IN )

IN DC Leakage Current

CS = V , IN = GND

1

10

CC

+

(REF )

REF DC Leakage Current

CS = V , REF = 5V

1

CC

–

(REF )

REF DC Leakage Current

CS = V , REF = GND

1

CC

sn2413 2413fs

3

LTC2413

U

DIGITAL I PUTS A D DIGITAL OUTPUTS

The ● denotes specifications which apply over the full

operating temperature range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

2.7V ≤ V ≤ 5.5V

MIN

TYP

MAX

UNITS

V

IH

V

IL

V

IH

V

IL

High Level Input Voltage

●

2.5

2.0

V

CC

CS, F

2.7V ≤ V ≤ 3.3V

O

CC

Low Level Input Voltage

CS, F

4.5V ≤ V ≤ 5.5V

0.8

0.6

V

CC

2.7V ≤ V ≤ 5.5V

O

CC

High Level Input Voltage

SCK

2.7V ≤ V ≤ 5.5V (Note 8)

2.5

2.0

V

CC

2.7V ≤ V ≤ 3.3V (Note 8)

CC

Low Level Input Voltage

SCK

4.5V ≤ V ≤ 5.5V (Note 8)

0.8

0.6

V

CC

2.7V ≤ V ≤ 5.5V (Note 8)

CC

I

Digital Input Current

0V ≤ V ≤ V

CC

–10

10

µA

pF

V

IN

CS, F

O

Digital Input Current

SCK

0V ≤ V ≤ V (Note 8)

10

IN

CC

C

V

Digital Input Capacitance

10

IN

CS, F

O

Digital Input Capacitance

SCK

(Note 8)

IN

High Level Output Voltage

SDO

I = –800µA

O

●

V

– 0.5V

OH

OL

OH

OL

CC

Low Level Output Voltage

SDO

I = 1.6mA

O

0.4

V

High Level Output Voltage

SCK

I = –800µA (Note 9)

O

V

Low Level Output Voltage

SCK

I = 1.6mA (Note 9)

O

0.4

10

V

I

Hi-Z Output Leakage

SDO

–10

µA

OZ

W U

POWER REQUIRE E TS

The ● denotes specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

Supply Voltage

Supply Current

CONDITIONS

MIN

TYP

MAX

UNITS

V

CC

●

2.7

5.5

V

I

CC

Conversion Mode

Sleep Mode

CS = 0V (Note 11)

●

200

20

300

30

µA

CS = V (Note 11)

CC

sn2413 2413fs

4

LTC2413

W U

TI I G CHARACTERISTICS

The ● denotes specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 3)

SYMBOL

PARAMETER

CONDITIONS

MIN

2.56

0.25

TYP

MAX

2000

390

UNITS

kHz

µs

f

t

External Oscillator Frequency Range

External Oscillator High Period

External Oscillator Low Period

Conversion Time

●

EOSC

HEO

390

µs

LEO

F = 0V

●

146.71

EOSC

ms

CONV

O

External Oscillator (Note 10)

20510/f

(in kHz)

f

Internal SCK Frequency

Internal Oscillator (Note 9)

External Oscillator (Notes 9, 10)

17.5

kHz

ISCK

f

/8

EOSC

D

Internal SCK Duty Cycle

(Note 9)

(Note 8)

●

45

55

%

kHz

ns

ISCK

f

t

External SCK Frequency Range

External SCK Low Period

2000

ESCK

250

1.80

LESCK

External SCK High Period

ns

HESCK

DOUT_ISCK

Internal SCK 32-Bit Data Output Time

Internal Oscillator (Notes 9, 11)

External Oscillator (Notes 9, 10)

●

1.83

1.86

ms

256/f

(in kHz)

EOSC

t

External SCK 32-Bit Data Output Time

CS ↓ to SDO Low Z

CS ↑ to SDO Hi-Z

(Note 8)

●

32/f

(in kHz)

ms

ns

DOUT_ESCK

1

ESCK

0

200

t2

t3

t4

CS ↓ to SCK ↓

(Note 9)

(Note 8)

0

CS ↓ to SCK ↑

50

t

SCK ↓ to SDO Valid

SDO Hold After SCK ↓

SCK Set-Up Before CS ↓

SCK Hold After CS ↓

220

50

KQMAX

KQMIN

(Note 5)

15

50

t

5

6

Note 1: Absolute Maximum Ratings are those values beyond which the

life of the device may be impaired.

Note 7: F_O= 0V (internal oscillator) or f_EOSC= 139800Hz ±2%

(external oscillator).

Note 2: All voltage values are with respect to GND.

Note 8: The converter is in external SCK mode of operation such that

the SCK pin is used as digital input. The frequency of the clock signal

driving SCK during the data output is f_ESCKand is expressed in kHz.

Note 3: V_CC= 2.7V to 5.5V unless otherwise specified.

V_REF= REF⁺– REF^–, V_REFCM= (REF⁺+ REF^–)/2;

V

_IN= IN⁺– IN^–, V_INCM= (IN⁺+ IN^–)/2.

Note 9: The converter is in internal SCK mode of operation such that

the SCK pin is used as digital output.

Note 10: The external oscillator is connected to the F_Opin. The external

Note 4: F_Opin tied to GND or to external conversion clock source with

_EOSC= 139800Hz unless otherwise specified.

f

oscillator frequency, f_EOSC, is expressed in kHz.

Note 5: Guaranteed by design, not subject to test.

Note 11: The converter uses the internal oscillator. F_O= 0V.

Note 12: The output noise includes the contribution of the internal

calibration operations.

Note 13: Guaranteed by design and test correlation.

Note 6: Integral nonlinearity is defined as the deviation of a code from

a straight line passing through the actual endpoints of the transfer

curve. The deviation is measured from the center of the quantization

band.

sn2413 2413fs

5

LTC2413

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Total Unadjusted Error vs

Temperature (V_CC= 5V,

Total Unadjusted Error vs

Temperature (V_CC= 5V,

V_REF= 2.5V)

Total Unadjusted Error vs

Temperature (V_CC= 2.7V,

V_REF= 2.5V)

V_REF= 5V)

1.5

1.0

1.5

1.0

10

8

V

= 5V

CC

+

REF = 2.5V

–

REF = GND

6

V

= 2.5V

INCM

= GND

REF

4

T

= 90°C

= 1.25V

A

0.5

F

O

2

T = 25°C

A

T

= 90°C

= 25°C

= –45°C

0

A

0

V

= 5V

T

= 90°C

= 25°C

–2

–4

–6

–8

–10

CC

A

+

V

= 2.7V

CC

REF = 5V

–0.5

–1.0

–1.5

–0.5

–1.0

–1.5

+

–

REF = 2.5V

REF = GND

A

–

REF = GND

V

F

= 5V

REF

INCM

O

T

= –45°C

V

= 2.5V

INCM

= GND

A

REF

= 2.5V

T

= –45°C

A

= 1.25V

= GND

F

O

–2.5 –2 –1.5 –1 –0.5

V

0

0.5

1

1.5

2

2.5

–1

–0.5

0

0.5

1

–1

–0.5

0

0.5

1

(V)

V

(V)

V

(V)

IN

2413 G01

2413 G02

2413 G03

Integral Nonlinearity vs

Temperature (V_CC= 5V,

V_REF= 2.5V)

Integral Nonlinearity vs

Temperature (V_CC= 5V,

V_REF= 5V)

Integral Nonlinearity vs

Temperature (V_CC= 2.7V,

V_REF= 2.5V)

1.5

1.0

1.5

1.0

10

8

V

= 2.7V

V

F

= 2.5V

REF

CC

V

= 5V

+

CC

T

= –45°C

REF = 2.5V

= 1.25V

A

+

INCM

REF = 5V

–

REF = GND

= GND

–

O

REF = GND

6

T

= –45°C

= 25°C

A

T

= 25°C

A

V

O

= 5V

REF

INCM

T

4

A

= 2.5V

0.5

F

= GND

T

= 90°C

2

A

0

T

A

= 90°C

V

= 5V

–2

–4

–6

–8

–10

CC

+

T

= 90°C

= 25°C

REF = 2.5V

A

–0.5

–1.0

–1.5

–0.5

–1.0

–1.5

–

REF = GND

T

V

F

= 2.5V

INCM

= GND

REF

= 1.25V

= –45°C

A

O

–2.5 –2 –1.5 –1 –0.5

V

0

0.5

1

1.5

2

2.5

–1

–0.5

0

0.5

1

–1

–0.5

0

0.5

1

(V)

V

(V)

V

(V)

IN

2413 G04

2413 G05

2413 G06

Noise Histogram (Output Rate =

6.83Hz, V_CC= 5V, V_REF= 5V)

Noise Histogram (Output Rate =

22.5Hz, V_CC= 5V, V_REF= 5V)

Noise Histogram (Output Rate =

52.5Hz, V_CC= 5V, V_REF= 5V)

12

10

8

12

10

8

12

10

8

10,000 CONSECUTIVE

READINGS

GAUSSIAN

10,000 CONSECUTIVE

READINGS

GAUSSIAN

10,000 CONSECUTIVE

READINGS

GAUSSIAN

DISTRIBUTION

m = 0.105ppm

σ = 0.153ppm

DISTRIBUTION

m = 0.067ppm

σ = 0.151ppm

DISTRIBUTION

m = 8.285ppm

σ = 0.311ppm

V

= 5V

V

= 5V

V

= 5V

CC

REF

IN

CC

REF

IN

CC

REF

= 5V

= 0V

IN

+

–

REF = 5V

–

REF = GND

+

–

+

–

+

–

IN = 2.5V

6

IN = 2.5V

F

= GND

= 25°C

F

= 460800Hz

= 25°C

F = 1075200Hz

O

T

T = 25°C

A

4

2

0

–0.8 –0.6 –0.4 –0.2

0

0.2 0.4 0.6 0.8

–0.8 –0.6 –0.4 –0.2

0

0.2 0.4 0.6 0.8

–9.8 –9.4 –9 –8.6 –8.2 –7.8 –7.4 –7 –6.6

OUTPUT CODE (ppm OF V

)

OUTPUT CODE (ppm OF V

)

OUTPUT CODE (ppm OF V

)

REF

sn2413 2413fs

2413 G07

2413 G08

2413 G09

6

LTC2413

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Noise Histogram (Output Rate =

6.83Hz V_CC= 5V, V_REF= 2.5V)

Noise Histogram (Output Rate =

22.5Hz, V_CC= 5V, V_REF= 2.5V)

Noise Histogram (Output Rate =

52.5Hz, V_CC= 5V, V_REF= 2.5V)

12

10

8

12

10

8

12

10

8

10,000 CONSECUTIVE

READINGS

GAUSSIAN

10,000 CONSECUTIVE

READINGS

GAUSSIAN

10,000 CONSECUTIVE

READINGS

GAUSSIAN

DISTRIBUTION

m = 0.033ppm

σ = 0.293ppm

DISTRIBUTION

m = 0.014ppm

σ = 0.292ppm

DISTRIBUTION

m = 3.852ppm

σ = 0.326ppm

V

= 5V

V

= 5V

V

= 5V

CC

REF

IN

CC

REF

IN

CC

REF

= 2.5V

= 0V

IN

+

–

REF = 2.5V

–

REF = GND

+

–

+

–

+

–

IN = 1.25V

6

IN = 1.25V

F

= GND

= 25°C

F

= 460800Hz

= 25°C

F = 1075200Hz

O

T

T = 25°C

A

4

2

0

–1.6

–0.8

0

0.8

1.6

–1.6 –1.2 –0.8 –0.4

0

0.4 0.8 1.2 1.6

–5.5 –5.1 –4.7 –4.3 –3.9 –3.5 –3.1 –2.7 –2.3

OUTPUT CODE (ppm OF V

)

OUTPUT CODE (ppm OF V

)

OUTPUT CODE (ppm OF V

)

REF

2413 G10

2413 G11

2413 G12

Noise Histogram (Output Rate =

22.5Hz, V_CC= 2.7V, V_REF= 2.5V)

Noise Histogram (Output Rate =

6.83Hz V_CC= 2.7V, V_REF= 2.5V)

Noise Histogram (Output Rate =

52.5Hz, V_CC= 2.7V, V_REF= 2.5V)

12

10

8

12

10

8

10

9

8

7

6

5

4

3

2

1

0

10,000 CONSECUTIVE

READINGS

GAUSSIAN

10,000 CONSECUTIVE

READINGS

GAUSSIAN

10,000 CONSECUTIVE

READINGS

GAUSSIAN

DISTRIBUTION

m = 0.079ppm

σ = 0.298ppm

DISTRIBUTION

m = 0.177ppm

σ = 0.297ppm

DISTRIBUTION

m = 3.714ppm

σ = 1.295ppm

V

= 2.7V

V

= 2.7V

V

= 2.7V

CC

REF

IN

CC

REF

IN

CC

REF

= 2.5V

= 0V

IN

+

–

REF = 2.5V

–

REF = GND

+

–

+

–

+

–

IN = 1.25V

6

IN = 1.25V

F

= GND

= 25°C

F

= 460800Hz

= 25°C

F = 1075200Hz

O

A

O

A

O

T

T = 25°C

A

4

2

0

–1.6 –1.2 –0.8 –0.4

0

0.4 0.8 1.2 1.6

–1.6 –1.2 –0.8 –0.4

0

0.4 0.8 1.2 1.6

–10 –8.5 –7 –5.5 –4 –2.5 –1 0.5

OUTPUT CODE (ppm OF V

2

OUTPUT CODE (ppm OF V

)

OUTPUT CODE (ppm OF V

)

REF

2413 G13

2413 G14

2413 G15

Long-Term Noise Histogram

(Time = 60 Hrs, V_CC= 5V,

V_REF= 5V)

Consecutive ADC Readings vs

Time

RMS Noise vs Input Differential

Voltage

12

10

8

1.0

0.8

0.5

0.4

0.3

0.2

0.1

0

GAUSSIAN DISTRIBUTION

m = 0.101837ppm

V

= 5V

CC

= 5V

REF

σ = 0.154515ppm

+

REF = 5V

0.6

–

REF = GND

0.4

ADC CONSECUTIVE

READINGS

V

= 2.5V

= GND

= 25°C

INCM

F

O

0.2

V

= 5V

T

CC

REF

IN

A

6

0

= 0V

+

–0.2

–0.4

–0.6

–0.8

–1.0

REF = 5V

–

4

REF = GND

+

–

IN = 2.5V

+

–

V

= 5V

T = 25°C

A

IN = 2.5V

CC

IN = 2.5V

+

= 5V REF = 5V IN = 2.5V

2

REF

F

= GND

= 25°C

–

O

A

= 0V REF = GND

IN

T

F

= GND

O

0

–0.8 –0.6 –0.4 –0.2

0

0.2 0.4 0.6 0.8

0

5

10 15 20 25 30 35 40 45 50 55 60

TIME (HOURS)

–2.5 –2 –1.5 –1 –0.5

0

0.5

1

1.5

2

2.5

OUTPUT CODE (ppm OF V

)

INPUT DIFFERENTIAL VOLTAGE (V)

REF

2413 G16

2413 G17

sn241²3⁴¹2³4^G11⁸3fs

7

LTC2413

U W

TYPICAL PERFOR A CE CHARACTERISTICS

RMS Noise vs V_INCM

RMS Noise vs Temperature (T_A)

RMS Noise vs V_CC

850

825

800

775

750

725

700

675

650

850

825

800

775

750

725

700

675

650

850

825

800

775

750

725

700

675

650

+

–

REF = 2.5V

V

= 5V

CC

+

REF = GND

REF = 5V

–

V

= 2.5V

REF

REF = GND

+

–

IN = GND

IN = 2.5V

–

IN = GND

IN = 2.5V

F

= GND

O

A

V

F

= 0V

= GND

IN

O

T

= 25°C

V

= 5V

CC

+

REF = 5V

–

REF = GND

V

= 5V

REF

+

–

IN = V

INCM

IN = V

V

= 0V

IN

F

= GND

O

T

= 25°C

A

–0.5 0 0.5

1

1.5

2

2.5

3

(V)

3.5

4

4.5

5

5.5

–50

–25

0

25

50

75

100

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

(V)

V

INCM

TEMPERATURE (°C)

V

CC

2413 G19

2413 G20

2413 G21

Offset Error vs V_INCM

RMS Noise vs V_REF

Offset Error vs Temperature (T_A)

850

825

800

775

750

725

700

675

650

0.3

0.2

0.3

0.2

V

= 5V

CC

–

REF = GND

+

–

IN = GND

F

= GND

= 25°C

O

A

0.1

T

V

= 5V

CC

+

REF = 5V

0

–

V

= 5V

REF = GND

CC

+

REF = 5V

V

= 5V

REF

–

+

–

REF = GND

IN = V

–0.1

–0.2

–0.3

–0.1

–0.2

–0.3

INCM

+

–

IN = 2.5V

IN = V

IN = 2.5V

V

F

A

= 0V

IN

O

V

F

= 0V

= GND

IN

O

T

= 25°C

0

0.5

1

1.5

2

V

2.5

(V)

3

3.5

4

4.5

5

–0.5 0 0.5

1

1.5

2

2.5

3

(V)

3.5

4

4.5

5

5.5

–50

–25

0

25

50

75

100

V

INCM

TEMPERATURE (°C)

REF

2413 G22

2413 G23

2413 G24

+Full-Scale Error vs

Temperature (T_A)

Offset Error vs V_CC

Offset Error vs V_REF

0.3

0.2

0.3

0.2

3

2

1

0.1

0

+

–

REF = 2.5V

V

= 5V

V

= 5V

CC

REF = GND

CC

–

+

REF = GND

REF = 5V

V

= 2.5V

–0.1

–0.2

–0.3

–0.1

–0.2

–0.3

–1

–2

–3

REF

+

–

+

IN = GND

REF = GND

IN = GND

+

–

IN = 2.5V

IN = GND

F

= GND

= 25°C

IN = GND

F

= GND

O

A

O

A

T

F = GND

T

= 25°C

O

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

(V)

0

0.5

1

1.5

2

V

2.5

(V)

3

3.5

4

4.5

5

–45 –30 –15

0

15 30 45 60 75 90

V

CC

TEMPERATURE (°C)

REF

2413 G25

2413 G26

2413 G27

sn2413 2413fs

8

LTC2413

U W

TYPICAL PERFOR A CE CHARACTERISTICS

–Full-Scale Error vs

Temperature (T_A)

+Full-Scale Error vs V_CC

+Full-Scale Error vs V_REF

3

2

3

2

3

2

V

= 5V

CC

+

REF = 5V

–

REF = GND

+

–

IN = GND

IN = 2.5V

1

F

= GND

O

0

+

–

V

= 5V

CC

REF = 2.5V

+

REF = V

REF

REF = GND

–

REF = GND

–1

–2

–3

–1

–2

–3

–1

–2

–3

V

= 2.5V

REF

+

–

+

IN = 0.5 • REF

IN = 1.25V

–

IN = GND

F

= GND

= 25°C

O

A

F

= GND

O

A

T

= 25°C

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

(V)

0

0.5

1

1.5

2

V

2.5

(V)

3

3.5

4

4.5

5

–45 –30 –15

0

15 30 45 60 75 90

V

TEMPERATURE (°C)

CC

REF

2413 G28

2413 G29

2413 G30

–Full-Scale Error vs V_CC

PSRR vs Frequency at V_CC

–Full-Scale Error vs V_REF

3

2

3

2

0

–20

+

–

V

= 5V

V

= 4.1V ± 1.4V

REF = 2.5V

CC

CC DC

+

REF = V

REF = 2.5V

REF = GND

REF

–

REF = GND

V

= 2.5V

REF

+

–

+

–

+

IN = GND

–40

+

–

IN = 0.5 • REF

IN = GND

IN = 1.25V

1

F

= GND

= 25°C

F

= GND

F

= GND

= 25°C

O

A

O

A

–60

T

= 25°C

A

T

0

–80

–1

–2

–3

–1

–2

–3

–100

–120

–140

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5

(V)

0

0.5

1

1.5

2

V

2.5

(V)

3

3.5

4

4.5

5

0.01

0.1

1

10

100

V

FREQUENCY AT V (Hz)

CC

REF

2413 G31

2413 G32

2413 G33

PSRR vs Frequency at V_CC

0

–20

0

–20

+

–

V

= 4.1V ± 1.4V

REF = 2.5V

V

= 4.1V ± 0.7V

CC

DC

CC DC

+

REF = 2.5V

REF = GND

REF = 2.5V

–20

–40

–

+

–

REF = GND

IN = GND

REF = GND

+

–

+

–

IN = GND

–40

IN = GND

F

= GND

IN = GND

O

A

F

= GND

= 25°C

T

= 25°C

F = GND

O

A

O

–60

T

A

= 25°C

–80

–100

–120

–140

–100

–120

–140

–100

–120

–140

0

20 40 60 80 100 120 140 160 180 200 220

FREQUENCY AT V (Hz)

1

10

100

1k

10k 100k

1M

13900

13950

FREQUENCY AT V (Hz)

14000

14050

14100

FREQUENCY AT V (Hz)

CC

2413 G34

2413 G35

2413 G36

sn2413 2413fs

9

LTC2413

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Conversion Current vs

Temperature (T_A)

Conversion Current vs

Output Data Rate

Sleep Current vs Temperature (T_A)

220

210

200

190

180

170

160

1100

1000

900

800

700

600

500

400

300

200

100

23

22

21

20

19

18

17

16

F

= GND

V

= 5V

F = GND

O

CC

+

CS = GND

SCK = NC

SDO = NC

REF = 5V

CS = V

CC

–

REF = GND

SCK = NC

SDO = NC

+

–

IN = GND

V

= 5.5V

CC

IN = GND

V

= 5.5V

= 2.7V

CC

T

= 25°C

= EXTERNAL OSC

A

O

F

V

= 4.1V

CC

CS = GND

SCK = NC

SDO = NC

V

= 4.1V

= 2.7V

CC

–45 –30 –15

0

15 30 45 60 75 90

TEMPERATURE (°C)

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC) ^{2413 G38}

–45 –30 –15

0

15 30 45 60 75 90

TEMPERATURE (°C)

2413 G37

2413 G39

U

PI FU CTIO S

GND (Pins 1, 7, 8, 9, 10, 15, 16): Ground. Multiple ground

pins internally connected for optimum ground current flow

and V_CCdecoupling. Connect each one of these pins to a

groundplanethroughalowimpedanceconnection.Allseven

pins must be connected to ground for proper operation.

SDO (Pin 12): Three-State Digital Output. During the Data

Output period, this pin is used as serial data output. When

the chip select CS is HIGH (CS = V_CC), the SDO pin is in a

high impedance state. During the Conversion and Sleep

periods, this pin is used as the conversion status output.

TheconversionstatuscanbeobservedbypullingCSLOW.

V_CC(Pin 2): Positive Supply Voltage. Bypass to GND

(Pin 1) with a 10µF tantalum capacitor in parallel with

0.1µF ceramic capacitor as close to the part as possible.

REF⁺(Pin 3), REF^–(Pin 4): Differential Reference Input.

ThevoltageonthesepinscanhaveanyvaluebetweenGND

and V_CCas long as the reference positive input, REF⁺, is

maintained more positive than the reference negative

input, REF ^–, by at least 0.1V.

IN⁺(Pin5), IN^–(Pin6):DifferentialAnalogInput. Thevoltage

on these pins can have any value between

GND–0.3VandV_CC+0.3V.Withintheselimits, theconverter

bipolar input range (V_IN= IN⁺– IN^–) extends from –0.5 •

(V_REF) to 0.5 • (V_REF). Outside this input range, the converter

produces unique overrange and underrange output codes.

SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal

Serial Clock Operation mode, SCK is used as digital output

for the internal serial interface clock during the Data

Output period. In External Serial Clock Operation mode,

SCK is used as digital input for the external serial interface

clock during the Data Output period. A weak internal pull-

up is automatically activated in Internal Serial Clock Op-

eration mode. The Serial Clock Operation mode is deter-

mined by the logic level applied to the SCK pin at power up

or during the most recent falling edge of CS.

F_O(Pin 14): Frequency Control Pin. Digital input that

controls the ADC’s notch frequencies and conversion

time. When the F_Opin is connected to GND (F_O= 0V), the

converter uses its internal oscillator and the digital filter

rejects 50Hz and 60Hz simultaneously. When the F_Opin is

CS (Pin 11): Active LOW Digital Input. A LOW on this pin

enables the SDO digital output and wakes up the ADC.

Following each conversion, the ADC automatically enters

the Sleep mode and remains in this low power state as

long as CS is HIGH. A LOW-to-HIGH transition on CS

during the Data Output transfer aborts the data transfer

and starts a new conversion.

driven by an external clock signal with a frequency f_EOSC

,

the converter uses this signal as its system clock and the

digital filter has 87dB minimum rejection in the range

f_EOSC/2560 ±14% and 110dB minimum rejection at

f_EOSC/2560 ±4%.

sn2413 2413fs

10

LTC2413

U

W

FU CTIO AL BLOCK DIAGRA

INTERNAL

OSCILLATOR

V

CC

GND

AUTOCALIBRATION

AND CONTROL

F

O

(INT/EXT)

+

IN

+

–

∫

SDO

SERIAL

INTERFACE

∑

ADC

SCK

CS

+

REF

–

DECIMATING FIR

–

+

DAC

2413 FD

Figure 1. Functional Block Diagram

V

CC

TEST CIRCUITS

1.69k

SDO

1.69k

C

= 20pF

LOAD

C

= 20pF

LOAD

Hi-Z TO V

OH

V

OL

V

OH

TO V

Hi-Z TO V

OL

TO Hi-Z

V

TO V

2413 TA03

OH

OL

TO Hi-Z

2413 TA04

U

W U U

APPLICATIO S I FOR ATIO

CONVERTER OPERATION

CONVERT

Converter Operation Cycle

SLEEP

The LTC2413 is a low power, delta-sigma analog-to-

digitalconverterwithaneasytouse3-wireserialinterface.

Its operation is made up of three states. The converter

operating cycle begins with the conversion, followed by

the low power sleep state and ends with the data output

(see Figure 2). The 3-wire interface consists of serial data

output (SDO), serial clock (SCK) and chip select (CS).

FALSE

CS = LOW

AND

SCK

TRUE

DATA OUTPUT

2413 F02

Initially, the LTC2413 performs a conversion. Once the

conversion is complete, the device enters the sleep state.

Whileinthissleepstate,powerconsumptionisreducedby

an order of magnitude. The part remains in the sleep state

as long as CS is HIGH. The conversion result is held

indefinitely in a static shift register while the converter is

in the sleep state.

Figure 2. LTC2413 State Transition Diagram

sn2413 2413fs

11

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

Once CS is pulled LOW, the device begins outputting the

conversion result. There is no latency in the conversion

result. The data output corresponds to the conversion just

performed. This result is shifted out on the serial data out

pin (SDO) under the control of the serial clock (SCK). Data

is updated on the falling edge of SCK allowing the user to

reliably latch data on the rising edge of SCK (see Figure 3).

The data output state is concluded once 32 bits are read

out of the ADC or when CS is brought HIGH. The device

automatically initiates a new conversion and the cycle

repeats.

TheLTC2413performsoffsetandfull-scalecalibrationsin

every conversion cycle. This calibration is transparent to

the user and has no effect on the cyclic operation de-

scribed above. The advantage of continuous calibration is

extreme stability of offset and full-scale readings with re-

specttotime,supplyvoltagechangeandtemperaturedrift.

Power-Up Sequence

The LTC2413 automatically enters an internal reset state

when the power supply voltage V_CCdrops below approxi-

mately 2.2V. This feature guarantees the integrity of the

conversion result and of the serial interface mode selec-

tion. (See the 2-wire I/O sections in the Serial Interface

Timing Modes section.)

Through timing control of the CS and SCK pins, the

LTC2413 offers several flexible modes of operation

(internal or external SCK and free-running conversion

modes). These various modes do not require program-

ming configuration registers; moreover, they do not dis-

turbthecyclicoperationdescribedabove. Thesemodesof

operation are described in detail in the Serial Interface

Timing Modes section.

When the V_CCvoltage rises above this critical threshold,

the converter creates an internal power-on-reset (POR)

signal with a duration of approximately 0.5ms. The POR

signal clears all internal registers. Following the POR

signal, the LTC2413 starts a normal conversion cycle and

followsthesuccessionofstatesdescribedabove. Thefirst

conversion result following POR is accurate within the

specifications of the device if the power supply voltage is

restored within the operating range (2.7V to 5.5V) before

the end of the POR time interval.

Conversion Clock

A major advantage the delta-sigma converter offers over

conventional type converters is an on-chip digital filter

(commonlyimplementedasasincorcombfilter).Forhigh

resolution, low frequency applications, this filter is de-

signed to simultaneously reject line frequencies of 50Hz

and 60Hz plus their harmonics. The filter rejection perfor-

mance is directly related to the accuracy of the converter

system clock. The LTC2413 incorporates a highly accu-

rate on-chip oscillator. This eliminates the need for exter-

nal frequency setting components such as crystals or

oscillators. The LTC2413 achieves a minimum of 87dB

over the range of 49Hz to 61.2Hz.

Reference Voltage Range

This converter accepts a truly differential external refer-

ence voltage. The absolute/common mode voltage speci-

ficationfortheREF⁺andREF^–pinscoverstheentirerange

from GND to V_CC. For correct converter operation, the

REF⁺pin must always be more positive than the REF^–pin.

The LTC2413 can accept a differential reference voltage

from 0.1V to V_CC. The converter output noise is deter-

mined by the thermal noise of the front-end circuits, and

as such, its value in nanovolts is nearly constant with

reference voltage. A decrease in reference voltage will not

significantly improve the converter’s effective resolution.

On the other hand, a reduced reference voltage will im-

prove the converter’s overall INL performance. A reduced

reference voltage will also improve the converter perfor-

mance when operated with an external conversion clock

(external F_Osignal) at substantially higher output data

Ease of Use

The LTC2413 data output has no latency, filter settling

delay or redundant data associated with the conversion

cycle.Thereisaone-to-onecorrespondencebetweenthe

conversion and the output data. Therefore, multiplexing

multiple analog voltages is easy.

rates (see the Output Data Rate section).

sn2413 2413fs

12

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

Input Voltage Range

This bit is HIGH during the conversion and goes LOW

when the conversion is complete.

The analog input is truly differential with an absolute/

common mode range for the IN⁺and IN^–input pins

extending from GND – 0.3V to V_CC+ 0.3V. Outside

these limits, the ESD protection devices begin to turn on

and the errors due to input leakage current increase

rapidly. Within these limits, the LTC2413 converts the

bipolar differential input signal, V_IN= IN⁺– IN^–, from

Bit 30 (second output bit) is a dummy bit (DMY) and is

always LOW.

Bit 29 (third output bit) is the conversion result sign indi-

cator (SIG). If V_INis >0, this bit is HIGH. If V_INis <0, this

bit is LOW.

Bit 28 (fourth output bit) is the most significant bit (MSB)

of the result. This bit in conjunction with Bit 29 also

provides the underrange or overrange indication. If both

Bit 29 and Bit 28 are HIGH, the differential input voltage is

above +FS. If both Bit 29 and Bit 28 are LOW, the

differential input voltage is below –FS.

–FS = –0.5 • V_REFto +FS = 0.5 • V_REFwhere V_REF

=

REF⁺– REF^–. Outside this range, the converter indicates

the overrange or the underrange condition using distinct

output codes.

Input signals applied to IN⁺and IN^–pins may extend by

300mV below ground and above V_CC. In order to limit any

fault current, resistors of up to 5k may be added in series

with the IN⁺and IN^–pins without affecting the perfor-

mance of the device. In the physical layout, it is important

to maintain the parasitic capacitance of the connection

betweentheseseriesresistorsandthecorrespondingpins

as low as possible; therefore, the resistors should be

located as close as practical to the pins. The effect of the

series resistance on the converter accuracy can be evalu-

ated from the curves presented in the Input Current/

Reference Current sections. In addition, series resistors

will introduce a temperature dependent offset error due to

the input leakage current. A 1nA input leakage current will

develop a 1ppm offset error on a 5k resistor if V_REF= 5V.

This error has a very strong temperature dependency.

The function of these bits is summarized in Table 1.

Table 1. LTC2413 Status Bits

Bit 31 Bit 30 Bit 29 Bit 28

Input Range

EOC

DMY

SIG MSB

V

≥ 0.5 • V

0

1

0

1

0

1

0

IN

REF

0V ≤ V < 0.5 • V

0

IN

REF

–0.5 • V ≤ V < 0V

0

REF

IN

V

< –0.5 • V

0

IN

REF

Bits 28-5 are the 24-bit conversion result MSB first.

Bit 5 is the least significant bit (LSB).

Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0 may

be included in averaging or discarded without loss of

resolution.

Output Data Format

DataisshiftedoutoftheSDOpinundercontroloftheserial

clock (SCK), see Figure 3. Whenever CS is HIGH, SDO

remains high impedance and any externally generated

SCK clock pulses are ignored by the internal data out shift

register.

The LTC2413 serial output data stream is 32 bits long. The

first 3 bits represent status information indicating the sign

and conversion state. The next 24 bits are the conversion

result, MSB first. The remaining 5 bits are sub LSBs

beyond the 24-bit level that may be included in averaging

or discarded without loss of resolution. The third and

fourthbitstogetherarealsousedtoindicateanunderrange

condition(thedifferentialinputvoltageisbelow–FS)oran

overrangecondition(thedifferentialinputvoltageisabove

+FS).

In order to shift the conversion result out of the device, CS

mustfirstbedrivenLOW. EOCisseenattheSDOpinofthe

deviceonceCSispulledLOW.EOCchangesrealtimefrom

HIGH to LOW at the completion of a conversion. This

signal may be used as an interrupt for an external

microcontroller. Bit 31 (EOC) can be captured on the first

risingedgeofSCK. Bit30isshiftedoutofthedeviceonthe

first falling edge of SCK. The final data bit (Bit 0) is shifted

Bit 31 (first output bit) is the end of conversion (EOC)

indicator. This bit is available at the SDO pin during the

conversion and sleep states whenever the CS pin is LOW.

out on the falling edge of the 31st SCK and may be latched

sn2413 2413fs

13

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

on the rising edge of the 32nd SCK pulse. On the falling

edgeofthe32ndSCKpulse,SDOgoesHIGHindicatingthe

initiation of a new conversion cycle. This bit serves as EOC

(Bit 31) for the next conversion cycle. Table 2 summarizes

the output data format.

Simultaneous Frequency Rejection

The LTC2413 internal oscillator provides better than 87dB

normalmoderejectionovertherangeof49Hzto61.2Hzas

shown in Figure 4. For this simultaneous 50Hz/60Hz

rejection, F_Oshould be connected to GND.

AslongasthevoltageontheIN⁺andIN^–pinsismaintained

within the –0.3V to (V_CC+ 0.3V) absolute maximum

operating range, a conversion result is generated for any

differential input voltage V_INfrom –FS = –0.5 • V_REFto

+FS=0.5•V_REF.Fordifferentialinputvoltagesgreaterthan

+FS, the conversion result is clamped to the value corre-

sponding to the +FS + 1LSB. For differential input voltages

below –FS, the conversion result is clamped to the value

corresponding to –FS – 1LSB.

When a fundamental rejection frequency different from

therange49Hzto61.2Hzisrequiredorwhentheconverter

must be sychronized with an outside source, the LTC2413

canoperatewithanexternalconversionclock.Theconveter

automatically detects the presence of an external clock

signal at the F_Opin and turns off the internal oscillator. The

frequency f_EOSCof the external signal must be at least

2560Hztobedetected.Theexternalclocksignaldutycycle

is not significant as long as the minimum and maximum

specifications for the high and low periods, t_HEOand t_LEO

,

are observed.

CS

BIT 31

EOC

BIT 30

“0”

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 5

BIT 0

SDO

SCK

LSB

24

Hi-Z

1

2

3

4

5

26

27

32

SLEEP

DATA OUTPUT

CONVERSION

2413 F03

Figure 3. Output Data Timing

Table 2. LTC2413 Output Data Format

Differential Input Voltage

V *

Bit 31

EOC

Bit 30

DMY

Bit 29

SIG

Bit 28

MSB

Bit 27

Bit 26

Bit 25

…

Bit 0

IN

V * ≥ 0.5 • V **

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

…

0

1

0

1

0

1

0

1

0

1

IN

REF

0.5 • V ** – 1LSB

REF

0.25 • V **

REF

0.25 • V ** – 1LSB

REF

0

–1LSB

–0.25 • V **

REF

–0.25 • V ** – 1LSB

REF

–0.5 • V **

REF

V * < –0.5 • V **

0

IN

REF

+

–

*The differential input voltage V = IN – IN .

IN

+

–

**The differential reference voltage V = REF – REF .

REF

sn2413 2413fs

14

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

–80

–90

While operating with an external conversion clock of a

frequency f_EOSC, the LTC2413 provides better than 110dB

normal mode rejection in a frequency range f_EOSC/2560

±4%. The normal mode rejection as a function of the input

frequency deviation from f_EOSC/2560 is shown in Figure 5.

–100

–120

–130

–140

Whenever an external clock is not present at the F_Opin the

converterautomaticallyactivatesitsinternaloscillatorand

enters the Internal Conversion Clock mode. The LTC2413

operation will not be disturbed if the change of conversion

clock source occurs during the sleep state or during the

data output state while the converter uses an external

serial clock. If the change occurs during the conversion

state, the result of the conversion in progress may be

outside specifications but the following conversions will

notbeaffected.Ifthechangeoccursduringthedataoutput

state and the converter is in the Internal SCK mode, the

serial clock duty cycle may be affected but the serial data

stream will remain valid.

48

50

52

54

56

58

60

62

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

2413 F04

Figure 4. LTC2413 Normal Mode Rejection

When Using an Internal Oscillator

–80

–85

–90

–95

–100

–105

–110

–115

–120

–125

–130

–135

–140

Table 3 summarizes the duration of each state and the

achievable output data rate as a function of F_O.

SERIAL INTERFACE PINS

The LTC2413 transmits the conversion results and re-

ceives the start of conversion command through a syn-

chronous 3-wire interface. During the conversion and

sleep states, this interface can be used to assess the

converter status and during the data output state it is used

to read the conversion result.

–12

–8

–4

0

4

8

12

DIFFERENTIAL INPUT SIGNAL FREQUENCY

DEVIATION FROM NOTCH FREQUENCY f

/2560(%)

2413 F05

EOSC

Figure 5. LTC2413 Normal Mode Rejection When

Using an External Oscillator of Frequency f_EOSC

Table 3. LTC2413 State Duration

State

Operating Mode

Duration

CONVERT

Internal Oscillator

F = LOW

Simultaneous 50Hz/60Hz Rejection

147ms, Output Data Rate ≤ 6.8 Readings/s

O

External Oscillator

F = External Oscillator

20510/f

s, Output Data Rate ≤ f

/20510 Readings/s

EOSC

O

EOSC

with Frequency f

kHz

EOSC

(f

EOSC

/2560 Rejection)

SLEEP

As Long As CS = HIGH Until CS = LOW and SCK

DATA OUTPUT

Internal Serial Clock

External Serial Clock with

F = LOW

(Internal Oscillator)

As Long As CS = LOW But Not Longer Than 1.83ms

(32 SCK cycles)

O

F = External Oscillator with

As Long As CS = LOW But Not Longer Than 256/f

ms

EOSC

O

Frequency f

kHz

(32 SCK cycles)

EOSC

As Long As CS = LOW But Not Longer Than 32/f ms

SCK

Frequency f

kHz

(32 SCK cycles)

SCK

sn2413 2413fs

15

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

Serial Clock Input/Output (SCK)

In addition, the CS signal can be used to trigger a new

conversion cycle before the entire serial data transfer has

been completed. The LTC2413 will abort any serial data

transfer in progress and start a new conversion cycle

anytime a LOW-to-HIGH transition is detected at the CS

pin after the converter has entered the data output state

(i.e., after the first rising edge of SCK occurs with

CS = LOW).

The serial clock signal present on SCK (Pin 13) is used to

synchronizethedatatransfer.Eachbitofdataisshiftedout

the SDO pin on the falling edge of the serial clock.

In the Internal SCK mode of operation, the SCK pin is an

output and the LTC2413 creates its own serial clock by

dividing the internal conversion clock by 8. In the External

SCK mode of operation, the SCK pin is used as input. The

internalorexternalSCKmodeisselectedonpower-upand

then reselected every time a HIGH-to-LOW transition is

detected at the CS pin. If SCK is HIGH or floating at power-

up or during this transition, the converter enters the inter-

nal SCK mode. If SCK is LOW at power-up or during this

transition, the converter enters the external SCK mode.

Finally, CS can be used to control the free-running modes

of operation, see Serial Interface Timing Modes section.

Grounding CS will force the ADC to continuously convert

at the maximum output rate selected by F_O. Tying a

capacitor to CS will reduce the output rate and power

dissipation by a factor proportional to the capacitor’s

value, see Figures 13 to 15.

Serial Data Output (SDO)

SERIAL INTERFACE TIMING MODES

The serial data output pin, SDO (Pin 12), provides the

result of the last conversion as a serial bit stream (MSB

first) during the data output state. In addition, the SDO pin

is used as an end of conversion indicator during the

conversion and sleep states.

The LTC2413’s 3-wire interface is SPI and MICROWIRE

compatible. This interface offers several flexible modes of

operation. These include internal/external serial clock,

2-or3-wireI/O,singlecycleconversionandautostart.The

following sections describe each of these serial interface

timing modes in detail. In all these cases, the converter

can use the internal oscillator (F_O= LOW) or an external

oscillator connected to the F_Opin. Refer to Table 4 for a

summary.

When CS (Pin 11) is HIGH, the SDO driver is switched to

a high impedance state. This allows sharing the serial

interface with other devices. If CS is LOW during the

convert or sleep state, SDO will output EOC. If CS is LOW

duringtheconversionphase, theEOCbitappearsHIGHon

the SDO pin. Once the conversion is complete, EOC goes

LOW. The device remains in the sleep state until the first

rising edge of SCK occurs while CS = LOW.

External Serial Clock, Single Cycle Operation

(SPI/MICROWIRE Compatible)

This timing mode uses an external serial clock to shift out

the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 6.

Chip Select Input (CS)

The active LOW chip select, CS (Pin 11), is used to test the

conversionstatusandtoenablethedataoutputtransferas

described in the previous sections.

Table 4. LTC2413 Interface Timing Modes

Configuration

SCK Source Conversion Cycle Control

Data Output Control

CS and SCK

SCK

Connection and Waveforms

Figures 6, 7

External SCK, Single Cycle Conversion

External SCK, 2-Wire I/O

External

Internal

CS and SCK

SCK

Figure 8

Internal SCK, Single Cycle Conversion

Internal SCK, 2-Wire I/O, Continuous Conversion

Internal SCK, Autostart Conversion

CS ↓

Figures 9, 10

Figure 11

Continuous

Internal

C

Internal

Figure 12

EXT

sn2413 2413fs

16

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

The serial clock mode is selected on the falling edge of CS.

Toselecttheexternalserialclockmode,theserialclockpin

(SCK) must be LOW during each CS falling edge.

As described above, CS may be pulled LOW at any time in

order to monitor the conversion status.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

CS HIGH anytime between the first rising edge and the

32nd falling edge of SCK, see Figure 7. On the rising edge

of CS, the device aborts the data output state and imme-

diately initiates a new conversion. This is useful for sys-

tems not requiring all 32 bits of output data, aborting an

invalid conversion cycle or synchronizing the start of a

conversion.

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

While CS is pulled LOW, EOC is output to the SDO pin.

EOC = 1 while a conversion is in progress and EOC = 0 if

the device is in the sleep state. Independent of CS, the

deviceautomaticallyentersthelowpowersleepstateonce

the conversion is complete.

When the device is in the sleep state (EOC = 0), its

conversion result is held in an internal static shift regis-

ter. The device remains in the sleep state until the first

risingedgeofSCKisseenwhileCSisLOW.Dataisshifted

out the SDO pin on each falling edge of SCK. This enables

external circuitry to latch the output on the rising edge of

SCK. EOC can be latched on the first rising edge of SCK

and the last bit of the conversion result can be latched on

the 32nd rising edge of SCK. On the 32nd falling edge of

SCK, thedevicebeginsanewconversion. SDOgoesHIGH

(EOC = 1) indicating a conversion is in progress.

External Serial Clock, 2-Wire I/O

This timing mode utilizes a 2-wire serial I/O interface. The

conversion result is shifted out of the device by an exter-

nally generated serial clock (SCK) signal, see Figure 8. CS

may be permanently tied to ground, simplifying the user

interface or isolation barrier.

The external serial clock mode is selected at the end of the

power-on reset (POR) cycle. The POR cycle is concluded

approximately 0.5ms after V_CCexceeds 2.2V. The level

applied to SCK at this time determines if SCK is internal or

external. SCK must be driven LOW prior to the end of POR

in order to enter the external serial clock timing mode.

At the conclusion of the data cycle, CS may remain LOW

and EOC monitored as an end-of-conversion interrupt.

Alternatively, CS may be driven HIGH setting SDO to Hi-Z.

2.7V TO 5.5V

1µF

= EXTERNAL OSCILLATOR

2

14

13

V

F

O

CC

= INTERNAL OSC/SIMULTANEOUS 50Hz/60Hz REJECTION

LTC2413

3

4

+

–

REFERENCE

VOLTAGE

REF

SCK

0.1V TO V

CC

3-WIRE

SPI INTERFACE

5

6

12

11

+

ANALOG INPUT RANGE

–0.5V TO 0.5V

IN

SDO

CS

REF

–

IN

1, 7, 8, 9, 10, 15, 16

GND

CS

TEST EOC

BIT 31

EOC

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 26

BIT 5

LSB

BIT 0

SDO

SUB LSB

Hi-Z

SCK

(EXTERNAL)

CONVERSION

SLEEP

DATA OUTPUT

CONVERSION

2413 F06

Figure 6. External Serial Clock, Single Cycle Operation

sn2413 2413fs

17

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

2.7V TO 5.5V

1µF

= EXTERNAL OSCILLATOR

2

14

13

V

F

O

CC

LTC2413

= INTERNAL OSC/SIMULTANEOUS 50Hz/60Hz REJECTION

3

+

REFERENCE

VOLTAGE

0.1V TO V

REF

SCK

4

–

CC

3-WIRE

SPI INTERFACE

5

6

12

11

+

ANALOG INPUT RANGE

–0.5V TO 0.5V

IN

SDO

CS

REF

–

IN

1, 7, 8, 9, 10, 15, 16

GND

CS

TEST EOC

BIT 0

EOC

BIT 31

EOC

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 9

BIT 8

SDO

Hi-Z

SCK

(EXTERNAL)

SLEEP

CONVERSION

DATA OUTPUT

SLEEP

DATA OUTPUT

CONVERSION

2413 F07

Figure 7. External Serial Clock, Reduced Data Output Length

Since CS is tied LOW, the end-of-conversion (EOC) can be

continuously monitored at the SDO pin during the convert

and sleep states. EOC may be used as an interrupt to an

external controller indicating the conversion result is

ready. EOC = 1 while the conversion is in progress and

EOC = 0 once the conversion enters the low power sleep

state. On the falling edge of EOC, the conversion result is

loaded into an internal static shift register. The device

remains in the sleep state until the first rising edge of SCK.

Data is shifted out the SDO pin on each falling edge of SCK

enabling external circuitry to latch data on the rising edge

of SCK. EOC can be latched on the first rising edge of SCK.

Onthe32ndfallingedgeofSCK,SDOgoesHIGH(EOC = 1)

indicating a new conversion has begun.

enter the internal serial clock mode if SCK is driven LOW

on the falling edge of CS. An internal weak pull-up resistor

is active on the SCK pin during the falling edge of CS;

therefore, the internal serial clock timing mode is auto-

matically selected if SCK is not externally driven.

The serial data output pin (SDO) is Hi-Z as long as CS is

HIGH. At any time during the conversion cycle, CS may be

pulled LOW in order to monitor the state of the converter.

Once CS is pulled LOW, SCK goes LOW and EOC is output

to the SDO pin. EOC = 1 while a conversion is in progress

and EOC = 0 if the device is in the sleep state.

WhentestingEOC,iftheconversioniscomplete(EOC=0),

thedevicewillexitthesleepstateandenterthedataoutput

state if CS remains LOW. In order to prevent the device

from exiting the low power sleep state, CS must be pulled

HIGH before the first rising edge of SCK. In the internal

SCK timing mode, SCK goes HIGH and the device begins

outputting data at time t_EOCtestafter the falling edge of CS

(if EOC = 0) or t_EOCtestafter EOC goes LOW (if CS is LOW

duringthefallingedgeofEOC).Thevalueoft_EOCtestis26µs

ifthedeviceisusingitsinternaloscillator(F₀=logicLOW).

Internal Serial Clock, Single Cycle Operation

This timing mode uses an internal serial clock to shift out

the conversion result and a CS signal to monitor and

control the state of the conversion cycle, see Figure 9.

In order to select the internal serial clock timing mode, the

serial clock pin (SCK) must be floating (Hi-Z) or pulled

HIGH prior to the falling edge of CS. The device will not

If F_Ois driven by an external oscillator of frequency f_EOSC

,

sn2413 2413fs

18

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

2.7V TO 5.5V

1µF

= EXTERNAL OSCILLATOR

= INTERNAL OSC/SIMULTANEOUS 50Hz/60Hz REJECTION

2

14

13

V

F

O

CC

LTC2413

3

+

–

REFERENCE

VOLTAGE

0.1V TO V

REF

SCK

4

CC

2-WIRE I/O

5

6

12

11

+

ANALOG INPUT RANGE

–0.5V TO 0.5V

IN

SDO

CS

REF REF

–

IN

1, 7, 8, 9, 10, 15, 16

GND

CS

BIT 31

EOC

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 26

BIT 5

LSB

BIT 0

SDO

24

SCK

(EXTERNAL)

CONVERSION

SLEEP

DATA OUTPUT

CONVERSION

2413 F08

Figure 8. External Serial Clock, CS = 0 Operation

2.7V TO 5.5V

V

CC

1µF

= EXTERNAL OSCILLATOR

= INTERNAL OSC/SIMULTANEOUS

50Hz/60Hz REJECTION

2

14

13

V

F

O

CC

10k

LTC2413

3

4

+

–

REFERENCE

VOLTAGE

REF

SCK

0.1V TO V

CC

3-WIRE

SPI INTERFACE

5

6

12

11

+

ANALOG INPUT RANGE

–0.5V TO 0.5V

IN

SDO

CS

REF

–

IN

1, 7, 8, 9, 10, 15, 16

GND

<t

EOCtest

CS

TEST EOC

BIT 31

EOC

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 26

BIT 5

LSB

BIT 0

SDO

24

Hi-Z

SCK

(INTERNAL)

CONVERSION

SLEEP

DATA OUTPUT

CONVERSION

2413 F09

Figure 9. Internal Serial Clock, Single Cycle Operation

sn2413 2413fs

19

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

then t_EOCtestis 3.6/f_EOSC. If CS is pulled HIGH before time

new conversion. This is useful for systems not requiring

all 32 bits of output data, aborting an invalid conversion

cycle, or synchronizing the start of a conversion. If CS is

pulled HIGH while the converter is driving SCK LOW, the

internal pull-up is not available to restore SCK to a logic

HIGH state. This will cause the device to exit the internal

serial clock mode on the next falling edge of CS. This can

be avoided by adding an external 10k pull-up resistor to

theSCKpinorbyneverpullingCSHIGHwhenSCKisLOW.

t

_EOCtest, the device remains in the sleep state. The conver-

sion result is held in the internal static shift register.

If CS remains LOW longer than t_EOCtest, the first rising

edge of SCK will occur and the conversion result is serially

shiftedoutoftheSDOpin. Thedataoutputcyclebeginson

this first rising edge of SCK and concludes after the 32nd

rising edge. Data is shifted out the SDO pin on each falling

edgeofSCK.Theinternallygeneratedserialclockisoutput

to the SCK pin. This signal may be used to shift the

conversion result into external circuitry. EOC can be

latchedonthefirstrisingedgeofSCKandthelastbitofthe

conversionresultonthe32ndrisingedgeofSCK. Afterthe

32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays

HIGH and a new conversion starts.

Whenever SCK is LOW, the LTC2413’s internal pull-up at

pin SCK is disabled. Normally, SCK is not externally driven

if the device is in the internal SCK timing mode. However,

certainapplicationsmayrequireanexternaldriveronSCK.

If this driver goes Hi-Z after outputting a LOW signal, the

LTC2413’s internal pull-up remains disabled. Hence, SCK

remains LOW. On the next falling edge of CS, the device is

switched to the external SCK timing mode. By adding an

external 10k pull-up resistor to SCK, this pin goes HIGH

once the external driver goes Hi-Z. On the next CS falling

edge, the device will remain in the internal SCK timing

mode.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

CS HIGH anytime between the first and 32nd rising edge

of SCK, see Figure 10. On the rising edge of CS, the device

aborts the data output state and immediately initiates a

2.7V TO 5.5V

V

CC

1µF

= EXTERNAL OSCILLATOR

= INTERNAL OSC/SIMULTANEOUS

50Hz/60Hz REJECTION

2

14

13

V

F

O

CC

LTC2413

10k

3

+

REFERENCE

REF

SCK

VOLTAGE

4

–

0.1V TO V

CC

3-WIRE

SPI INTERFACE

5

6

12

11

+

ANALOG INPUT RANGE

–0.5V TO 0.5V

IN

SDO

CS

REF REF

–

IN

1, 7, 8, 9, 10, 15, 16

<t

EOCtest

GND

>t

EOCtest

CS

TEST EOC

BIT 0

EOC

BIT 31

EOC

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 26

BIT 8

SDO

Hi-Z

SCK

(INTERNAL)

SLEEP

CONVERSION

DATA OUTPUT

SLEEP

DATA OUTPUT

CONVERSION

2413 F10

Figure 10. Internal Serial Clock, Reduced Data Output Length

sn2413 2413fs

20

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

A similar situation may occur during the sleep state when

CS is pulsed HIGH-LOW-HIGH in order to test the conver-

sionstatus.Ifthedeviceisinthesleepstate(EOC=0),SCK

will go LOW. Once CS goes HIGH (within the time period

defined above as t_EOCtest), the internal pull-up is activated.

For a heavy capacitive load on the SCK pin, the internal

pull-up may not be adequate to return SCK to a HIGH level

before CS goes low again. This is not a concern under

normal conditions where CS remains LOW after detecting

EOC = 0. This situation is easily overcome by adding an

external 10k pull-up resistor to the SCK pin.

weak pull-up is active during the POR cycle; therefore, the

internal serial clock timing mode is automatically selected

if SCK is not externally driven LOW (if SCK is loaded such

that the internal pull-up cannot pull the pin HIGH, the

external SCK mode will be selected).

During the conversion, the SCK and the serial data output

pin (SDO) are HIGH (EOC = 1). Once the conversion is

complete, SCK and SDO go LOW (EOC = 0) indicating the

conversion has finished and the device has entered the

low power sleep state. The part remains in the sleep state

a minimum amount of time (1/2 the internal SCK period)

thenimmediatelybeginsoutputtingdata.Thedataoutput

cyclebeginsonthefirstrisingedgeofSCKandendsafter

the 32nd rising edge. Data is shifted out the SDO pin on

each falling edge of SCK. The internally generated serial

clock is output to the SCK pin. This signal may be used

to shift the conversion result into external circuitry. EOC

can be latched on the first rising edge of SCK and the last

bit of the conversion result can be latched on the 32nd

rising edge of SCK. After the 32nd rising edge, SDO goes

HIGH(EOC=1)indicatinganewconversionisinprogress.

SCK remains HIGH during the conversion.

Internal Serial Clock, 2-Wire I/O,

Continuous Conversion

This timing mode uses a 2-wire, all output (SCK and SDO)

interface. The conversion result is shifted out of the device

by an internally generated serial clock (SCK) signal, see

Figure 11. CS may be permanently tied to ground, simpli-

fying the user interface or isolation barrier.

The internal serial clock mode is selected at the end of the

power-on reset (POR) cycle. The POR cycle is concluded

approximately 0.5ms after V_CCexceeds 2.2V. An internal

2.7V TO 5.5V

1µF

= EXTERNAL OSCILLATOR

2

14

13

V

F

O

CC

LTC2413

= INTERNAL OSC/SIMULTANEOUS 50Hz/60Hz REJECTION

3

+

REFERENCE

REF

SCK

VOLTAGE

4

–

0.1V TO V

CC

2-WIRE I/O

5

6

12

11

+

ANALOG INPUT RANGE

IN

SDO

CS

–0.5V

TO 0.5V

REF

–

IN

1, 7, 8, 9, 10, 15, 16

GND

CS

BIT 31

EOC

BIT 30

BIT 29

SIG

BIT 28

MSB

BIT 27

BIT 26

BIT 5

LSB

BIT 0

SDO

24

SCK

(INTERNAL)

CONVERSION

DATA OUTPUT

CONVERSION

2413 F11

SLEEP

Figure 11. Internal Serial Clock, CS = 0 Continuous Operation

sn2413 2413fs

21

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

Internal Serial Clock, Autostart Conversion

used to shift the conversion result into external circuitry.

After the 32nd rising edge, CS is pulled HIGH and a new

conversion is immediately started. This is useful in appli-

cations requiring periodic monitoring and ultralow power.

Figure 15 shows the average supply current as a function

of capacitance on CS.

This timing mode is identical to the internal serial clock,

2-wire I/O described above with one additional feature.

Instead of grounding CS, an external timing capacitor is

tied to CS.

While the conversion is in progress, the CS pin is held

HIGH by an internal weak pull-up. Once the conversion is

complete, the device enters the low power sleep state and

an internal 25nA current source begins discharging the

capacitor tied to CS, see Figure 12. The time the converter

spends in the sleep state is determined by the value of the

external timing capacitor, see Figures 13 and 14. Once the

voltageatCSfallsbelowaninternalthreshold(≈1.4V), the

device automatically begins outputting data. The data

output cycle begins on the first rising edge of SCK and

ends on the 32nd rising edge. Data is shifted out the SDO

pin on each falling edge of SCK. The internally generated

serial clock is output to the SCK pin. This signal may be

It should be noticed that the external capacitor discharge

current is kept very small in order to decrease the con-

verter power dissipation in the sleep state. In the autostart

mode, the analog voltage on the CS pin cannot be ob-

served without disturbing the converter operation using a

regular oscilloscope probe. When using this configura-

tion, it is important to minimize the external leakage

current at the CS pin by using a low leakage external

capacitor and properly cleaning the PCB surface.

The internal serial clock mode is selected every time the

voltage on the CS pin crosses an internal threshold volt-

age. An internal weak pull-up at the SCK pin is active while

2.7V TO 5.5V

1µF

= EXTERNAL OSCILLATOR

2

14

13

V

F

O

CC

= INTERNAL OSC/SIMULTANEOUS 50Hz/60Hz REJECTION

LTC2413

3

4

+

REFERENCE

VOLTAGE

REF

SCK

–

0.1V TO V

CC

2-WIRE I/O

5

6

12

11

+

ANALOG INPUT RANGE

IN

SDO

CS

–0.5V

TO 0.5V

REF

–

IN

1, 7, 8, 9, 10, 15, 16

GND

C

EXT

V

CC

CS

GND

BIT 31

EOC

BIT 30

BIT 29

SIG

BIT 0

SDO

Hi-Z

SCK

(INTERNAL)

CONVERSION

DATA OUTPUT

CONVERSION

SLEEP

2413 F12

Figure 12. Internal Serial Clock, Autostart Operation

sn2413 2413fs

22

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

7

6

5

4

3

2

CS is discharging; therefore, the internal serial clock

timing mode is automatically selected if SCK is floating. It

is important to ensure there are no external drivers pulling

SCK LOW while CS is discharging.

PRESERVING THE CONVERTER ACCURACY

The LTC2413 is designed to reduce as much as possible

the conversion result sensitivity to device decoupling,

PCB layout, antialiasing circuits, line frequency perturba-

tions and so on. Nevertheless, in order to preserve the

extreme accuracy capability of this part, some simple

precautions are desirable.

V

= 5V

CC

1

0

V

= 3V

CC

10

100

100000

1

1000

10000

CAPACITANCE ON CS (pF)

2413 F13

Figure 13. CS Capacitance vs t_SAMPLE

Digital Signal Levels

8

7

6

The LTC2413’s digital interface is easy to use. Its digital

inputs(F_O,CSandSCKinExternalSCKmodeofoperation)

accept standard TTL/CMOS logic levels and the internal

hysteresis receivers can tolerate edge rates as slow as

100µs.However,someconsiderationsarerequiredtotake

advantage of the exceptional accuracy and low supply

current of this converter.

V

= 5V

CC

5

V

= 3V

CC

4

3

2

1

0

The digital output signals (SDO and SCK in Internal SCK

mode of operation) are less of a concern because they are

not generally active during the conversion state.

10

100

10000

100000

0

1000

CAPACITANCE ON CS (pF)

While a digital input signal is in the range 0.5V to

(V_CC– 0.5V), the CMOS input receiver draws additional

current from the power supply. It should be noted that,

when any one of the digital input signals (F_O, CS and SCK

inExternalSCKmodeofoperation)iswithinthisrange,the

LTC2413 power supply current may increase even if the

signal in question is at a valid logic level. For micropower

operation, it is recommended to drive all digital input

2413 F14

Figure 14. CS Capacitance vs Output Rate

300

250

V

= 5V

= 3V

CC

200

150

signals to full CMOS levels [V_IL< 0.4V and V_IH

(V_CC– 0.4V)].

>

100

50

0

During the conversion period, the undershoot and/or

overshootofafastdigitalsignalconnectedtotheLTC2413

pins may severely disturb the analog to digital conversion

process.Undershootandovershootcanoccurbecauseof

the impedance mismatch at the converter pin when the

transition time of an external control signal is less than

twice the propagation delay from the driver to LTC2413.

Forreference,onaregularFR-4board,signalpropagation

sn2413 2413fs

1

10

100

1000

10000 100000

CAPACITANCE ON CS (pF)

2413 F15

Figure 15. CS Capacitance vs Supply Current

23

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

velocity is approximately 183ps/inch for internal traces

and 170ps/inch for surface traces. Thus, a driver gener-

ating a control signal with a minimum transition time of

1ns must be connected to the converter pin through a

trace shorter than 2.5 inches. This problem becomes

particularly difficult when shared control lines are used

and multiple reflections may occur. The solution is to

carefully terminate all transmission lines close to their

characteristic impedance.

ence. In this situation, the user must reduce to a minimum

the loop area for the F_Osignal as well as the loop area for

the differential input and reference connections.

Driving the Input and Reference

The input and reference pins of the LTC2413 converter are

directly connected to a network of sampling capacitors.

Depending upon the relation between the differential input

voltage and the differential reference voltage, these ca-

pacitorsareswitchingbetweenthesefourpinstransfering

small amounts of charge in the process. A simplified

equivalent circuit is shown in Figure 16.

Parallel termination near the LTC2413 pin will eliminate

thisproblembutwillincreasethedriverpowerdissipation.

A series resistor between 27Ω and 56Ω placed near the

driver or near the LTC2413 pin will also eliminate this

problem without additional power dissipation. The actual

resistor value depends upon the trace impedance and

connection topology.

For a simple approximation, the source impedance R_S

driving an analog input pin (IN⁺, IN^–, REF⁺or REF^–) can be

considered to form, together with R_SWand C_EQ(see

Figure 16), a first order passive network with a time

constant τ = (R_S+ R_SW) • C_EQ. The converter is able to

sample the input signal with better than 1ppm accuracy if

the sampling period is at least 14 times greater than the

input circuit time constant τ. The sampling process on the

four input analog pins is quasi-independent so each time

constant should be considered by itself and, under worst-

case circumstances, the errors may add.

An alternate solution is to reduce the edge rate of the

control signals. It should be noted that using very slow

edges will increase the converter power supply current

during the transition time. The multiple ground pins used

in this package configuration, as well as the differential

input and reference architecture, reduce substantially the

converter’s sensitivity to ground currents.

When using the internal oscillator (F_O= LOW), the

LTC2413’sfront-endswitched-capacitornetworkisclocked

at 69900Hz corresponding to a 14.3µs sampling period.

Thus, for settling errors of less than 1ppm, the driving

source impedance should be chosen such that

τ ≤ 14.3µs/14 = 1.02µs. When an external oscillator of

frequency f_EOSCis used, the sampling period is 2/f_EOSC

Particular attention must be given to the connection of the

F_Osignal when the LTC2413 is used with an external

conversion clock. This clock is active during the conver-

sion time and the normal mode rejection provided by the

internal digital filter is not very high at this frequency. A

normal mode signal of this frequency at the converter

reference terminals may result in DC gain and INL errors.

A normal mode signal of this frequency at the converter

input terminals may result in a DC offset error. Such

perturbations may occur due to asymmetric capacitive

coupling between the F_Osignal trace and the converter

input and/or reference connection traces. An immediate

solution is to maintain maximum possible separation

between the F_Osignal trace and the input/reference sig-

nals. When the F_Osignal is parallel terminated near the

converter, substantial AC current is flowing in the loop

formedbytheF_Oconnectiontrace, theterminationandthe

ground return path. Thus, perturbation signals may be

inductively coupled into the converter input and/or refer-

and, for a settling error of less than 1ppm, τ ≤ 0.14/f_EOSC

.

Input Current

If complete settling occurs on the input, conversion re-

sults will be unaffected by the dynamic input current. An

incomplete settling of the input signal sampling process

may result in gain and offset errors, but it will not degrade

theINLperformanceoftheconverter. Figure16showsthe

mathematical expressions for the average bias currents

flowing through the IN⁺and IN^–pins as a result of the

sampling charge transfers when integrated over a sub-

stantial time period (longer than 64 internal clock cycles).

sn2413 2413fs

24

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

V

CC

I

+

REF

R

(TYP)

SW

I

LEAK

V

_IN+ V_INCM− V_REFCM

I IN⁺

=

20k

(

)

AVG

V

0.5• R_EQ

−V_IN+ V_INCM− V_REFCM

0.5• R_EQ

REF

I IN⁻

(

V

CC

V²

I

+

IN

1.5• V_REF− V_INCM+ V_REFCM

IN

I REF⁺

=

−

(TYP)

20k

I

(

)

LEAK

AVG

0.5• R_EQ

V

_REF• R_EQ

V

+

IN

V²

−1.5• V_REF− V_INCM+ V_REFCM

0.5• R_EQ

C

IN

I REF⁻

=

+

EQ

(

)

18pF

AVG

V

_REF• R_EQ

(TYP)

V

where:

CC

I

–

IN

V_REF= REF⁺−REF⁻

R

(TYP)

SW

I

LEAK

20k

REF⁺+ REF⁻

V

V_REFCM

=

2

V

_IN= IN⁺−IN⁻

V

CC

I

–

REF

IN⁺− IN⁻

(TYP)

20k

SW

V

INCM

=

I

LEAK

2

2413 F16

V

REF

R_EQ= 3.97MΩ INTERNAL OSCILLATOR

R_EQ= 0.555• 10¹²/ f_EOSCEXTERNAL OSCILLATOR

(

)

SWITCHING FREQUENCY

f

= 69900Hz INTERNAL OSCILLATOR

SW

= 0.5 • f

EXTERNAL OSCILLATOR

EOSC

Figure 16. LTC2413 Equivalent Analog Input Circuit

R

SOURCE

The effect of this input dynamic current can be analyzed

using the test circuit of Figure 17. The C_PARcapacitor

includes the LTC2413 pin capacitance (5pF typical) plus

thecapacitanceofthetestfixtureusedtoobtaintheresults

shown in Figures 18 and 19. A careful implementation can

bring the total input capacitance (C_IN+ C_PAR) closer to 5pF

thus achieving better performance than the one predicted

by Figures 18 and 19. For simplicity, two distinct situa-

tions can be considered.

+

IN

C

PAR

V

+ 0.5V

C

INCM

IN

20pF

LTC2413

R

SOURCE

–

IN

2413 F17

PAR

20pF

V

– 0.5V

IN

Figure 17. An RC Network at IN⁺and IN^–

50

0

C

= 0.01µF

IN

V

= 5V

CC

+

REF = 5V

C

= 0.001µF

IN

C

–

REF = GND

40

30

20

10

0

–10

–20

–30

–40

–50

+

–

= 100pF

IN

IN = GND

IN = 2.5V

C

= 0pF

IN

F

= GND

= 25°C

O

A

T

V

= 5V

CC

+

–

REF = 5V

C

= 0.01µF

REF = GND

IN

+

–

IN = 5V

C

= 0.001µF

IN

C

IN = 2.5V

F

= GND

O

= 100pF

IN

C

T

= 25°C

A

= 0pF

IN

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05

(Ω)

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05

(Ω)

R

SOURCE

2413 F18

2413 F19

Figure 18. +FS Error vs R_SOURCEat IN⁺or IN^–(Small C_IN)

Figure 19. –FS Error vs R_SOURCEat IN⁺or IN^–(Small C_IN)

sn2413 2413fs

25

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

For relatively small values of input capacitance (C_IN

<

converter average input current will not degrade the INL

performance,indirectdistortionmayresultfromthemodu-

lation of the offset error by the common mode component

of the input signal. Thus, when using large C_INcapacitor

values, itisadvisabletocarefullymatchthesourceimped-

ance seen by the IN⁺and IN^–pins. When internal oscillator

is used (F_O= LOW), every 1Ω mismatch in source imped-

ance transforms a full-scale common mode input signal

into a differential mode input signal of 0.25ppm. When F_O

0.01µF), the voltage on the sampling capacitor settles

almost completely and relatively large values for the

source impedance result in only small errors. Such values

for C_INwill deteriorate the converter offset and gain

performancewithoutsignificantbenefitsofsignalfiltering

and the user is advised to avoid them. Nevertheless, when

small values of C_INare unavoidably present as parasitics

of input multiplexers, wires, connectors or sensors, the

LTC2413 can maintain its exceptional accuracy while

operatingwithrelativelargevaluesofsourceresistanceas

shown in Figures 18 and 19. These measured results may

be slightly different from the first order approximation

suggested earlier because they include the effect of the

actual second order input network together with the non-

linearsettlingprocessoftheinputamplifiers.ForsmallC_IN

values, the settling on IN⁺and IN^–occurs almost indepen-

dently and there is little benefit in trying to match the

source impedance for the two pins.

is driven by an external oscillator with a frequency f_EOSC

,

every 1Ω mismatch in source impedance transforms a

full-scale common mode input signal into a differential

mode input signal of 1.78 • 10^–6• f_EOSCppm. Figure 22

shows the typical offset error due to input common mode

voltage for various values of source resistance imbalance

between the IN⁺and IN^–pins when large C_INvalues are

used.

If possible, it is desirable to operate with the input signal

common mode voltage very close to the reference signal

common mode voltage as is the case in the ratiometric

measurement of a symmetric bridge. This configuration

eliminates the offset error caused by mismatched source

impedances.

Larger values of input capacitors (C_IN> 0.01µF) may be

required in certain configurations for antialiasing or gen-

eral input signal filtering. Such capacitors will average the

input sampling charge and the external source resistance

will see a quasi constant input differential impedance.

When internal oscillator is used (F_O= LOW), the typical

differential input resistance is 2MΩ which will generate a

gain error of approximately 0.25ppm for each ohm of

source resistance driving IN⁺or IN^–. When F_Ois driven by

an external oscillator with a frequency f_EOSC(external

conversion clock operation), the typical differential input

resistance is 0.28 • 10¹²/f_EOSCΩ and each ohm of

source resistance driving IN⁺or IN^–will result in

1.78 • 10^–6• f_EOSCppm gain error. The effect of the source

resistance on the two input pins is additive with respect to

thisgainerror.Thetypical+FSand–FSerrorsasafunction

of the sum of the source resistance seen by IN⁺and IN^–for

large values of C_INare shown in Figures 20 and 21.

Themagnitudeofthedynamicinputcurrentdependsupon

thesizeoftheverystableinternalsamplingcapacitorsand

upon the accuracy of the converter sampling clock. The

accuracy of the internal clock over the entire temperature

and power supply range is typical better than 0.5%. Such

a specification can also be easily achieved by an external

clock. When relatively stable resistors (50ppm/°C) are

used for the external source impedance seen by IN⁺and

IN^–, the expected drift of the dynamic current, offset and

gain errors will be insignificant (about 1% of their respec-

tive values over the entire temperature and voltage range).

Even for the most stringent applications a one-time cali-

bration operation may be sufficient.

In addition to the input sampling charge, the input ESD

protection diodes have a temperature dependent leakage

current. This current, nominally 1nA (±10nA max), results

inasmalloffsetshift. A100Ωsourceresistancewillcreate

a 0.1µV typical and 1µV maximum offset voltage.

In addition to this gain error, an offset error term may also

appear. The offset error is proportional with the mismatch

between the source impedance driving the two input pins

IN⁺and IN^–and with the difference between the input and

reference common mode voltages. While the input drive

circuit nonzero source impedance combined with the

sn2413 2413fs

26

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

300

Reference Current

V

= 5V

CC

+

REF = 5V

–

C

= 1µF, 10µF

In a similar fashion, the LTC2413 samples the differential

reference pins REF⁺and REF^–transfering small amount of

charge to and from the external driving circuits, thus

produces a dynamic reference current. This current does

notchangetheconverteroffsetbutitmaydegradethegain

and INL performance. The effect of this current can be

analyzed in the same two distinct situations.

IN

REF = GND

240

180

120

60

+

–

IN = 3.75V

IN = 1.25V

F

= GND

= 25°C

O

A

T

C

IN

= 0.1µF

C

IN

= 0.01µF

Forrelativelysmallvaluesoftheexternalreferencecapaci-

tors(C_REF<0.01µF),thevoltageonthesamplingcapacitor

settles almost completely and relatively large values for

the source impedance result in only small errors. Such

values for C_REFwill deteriorate the converter offset and

gainperformancewithoutsignificantbenefitsofreference

filtering and the user is advised to avoid them.

0

100 200 300 400 500 600 700 800 9001000

(Ω)

R

SOURCE

2413 F19

Figure 20. +FS Error vs R_SOURCEat IN⁺or IN^–(Large C_IN)

0

C

IN

= 0.01µF

–60

–120

–180

–240

–300

Larger values of reference capacitors (C_REF> 0.01µF) may

be required as reference filters in certain configurations.

Suchcapacitorswillaveragethereferencesamplingcharge

and the external source resistance will see a quasi con-

stant reference differential impedance. When internal os-

cillator is used (F_O= LOW), the typical differential input

resistance is 1.43MΩ which will generate a gain error of

approximately 0.35ppm for each ohm of source resis-

tance driving REF⁺or REF^–. When F_Ois driven by an

externaloscillatorwithafrequencyf_EOSC(externalconver-

sion clock operation), the typical differential reference

resistance is 0.20 • 10¹²/f_EOSCΩ and each ohm of source

resistance drving REF⁺or REF^–will result in

2.47 • 10^–6• f_EOSCppm gain error. The effect of the source

resistance on the two reference pins is additive with

respect to this gain error. The typical +FS and –FS errors

for various combinations of source resistance seen by the

REF⁺and REF^–pins and external capacitance C_REFcon-

nected to these pins are shown in Figures 23, 24, 25

and 26.

C

IN

= 0.1µF

V

= 5V

CC

+

REF = 5V

–

REF = GND

+

–

IN = 1.25V

IN = 3.75V

C

IN

= 1µF, 10µF

F

= GND

= 25°C

O

A

T

0

100 200 300 400 500 600 700 800 9001000

(Ω)

R

SOURCE

2413 F21

Figure 21. –FS Error vs R_SOURCEat IN⁺or IN^–(Large C_IN)

120

V

= 5V

CC

+

100

80

REF = 5V

–

A

B

REF = GND

IN = IN = V

+

–

INCM

60

40

C

D

E

F

20

0

–20

–40

–60

–80

–100

–120

G

F

= GND

O

A

T

= 25°C

R

C

– = 500Ω

SOURCEIN

= 10µF

In addition to this gain error, the converter INL perfor-

mance is degraded by the reference source impedance.

Wheninternaloscillatorisused(F_O=LOW), every100Ωof

source impedance driving REF⁺or REF^–translates into

about 1.2ppm additional INL error. When F_Ois driven by

an external oscillator with a frequency f_EOSC, every 100Ω

of source resistance driving REF⁺or REF^–translates into

IN

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

V

INCM

(V)

A: ∆R = +400Ω

E: ∆R = –100Ω

IN

B: ∆R = +200Ω

F: ∆R = –200Ω

IN

C: ∆R = +100Ω

G: ∆R = –400Ω

IN

D: ∆R = 0Ω

2413 F22

Figure 22. Offset Error vs Common Mode Voltage

(V_INCM= IN⁺= IN^–) and Input Source Resistance Imbalance

(∆R_IN= R_SOURCEIN+ – R_SOURCEIN–) for Large C_INValues (C_IN≥ 1µF)

about 8.73 • 10^–6• f_EOSCppm additional INL error.

sn2413 2413fs

27

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

Figure 27 shows the typical INL error due to the source

resistance driving the REF⁺or REF^–pins when large C_REF

values are used. The effect of the source resistance on the

tworeferencepinsisadditivewithrespecttothisINLerror.

In general, matching of source impedance for the REF⁺

and REF^–pins does not help the gain or the INL error. The

user is thus advised to minimize the combined source

impedance driving the REF⁺and REF^–pins rather than to

try to match it.

0.5%. Such a specification can also be easily achieved by

an external clock. When relatively stable resistors

(50ppm/°C) are used for the external source impedance

seen by REF⁺and REF^–, the expected drift of the dynamic

current gain error will be insignificant (about 1% of its

valueovertheentiretemperatureandvoltagerange). Even

for the most stringent applications, a one-time calibration

operation may be sufficient.

Inadditiontothereferencesamplingcharge,thereference

pinsESDprotectiondiodeshaveatemperaturedependent

leakage current. This leakage current, nominally 1nA

(±10nA max), results in a small gain error. A 100Ω source

resistance will create a 0.05µV typical and 0.5µV maxi-

mum full-scale error.

The magnitude of the dynamic reference current depends

upon the size of the very stable internal sampling capaci-

tors and upon the accuracy of the converter sampling

clock. The accuracy of the internal clock over the entire

temperature and power supply range is typical better than

0

50

C

= 0.01µF

REF

V

= 5V

CC

+

REF = 5V

C

= 0.001µF

REF

–

REF = GND

–10

–20

–30

–40

–50

40

30

20

10

0

+

–

C

= 100pF

IN = 5V

REF

IN = 2.5V

C

= 0pF

REF

F

= GND

= 25°C

O

A

T

V

= 5V

CC

+

–

REF = 5V

C

= 0.01µF

REF = GND

REF

+

–

IN = GND

C

= 0.001µF

REF

IN = 2.5V

F

= GND

O

C

= 100pF

REF

T

= 25°C

A

C

= 0pF

REF

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05

(Ω)

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05

(Ω)

R

SOURCE

2413 F23

2413 F24

Figure 23. +FS Error vs R_SOURCEat REF⁺or REF^–(Small C_REF

)

Figure 24. –FS Error vs R_SOURCEat REF⁺or REF^–(Small C_REF

)

0

450

C

= 0.01µF

= 0.1µF

REF

V

= 5V

CC

+

REF = 5V

C

REF

= 1µF, 10µF

–

REF = GND

–90

–180

–270

–360

–450

360

270

180

90

+

–

IN = 1.25V

IN = 3.75V

F

= GND

= 25°C

O

A

C

REF

T

V

= 5V

CC

C

REF

= 0.1µF

+

REF = 5V

–

REF = GND

+

–

IN = 3.75V

IN = 1.25V

C

REF

= 0.01µF

C

= 1µF, 10µF

REF

F

= GND

= 25°C

O

A

T

0

100 200 300 400 500 600 700 800 9001000

(Ω)

0

100 200 300 400 500 600 700 800 9001000

(Ω)

R

SOURCE

2413 F25

2413 F26

Figure 25. +FS Error vs R_SOURCEat REF⁺or REF^–(Large C_REF

)

Figure 26. –FS Error vs R_SOURCEat REF⁺or REF^–(Large C_REF

)

sn2413 2413fs

28

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

15

12

9

R

= 1000Ω

SOURCE

R

= 500Ω

6

SOURCE

3

0

–3

–6

–9

–12

–15

R

= 100Ω

SOURCE

–0.5–0.4–0.3–0.2–0.1

0

0.1 0.2 0.3 0.4 0.5

V

/V

INDIF REFDIF

V

= 5V

F = GND

O

CC

REF+ = 5V

C

= 10µF

REF

REF– = GND

V

T = 25°C

A

+

–

= 0.5 • (IN + IN ) = 2.5V

2413 F27

INCM

Figure 27. INL vs Differential Input Voltage (V_IN= IN⁺– IN^–)

and Reference Source Resistance (R_SOURCEat REF⁺and REF^–for

Large C_REFValues (C_REF≥ 1µF)

First, a change in f_EOSCwill result in a proportional change

in the internal notch position and in a reduction of the

converter differential mode rejection at the power-line

frequency. In many applications, the subsequent perfor-

mance degradation can be substantially reduced by rely-

ing upon the LTC2413’s exceptional common mode rejec-

tion and by carefully eliminating common mode to differ-

ential mode conversion sources in the input circuit. The

user should avoid single-ended input filters and should

maintain a very high degree of matching and symmetry in

the circuits driving the IN⁺and IN^–pins.

Output Data Rate

When using its internal oscillator, the LTC2413 can pro-

duceupto6.8readingspersecond. Theactualoutputdata

rate will depend upon the length of the sleep and data

output phases which are controlled by the user and which

can be made insignificantly short. When operated with an

external conversion clock (F_Oconnected to an external

oscillator), the LTC2413 output data rate can be increased

asdesired. Thedurationoftheconversionphaseis20510/

f_EOSC. If f_EOSC= 139800Hz, the converter behaves as if the

internal oscillator is used with simultaneous 50Hz/60Hz

rejection. ThereisnosignificantdifferenceintheLTC2413

performance between these two operation modes.

Second, the increase in clock frequency will increase

proportionally the amount of sampling charge transferred

through the input and the reference pins. If large external

input and/or reference capacitors (C_IN, C_REF) are used, the

previous section provides formulae for evaluating the

effect of the source resistance upon the converter perfor-

mance for any value of f_EOSC. If small external input and/

or reference capacitors (C_IN, C_REF) are used, the effect of

the external source resistance upon the LTC2413 typical

performance can be inferred from Figures 18, 19, 23 and

An increase in f_EOSCover the nominal 139800Hz will

translate into a proportional increase in the maximum

output data rate. This substantial advantage is neverthe-

less accompanied by three potential effects, which must

be carefully considered.

24 in which the horizontal axis is scaled by 139800/f_EOSC

.

sn2413 2413fs

29

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

Third, an increase in the frequency of the external oscilla-

torabove460800Hz(amorethan3×increaseintheoutput

data rate) will start to decrease the effectiveness of the

internal autocalibration circuits. This will result in a pro-

gressive degradation in the converter accuracy and linear-

ity. Typical measured performance curves for output data

rates up to 100 readings per second are shown in Fig-

ures 28 through 35, inclusive. In order to obtain the

highest possible level of accuracy from this converter at

output data rates above 20 readings per second, the user

is advised to maximize the power supply voltage used and

to limit the maximum ambient operating temperature. In

certaincircumstances, areductionofthedifferentialrefer-

ence voltage may be beneficial.

500

V

= 5V

450

400

350

300

250

200

150

100

50

CC

+

REF = 5V

–

REF = GND

V

O

= 2.5V

INCM

= 0V

IN

= EXTERNAL OSCILLATOR

F

T

= 85°C

A

T

A

= 25°C

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

2413 F28

Figure 28. Offset Error vs Output Data Rate and Temperature

7000

6000

5000

4000

3000

2000

1000

0

–1000

–2000

V

= 5V

CC

+

REF = 5V

–

T

= 85°C

REF = GND

A

+

–

IN = 3.75V

IN = 1.25V

T

A

= 25°C

F

O

= EXTERNAL OSCILLATOR

–3000

–4000

–5000

–6000

–7000

V

= 5V

CC

T

A

= 85°C

+

REF = 5V

–

REF = GND

+

–

IN = 1.25V

T

A

= 25°C

IN = 3.75V

F

= EXTERNAL OSCILLATOR

O

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

2413 F29

2413 F30

Figure 29. +FS Error vs Output Data Rate and Temperature

Figure 30. –FS Error vs Output Data Rate and Temperature

sn2413 2413fs

30

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

24

23

22

20

18

16

14

12

10

8

RESOLUTION = LOG (V /INL )

MAX

2

REF

T

= 25°C

A

21

20

19

18

17

16

15

14

13

12

T

= 85°C

T = 25°C

A

T

= 85°C

A

V

= 5V

CC

+

V

= 5V

REF = 5V

CC

+

–

REF = 5V

REF = GND

–

REF = GND

V

F

= 2.5V

INCM

V

= 2.5V

= 0V

INCM

IN

–2.5V < V < 2.5V

= EXTERNAL OSCILLATOR

RESOLUTION = LOG (V /NOISE )

RMS

IN

O

F

O

= EXTERNAL OSCILLATOR

2

REF

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

2413 F31

2413 F32

Figure 32. Resolution (INL_RMS≤ 1LSB)

vs Output Data Rate and Temperature

Figure 31. Resolution (Noise_RMS≤ 1LSB)

vs Output Data Rate and Temperature

250

24

23

V

= 5V

225

200

175

150

125

100

75

CC

V

= 5V

REF

+

REF = GND

22

21

20

19

18

17

16

15

14

13

12

V

= 2.5V

INCM

= 0V

V

= 2.5V

IN

REF

F

= EXTERNAL OSCILLATOR

= 25°C

O

A

T

V

= 5V

CC

–

REF = GND

V

= 5V

REF

V

F

= 2.5V

INCM

= 0V

IN

V

= 2.5V

REF

= EXTERNAL OSCILLATOR

= 25°C

50

O

T

A

25

RESOLUTION = LOG (V /NOISE )

RMS

2

REF

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

2413 F33

2413 F34

Figure 33. Offset Error vs Output

Data Rate and Reference Voltage

Figure 34. Resolution (Noise_RMS≤ 1LSB) vs

Output Data Rate and Reference Voltage

22

RESOLUTION =

LOG (V /INL

)

20

18

16

14

12

10

8

2

REF

MAX

V

= 2.5V

V

= 5V

REF

T

= 25°C

= 5V

A

CC

V

–

REF = GND

= 0.5 • REF

+

V

INCM

–0.5V • V

< V < 0.5 • V

REF

IN REF

F

= EXTERNAL OSCILLATOR

O

0

10 20 30 40 50 60 70 80 90 100

OUTPUT DATA RATE (READINGS/SEC)

2413 F35

Figure 35. Resolution (INL_MAX≤ 1LSB) vs Output Data Rate and Reference Voltage

sn2413 2413fs

31

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

Input Bandwidth

high gain, low bandwidth amplifier stage followed by a

high bandwidth unity-gain buffer.

The combined effect of the internal sinc⁴digital filter and

of the analog and digital autocalibration circuits deter-

mines the LTC2413 input bandwidth. When the internal

oscillator is used (F_O= LOW), the 3dB input bandwidth is

3.3Hz. If an external conversion clock generator of fre-

quency f_EOSCis connected to the F_Opin, the 3dB input

When external amplifiers are driving the LTC2413, the

ADCinputreferredsystemnoisecalculationcanbesimpli-

fied by Figure 37. The noise of an amplifier driving the

LTC2413 input pin can be modeled as a band limited white

noise source. Its bandwidth can be approximated by the

bandwidth of a single pole lowpass filter with a corner

frequency f_i. The amplifier noise spectral density is n_i.

From Figure 37, using f_ias the x-axis selector, we can find

on the y-axis the noise equivalent bandwidth freq_iof the

input driving amplifier. This bandwidth includes the band

limitingeffectsoftheADCinternalcalibrationandfiltering.

The noise of the driving amplifier referred to the converter

input and including all these effects can be calculated as

N = n_i• √freq_i. The total system noise (referred to the

LTC2413 input) can now be obtained by summing as

squarerootofsumofsquaresthethreeADCinputreferred

noise sources: the LTC2413 internal noise (800nV), the

noise of the IN⁺driving amplifier and the noise of the IN^–

driving amplifier.

bandwidth is 0.236 • 10^–6• f_EOSC

.

Due to the complex filtering and calibration algorithms

utilized,theconverterinputbandwidthisnotmodeledvery

accurately by a first order filter with the pole located at the

3dB frequency. When the internal oscillator is used, the

shape of the LTC2413 input bandwidth is shown in

Figure 36. When an external oscillator of frequency f_EOSC

is used, the shape of the LTC2413 input bandwidth can be

derived from Figure 36, in which the horizontal axis is

scaled by f_EOSC/139800.

The conversion noise (800nV_RMStypical for V_REF= 5V)

can be modeled as a white noise source connected to a

noisefreeconverter.Thenoisespectraldensityis63nV/√Hz

for an infinite bandwidth source and 77nV/√Hz for a single

0.5MHz pole source. From these numbers, it is clear that

particular attention must be given to the design of external

amplification circuits. Such circuits face the simultaneous

requirements of very low bandwidth (just a few Hz) in

order to reduce the output referred noise and relatively

high bandwidth (at least 500kHz) necessary to drive the

input switched-capacitor network. A possible solution is a

If the F_Opin is driven by an external oscillator of frequency

f_EOSC, Figure37canstillbeusedfornoisecalculationifthe

x-axis is scaled by f_EOSC/139800. For large values of the

ratio f_EOSC/139800, the Figure 37 plot accuracy begins to

decrease, but in the same time the LTC2413 noise floor

rises and the noise contribution of the driving amplifiers

lose significance.

1000

100

0.0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

–4.5

–5.0

–5.5

–6.0

F

= LOW

O

10

1

0.1

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

1

10 100 1k 10k 100k 1M

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

INPUT NOISE SOURCE SINGLE POLE

EQUIVALENT BANDWIDTH (Hz)

2413 F37

2413 F36

Figure 36. Input Signal Bandwidth Using the Internal Oscillator

Figure 37. Input Referred Noise Equivalent Bandwidth

of an Input Connected White Noise Source

sn2413 2413fs

32

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

Normal Mode Rejection and Antialiasing

the maximum output data rate. In the internal oscillator

mode, f_S= 13980Hz. In the external oscillator mode, f_S=

f_EOSC/10.

One of the advantages delta-sigma ADCs offer over con-

ventional ADCs is on-chip digital filtering. Combined with

a large oversampling ratio, the LTC2413 significantly

simplifies antialiasing filter requirements.

The sinc⁴digital filter provides greater than 120dB normal

mode rejection at all frequencies except DC and integer

multiples of the modulator sampling frequency (f_S). The

LTC2413’s autocalibration circuits further simplify the

antialiasing requirements by additional normal mode sig-

nal filtering both in the analog and digital domain. Inde-

pendent of the operating mode, f_S= 256 • f_N= 2048 •

f_OUTMAXwhere f_Nin the notch frequency and f_OUTMAXis

The combined normal mode rejection performance is

showninFigure 38. Theregionsoflowrejectionoccurring

at integer multiples of f_Shave a very narrow bandwidth.

Magnified details of the normal mode rejection curves are

shown in Figure 39 (rejection near DC) and Figure 40

(rejection at f_S= 256f_N) where f_Nrepresents the notch

frequency. These curves have been derived for the exter-

nal oscillator mode but they can be used in all operating

modes by appropriately selecting the f_Nvalue.

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

F

= LOW OR

O

= EXTERNAL OSCILLATOR,

f

= 10 • f

EOSC

S

0

f

2f 3f 4f 5f 6f 7f 8f 9f 10f

S S S S S S S S S S

DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)

2413 F38

Figure 38. Input Normal Mode Rejection

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

250f 252f 254f 256f 258f 260f 262f

N

0

f

2f

N

3f

4f

N

5f

6f

7f

8f

N

INPUT SIGNAL FREQUENCY (Hz)

2413 F40

2413 F39

Figure 39. Input Normal Mode Rejection

Figure 40. Input Normal Mode Rejection

sn2413 2413fs

33

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

The user can expect to achieve in practice this level of

performance using the internal oscillator, as it is demon-

strated by Figure 41. Typical measured values of the

normal mode rejection of the LTC2413 operating with the

internal oscillator are shown in Figure 41 superimposed

over the theoretical calculated curve.

Traditional high order delta-sigma modulators, while pro-

viding very good linearity and resolution, suffer from po-

tential instabilities at large input signal levels. The propri-

etaryarchitectureusedfortheLTC2413thirdordermodu-

lator resolves this problem and guarantees a predictable

stable behavior at input signal levels of up to 150% of full

scale. In many industrial applications, it is not uncommon

to have to measure microvolt level signals superimposed

over volt level perturbations and LTC2413 is eminently

suitedforsuchtasks.Whentheperturbationisdifferential,

the specification of interest is the normal mode rejection

for large input signal levels. With a reference voltage

As a result of these remarkable normal mode specifica-

tions, minimal (if any) antialias filtering is required in front

of the LTC2413. If passive RC components are placed in

front of the LTC2413, the input dynamic current should be

considered (see Input Current section). In cases where

large effective RC time constants are used, an external

buffer amplifier may be required to minimize the effects of

dynamic input current.

V

_REF= 5V, the LTC2413 has a full-scale differential input

0

–20

MEASURED DATA

CALCULATED DATA

V

= 5V

CC

+

REF = 5V

REF = GND

–

V

= 2.5V

INCM

–40

= 5V

IN(P-P)

T

= 25°C

A

–60

–80

–100

–120

0

20

40

60

80

100

120

140

160

180

200

220

INPUT FREQUENCY (Hz)

2413 F41

Figure 41. Input Normal Mode Rejection vs Input

Frequency with Input Perturbation of 100% of Full Scale

sn2413 2413fs

34

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

range of 5V peak-to-peak. Figure 42 shows measurement

results for the LTC2413 normal mode rejection ratio with

a 7.5V peak-to-peak (150% of full scale) input signal su-

perimposed over the more traditional normal mode rejec-

tion ratio results obtained with a 5V peak-to-peak (full

scale) input signal. It is clear that the LTC2413 rejection

performance is maintained with no compromises in this

extreme situation. When operating with large input signal

levels, the user must observe that such signals do not

violate the device’s absolute maximum ratings.

limited to 5V. This gives only 10mV full scale, which can

beresolvedto1partin10000withoutaveraging.Formany

solid state sensors, this is still better than the sensor. For

example, averaging 64 samples however reduces the

noise level by a factor of eight, bringing the resolving

power to 1 part in 80000, comparable to better weighing

systems. Hysteresis and creep effects in the load cells are

typically much greater than this. Most applications that

require strain measurements to this level of accuracy are

measuring slowly changing phenomena, hence the time

required to average a large number of readings is usually

not an issue. For those systems that require accurate

measurement of a small incremental change on a signifi-

cant tare weight, the lack of history effects in the LTC2400

family is of great benefit.

BRIDGE APPLICATIONS

Typical strain gauge based bridges deliver only 2mV/Volt

of excitation. As the maximum reference voltage of the

LTC2413 is 5V, remote sensing of applied excitation

without additional circuitry requires that excitation be

0

–20

V

= 5V

= 7.5V

V

= 5V

IN(P-P)

CC

+

REF = 5V

REF = GND

IN(P-P)

–

(150% OF FULL SCALE)

V

= 2.5V

INCM

= 25°C

–40

T

A

–60

–80

–100

–120

0

20

40

60

80

100

120

140

160

180

200

220

INPUT FREQUENCY (Hz)

2413 F42

Figure 42. Measured Input Normal Mode Rejection vs Input

Frequency with Input Perturbation of 150% of Full Scale

sn2413 2413fs

35

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

For those applications that cannot be fulfilled by the

LTC2413 alone, compensating for error in external ampli-

fication can be done effectively due to the “no latency”

feature of the LTC2413. No latency operation allows

samples of the amplifier offset and gain to be interleaved

withweighingmeasurements.Theuseofcorrelateddouble

sampling allows suppression of 1/f noise, offset and

thermocouple effects within the bridge. Correlated double

samplinginvolvesalternatingthepolarityofexcitationand

dealing with the reversal of input polarity mathematically.

Alternatively, bridge excitation can be increased to as

much as ±10V, if one of several precision attenuation

techniquesisusedtoproduceaprecisiondivideoperation

on the reference signal. Another option is the use of a

reference within the 5V input range of the LTC2413 and

developing excitation via fixed gain, or LTC1043 based

voltage multiplication, along with remote feedback in the

excitation amplifiers, as shown in Figures 48 and 50.

cells located at each load bearing point, the output of

which can be summed passively prior to the signal pro-

cessing circuitry, actively with amplification prior to the

ADC, or can be digitized via multiple ADC channels and

summed mathematically. The mathematical summation

oftheoutputofmultipleLTC2413’sprovidesthebenefitof

arootsquarereductioninnoise. Thelowpowerconsump-

tion of the LTC2413 makes it attractive for multidrop

communication schemes where the ADC is located within

the load-cell housing.

A direct connection to a load cell is perhaps best incorpo-

rated into the load-cell body, as minimizing the distance to

the sensor largely eliminates the need for protection

devices, RFI suppression and wiring. The LTC2413 exhib-

its extremely low temperature dependent drift. As a result,

exposure to external ambient temperature ranges does

not compromise performance. The incorporation of any

amplification considerably complicates thermal stability,

as input offset voltages and currents, temperature coeffi-

cient of gain settling resistors all become factors.

Figure 43 shows an example of a simple bridge connec-

tion. Note that it is suitable for any bridge application

where measurement speed is not of the utmost impor-

tance. For many applications where large vessels are

weighed, the average weight over an extended period of

time is of concern and short term weight is not readily

determined due to movement of contents, or mechanical

resonance.Often,largeweighingapplicationsinvolveload

The circuit in Figure 44 shows an example of a simple

amplification scheme. This example produces a differen-

tial output with a common mode voltage of 2.5V, as

determined by the bridge. The use of a true three amplifier

instrumentationamplifierisnotnecessary,astheLTC2413

LT1019

+

R1

2

V

REF

3

4

12

+

REF

SDO

350Ω

BRIDGE

13

–

SCK

5

11

+

IN

CS

LTC2413

6

14

–

IN

F

O

GND

R2

1, 7, 8, 9,

10, 15, 16

2413 F43

R1 AND R2 CAN BE USED TO INCREASE TOLERABLE AC COMPONENT ON REF SIGNALS

Figure 43. Simple Bridge Connection

sn2413 2413fs

36

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

has common mode rejection far beyond that of most

amplifiers. The LTC1051 is a dual autozero amplifier that

can be used to produce a gain of 15 before its input

referred noise dominates the LTC2413 noise. This ex-

ampleshowsagainof34, thatisdeterminedbyafeedback

network built using a resistor array containing 8 individual

resistors. The resistors are organized to optimize tem-

peraturetrackinginthepresenceofthermalgradients.The

second LTC1051 buffers the low noise input stage from

the transient load steps produced during conversion.

Figure 45 shows an example of a single amplifier used to

produce single-ended gain. This topology is best used in

applications where the gain setting resistor can be made

to match the temperature coefficient of the strain gauges.

If the bridge is composed of precision resistors, with only

one or two variable elements, the reference arm of the

bridgecanbemadetoactinconjunctionwiththefeedback

resistor to determine the gain. If the feedback resistor is

incorporated into the design of the load cell, using resis-

tors which match the temperature coefficient of the load-

cell elements, good results can be achieved without the

needforresistorswithahighdegreeofabsoluteaccuracy.

Thecommonmodevoltageinthiscase, isagainafunction

of the bridge output. Differential gain as used with a 350Ω

bridge is A_V= (R1+ R2)/(R1+175Ω). Common mode gain

is half the differential gain. The maximum differential

signal that can be used is 1/4 V_REF, as opposed to 1/2 V_REF

in the 2-amplifier topology above.

The gain stability and accuracy of this approach is very

good, due to a statistical improvement in resistor match-

ing due to individual error contribution being reduced. A

gain of 34 may seem low, when compared to common

practiceinearliergenerationsofload-cellinterfaces, how-

ever the accuracy of the LTC2413 changes the rationale.

Achieving high gain accuracy and linearity at higher gains

may prove difficult, while providing little benefit in terms

of noise reduction.

Remote Half Bridge Interface

At a gain of 100, the gain error that could result from

typical open-loop gain of 160dB is –1ppm, however,

worst-case is at the minimum gain of 116dB, giving a gain

error of –158ppm. Worst-case gain error at a gain of 34,

is –54ppm. The use of the LTC1051A reduces the worst-

case gain error to –33ppm. The advantage of gain higher

than 34, then becomes dubious, as the input referred

noiseseeslittleimprovement¹andgainaccuracyispoten-

tially compromised.

As opposed to full bridge applications, typical half bridge

applications must contend with nonlinearity in the bridge

output,assignalswingisoftenmuchgreater.Applications

include RTD’s, thermistors and other resistive elements

that undergo significant changes over their span. For

singlevariableelementbridges, thenonlinearityofthehalf

bridge output can be eliminated completely; if the refer-

ence arm of the bridge is used as the reference to the ADC,

as shown in Figure 46. The LTC2413 can accept inputs up

to 1/2 V_REF. Hence, the reference resistor R1 must be at

least 2x the highest value of the variable resistor.

Note that this 4-amplifier topology has advantages over

the typical integrated 3-amplifier instrumentation ampli-

fier in that it does not have the high noise level common in

the output stage that usually dominates when an instru-

mentation amplifier is used at low gain. If this amplifier is

used at a gain of 10, the gain error is only 10ppm and input

referred noise is reduced to 0.1µV_RMS. The buffer stages

canalsobeconfiguredtoprovidegainofupto50withhigh

gain stability and linearity.

In the case of 100Ω platinum RTD’s, this would suggest a

value of 800Ω for R1. Such a low value for R1 is not

advisable due to self-heating effects. A value of 25.5k is

shown for R1, reducing self-heating effects to acceptable

levels for most sensors.

¹Input referred noise for A_V= 34 for approximately 0.05µV_RMS, whereas at a gain of 50, it would be

0.048µV_RMS

.

sn2413 2413fs

37

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

The basic circuit shown in Figure 46 shows connections

for a full 4-wire connection to the sensor, which may be

located remotely. The differential input connections will

reject induced or coupled 60Hz interference, however, the

reference inputs do not have the same rejection. If 60Hz or

other noise is present on the reference input, a low pass

filterisrecommendedasshowninFigure47.Notethatyou

cannot place a large capacitor directly at the junction of R1

and R2, as it will store charge from the sampling process.

Abetterapproachistoproducealowpassfilterdecoupled

from the input lines with a high value resistor (R3).

higher frequencies, will be reduced. A filter can be intro-

duced into the network, in the form of one or more

capacitors,orferritebeads,aslongasthesamplingpulses

are not translated into an error. The reference voltage is

alsoreduced, butthisisnotundesirable, asitwilldecrease

the value of the LSB, although, not the input referred noise

level.

The circuit shown in Figure 47 shows a more rigorous

example of Figure 46, with increased noise suppression

and more protection for remote applications.

Figure48showsanexampleofgainintheexcitationcircuit

and remote feedback from the bridge. The LTC1043’s

provide voltage multiplication, providing ±10V from a 5V

reference with only 1ppm error. The amplifiers are used at

unity-gain and, hence, introduce a very little error due to

gainerrororduetooffsetvoltages.A1µV/°Coffsetvoltage

drift translates into 0.05ppm/°C gain error. Simpler alter-

natives, with the amplifiers providing gain using resistor

arrays for feedback, can produce results that are similar to

bridge sensing schemes via attenuators. Note that the

amplifiersmusthavehighopen-loopgainorgainerrorwill

The use of a third resistor in the half bridge, between the

variable and fixed elements gives essentially the same

result as the two resistor version, but has a few benefits.

If, for example, a 25k reference resistor is used to set the

excitation current with a 100Ω RTD, the negative refer-

ence input is sampling the same external node as the

positive input, but may result in errors if used with a long

cable. For short cable applications, the errors may be

acceptably low. If instead the single 25k resistor is re-

placed with a 10k 5% and a 10k 0.1% reference resistor,

the noise level introduced at the reference, at least at

5V

REF

0.1µF

5V

8

3

2

+

–

0.1µF

1

U1A

4

5V

2

8

2

3

350Ω

BRIDGE

–

+

V

CC

1

3

4

12

+

–

U2A

REF

SDO

15

14

4

5

12

13

SCK

1

4

RN1

16

5

11

+

6

11

7

10

8

9

IN

CS

2

3

13

LTC2413

6

5

6

5

–

+

–

+

7

6

14

–

IN

U2B

U1B

F

O

GND

1, 7, 8, 9,

10, 15, 16

2413 F44

RN1 = 5k × 8 RESISTOR ARRAY

U1A, U1B, U2A, U2B = 1/2 LTC1051

Figure 44. Using Autozero Amplifiers to Reduce Input Referred Noise

sn2413 2413fs

38

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

be a source of error. The fact that input offset voltage has

relatively little effect on overall error may lead one to use

low performance amplifiers for this application. Note that

the gain of a device such as an LF156, (25V/mV over

temperature) will produce a worst-case error of –180ppm

at a noise gain of 3, such as would be encountered in an

inverting gain of 2, to produce –10V from a 5V reference.

The circuits in Figures 48 and 50 could be used where

multiplebridgecircuitsareinvolvedandbridgeoutputcan

be multiplexed onto a single LTC2413, via an inexpensive

multiplexer such as the 74HC4052.

Figure 49 shows the use of an LTC2413 with a differential

multiplexer. This is an inexpensive multiplexer that will

contribute some error due to leakage if used directly with

the output from the bridge, or if resistors are inserted as

a protection mechanism from overvoltage. Although the

bridge output may be within the input range of the A/D and

multiplexer in normal operation, some thought should be

given to fault conditions that could result in full excitation

voltage at the inputs to the multiplexer or ADC. The use of

amplification prior to the multiplexer will largely eliminate

errors associated with channel leakage developing error

voltages in the source impedance.

The error associated with the 10V excitation would be

–80ppm. Hence, overall reference error could be as high

as 130ppm, the average of the two.

Figure 50 shows a similar scheme to provide excitation

using resistor arrays to produce precise gain. The circuit

is configured to provide 10V and –5V excitation to the

bridge, producing a common mode voltage at the input to

the LTC2413 of 2.5V, maximizing the AC input range for

applications where induced 60Hz could reach amplitudes

up to 2V_RMS

.

5V

+

10µF

0.1µF

5V

350Ω

2

BRIDGE

0.1µV

V

7

CC

3

2

3

4

+

–

+

REF

175Ω

1µF

6

LTC1050S8

+

–

20k

5

+

4

IN

1µF

R1

4.99k

R2

46.4k

LTC2413

6

–

IN

GND

1, 7, 8, 9,

10, 15, 16

R1 + R2

2413 F45

A

= 9.95 =

V

(

)

R1 + 175Ω

Figure 45. Bridge Amplification Using a Single Amplifier

sn2413 2413fs

39

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

V

S

2.7V TO 5.5V

2

V

CC

3

4

+

–

R1

25.5k

0.1%

REF

LTC2413

5

6

+

IN

PLATINUM

100Ω

RTD

–

GND

1, 7, 8, 9,

10, 15, 16

2413 F46

Figure 46. Remote Half Bridge Interface

5V

2

R2

V

10k

CC

3

4

+

–

0.1%

REF

+

R3

10k

5%

560Ω

1µF

R1

10k, 5%

LTC1050

–

LTC2413

10k

5

6

+

IN

PLATINUM

100Ω

–

RTD

GND

1, 7, 8, 9,

10, 15, 16

2413 F47

Figure 47. Remote Half Bridge Sensing with Noise Suppression on Reference

sn2413 2413fs

40

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

15V

U1

15V

7

LTC1043

4

200Ω

10V

5V

3

2

8

7

+

LT1236-5

10V

20Ω

*

6

+

Q1

2N3904

LTC1150

1µF

11

12

47µF

0.1µF

–

4

–15V

33Ω

14

13

10µF

0.1µF

1k

17

350Ω

BRIDGE

5V

0.1µF

2

V

CC

LTC2413

+

3

4

REF

–

REF

33Ω

5

6

+

IN

–

IN

U2

15V

7

GND

LTC1043

1, 7, 8, 9,

10, 15, 16

Q2

2N3906

3

2

5

15

8

6

+

*

6

LTC1150

2

3

20Ω

–

4

–15V

18

0.1µF

1k

*FLYING CAPACITORS ARE

1µF FILM (MKP OR EQUIVALENT)

5V

U2

LTC1043

4

SEE LTC1043 DATA SHEET FOR

DETAILS ON UNUSED HALF OF U1

7

*

11

12

1µF

FILM

200Ω

14

13

–10V

17

–10V

2413 F48

Figure 48. LTC1043 Provides Precise 4X Reference for Excitation Voltages

sn2413 2413fs

41

LTC2413

U

W U U

APPLICATIO S I FOR ATIO

5V

+

16

2

47µF

12

14

15

11

V

CC

3

4

+

–

REF

LTC2413

74HC4052

1

5

13

3

5

6

+

IN

–

2

4

TO OTHER

DEVICES

GND

6

1, 7, 8, 9,

10, 15, 16

8

9

10

A0

A1

2413 F49

Figure 49. Use a Differential Multiplexer to Expand Channel Capability

sn2413 2413fs

42

LTC2413

U

PACKAGE DESCRIPTIO

GN Package

16-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

TOP VIEW

1

16

15

14

13

12

11

10

9

GND

V

2

CC

+

3

4

5

6

7

8

F

REF

IN

O

–

+

–

SCK

SDO

CS

IN

GND

GN PACKAGE

16-LEAD PLASTIC SSOP

sn2413 2413fs

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will notinfringe onexisting patent rights.

43

LTC2413

U

TYPICAL APPLICATIO

15V

5V

3

2

+

LT1236-5

20Ω

1/2

LT1112

1

+

Q1

2N3904

C3

47µF

C1

0.1µF

–

C1

0.1µF

22Ω

RN1

10k

10V

5V

1

2

3

2

RN1

10k

V

CC

4

350Ω BRIDGE

TWO ELEMENTS

VARYING

LTC2413

+

3

REF

4

–

REF

5

6

+

IN

–5V

–

IN

8

RN1

10k

GND

1, 7, 8, 9,

10, 15, 16

RN1

10k

7

5

6

15V

C2

0.1µF

33Ω

×2

RN1 IS CADDOCK T914 10K-010-02

8

6

–

Q2, Q3

2N3906

×2

20Ω

1/2

LT1112

7

5

+

4

–15V

2413 F50

–15V

Figure 50. Use Resistor Arrays to Provide Precise Matching in Excitation Amplifier

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LT1019

Precision Bandgap Reference, 2.5V, 5V

Micropower Thermocouple Cold Junction Compensator

3ppm/°C Drift, 0.05% Max Initial Accuracy

80µA Supply Current, 0.5°C Initial Accuracy

Precise Charge, Balanced Switching, Low Power

LT1025

LTC1043

Dual Precision Instrumentation Switched Capacitor

Building Block

LTC1050

Precision Chopper Stabilized Op Amp

Precision Bandgap Reference, 5V

No External Components 5µV Offset, 1.6µV Noise

P-P

LT1236A-5

LT1460

0.05% Max Initial Accuracy, 5ppm/°C Drift

Micropower Series Reference

0.075% Max, 10ppm/°C Max Drift

LTC2400

24-Bit, No Latency ∆Σ ADC in SO-8

1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP

4-/8-Channel, 24-Bit, No Latency ∆Σ ADC

0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA

0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA

0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA

LTC2401/LTC2402

LTC2404/LTC2408

LTC2410

24-Bit, Fully Differential, No Latency ∆Σ ADC in SSOP-16 0.16ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA

LTC2411

24-Bit, Fully Differential, No Latency ∆Σ ADC in MS10

24-Bit, Fully Differential, ∆Σ ADC

0.29ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA

15Hz Output Rate at 60Hz Rejection, Pin Compatible with LTC2410

1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400

LTC2415

LTC2420

20-Bit, No Latency ∆Σ ADC in SO-8

LTC2424/LTC2428

4-/8-Channel, 20-Bit, No Latency ∆Σ ADC

1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2404/LTC2408

sn2413 2413fs

LT/TP 0501 4K • PRINTED IN USA

44 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

(408)432-1900 FAX:(408)434-0507 www.linear-tech.com

LINEAR TECHNOLOGY CORPORATION 2000


型号：	LTC2413IGN
厂家：	Linear
描述：	24-Bit No Latency ADC, with Simultaneous 50Hz/60Hz Rejection 24位无延迟的ADC ，具有同时抑制50Hz / 60Hz抑制
文件：	总44页 (文件大小：453K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2413IGN [Linear]

相关型号：

LTC2414

LTC2414CGN

LTC2414CGN#TR

LTC2414IGN

LTC2414_15

LTC2415

LTC2415-1CGN

LTC2415-1CGN#PBF

LTC2415-1CGN#TR

LTC2415-1CGN#TRPBF

LTC2415-1IGN

LTC2415-1IGN#TRPBF