LTC2435IGN#TRPBF [Linear]
LTC2435/LTC2435-1 - 20-Bit No Latency ΔΣ™ ADCs with Differential Input and Differential Reference; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C;型号: | LTC2435IGN#TRPBF |
厂家: | Linear |
描述: | LTC2435/LTC2435-1 - 20-Bit No Latency ΔΣ™ ADCs with Differential Input and Differential Reference; Package: SSOP; Pins: 16; Temperature Range: -40°C to 85°C 光电二极管 转换器 |
文件: | 总40页 (文件大小:463K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC2435/LTC2435-1
20-Bit No Latency ΔΣTM
ADCs with Differential Input and
Differential Reference
U
DESCRIPTIO
FEATURES
The LTC®2435/2435-1 are 2.7V to 5.5V micropower
20-bit differential ΔΣ analog to digital converters with
integrated oscillator, 3ppm INL and 0.8ppm RMS noise.
Theyusedelta-sigmatechnologyandprovidesinglecycle
settling time for multiplexed applications. Through a
single pin, the LTC2435 can be configured for better than
110dB input differential mode rejection at 50Hz or 60Hz
2%, oritcanbedrivenbyanexternaloscillatorforauser
defined rejection frequency. The LTC2435-1 can be con-
figured for better than 87dB input differential mode rejec-
tion over the range of 49Hz to 61.2Hz (50Hz and 60Hz
2% simultaneously). The internal oscillator requires no
external frequency setting components.
■
2× Speed Up Version of the LTC2430: 15Hz Output
Rate, 60Hz Notch—LTC2435; 13.75Hz Output Rate,
Simultaneous 50Hz/60Hz Notch—LTC2435-1
Differential Input and Differential Reference with
GND to VCC Common Mode Range
3ppm INL, No Missing Codes
10ppm Gain Error
0.8ppm Noise
Single Conversion Settling Time for Multiplexed
Applications
Internal Oscillator—No External Components
Required
■
■
■
■
■
■
■
■
■
Single Supply 2.7V to 5.5V Operation
Low Supply Current (200μA,4μA in Auto Sleep)
20-Bit ADC in Narrow SSOP-16 Package
(SO-8 Footprint)
The converters accept any external differential reference
voltage from 0.1V to VCC for flexible ratiometric and
remote sensing measurement configurations. The full-
scale differential input range is from –0.5VREF to 0.5VREF
.
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The reference common mode voltage, VREFCM, and the
input common mode voltage, VINCM, may be indepen-
dently set anywhere within the GND to VCC range of the
LTC2435/LTC2435-1. The DC common mode input rejec-
tion is better than 120dB.
APPLICATIO S
■
Direct Sensor Digitizer
■
Weight Scales
■
Direct Temperature Measurement
■
Gas Analyzers
The LTC2435/LTC2435-1 communicate through a flexible
3-wire digital interface which is compatible with SPI and
MICROWIRETM protocols.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
No Latency ΔΣ is a trademark of Linear Technology Corporation.
Protected by U.S. Patents including 6140950, 6169506.
■
Strain Gage Transducers
■
Instrumentation
Data Acquisition
■
■
Industrial Process Control
■
6-Digit DVMs
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Integral Nonlinearity vs Input
TYPICAL APPLICATIO S
10
8
6
2.7V TO 5.5V
V
CC
1μF
4
2
= INTERNAL OSC/50Hz REJECTION (LTC2435)
2
14
T
T
= 25°C
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION (LTC2435)
= INTERNAL 50Hz/60Hz REJECTION (LTC2435-1)
A
V
F
CC
LTC2435/
O
T
= 85°C
A
0
LTC2435-1
–2
–4
–6
–8
–10
3
4
= –45°C
+
A
13
REFERENCE
VOLTAGE
REF
REF
SCK
–
0.1V TO V
F
= GND
CC
O
3-WIRE
SPI INTERFACE
V
V
V
= 5V
CC
REF
INCM
5
6
12
11
+
ANALOG INPUT RANGE
= 5V
= V
IN
SDO
CS
–0.5V
TO 0.5V
= 2.5V
–0.5
REF
REF
INCM
–
IN
1, 7, 8, 9, 10, 15, 16
–2.5
–1.5
0.5
1.5
2.5
GND
2435 TA01
INPUT VOLTAGE (V)
2435 G04
24351fb
1
LTC2435/LTC2435-1
W W
U W
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ABSOLUTE AXI U RATI GS
PI CO FIGURATIO
(Notes 1, 2)
TOP VIEW
Supply Voltage (VCC) to GND.......................–0.3V to 7V
Analog Input Pins Voltage to GND ...–0.3V to (VCC + 0.3V)
Reference Input Pins Voltage
to GND.................................... –0.3V to (VCC + 0.3V)
Digital Input Voltage to GND........ –0.3V to (VCC + 0.3V)
Digital Output Voltage to GND ..... –0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2435C/LTC2435-1C........................... 0°C to 70°C
LTC2435I/LTC2435-1I ........................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
1
16
15
14
13
12
11
10
9
GND
GND
2
GND
V
CC
+
3
4
5
6
7
8
F
O
REF
REF
IN
–
+
–
SCK
SDO
CS
IN
GND
GND
GND
GND
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 95°C/W
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W
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ORDER I FOR ATIO
LEAD FREE FINISH
LT2435CGN#PBF
LT2435IGN#PBF
LT2435-1CGN#PBF
LT2435-1IGN#PBF
TAPE AND REEL
PART MARKING
2435
2435I
PACKAGE DESCRIPTION
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
16-Lead Plastic SSOP
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
LTC2435CGN#TRPBF
LTC2435CGN#TRPBF
LTC2435-1CGN#TRPBF
LTC2435-1IGN#TRPBF
24351
24351I
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Bits
Resolution (No Missing Codes) 0.1V ≤ V ≤ V , –0.5 • V ≤ V ≤ 0.5 • V , (Note 5)
●
●
●
20
REF
CC
REF
IN
–
REF
+
Integral Nonlinearity
5V ≤ V ≤ 5.5V, REF = 2.5V, REF = GND, V
= 1.25V, (Note 6)
2
3
10
ppm of V
ppm of V
ppm of V
CC
INCM
REF
REF
REF
+
–
5V ≤ V ≤ 5.5V, REF = 5V, REF = GND, V
= 2.5V, (Note 6)
= 1.25V, (Note 6)
INCM
20
5
CC
INCM
+
–
2.7V ≤ V ≤ 5.5V, REF = 2.5V, REF = GND, V
CC
+
–
Offset Error
2.5V ≤ REF ≤ V , REF = GND,
2
100
10
0.1
10
0.1
4
mV
CC
+
–
GND ≤ IN = IN ≤ V , (Note 14)
CC
+
–
Offset Error Drift
Positive Gain Error
Positive Gain Error Drift
Negative Gain Error
Negative Gain Error Drift
Output Noise
2.5V ≤ REF ≤ V , REF = GND,
nV/°C
CC
+
–
GND ≤ IN = IN ≤ V
CC
+
–
2.5V ≤ REF ≤ V , REF = GND,
●
●
25
25
ppm of V
REF
CC
+
+
–
+
+
IN = 0.75REF , IN = 0.25 • REF
+
–
2.5V ≤ REF ≤ V , REF = GND,
ppm of V /°C
CC
REF
+
+
–
IN = 0.75REF , IN = 0.25 • REF
+
–
2.5V ≤ REF ≤ V , REF = GND,
ppm of V
CC
REF
+
+
–
+
+
IN = 0.25 • REF , IN = 0.75 • REF
+
–
2.5V ≤ REF ≤ V , REF = GND,
ppm of V /°C
CC
REF
+
+
–
IN = 0.25 • REF , IN = 0.75 • REF
+
–
5V ≤ V ≤ 5.5V, REF = 5V, REF = GND,
μV
RMS
CC
–
+
GND ≤ IN = IN ≤ V , (Note 13)
CC
24351fb
2
LTC2435/LTC2435-1
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CO VERTER CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
–
Input Common Mode Rejection DC 2.5V ≤ REF ≤ V , REF = GND,
●
●
●
●
●
●
●
●
●
●
110
120
dB
CC
–
+
GND ≤ IN = IN ≤ V (Note 5)
CC
+
–
Input Common Mode Rejection
60Hz 2% (LTC2435)
2.5V ≤ REF ≤ V , REF = GND,
140
140
110
110
120
87
dB
dB
dB
dB
dB
dB
dB
dB
dB
CC
–
+
GND ≤ IN = IN ≤ V , (Notes 5, 7)
CC
+
–
Input Common Mode Rejection
50Hz 2% (LTC2435)
2.5V ≤ REF ≤ V , REF = GND,
CC
–
+
GND ≤ IN = IN ≤ V , (Notes 5, 8)
CC
Input Normal Mode Rejection
60Hz 2% (LTC2435)
(Notes 5, 7)
(Notes 5, 8)
120
120
Input Normal Mode Rejection
50Hz 2% (LTC2435)
+
–
Input Common Mode Rejection
49Hz to 61.2Hz (LTC2435-1)
2.5V ≤ REF ≤ V , REF = GND,
CC
–
+
GND ≤ IN = IN ≤ V , (Notes 5, 7)
CC
Input Normal Mode Rejection
49Hz to 61.2Hz (LTC2435-1)
F = GND (Note 5)
O
Input Normal Mode Rejection
External Oscillator (Note 5)
87
External Clock f
/2560 14%
EOSC
Input Normal Mode Rejection
External Clock f /2560 4%
External Oscillator (Note 5)
110
130
120
140
EOSC
+
–
Reference Common Mode
Rejection DC
2.5V ≤ REF ≤ V , GND ≤ REF ≤ 2.5V,
CC
–
+
V
= 2.5V, IN = IN = GND (Note 5)
REF
+
–
–
+
Power Supply Rejection, DC
REF = V , REF = GND, IN = IN = GND
100
120
120
dB
dB
dB
CC
+
–
–
+
Power Supply Rejection, 60Hz 2% REF = 2.5V, REF = GND, IN = IN = GND, (Note 7)
+
–
–
+
Power Supply Rejection, 50Hz 2% REF = 2.5V, REF = GND, IN = IN = GND, (Note 8)
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U
U
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A ALOG I PUT A D REFERE CE The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
+
IN
Absolute/Common Mode IN Voltage
●
●
●
GND – 0.3V
GND – 0.3V
V
V
+ 0.3V
V
V
V
CC
CC
–
–
IN
Absolute/Common Mode IN Voltage
+ 0.3V
/2
V
Input Differential Voltage Range
–V /2
REF
V
REF
IN
+
–
(IN – IN )
+
–
+
REF
REF
Absolute/Common Mode REF Voltage
●
●
●
0.1
GND
0.1
V
V
V
V
CC
–
Absolute/Common Mode REF Voltage
V
– 0.1V
CC
V
Reference Differential Voltage Range
V
CC
REF
+
–
(REF – REF )
+
+
C (IN )
IN Sampling Capacitance
1.5
1.5
1.5
1.5
1
pF
pF
pF
pF
nA
nA
nA
nA
S
–
–
C (IN )
IN Sampling Capacitance
S
+
+
C (REF )
REF Sampling Capacitance
S
–
–
C (REF )
REF Sampling Capacitance
S
+
+
+
I
I
I
I
(IN )
IN DC Leakage Current
CS = V , IN = GND
●
●
●
●
–10
–10
–10
–10
10
DC_LEAK
DC_LEAK
DC_LEAK
DC_LEAK
CC
–
–
–
(IN )
IN DC Leakage Current
CS = V , IN = V
1
10
10
10
CC
CC
+
+
+
(REF )
REF DC Leakage Current
CS = V , REF = V
1
CC
CC
–
–
–
(REF )
REF DC Leakage Current
CS = V , REF = GND
1
CC
24351fb
3
LTC2435/LTC2435-1
U
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
High Level Input Voltage
2.7V ≤ V ≤ 5.5V
●
●
●
●
●
●
2.5
2.0
V
V
IH
CC
CS, F
2.7V ≤ V ≤ 3.3V
O
CC
V
IL
Low Level Input Voltage
4.5V ≤ V ≤ 5.5V
0.8
0.6
V
V
CC
CS, F
2.7V ≤ V ≤ 5.5V
O
CC
V
IH
High Level Input Voltage
SCK
2.7V ≤ V ≤ 5.5V (Note 9)
2.5
2.0
V
V
CC
2.7V ≤ V ≤ 3.3V (Note 9)
CC
V
IL
Low Level Input Voltage
SCK
4.5V ≤ V ≤ 5.5V (Note 9)
0.8
0.6
V
V
CC
2.7V ≤ V ≤ 5.5V (Note 9)
CC
I
Digital Input Current
0V ≤ V ≤ V
CC
–10
–10
10
μA
μA
pF
pF
V
IN
IN
CS, F
O
I
Digital Input Current
SCK
0V ≤ V ≤ V (Note 9)
10
IN
IN
CC
C
C
V
V
V
V
I
Digital Input Capacitance
10
10
IN
CS, F
O
Digital Input Capacitance
SCK
(Note 9)
IN
High Level Output Voltage
SDO
I = –800μA
O
●
●
●
●
●
V
V
– 0.5
OH
OL
OH
OL
CC
CC
Low Level Output Voltage
SDO
I = 1.6mA
O
0.4
V
High Level Output Voltage
SCK
I = –800μA (Note 10)
O
– 0.5
V
Low Level Output Voltage
SCK
I = 1.6mA (Note 10)
O
0.4
10
V
Hi-Z Output Leakage
SDO
–10
μA
OZ
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POWER REQUIRE E TS
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
Supply Voltage
Supply Current
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
●
2.7
5.5
V
I
CC
Conversion Mode
Sleep Mode
Sleep Mode
CS = 0V (Note 12)
●
●
●
200
4
2
300
10
μA
μA
μA
CS = V (Note 12)
CC
CS = V , 2.7V ≤ V ≤ 3.3V (Note 12)
CC
CC
24351fb
4
LTC2435/LTC2435-1
W U
TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
5
TYP
MAX
2000
200
UNITS
kHz
μs
f
t
t
t
External Oscillator Frequency Range
External Oscillator High Period
External Oscillator Low Period
Conversion Time (LTC2435)
●
●
●
EOSC
HEO
0.25
0.25
200
μs
LEO
F = 0V
●
●
●
65.6
78.7
66.9
80.3
EOSC
73.5
EOSC
68.3
81.9
(in kHz)
ms
ms
ms
CONV
O
F = V
O
CC
External Oscillator (Note 11)
10278/f
10278/f
Conversion Time (LTC2435-1)
Internal SCK Frequency
F = 0V
●
●
72
45
75
(in kHz)
ms
ms
O
External Oscillator (Note 11)
f
Internal Oscillator (Note 10), LTC2435
Internal Oscillator (Note 10), LTC2435-1
External Oscillator (Notes 10, 11)
19.2
17.5
kHz
kHz
kHz
ISCK
f
/8
EOSC
D
ISCK
Internal SCK Duty Cycle
(Note 10)
(Note 9)
(Note 9)
(Note 9)
●
●
●
●
55
%
kHz
ns
f
t
t
t
External SCK Frequency Range
External SCK Low Period
External SCK High Period
2000
ESCK
250
250
LESCK
ns
HESCK
DOUT_ISCK
Internal SCK 24-Bit Data Output Time Internal Oscillator (Notes 10, 12), LTC2435
Internal Oscillator (Notes 10, 12), LTC2435-1
●
●
●
1.22
1.34
1.25
1.37
1.28
1.40
ms
ms
ms
External Oscillator (Notes 10, 11)
192/f
(in kHz)
EOSC
t
t
External SCK 24-Bit Data Output Time (Note 9)
CS ↓ to SDO Low Z
●
●
●
●
●
●
●
●
●
24/f
(in kHz)
ms
ns
ns
ns
ns
ns
ns
ns
ns
DOUT_ESCK
1
ESCK
0
0
200
200
200
t2
t3
t4
t
CS ↑ to SDO High Z
CS ↓ to SCK ↓
(Note 10)
(Note 9)
0
CS ↓ to SCK ↑
50
SCK ↓ to SDO Valid
SDO Hold After SCK ↓
SCK Set-Up Before CS ↓
SCK Hold After CS ↓
220
50
KQMAX
t
(Note 5)
15
50
KQMIN
t
t
5
6
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz 2%
(external oscillator).
Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is fESCK and is expressed in kHz.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7 to 5.5V unless otherwise specified.
Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance CLOAD = 20pF.
VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2;
V
IN = IN+ – IN–, VINCM = (IN+ + IN–)/2.
Note 4: FO pin tied to GND or to VCC or to external conversion clock
Note 11: The external oscillator is connected to the FO pin. The external
source with fEOSC = 153600Hz unless otherwise specified.
oscillator frequency, fEOSC, is expressed in kHz.
Note 5: Guaranteed by design, not subject to test.
Note 12: The converter uses the internal oscillator.
FO = 0V or FO = VCC
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Refer to Offset Accuracy and Drift in the Applications
.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band.
Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz 2%
(external oscillator) for the LTC2435 or fEOSC = 139800Hz 2% for the
LTC2435-1.
Information section.
24351fb
5
LTC2435/LTC2435-1
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TYPICAL PERFOR A CE CHARACTERISTICS
Total Unadjusted Error (VCC = 5V,
REF = 5V)
Total Unadjusted Error (VCC = 5V,
VREF = 2.5V)
Total Unadjusted Error (VCC = 2.7V,
VREF = 2.5V)
V
–680
–685
–690
–695
–700
–705
–710
–320
–330
–340
–350
–360
–340
–345
–350
–355
–360
F
= GND
O
F
= GND
= 2.7V
F
= GND
= 5V
O
CC
O
CC
V
V
V
= 5V
V
V
CC
REF
= 2.5V
V
V
= 2.5V
= V = 1.25V
INCM
V
V
= 5V
= V
REF
REF
INCM
T
= –45°C
= V = 1.25V
A
T
= –45°C
= 2.5V
INCM
INCM
INCM
A
INCM
T = –45°C
A
T
= 25°C
A
T
A
= 25°C
T
A
= 25°C
T
= 85°C
A
T
A
= 85°C
T
A
= 85°C
–1.25 –0.75 –0.25
0.25
0.75
1.25
–1.25 –0.75 –0.25
0.25
0.75
1.25
–2.5
–1.5
–0.5
0.5
1.5
2.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2435 G02
2435 G03
2435 G01
Integral Nonlinearity (VCC = 5V,
VREF = 5V)
Integral Nonlinearity (VCC = 5V,
VREF = 2.5V)
Integral Nonlinearity (VCC = 2.7V,
VREF = 2.5V)
10
8
3
2
10
8
F
= GND
= 2.7V
O
CC
V
V
V
= 2.5V
REF
INCM
6
6
= V
= 1.25V
INCM
T
A
= 25°C
T
= –45°C
A
4
4
1
T
T
= 25°C
A
2
T
A
= –45°C
2
T
= 85°C
A
0
0
0
–2
–4
–6
–8
–10
– 2
– 4
– 6
– 8
–10
T
A
= 85°C
= –45°C
A
T
= 85°C
A
–1
–2
–3
T
= 25°C
A
F
= GND
= 5V
F
= GND
= 5V
REF
INCM
O
CC
O
CC
V
V
V
V
V
V
= 5V
= V
= 2.5V
= V
REF
INCM
= 2.5V
–0.5
= 1.25V
INCM
INCM
–2.5
–1.5
0.5
1.5
2.5
–1.25 –0.75 –0.25
0.25
0.75
1.25
–1.25 –0.75 –0.25
0.25
0.75
1.25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2435 G04
2435 G05
2435 G06
Noise Histogram (Output Rate =
15Hz, VCC = 2.7V, VREF = 2.5V)
Noise Histogram (Output Rate =
15Hz, VCC = 5V, VREF = 5V)
14
12
10
8
30
10,000 CONSECUTIVE READINGS
10,000 CONSECUTIVE READINGS
V
V
= 5V
= 5V
V
V
V
V
F
= 2.7V
= 2.5V
GAUSSIAN
CC
CC
REF
IN
DISTRIBUTION
m = –365ppm
σ = 1.55ppm
25 REF
GAUSSIAN
V
V
F
= 0V
= 0V
IN
DISTRIBUTION
m = –325.4ppm
σ = 0.79ppm
= 2.5V
= 2.5V
INCM
INCM
20
15
10
5
= GND
= 25°C
= GND
O
A
O
T
T
A
= 25°C
6
4
2
0
0
–372 –370 –368 –366 –364 –362 –360 –358
OUTPUT CODE (ppm OF V
–330 –329–328 –327–326 –325–324–323–322–321
OUTPUT CODE(ppm OF V
)
)
REF
REF
2435 G08
2435 G07
24351fb
6
LTC2435/LTC2435-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
RMS Noise vs Input Differential
Voltage
RMS Noise vs VINCM
RMS Noise vs Temperature (TA)
5.0
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
F
= GND
= 5V
F
= GND
V
V
V
F
= 5V
= 5V
O
CC
O
CC
REF
+
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
V
V
V
V
REF = 5V
–
= 5V
REF = GND
T
V
V
V
= 2.5V
REF
INCM
= 0V
= 25°C
= GND
IN
INCM
A
O
= GND
= 5V
T
= 25°C
CC
A
= 0V
IN
INCM
= GND
–50
0
25
50
75
100
–25
–0.5
–1
0
1
2
3
4
5
6
–2.5 –2 –1.5 –1
0
0.5
1
1.5
2
2.5
TEMPERATURE (°C)
V
(V)
INPUT DIFFERENTIAL VOLTAGE (V)
INCM
2435 G12
2435 G11
2435 G10
RMS Noise vs VCC = VREF
RMS Noise vs VREF
Offset Error vs VINCM
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
–320
–322
–324
–326
–328
–330
–332
–334
–336
–338
–340
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
F
= GND
F
= GND
O
O
–
+
REF = GND
REF = V
CC
–
T
= 25°C
REF = GND
T
V
V
A
V
V
V
= 5V
= 25°C
CC
A
= 0V
= 0V
IN
INCM
IN
= GND
= GND
INCM
V
= 5V
CC
+
REF = 5V
–
REF = GND
V
= 0V
IN
F
= GND
O
A
T
= 25°C
0
2
V
3
(V)
4
5
–1
1
2
3
(V)
4
6
2.7
3.5 3.9 4.3
(V)
4.7 5.1 5.5
1
0
5
3.1
V
V
INCM
REF
CC
2435 G14
2435 G15
2435 G13
Offset Error vs Temperature
Offset Error vs VCC = VREF
Offset Error vs VREF
–320
–322
–324
–326
–328
–330
–332
–334
–336
–338
–340
–320
–322
–324
–326
–328
–330
–332
–334
–336
–338
–340
–1.60
–1.61
–1.62
–1.63
–1.64
–1.65
–1.66
–1.67
–1.68
–1.69
–1.70
+
REF = V
CC
V
V
V
V
F
= 5V
CC
–
REF = GND
= 5V
REF
V
V
F
= 0V
= 0V
IN
INCM
IN
INCM
= GND
= GND
= GND
= GND
O
O
T
= 25°C
A
F
= GND
O
–
REF = GND
T
= 25°C
A
V
V
V
= 5V
= 0V
CC
IN
= GND
INCM
–45 –30 –15
0
15 30 45 60 75 90
TEMPERATURE (°C)
0
2
V
3
(V)
4
5
2.7 3.1
3.5 3.9 4.3 4.7 5.1 5.5
(V)
1
V
CC
REF
2435 G16
2435 G17
2435 G18
24351fb
7
LTC2435/LTC2435-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Full-Scale Error vs Temperature
Full-Scale Error vs VCC
+Full-Scale Gain Error vs VCC
20
15
10
5
–330
–340
–350
–360
–370
–300
–400
–500
–600
–700
–800
–900
V
= 2.5V
V
= 2.5V
REF
REF
–
F
= GND
–
O
+FS ERROR
REF = GND
REF = GND
V
V
V
= 5V
CC
REF
V
F
= 0.5V
V
F
A
= 0.5V
= GND
= 25°C
INCM
REF
INCM
O
REF
= 5V
= GND
O
= 2.5V
INCM
T
= 25°C
T
A
+FS ERROR
–FS ERROR
–FS ERROR
0
–5
4.3
(V)
5.1
5.5
2.7 3.1
3.5 3.9
4.7
4.7
2.7 3.1
3.5 3.9 4.3
(V)
5.1 5.5
–60
–40
0
20 40 60
TEMPERATURE (°C)
100
–20
80
V
V
CC
CC
2435 G21
2435 G20
2435 G19
PSRR vs Frequency at VCC
(LTC2435-1)
PSRR vs Frequency at VCC
(LTC2435-1)
PSRR vs Frequency at VCC
(LTC2435-1)
0
–20
0
0
–20
V
= 4.1V
DC
V
= 4.1V
1.4V
V
= 4.1V
0.7V
CC
CC
DC
CC
DC
+
+
+
REF = 2.5V
REF = 2.5V
REF = 2.5V
–
–
–
–20
REF = GND
IN = GND
IN = GND
REF = GND
IN = GND
IN = GND
REF = GND
IN = GND
–40 IN = GND
+
–
+
–
+
–
–40
–40
F
= GND
= 25°C
F
= GND
= 25°C
F
= GND
= 25°C
O
O
O
T
T
T
A
A
A
–60
–60
–80
–60
–80
–80
–100
–120
–140
–100
–120
–140
–100
–120
–140
1
100 1000 10000 1000001000000
13800
13850
13900
13950
14000
10
0
60 80 100 120 140 160 180 200 220
20 40
FREQUENCY AT V (Hz)
FREQUENCY AT V (Hz)
CC
CC
FREQUENCY AT V (Hz)
CC
2435 G23
2435 G24
2435 G22
PSRR vs Frequency at VCC
(LTC2435)
PSRR vs Frequency at VCC
(LTC2435)
PSRR vs Frequency at VCC
(LTC2435)
0
–20
0
–20
0
–20
V
= 4.1V
DC
V
= 4.1V
1.4V
V
= 4.1V
0.7V
DC
CC
CC
DC
CC
+
+
+
REF = 2.5V
REF = 2.5V
REF = 2.5V
–
–
–
REF = GND
IN = GND
IN = GND
REF = GND
IN = GND
IN = GND
REF = GND
IN = GND
IN = GND
+
–
+
–
+
–
–40
–40
–40
F
= GND
= 25°C
F
= GND
= 25°C
F
= GND
O
A
O
A
O
T
T
T
= 25°C
A
–60
–60
–60
–80
–80
–80
–100
–120
–140
–100
–120
–140
–100
–120
–140
1
100 1000 10000 1000001000000
10
15300
15350
15450
0
80
120
160
200
240
15250
15400
40
FREQUENCY AT V (Hz)
FREQUENCY AT V (Hz)
CC
FREQUENCY AT V (Hz)
CC
CC
2435 G26
2435 G25
2435 G27
24351fb
8
LTC2435/LTC2435-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Conversion Current vs
Temperature
Conversion Current vs
Output Data Rate
Sleep-Mode Current vs
Temperature
240
230
220
210
200
190
180
170
160
1000
900
800
700
600
500
400
300
200
100
6
V
= V
CC
REF
F = GND
O
V
V
= 5.5V
= 5V
CC
CC
+
IN = GND
CS = V
CC
–
IN = GND
5
4
3
2
1
0
SCK = NC
SDO = NC
SCK = NC
SDO = NC
SDI = GND
CS = GND
V
= 5V
CC
V
= 5.5V
CC
F
= GND
O
CS = GND
SCK = NC
SDO = NC
F
= EXT OSC
= 25°C
O
A
T
V
V
= 5V
= 3V
CC
CC
V
= 3V
CC
V
V
= 3V
CC
CC
V
= 2.7V
= 2.7V
CC
0
15 30 45 60 75 90
–45 –30 –15
40
50 60 70 80 90 100
0
10 20 30
0
15 30 45 60 75 90
–45 –30 –15
TEMPERATURE (°C)
OUTPUT DATA RATE (READINGS/SEC)
TEMPERATURE (°C)
2435 G28
2435 G29
2435 G30
Offset Change* vs Output Data
Rate
Resolution (NoiseRMS ≤ 1LSB) vs
Output Data Rate
Resolution (INLMAX ≤ 1LSB) vs
Output Data Rate
22
21
20
19
18
17
16
15
21
20
19
18
17
16
15
14
50
40
V
V
= V
REFCM
INCM
= 0V
IN
–
REF = GND
= EXT OSC
= 25°C
V
= V
= 5V
REF
CC
V
= V
REF
= 5V
30
CC
F
O
A
T
20
V
= V = 5V
REF
V
V
= 2.7V
= 2.5V
10
CC
V
V
= 2.7V
= 2.5V
CC
REF
CC
REF
0
–10
–20
–30
–40
–50
V
V
= V
REFCM
V
V
= V
REFCM
INCM
= 0V
INCM
= 0V
V
V
= 2.7V
= 2.5V
CC
IN
IN
REF
–
–
REF = GND
= EXT OSC
= 25°C
REF = GND
= EXT OSC
F
F
O
O
T
T
= 25°C
A
A
* RELATIVE TO OFFSET AT
NORMAL OUTPUT RATE
RES = LOG (V /NOISE
)
RES = LOG (V /INL
)
2
REF
RMS
2
REF
MAX
80
0
20 40 60
100 120 140 160 180 200
80
0
20 40 60
100 120 140 160 180 200
80
100 120 140 160 180 200
0
20 40 60
OUTPUT DATA RATE (READINGS/SEC)
OUTPUT DATA RATE (READINGS/SEC)
OUTPUT DATA RATE (READINGS/SEC)
2435 G32
2435 G33
2435 G31
24351fb
9
LTC2435/LTC2435-1
U
U
U
PI FU CTIO S
GND (Pins 1, 7, 8, 9, 10, 15, 16): Ground. Multiple ground SDO (Pin 12): Three-State Digital Output. During the Data
pins internally connected for optimum ground current flow Output period, this pin is used as serial data output. When
and VCC decoupling. Connect each one of these pins to a the chip select CS is HIGH (CS = VCC) the SDO pin is in a
groundplanethroughalowimpedanceconnection.Allseven high impedance state. During the Conversion and Sleep
pins must be connected to ground for proper operation.
periods, this pin is used as the conversion status output.
TheconversionstatuscanbeobservedbypullingCSLOW.
VCC (Pin 2): Positive Supply Voltage. Bypass to GND
(Pin 1) with a 10μF tantalum capacitor in parallel with SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
0.1μF ceramic capacitor as close to the part as possible.
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as digital input for the external serial interface
clock during the Data Output period. A weak internal pull-
up is automatically activated in Internal Serial Clock Op-
eration mode. The Serial Clock Operation mode is deter-
mined by the logic level applied to the SCK pin at power up
or during the most recent falling edge of CS.
REF+ (Pin 3), REF– (Pin 4): Differential Reference Input.
ThevoltageonthesepinscanhaveanyvaluebetweenGND
and VCC as long as the reference positive input, REF+, is
maintained more positive than the reference negative
input, REF –, by at least 0.1V.
IN+ (Pin 5), IN– (Pin 6): Differential Analog Input. The
voltage on these pins can have any value between
GND – 0.3V and VCC + 0.3V. Within these limits the
converter bipolar input range (VIN = IN+ – IN–) extends
from–0.5•(VREF)to0.5•(VREF). Outsidethisinputrange
the converter produces unique overrange and underrange
output codes.
FO (Pin 14): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. WhentheFO pinisconnectedtoVCC (LTC2435only),
the converter uses its internal oscillator and the digital
filter first null is located at 50Hz. When the FO pin is
connectedtoGND(FO =OV),theconverterusesitsinternal
oscillator and the digital filter first null is located at 60Hz
(LTC2435) or simultaneous 50Hz/60Hz (LTC2435-1).
When FO is driven by an external clock signal with a
frequency fEOSC, the converter uses this signal as its
system clock and the digital filter first null is located at a
frequency fEOSC/2560.
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
24351fb
10
LTC2435/LTC2435-1
U
U
W
FU CTIO AL BLOCK DIAGRA
INTERNAL
OSCILLATOR
V
CC
GND
AUTOCALIBRATION
AND CONTROL
F
O
(INT/EXT)
+
IN
IN
+
–
–
∫
∫
∫
SDO
SERIAL
INTERFACE
∑
ADC
SCK
CS
+
REF
REF
–
DECIMATING FIR
–
+
DAC
2435 F01
Figure 1. Functional Block Diagram
TEST CIRCUITS
V
CC
1.69k
SDO
SDO
1.69k
C
LOAD
= 20pF
C
= 20pF
LOAD
Hi-Z TO V
OH
OH
Hi-Z TO V
OL
OL
V
TO V
OL
OH
V
V
TO V
OH
OL
V
TO Hi-Z
2435 TA03
TO Hi-Z
2435 TA04
24351fb
11
LTC2435/LTC2435-1
U
W
U U
APPLICATIO S I FOR ATIO
CONVERTER OPERATION
There is no latency in the conversion result. The data
output corresponds to the conversion just performed.
This result is shifted out on the serial data out pin (SDO)
underthecontroloftheserialclock(SCK). Dataisupdated
onthefallingedgeofSCKallowingtheusertoreliablylatch
data on the rising edge of SCK (see Figure 3). The data
output state is concluded once 24 bits are read out of the
ADC or when CS is brought HIGH. The device automati-
cally initiates a new conversion and the cycle repeats.
Converter Operation Cycle
TheLTC2435/LTC2435-1arelowpower,delta-sigmaana-
log-to-digital converters with an easy to use 3-wire serial
interface (see Figure 1). Their operation is made up of
threestates. Theconverteroperatingcyclebeginswiththe
conversion, followed by the sleep state and ends with the
dataoutput(seeFigure2). The3-wireinterfaceconsistsof
serialdataoutput(SDO),serialclock(SCK)andchipselect
(CS).
Through timing control of the CS and SCK pins, the
LTC2435/LTC2435-1 offer several flexible modes of op-
eration (internal or external SCK and free-running conver-
sion modes). These various modes do not require pro-
gramming configuration registers; moreover, they do not
disturbthecyclicoperationdescribedabove.Thesemodes
of operation are described in detail in the Serial Interface
Timing Modes section.
CONVERT
SLEEP
Conversion Clock
FALSE
CS = LOW
AND
SCK
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50Hz or
60Hz plus their harmonics. The filter rejection perfor-
mance is directly related to the accuracy of the converter
system clock. The LTC2435/LTC2435-1 incorporate a
highly accurate on-chip oscillator. This eliminates the
need for external frequency setting components such as
crystals or oscillators. Clocked by the on-chip oscillator,
the LTC2435 achieves a minimum of 110dB rejection at
the line frequency (50Hz or 60Hz 2%), while the
LTC2435-1 achieves a minimum of 87db rejection at 50Hz
2% and 60Hz 2% simultaneously.
TRUE
DATA OUTPUT
2435 F02
Figure 2. LTC2435 State Transition Diagram
Initially, the LTC2435/LTC2435-1 perform a conversion.
Once the conversion is complete, the device enters the
sleep state. While in this sleep state, power consumption
isreducedbyanorderofmagnitudeifCSisHIGH. Thepart
remains in the sleep state as long as CS is HIGH. The
conversion result is held indefinitely in a static shift
register while the converter is in the sleep state.
Once CS is pulled LOW, the device exits the low power
sleepmodeandentersthedataoutputstate. IfCSispulled
HIGHbeforethefirstrisingedgeofSCK,thedevicereturns
to the sleep mode and the conversion result is still held in
the internal static shift register. If CS remains LOW after
the first rising edge of SCK, the device begins outputting
the conversion result. Taking CS HIGH at this point will
terminatethedataoutputstateandstartanewconversion.
Ease of Use
The LTC2435/LTC2435-1 data output has no latency,
filter settling delay or redundant data associated with the
conversion cycle. There is a one-to-one correspondence
between the conversion and the output data. Therefore,
multiplexing multiple analog voltages is easy.
24351fb
12
LTC2435/LTC2435-1
U
W U U
APPLICATIO S I FOR ATIO
The LTC2435/LTC2435-1 perform a full-scale calibration
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation de-
scribed above. The advantage of continuous calibration is
extremestabilityoffull-scalereadingswithrespecttotime,
supply voltage change and temperature drift.
The LTC2435/LTC2435-1 can accept a differential refer-
ence voltage from 0.1V to VCC. The converter output noise
is determined by the thermal noise of the front-end cir-
cuits, and as such, its value is nearly constant with
reference voltage. A decrease in reference voltage will not
significantly improve the converter’s effective resolution.
On the other hand, a reduced reference voltage will im-
prove the converter’s overall INL performance. A reduced
reference voltage will also improve the converter perfor-
mance when operated with an external conversion clock
(external FO signal) at substantially higher output data
rates (see the Output Data Rate section).
Unlike the LTC2430, the LTC2435 and LTC2435-1 do not
perform an offset calibration every conversion cycle. This
enables the LTC2435/LTC2435-1 to double their output
rate while maintaining line frequency rejection. The initial
offset of the LTC2435/LTC2435-1 is within 5mV indepen-
dentofVREF.BasedontheLTC2435/LTC2435-1newmodu-
lator architecture, the temperature drift of the offset is less
than 100nV/°C. More information on the LTC2435/
LTC2435-1 offset is described in the Offset Accuracy and
Drift section of this data sheet.
Input Voltage Range
The analog input is truly differential with an absolute/
common mode range for the IN+ and IN– input pins
extending from GND – 0.3V to VCC + 0.3V. Outside
these limits, the ESD protection devices begin to turn on
and the errors due to input leakage current increase
rapidly. Withintheselimits, theLTC2435/LTC2435-1con-
vert the bipolar differential input signal, VIN = IN+ – IN–,
Power-Up Sequence
The LTC2435/LTC2435-1 automatically enter an internal
reset state when the power supply voltage VCC drops
below approximately 2.2V. This feature guarantees the
integrity of the conversion result and of the serial interface
mode selection. (See the 2-wire I/O sections in the Serial
Interface Timing Modes section.)
from –FS = –0.5 • VREF to +FS = 0.5 • VREF where VREF
=
REF+ – REF–. Outside this range, the converters indicate
the overrange or the underrange condition using distinct
output codes.
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 1ms. The POR
signal clears all internal registers. Following the POR
signal,theLTC2435/LTC2435-1startanormalconversion
cycleandfollowthesuccessionofstatesdescribedabove.
The first conversion result following POR is accurate
within the specifications of the device if the power supply
voltage is restored within the operating range (2.7V to
5.5V) before the end of the POR time interval.
Input signals applied to IN+ and IN– pins may extend by
300mV below ground and above VCC. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN+ and IN– pins without affecting the perfor-
mance of the device. In the physical layout, it is important
to maintain the parasitic capacitance of the connection
betweentheseseriesresistorsandthecorrespondingpins
as low as possible; therefore, the resistors should be
located as close as practical to the pins. The effect of the
series resistance on the converter accuracy can be evalu-
ated from the curves presented in the Input Current/
Reference Current sections. In addition, series resistors
will introduce a temperature dependent offset error due to
the input leakage current. A 1nA input leakage current will
develop a 1ppm offset error on a 5k resistor if VREF = 5V.
This error has a very strong temperature dependency.
Reference Voltage Range
These converters accept a truly differential external refer-
ence voltage. The absolute/common mode voltage speci-
ficationfortheREF+ andREF– pinscoverstheentirerange
from GND to VCC. For correct converter operation, the
REF+ pin must always be more positive than the REF– pin.
24351fb
13
LTC2435/LTC2435-1
U
W
U U
APPLICATIO S I FOR ATIO
Output Data Format
SCK clock pulses are ignored by the internal data out shift
register.
The LTC2435/LTC2435-1 serial output data stream is 24
bits long. The first 3 bits represent status information
indicating the sign and conversion state. The next 21 bits
are the conversion result, MSB first. The third and fourth
bit together are also used to indicate an underrange
condition(thedifferentialinputvoltageisbelow–FS)oran
overrangecondition(thedifferentialinputvoltageisabove
+FS).
In order to shift the conversion result out of the device, CS
mustfirstbedrivenLOW. EOCisseenattheSDOpinofthe
deviceonceCSispulledLOW.EOCchangesrealtimefrom
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external
microcontroller. Bit 23 (EOC) can be captured on the first
risingedgeofSCK. Bit22isshiftedoutofthedeviceonthe
first falling edge of SCK. The final data bit (Bit 0) is shifted
out on the falling edge of the 23rd SCK and may be latched
on the rising edge of the 24th SCK pulse. On the falling
edge of the 24th SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 23) for the next conversion cycle. Table 2 summarizes
the output data format.
AslongasthevoltageontheIN+ andIN–pinsismaintained
within the –0.3V to (VCC + 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 • VREF to
+FS = 0.5 • VREF. For differential input voltages greater
than +FS, the conversion result is clamped to the value
corresponding to the +FS. For differential input voltages
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 21 (third output bit) is the conversion result sign indi-
cator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this
bit is LOW.
Bit 20 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 21 also
provides the underrange or overrange indication. If both
Bit 21 and Bit 20 are HIGH, the differential input voltage is
above +FS. If both are LOW, the differential input voltage
is below –FS.
Offset Accuracy and Drift
The function of these bits is summarized in Table 1.
Unlike the LTC2430 and most of the LTC2400 family, the
LTC2435/LTC2435-1 do not perform an offset calibration
everycycle. Thereasonforthisistoincreasethedataoutput
rate while maintaining line frequency rejection.
Table 1. LTC2435/LTC2435-1 Status Bits
Bit 23 Bit 22 Bit 21 Bit 20
Input Range
EOC
DMY
SIG
MSB
V
≥ 0.5 • V
0
0
0
0
0
1
1
0
1
0
IN
REF
While the initial accuracy of the LTC2435/LTC2435-1
offset is within 5mV (see Figure 4), several unique prop-
ertiesoftheLTC2435/LTC2435-1architecturenearlyelimi-
natethedriftoftheoffseterrorwithrespecttotemperature
and supply.
0V ≤ V < 0.5 • V
0
1
IN
REF
–0.5 • V ≤ V < 0V
0
0
REF
IN
V
< –0.5 • V
0
0
IN
REF
Bits 20-0 are the 21-bit conversion result MSB first.
Bit 0 is the least significant bit (LSB).
AsshowninFigure5, theoffsetvariationwithtemperature
is less than 3ppm over the complete temperature range of
–50°C to 100°C. This corresponds to a temperature drift
of 0.022ppm/°C.
DataisshiftedoutoftheSDOpinundercontroloftheserial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any externally generated
While the variation in offset with supply voltage is propor-
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14
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APPLICATIO S I FOR ATIO
tional to VCC (see Figure 4), several characteristics of this
variation can be used to eliminate the effects. First, the
variation with respect to supply voltage is linear. Second,
the magnitude of the offset error decreases with de-
creased supply voltage. Third, the offset error in micro-
volts is almost independent with reference and therefore
the offset in ppm is inverse proportional to reference
voltage. As a result, by tying VCC to VREF, the variation with
supply can be reduced, see Figure 6. The variation with
supply is less than 15ppm over the entire 2.7V to 5.5V
supply range.
Frequency Rejection Selection LTC2435 (F )
O
Table 2. LTC2435/LTC2435-1 Output Data Format
Differential Input Voltage
V *
IN
Bit 23
EOC
Bit 22
DMY
Bit 21
SIG
Bit 20
MSB
Bit 19
Bit 18
Bit 17
…
Bit 0
V * ≥ 0.5 • V **
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
…
…
…
…
…
…
…
…
…
…
0
1
0
1
0
1
0
1
0
IN
REF
0.5 • V ** – 1LSB
REF
0.25 • V **
REF
0.25 • V ** – 1LSB
REF
0
–1LSB
–0.25 • V **
REF
–0.25 • V ** – 1LSB
REF
–0.5 • V **
REF
V * < –0.5 • V **
0
1
IN
REF
+
–
+
–
*The differential input voltage V = IN – IN .
**The differential reference voltage V = REF – REF .
IN
REF
CS
BIT 23
EOC
BIT 22
“0”
BIT 21
SIG
BIT 20
MSB
BIT 19
BIT 5
BIT 0
LSB
SDO
SCK
Hi-Z
SLEEP
DATA OUTPUT
CONVERSION
2435 F03
Figure 3. Output Data Timing
–324
–350
–400
–450
–500
–550
–600
–650
–700
–750
–300
–305
–310
–315
–320
–325
–330
–335
–340
–345
–350
+
–
+
–
V
V
V
V
F
= 5V
REF = 2.5V
REF = V
CC
CC
= 5V
REF = GND
REF = GND
REF
–325
–326
–327
–328
–329
–330
= 0V
V
V
F
= 0V
V
V
F
= 0V
IN
INCM
= GND
IN
INCM
IN
INCM
= GND
= GND
= GND
= GND
= GND
O
O
O
T
= 25°C
T
= 25°C
A
A
–
5.0
2.5
3.0
3.5
4.0
(V)
4.5
5.5
5.0
2.5
3.0
3.5
V
4.0
and V
4.5
(V)
5.5
–45 –30 –15
0
15 30 45 60 75 90
TEMPERATURE (°C)
V
CC
CC
REF
2435 F04
2435 F06
Figure 4. Offset vs VCC
Figure 5. Offset vs Temperature2435 F05
Figure 6. Offset vs VCC (VREF = VCC)
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The LTC2435 internal oscillator provides better than 110dB
normalmoderejectionatthelinefrequencyanditsharmon-
If the change occurs during the data output state and the
converter is in the Internal SCK mode, the serial clock duty
cycle may be affected but the serial data stream will remain
valid.
ics for 50Hz 2% or 60Hz 2%. For 60Hz rejection, F
should be connected to GND while for 50Hz rejection the F
O
O
pin should be connected to V .
CC
Table 3a summarizes the duration of each state and the
Theselectionof50Hzor60Hzrejectioncanalsobemadeby
achievable output data rate as a function of F .
O
driving F to an appropriate logic level. A selection change
O
Frequency Rejection Selection LTC2435-1 (FO)
during the sleep or data output states will not disturb the
converter operation. If the selection is made during the
conversion state, the result of the conversion in progress
may be outside specifications but the following conver-
sions will not be affected.
The LTC2435-1 internal oscillator provides better than
87dB normal mode rejection over the range of 49Hz to
61.2HzasshowninFigure7b.Forsimultaneous50Hz/60Hz
rejection, F should be connected to GND.
O
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2435 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
In order to achieve 87dB normal mode rejection of 50Hz
2% and 60Hz 2%, two consecutive conversions must be
averaged. By performing a continuous running average of
the two most current results, both simultaneous rejection
is achieved and a nearly 2× increase in throughput is
realized relative to the LTC2430 (see Normal Mode Rejec-
tion, Ouput Rate and Running Averages sections of this
data sheet).
signal at the F pin and turns off the internal oscillator. The
O
EOSC
frequency f
of the external signal must be at least 5kHz
to be detected. The external clock signal duty cycle is not
significant as long as the minimum and maximum specifi-
When a fundamental rejection frequency different from
therange49Hzto61.2Hzisrequiredorwhentheconverter
must be synchronized with an outside source, the
LTC2435-1canoperatewithanexternalconversionclock.
The performance of the LTC2435-1 is the same as the
LTC2435 when driven by an external conversion clock at
the FO pin.
cations for the high and low periods t
observed.
and t
are
HEO
LEO
While operating with an external conversion clock of a
frequency f , the LTC2435 provides better than 110dB
EOSC
normal mode rejection in a frequency range f
/2560
EOSC
4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from f
is shown in Figure 7a.
/2560
EOSC
Table 3b summarizes the duration of each state and the
achievable output data rate as a function of FO.
Whenever an external clock is not present at the F pin, the
O
converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The LTC2435
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external serial
clock. If the change occurs during the conversion state, the
result of the conversion in progress may be outside speci-
fications but the following conversions will not be affected.
Serial Interface Pins
The LTC2435/LTC2435-1 transmit the conversion results
and receive the start of conversion command through a
synchronous 3-wire interface. During the conversion and
sleep states, this interface can be used to assess the
converter status and during the data output state it is used
to read the conversion result.
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–80
–90
–60
–70
–80
–85
–90
–80
–95
–100
–100
–120
–130
–140
–100
–105
–110
–115
–120
–125
–130
–135
–140
–90
–100
–110
–120
–130
–140
–12
–8
–4
0
4
8
12
48
50
52
54
56
58
60
62
–12
–8
–4
0
4
8
12
INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY f
/2560(%)
EOSC
2435 F07a
2435 F07b
2435 F07c
Figure 7a. LTC2435/LTC2435-1 Normal Mode
Rejection When Using an External Oscillator
of Frequency fEOSC without Running Averages
Figure 7b. LTC2435-1 Normal Mode
Rejection When Using an Internal
Oscillator with Running Averages
Figure 7c. LTC2435/LTC2435-1
Normal Mode Rejection When Using
an External Oscillator of Frequency
fEOSC with Running Averages
Table 3a. LTC2435 State Duration
State
Operating Mode
Duration
CONVERT
Internal Oscillator
F = LOW, (60Hz Rejection)
67ms, Output Data Rate ≤ 15 Readings/s
80ms, Output Data Rate ≤ 12.4 Readings/s
s, Output Data Rate ≤ f /10278 Readings/s
O
F = HIGH, (50Hz Rejection)
O
External Oscillator
F = External Oscillator with Frequency 10278/f
O
EOSC
EOSC
f
kHz (f /2560 Rejection)
EOSC
EOSC
SLEEP
As Long As CS = HIGH
As Long As CS = LOW But Not Longer Than 1.25ms (24 SCK cycles)
As Long As CS = LOW But Not Longer Than 192/f ms (24 SCK cycles)
DATA OUTPUT Internal Serial Clock F = LOW/HIGH, (Internal Oscillator)
O
F = External Oscillator with
O
EOSC
Frequency f
kHz
EOSC
External Serial Clock with Frequency f
kHz
As Long As CS = LOW But Not Longer Than 24/f ms (24 SCK cycles)
SCK
SCK
Table 3b. LTC2435-1 State Duration
State
Operating Mode
Duration
CONVERT
Internal Oscillator
F = LOW
Simultaneous 50Hz/60Hz Rejection
73ms, Output Data Rate ≤ 14 Readings/s
O
External Oscillator
F = External Oscillator with Frequency 10278/f
s, Output Data Rate ≤ f
/10278 Readings/s
EOSC
O
EOSC
f
kHz (f /2560 Rejection)
EOSC
EOSC
SLEEP
As Long As CS = HIGH
As Long As CS = LOW But Not Longer Than 1.4ms (24 SCK cycles)
As Long As CS = LOW But Not Longer Than 192/f ms (24 SCK cycles)
DATA OUTPUT Internal Serial Clock F = LOW (Internal Oscillator)
O
F = External Oscillator with
O
EOSC
Frequency f
kHz
EOSC
External Serial Clock with Frequency f
kHz
As Long As CS = LOW But Not Longer Than 24/f ms (24 SCK cycles)
SCK
SCK
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Serial Clock Input/Output (SCK)
Chip Select Input (CS)
The serial clock signal present on SCK (Pin 13) is used to
synchronizethedatatransfer.Eachbitofdataisshiftedout
the SDO pin on the falling edge of the serial clock.
The active LOW chip select, CS (Pin 11), is used to test the
conversionstatusandtoenablethedataoutputtransferas
described in the previous sections.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2435/LTC2435-1 create their own se-
rial clock by dividing the internal conversion clock by 8. In
the External SCK mode of operation, the SCK pin is used
as input. The internal or external SCK mode is selected on
power-up and then reselected every time a HIGH-to-LOW
transition is detected at the CS pin. If SCK is HIGH or float-
ing at power-up or during this transition, the converter
enters the internal SCK mode. If SCK is LOW at power-up
or during this transition, the converter enters the external
SCK mode.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2435/LTC2435-1 will abort any
serial data transfer in progress and start a new conversion
cycle anytime a LOW-to-HIGH transition is detected at the
CSpinaftertheconverterhasenteredthedataoutputstate
(i.e., after the first rising edge of SCK occurs with
CS = LOW).
Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
Grounding CS will force the ADC to continuously convert
at the maximum output rate selected by FO.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 12), provides the
result of the last conversion as a serial bit stream (MSB
first) during the data output state. In addition, the SDO pin
is used as an end of conversion indicator during the
conversion and sleep states.
SERIAL INTERFACE TIMING MODES
The LTC2435/LTC2435-1 3-wire interface is SPI and
MICROWIRE compatible. This interface offers several
flexible modes of operation. These include internal/exter-
nal serial clock, 2- or 3-wire I/O, single cycle conversion
and autostart. The following sections describe each of
these serial interface timing modes in detail. In all these
cases, the converter can use the internal oscillator (FO =
LOW or FO = HIGH) or an external oscillator connected to
the FO pin. Refer to Table 4 for a summary.
When CS (Pin 11) is HIGH, the SDO driver is switched to
a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
duringtheconversionphase, theEOCbitappearsHIGHon
the SDO pin. Once the conversion is complete, EOC goes
LOW.
Table 4. LTC2435/LTC2435-1 Interface Timing Modes
Conversion
Cycle
Control
Data
Output
Control
Connection
and
Waveforms
SCK
Configuration
Source
External
External
Internal
Internal
External SCK, Single Cycle Conversion
External SCK, 2-Wire I/O
CS and SCK
SCK
CS and SCK
SCK
Figures 8, 9
Figure 10
Internal SCK, Single Cycle Conversion
Internal SCK, 2-Wire I/O, Continuous Conversion
CS ↓
CS ↓
Figures 11, 12
Figure 13
Continuous
Internal
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External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
latched on the 24th rising edge of SCK. On the 24th falling
edge of SCK, the device begins a new conversion. SDO
goesHIGH(EOC=1)indicatingaconversionisinprogress.
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
The serial clock mode is selected on the falling edge of CS.
Toselecttheexternalserialclockmode,theserialclockpin
(SCK) must be LOW during each CS falling edge.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the
24th falling edge of SCK, see Figure 9. On the rising edge
of CS, the device aborts the data output state and imme-
diately initiates a new conversion. This is useful for sys-
tems not requiring all 24 bits of output data, aborting an
invalid conversion cycle or synchronizing the start of a
conversion.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the conversion is over. With CS HIGH, the device auto-
matically enters the sleep state once the conversion is
complete.
When CS is low, the device enters the data output mode.
The result is held in the internal static shift register until
the first SCK rising edge is seen while CS is LOW. Data is
shifted out the SDO pin on each falling edge of SCK. This
enables external circuitry to latch the output on the rising
edge of SCK. EOC can be latched on the first rising edge
of SCK and the last bit of the conversion result can be
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nallygeneratedserialclock(SCK)signal,seeFigure10.CS
may be permanently tied to ground, simplifying the user
interface or isolation barrier.
2.7V TO 5.5V
V
CC
1μF
= 50Hz REJECTION (LTC2435)
2
14
13
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2435)
= 50Hz/60Hz REJECTION (LTC2435-1)
V
F
O
CC
LTC2435/
LTC2435-1
3
4
+
REFERENCE
VOLTAGE
REF
REF
SCK
–
0.1V TO V
CC
3-WIRE
SPI INTERFACE
5
6
12
11
+
ANALOG INPUT RANGE
–0.5V TO 0.5V
IN
SDO
CS
REF
REF
–
IN
1, 7, 8, 9, 10, 15, 16
GND
CS
TEST EOC
TEST EOC
BIT 23
EOC
BIT 22
BIT 21
SIG
BIT 20
MSB
BIT 19
BIT 18
BIT 5
BIT 0
LSB
SDO
Hi-Z
Hi-Z
Hi-Z
SCK
(EXTERNAL)
CONVERSION
DATA OUTPUT
CONVERSION
SLEEP
TEST EOC
2435 F08
SLEEP
Figure 8. External Serial Clock, Single Cycle Operation
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2.7V TO 5.5V
V
CC
1μF
= 50Hz REJECTION (LTC2435)
2
14
13
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2435)
= 50Hz/60Hz REJECTION (LTC2435-1)
V
F
CC
O
LTC2435/
LTC2435-1
+
3
REFERENCE
VOLTAGE
0.1V TO V
REF
REF
SCK
4
–
CC
3-WIRE
SPI INTERFACE
5
6
12
11
+
ANALOG INPUT RANGE
–0.5V TO 0.5V
IN
SDO
CS
REF REF
–
IN
1, 7, 8, 9, 10, 15, 16
GND
CS
TEST EOC
TEST EOC
BIT 0
EOC
BIT 23
EOC
BIT 22
BIT 21
SIG
BIT 20
MSB
BIT 19
BIT 9
BIT 8
SDO
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCK
(EXTERNAL)
SLEEP
DATA OUTPUT
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
2435 F09
SLEEP
TEST EOC
Figure 9. External Serial Clock, Reduced Data Output Length
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after VCC exceeds 2.2V. The level
applied to SCK at this time determines if SCK is internal or
external. SCK must be driven LOW prior to the end of POR
in order to enter the external serial clock timing mode.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 11.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and
EOC = 0oncetheconversionisover. Onthefallingedgeof
EOC, the conversion result is loaded into an internal static
shift register. Data is shifted out the SDO pin on each
falling edge of SCK enabling external circuitry to latch data
on the rising edge of SCK. EOC can be latched on the first
rising edge of SCK. On the 24th falling edge of SCK, SDO
goes HIGH (EOC = 1) indicating a new conversion has
begun.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the conversion is over.
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WhentestingEOC,iftheconversioniscomplete(EOC=0),
thedevicewillexitthesleepstateandenterthedataoutput
state. In order to allow the device to return to the sleep
state, CS must be pulled HIGH before the first rising edge
of SCK. In the internal SCK timing mode, SCK goes HIGH
and the device begins outputting data at time tEOCtest after
the falling edge of CS (if EOC = 0) or tEOCtest after EOC goes
LOW (if CS is LOW during the falling edge of EOC). The
value of tEOCtest is 23μs (LTC2435), 26μs (LTC2435-1) if
the device is using its internal oscillator (F0 = logic LOW or
2.7V TO 5.5V
V
CC
1μF
= 50Hz REJECTION (LTC2435)
2
14
13
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2435)
= 50Hz/60Hz REJECTION (LTC2435-1)
V
F
CC
LTC2435/
O
LTC2435-1
3
4
+
REFERENCE
VOLTAGE
REF
REF
SCK
–
2-WIRE
INTERFACE
0.1V TO V
CC
5
6
12
11
+
ANALOG INPUT RANGE
–0.5V TO 0.5V
IN
SDO
CS
REF
REF
–
IN
1, 7, 8, 9, 10, 15, 16
GND
CS
BIT 23
EOC
BIT 22
BIT 21
SIG
BIT 20
MSB
BIT 19
BIT 18
BIT 5
BIT 0
LSB
SDO
SCK
(EXTERNAL)
CONVERSION
DATA OUTPUT
CONVERSION
2435 F10
Figure 10. External Serial Clock, CS = 0 Operation (2-Wire)
2.7V TO 5.5V
V
CC
V
CC
1μF
= 50Hz REJECTION (LTC2435)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2435)
= 50Hz/60Hz REJECTION (LTC2435-1)
2
14
13
V
F
CC
O
10k
LTC2435/
LTC2435-1
+
3
4
REFERENCE
VOLTAGE
REF
REF
SCK
–
0.1V TO V
CC
3-WIRE
SPI INTERFACE
5
6
12
11
+
ANALOG INPUT RANGE
–0.5V TO 0.5V
IN
SDO
CS
REF REF
–
IN
1, 7, 8, 9, 10, 15, 16
GND
<t
EOCtest
CS
TEST EOC
BIT 23
EOC
BIT 22
BIT 21
SIG
BIT 20
MSB
BIT 19
BIT 18
BIT 5
BIT 0
LSB
SDO
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCK
(INTERNAL)
CONVERSION
SLEEP
SLEEP
DATA OUTPUT
CONVERSION
2435 F11
TEST EOC
Figure 11. Internal Serial Clock, Single Cycle Operation
24351fb
21
LTC2435/LTC2435-1
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APPLICATIO S I FOR ATIO
HIGH). IfFO isdrivenbyanexternaloscillatorof frequency
new conversion. This is useful for systems not requiring
all 24 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
theSCKpinorbyneverpullingCSHIGHwhenSCKisLOW.
f
EOSC, thentEOCtest is3.6/fEOSC. IfCSispulledHIGHbefore
time tEOCtest, the device returns to the sleep state. The
conversionresultisheldintheinternalstaticshiftregister.
If CS remains LOW longer than tEOCtest, the first rising
edge of SCK will occur and the conversion result is serially
shiftedoutoftheSDOpin. Thedataoutputcyclebeginson
this first rising edge of SCK and concludes after the 24th
rising edge. Data is shifted out the SDO pin on each falling
edgeofSCK.Theinternallygeneratedserialclockisoutput
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latchedonthefirstrisingedgeofSCKandthelastbitofthe
conversion result on the 24th rising edge of SCK. After the
24th rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH and a new conversion starts.
Whenever SCK is LOW, the LTC2435/LTC2435-1 internal
pull-up at pin SCK is disabled. Normally, SCK is not
externally driven if the device is in the internal SCK timing
mode.However,certainapplicationsmayrequireanexter-
nal driver on SCK. If this driver goes Hi-Z after outputting
a LOW signal, the LTC2435/LTC2435-1 internal pull-up
remains disabled. Hence, SCK remains LOW. On the next
falling edge of CS, the device is switched to the external
SCK timing mode. By adding an external 10k pull-up
resistortoSCK,thispingoesHIGHoncetheexternaldriver
goes Hi-Z. On the next CS falling edge, the device will
remain in the internal SCK timing mode.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 24th rising edge of
SCK, see Figure 12. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
2.7V TO 5.5V
V
CC
V
CC
1μF
= 50Hz REJECTION (LTC2435)
2
14
13
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2435)
= 50Hz/60Hz REJECTION (LTC2435-1)
V
F
CC
O
10k
LTC2435/
LTC2435-1
+
3
REFERENCE
REF
REF
SCK
VOLTAGE
4
–
0.1V TO V
CC
3-WIRE
SPI INTERFACE
5
6
12
11
+
ANALOG INPUT RANGE
–0.5V TO 0.5V
IN
SDO
CS
REF REF
–
IN
1, 7, 8, 9, 10, 15, 16
<t
EOCtest
GND
>t
EOCtest
CS
TEST EOC
TEST EOC
BIT 0
EOC
BIT 23
EOC
BIT 22
BIT 21
SIG
BIT 20
MSB
BIT 19
BIT 18
BIT 8
SDO
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCK
(INTERNAL)
SLEEP
DATA OUTPUT
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
SLEEP
2435 F12
TEST EOC
Figure 12. Internal Serial Clock, Reduced Data Output Length
24351fb
22
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A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sionstatus.Ifthedeviceisinthesleepstate(EOC=0),SCK
will go LOW. Once CS goes HIGH (within the time period
defined above as tEOCtest), the internal pull-up is activated.
For a heavy capacitive load on the SCK pin, the internal
pull-up may not be adequate to return SCK to a HIGH level
before CS goes low again. This is not a concern under
normal conditions where CS remains LOW after detecting
EOC = 0. This situation is easily overcome by adding an
external 10k pull-up resistor to the SCK pin.
approximately 1ms after VCC exceeds 2.2V. An internal
weak pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished. The data output cycle begins on
the first rising edge of SCK and ends after the 24th rising
edge. Data is shifted out the SDO pin on each falling edge
of SCK. The internally generated serial clock is output to
the SCK pin. This signal may be used to shift the conver-
sion result into external circuitry. EOC can be latched on
the first rising edge of SCK and the last bit of the
conversion result can be latched on the 24th rising edge
of SCK. After the 24th rising edge, SDO goes HIGH (EOC
= 1) indicating a new conversion is in progress. SCK
remains HIGH during the conversion.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 13. CS may be permanently tied to ground, simpli-
fying the user interface or isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
2.7V TO 5.5V
V
CC
1μF
= 50Hz REJECTION (LTC2435)
2
14
13
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2435)
= 50Hz/60Hz REJECTION (LTC2435-1)
V
F
CC
LTC2435/
O
LTC2435-1
3
+
REFERENCE
REF
REF
SCK
VOLTAGE
4
–
2-WIRE
INTERFACE
0.1V TO V
CC
5
6
12
11
+
ANALOG INPUT RANGE
IN
SDO
CS
–0.5V
TO 0.5V
REF
REF
–
IN
1, 7, 8, 9, 10, 15, 16
GND
CS
BIT 23
EOC
BIT 22
BIT 21
SIG
BIT 20
MSB
BIT 19
BIT 18
BIT 5
BIT 0
LSB
SDO
SCK
(INTERNAL)
CONVERSION
DATA OUTPUT
CONVERSION
2435 F13
Figure 13. Internal Serial Clock, Continuous Operation
24351fb
23
LTC2435/LTC2435-1
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PRESERVING THE CONVERTER ACCURACY
converterpinthroughatraceshorterthan2.5inches.This
problem becomes particularly difficult when shared con-
trollinesareusedandmultiplereflectionsmayoccur. The
solution is to carefully terminate all transmission lines
close to their characteristic impedance.
The LTC2435/LTC2435-1 are designed to reduce as much
as possible conversion result sensitivity to device
decoupling, PCB layout, antialiasing circuits, line fre-
quency perturbations and so on. Nevertheless, in order to
preserve the extreme accuracy capability of this part, Parallel termination near the LTC2435/LTC2435-1 pins
some simple precautions are desirable.
will eliminate this problem but will increase the driver
powerdissipation.Aseriesresistorbetween27Ωand56Ω
placed near the driver or near the LTC2435/LTC2435-1
pins will also eliminate this problem without additional
powerdissipation. Theactualresistorvaluedependsupon
the trace impedance and connection topology.
Digital Signal Levels
The LTC2435/LTC2435-1 digital interface is easy to use.
Its digital inputs (FO, CS and SCK in External SCK mode of
operation)acceptstandardTTL/CMOSlogiclevelsandthe
internalhysteresisreceiverscantolerateedgeratesasslow
as 100μs. However, some considerations are required to
takeadvantageoftheexceptionalaccuracyandlowsupply
current of this converter.
An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The multiple ground pins used
in this package configuration, as well as the differential
input and reference architecture, reduce substantially the
converter’s sensitivity to ground currents.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during conversion.
Particular attention must be given to the connection of the
FO signal when the LTC2435/LTC2435-1 are used with an
external conversion clock. This clock is active during the
conversion time and the normal mode rejection provided
by the internal digital filter is not very high at this fre-
quency. A normal mode signal of this frequency at the
converter reference terminals may result in DC gain and
INL errors. A normal mode signal of this frequency at the
converter input terminals may result in a DC offset error.
Such perturbations may occur due to asymmetric capaci-
tivecouplingbetweentheFO signaltraceandtheconverter
input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation
between the FO signal trace and the input/reference sig-
nals. When the FO signal is parallel terminated near the
converter, substantial AC current is flowing in the loop
formedbytheFO connectiontrace, theterminationandthe
ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or refer-
ence. In this situation, the user must reduce to a minimum
the loop area for the FO signal as well as the loop area for
the differential input and reference connections.
While a digital input signal is in the range 0.5V to
(VCC – 0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (FO, CS and SCK
inExternalSCKmodeofoperation)iswithinthisrange,the
LTC2435/LTC2435-1 power supply current may increase
even if the signal in question is at a valid logic level. For
micropower operation, it is recommended to drive all
digital input signals to full CMOS levels [VIL < 0.4V and
VOH > (VCC – 0.4V)].
During the conversion period, the undershoot and/or
overshootofafastdigitalsignalconnectedtotheLTC2435/
LTC2435-1pinsmayseverelydisturbtheanalogtodigital
conversion process. Undershoot and overshoot can oc-
cur because of the impedance mismatch at the converter
pin when the transition time of an external control signal
is less than twice the propagation delay from the driver to
LTC2435/LTC2435-1. For reference, on a regular FR-4
board, signal propagation velocity is approximately
183ps/inch for internal traces and 170ps/inch for surface
traces. Thus, a driver generating a control signal with a
minimum transition time of 1ns must be connected to the
24351fb
24
LTC2435/LTC2435-1
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Driving the Input and Reference
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 15. The CPAR capacitor
includes the LTC2435/LTC2435-1 pin capacitance (5pF
typical) plus the capacitance of the test fixture used to
obtain the results shown in Figures 16 and 17. A careful
implementation can bring the total input capacitance (CIN
+ CPAR) closer to 5pF thus achieving better performance
than the one predicted by Figures 16 and 17. For simplic-
ity, two distinct situations can be considered.
The input and reference pins of the LTC2435/LTC2435-1
convertersaredirectlyconnectedtoanetworkofsampling
capacitors. Depending upon the relation between the
differential input voltage and the differential reference
voltage, these capacitors are switching between these
four pins transferring small amounts of charge in the
process. A simplified equivalent circuit is shown in
Figure 14.
For relatively small values of input capacitance (CIN
<
For a simple approximation, the source impedance RS
driving an analog input pin (IN+, IN–, REF+ or REF–) can be
considered to form, together with RSW and CEQ (see
Figure 14), a first order passive network with a time
constant τ = (RS + RSW) • CEQ. The converter is able to
sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant τ. The sampling process on the
four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worst-
case circumstances, the errors may add.
0.01μF), the voltage on the sampling capacitor settles
almost completely and relatively large values for the
source impedance result in only small errors. Such values
for CIN will deteriorate the converter offset and gain
performancewithoutsignificantbenefitsofsignalfiltering
and the user is advised to avoid them. Nevertheless, when
small values of CIN are unavoidably present as parasitics
of input multiplexers, wires, connectors or sensors, the
LTC2435/LTC2435-1canmaintaintheirexceptionalaccu-
racy while operating with relative large values of source
resistance as shown in Figures 16 and 17. These mea-
sured results may be slightly different from the first order
approximation suggested earlier because they include the
effect of the actual second order input network together
with the nonlinear settling process of the input amplifiers.
For small CIN values, the settling on IN+ and IN– occurs
almost independently and there is little benefit in trying to
match the source impedance for the two pins.
Whenusingtheinternaloscillator(FO =LOWorHIGH), the
LTC2435’sfront-endswitched-capacitornetworkisclocked
at 76800Hz corresponding to a 13μs sampling period and
the LTC2435-1’s front end is clocked at 69900Hz corre-
sponding to 14.2μs. Thus, for settling errors of less than
1ppm, the driving source impedance should be chosen
such that τ ≤ 13μs/14 = 920ns (LTC2435) and τ <14.2μs/
14 = 1.01μs (LTC2435-1). When an external oscillator of
frequency fEOSC is used, the sampling period is 2/fEOSC
Larger values of input capacitors (CIN > 0.01μF) may be
required in certain configurations for antialiasing or gen-
eral input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When FO = LOW (internal oscillator and 60Hz notch), the
typical differential input resistance is 22MΩ (LTC2435) or
24MΩ (LTC2435-1) which will generate a +FS gain error
of approximately 0.023ppm (LTC2435) or 0.021ppm
(LTC2435-1) for each ohm of source resistance driving
IN+ or IN–. For the LTC2435, when FO = HIGH (internal
oscillator and 50Hz notch), the typical differential input
resistance is 26MΩ which will generate a +FS gain error of
approximately 0.019ppm for each ohm of source resis-
and, for a settling error of less than 1ppm, τ ≤ 0.14/fEOSC
.
Input Current
If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
theINLperformanceoftheconverter. Figure14showsthe
mathematical expressions for the average bias currents
flowing through the IN+ and IN– pins as a result of the
sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).
24351fb
25
LTC2435/LTC2435-1
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APPLICATIO S I FOR ATIO
V
V
IN + VINCM − VREFCM
CC
I IN+
=
=
I
+
(
)
)
REF
AVG
AVG
0.5 •REQ
−VIN + VINCM − VREFCM
0.5 • REQ
R
(TYP)
SW
I
LEAK
20k
I IN−
(
V
REF
+
I
V2
IN
VREF • REQ
LEAK
1.5 • VREF − VINCM + VREFCM
I REF+
=
−
(
)
V
AVG
CC
0.5 • REQ
I
IN
+
V2
R
SW
(TYP)
20k
−1.5• VREF − VINCM + VREFCM
I
I
IN
I REF−
=
+
LEAK
LEAK
(
)
AVG
0.5 •REQ
VREF • REQ
V
+
IN
C
where:
EQ
18pF
VREF = REF+ − REF−
(TYP)
V
CC
REF + REF−
+
⎛
⎞
I
–
–
IN
IN
VREFCM
=
R
R
(TYP)
20k
⎜
⎟
SW
I
2
⎝
⎠
LEAK
LEAK
SWITCHING FREQUENCY
IN = IN+ − IN−
V
V
f
= 76800Hz INTERNAL
OSCILLATOR (LTC2435)
SW
I
+
IN − IN−
⎛
⎞
V
INCM
=
(F = LOW OR HIGH)
O
SW
⎜
⎟
2
V
⎝
⎠
CC
f
= 69900Hz INTERNAL
OSCILLATOR (LTC2435-1)
I
–
–
REF
(TYP)
20k
REQ = 43.2MΩ INTERNAL OSCILLATOR 60Hz NOTCH (F = LOW) LTC2435
REQ = 52MΩ INTERNAL OSCILLATOR 50Hz NOTCH (F = HIGH) LTC2435
REQ = 48MΩ INTERNAL OSCILLATOR 50Hz/60Hz NOTCH (F = LOW) LTC2435-1
REQ = (6.7 • 10 )/f
SW
O
I
I
LEAK
LEAK
(F = LOW)
O
SW
O
f
= 0.5 • f
EXTERNAL OSCILLATOR
EOSC
V
REF
O
2435 F18
12
EXTERNAL OSCILLATOR
EOSC
Figure 14. LTC2435/LTC2435-1 Equivalent Analog Input Circuit
R
R
SOURCE
+
IN
C
PAR
V
V
+ 0.5V
C
INCM
INCM
IN
IN
≅20pF
LTC2435/
LTC2435-1
SOURCE
–
IN
2435 F19
C
PAR
– 0.5V
C
IN
IN
≅20pF
Figure 15. An RC Network at IN+ and IN–
10
100
90
80
70
60
50
40
30
20
10
0
C
= 0pF
IN
V
V
V
V
V
= 5V
CC
0
+
–
= 5V
REF
REF
C
= 0.01μF
IN
= GND
= 1.25V
= 3.75V
C
= 0.01μF
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
IN
+
IN
IN
–
C
= 100pF
IN
F
= GND
= 25°C
O
C
= 0.001μF
T
IN
A
C
= 0.001μF
IN
C
= 100pF
V
= 5V
+
IN
CC
REF
V
V
V
V
= 5V
–
= GND
REF
+
= 3.75V
= 1.25V
IN
IN
–
F
= GND
O
A
T
= 25°C
C
= 0pF
IN
–10
1
10
100
R
1000 10000 100000
1
10
100
1000 10000 100000
(W)
R
(W)
SOURCE
SOURCE
2435 F16
2435 F17
Figure 16. +FS Error vs RSOURCE at IN+ or IN– (Small CIN)
Figure 17. –FS Error vs RSOURCE at IN+ or IN– (Small CIN)
24351fb
26
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APPLICATIO S I FOR ATIO
tance driving IN+ or IN–. When FO is driven by an external
oscillator with a frequency fEOSC (external conversion
clock operation), the typical differential input resistance is
3.3 • 1012/fEOSCΩ and each ohm of source resistance
driving IN+ or IN– will result in 0.15 • 10–6 • fEOSC ppm +FS
gain error. The effect of the source resistance on the two
input pins is additive with respect to this gain error. The
typical +FS and –FS errors as a function of the sum of the
source resistance seen by IN+ and IN– for large values of
CIN are shown in Figures 18 and 19.
notch), every 1Ω mismatch in source impedance trans-
forms a full-scale common mode input signal into a
differential mode input signal of 0.02ppm. When FO is
driven by an external oscillator with a frequency fEOSC
,
every 1Ω mismatch in source impedance transforms a
full-scale common mode input signal into a differential
mode input signal of 0.15 • 10–6 • fEOSCppm. Figure 20
shows the typical offset error due to input common mode
voltage for various values of source resistance imbalance
between the IN+ and IN– pins when large CIN values are
used.
In addition to this gain error, an offset error term may also
appear. The offset error is proportional to the mismatch
between the source impedance driving the two input pins
IN+ and IN– and with the difference between the input and
reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the
converter average input current will not degrade the INL
performance,indirectdistortionmayresultfromthemodu-
lation of the offset error by the common mode component
of the input signal. Thus, when using large CIN capacitor
values, itisadvisabletocarefullymatchthesourceimped-
ance seen by the IN+ and IN– pins. When FO = LOW
(internal oscillator and 60Hz notch), every 1Ω mismatch
in source impedance transforms a full-scale common
mode input signal into a differential mode input signal of
0.023ppm. When FO = HIGH (internal oscillator and 50Hz
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
Themagnitudeofthedynamicinputcurrentdependsupon
thesizeoftheverystableinternalsamplingcapacitorsand
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by IN+ and
IN–, the expected drift of the dynamic current, offset and
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
100
90
80
70
60
50
40
30
20
10
0
–310
A: ΔR = 1k
E: ΔR = –200Ω
IN
IN
V
V
V
V
V
F
= 5V
+
C
= 0.01μF
CC
REF
REF
IN
IN
IN
B: ΔR = 500Ω F: ΔR = –500Ω
A
IN
IN
IN
= 5V
–320
–330
–340
–350
–360
–370
–380
C: ΔR = 200Ω G: ΔR = –1k
–
IN
= GND
D: ΔR = 0Ω
+
–
IN
= 1.25V
= 3.75V
B
C
= GND
= 25°C
C
IN
= 0.1μF
O
T
A
C
= 1μF, 10μF
IN
D
E
V
V
V
V
V
F
= 5V
+
CC
REF
REF
IN
IN
C
= 1μF, 10μF
= 5V
IN
–
= GND
+
–
C
= 0.1μF
= 3.75V
= 1.25V
IN
V
V
V
V
= 5V
+
F
= GND
= 25°C
= 10μF
F
CC
REF
REF
O
A
= 5V
T
C
= 0.01μF
IN
–
= GND
= 25°C
= GND
C
IN
O
+
–
T
= V = V
IN
G
A
IN
INCM
800
R
800
R
5.0
0
400
1200
1600
2000
0
400
1200
1600
2000
0
0.5
3.0 3.5 4.0 4.5
(V)
1.0 1.5 2.0 2.5
V
(Ω)
(Ω)
INCM
SOURCE
SOURCE
2435 F18
2435 F19
2435 F20
Figure 20. Offset Error vs Common Mode
Voltage (VINCM = VIN+ = VIN–) and Input
Figure 18. +FS Error vs RSOURCE
at IN+ or IN– (Large CIN)
Figure 19. –FS Error vs RSOURCE
at IN+ or IN– (Large CIN)
Source Resistance Imbalance (ΔRIN
=
RSOURCEIN+ – RSOURCEIN–) for Large CIN
Values (CIN ≥ 1μF)
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gain errors will be insignificant (about 1% of their respec-
tive values over the entire temperature and voltage range).
Even for the most stringent applications, a one-time
calibration operation may be sufficient.
Larger values of reference capacitors (CREF > 0.01μF) may
be required as reference filters in certain configurations.
Suchcapacitorswillaveragethereferencesamplingcharge
and the external source resistance will see a quasi con-
stant reference differential impedance. For the LTC2435,
when FO = LOW (internal oscillator and 60Hz notch), the
typical differential reference resistance is 15.6MΩ which
will generate a +FS gain error of approximately 0.032ppm
for each ohm of source resistance driving REF+ or REF–.
When FO = HIGH (internal oscillator and 50Hz notch), the
typical differential reference resistance is 18.7MΩ which
will generate a +FS gain error of approximately 0.027ppm
for each ohm of source resistance driving REF+ or REF–.
For the LTC2435-1, the typical differential reference resis-
tance is 17.1MΩ which will generate a +FS gain error of
approximately 0.029ppm for each ohm of source resis-
tance driving REF+ or REF–. When FO is driven by an
externaloscillatorwithafrequencyfEOSC (externalconver-
sion clock operation), the typical differential reference
resistance is 2.4 • 1012/fEOSCΩ and each ohm of source
resistance driving REF+ or REF– will result in
0.21 • 10–6 • fEOSCppm +FS gain error. The effect of the
source resistance on the two reference pins is additive
with respect to this gain error. The typical +FS and –FS
errors for various combinations of source resistance seen
by the REF+ and REF– pins and external capacitance CREF
connected to these pins are shown in Figures 21, 22, 23
and 24.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA ( 10nA max), results
inasmalloffsetshift. A100Ωsourceresistancewillcreate
a 0.1μV typical and 1μV maximum offset voltage.
Reference Current
In a similar fashion, the LTC2435/LTC2435-1 sample the
differential reference pins REF+ and REF– transferring
small amount of charge to and from the external driving
circuits thus producing a dynamic reference current. This
current does not change the converter offset, but it may
degrade the gain and INL performance. The effect of this
current can be analyzed in the same two distinct situa-
tions.
Forrelativelysmallvaluesoftheexternalreferencecapaci-
tors(CREF <0.01μF),thevoltageonthesamplingcapacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gainperformancewithoutsignificantbenefitsofreference
filtering and the user is advised to avoid them.
100
10
V
V
V
V
V
= 5V
+
C
= 0pF
IN
CC
REF
REF
IN
IN
90
80
70
60
50
40
30
20
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
= 5V
C
= 0.01μF
IN
–
= GND
C
= 0.01μF
IN
+
–
= 3.75V
= 1.25V
C
= 100pF
IN
F
= GND
= 25°C
O
T
C
= 0.001μF
IN
A
C
= 0.001μF
IN
V
V
V
V
V
= 5V
+
–
C
= 100pF
CC
REF
REF
IN
IN
IN
= 5V
= GND
+
–
= 1.25V
= 3.75V
F
= GND
= 25°C
O
C
= 0pF
T
IN
A
–10
1
10
100
1000 10000 100000
1
10
100
R
1000 10000 100000
R
(Ω)
(Ω)
SOURCE
SOURCE
2435 F21
2435 F22
Figure 21. +FS Error vs RSOURCE at REF+ or REF– (Small CIN)
Figure 22. –FS Error vs RSOURCE at REF+ or REF– (Small CIN)
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100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
V
V
V
V
V
= 5V
CC
+
90
80
70
60
50
40
30
20
10
0
= 5V
REF
REF
C
= 0.01μF
–
IN
= GND
+
= 3.75V
= 1.25V
IN
IN
C
= 1μF, 10μF
IN
–
F
= GND
= 25°C
O
T
A
C
IN
= 0.1μF
C
= 0.1μF
C
= 1μF, 10μF
IN
IN
V
V
V
V
V
F
= 5V
+
CC
REF
REF
IN
IN
= 5V
–
= GND
+
–
= 1.25V
= 3.75V
C
= 0.01μF
IN
= GND
= 25°C
O
T
A
800
R
0
400
1200
1600
2000
800
R
0
400
1200
1600
2000
(Ω)
(Ω)
SOURCE
SOURCE
2435 F23
2435 F24
Figure 24. –FS Error vs RSOURCE at REF+ and REF– (Large CREF
)
Figure 23. +FS Error vs RSOURCE at REF+ and REF– (Large CREF
)
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
WhenFO =LOW(internaloscillatorand60Hznotch),every
100ΩofsourceresistancedrivingREF+ orREF– translates
intoabout0.11ppmadditionalINLerror. FortheLTC2435,
whenFO =HIGH(internaloscillatorand50Hznotch),every
100ΩofsourceresistancedrivingREF+ orREF– translates
into about 0.092ppm additional INL error; and for the
LTC2435-1 operating with simultaneous 50Hz/60Hz re-
jection, every 100Ω of source resistance leads to an
additional 0.10ppm of additional INL error. When FO is
an external clock. When relatively stable resistors
(50ppm/°C) are used for the external source impedance
seen by REF+ and REF–, the expected drift of the dynamic
current gain error will be insignificant (about 1% of its
valueovertheentiretemperatureandvoltagerange). Even
for the most stringent applications a one-time calibration
operation may be sufficient.
Inadditiontothereferencesamplingcharge,thereference
pinsESDprotectiondiodeshaveatemperaturedependent
leakage current. This leakage current, nominally 1nA
( 10nA max), results in a small gain error. A 100Ω source
resistance will create a 0.05μV typical and 0.5μV maxi-
mum full-scale error.
driven by an external oscillator with a frequency fEOSC
,
every 100Ω of source resistance driving REF+ or REF–
translatesintoabout0.73 •10–6 •fEOSCppmadditionalINL
error. Figure 25 shows the typical INL error due to the
source resistance driving the REF+ or REF– pins when
large CREF values are used. The effect of the source
resistance on the two reference pins is additive with
respect to this INL error. In general, matching of source
impedance for the REF+ and REF– pins does not help the
gain or the INL error. The user is thus advised to minimize
the combined source impedance driving the REF+ and
REF– pins rather than to try to match it.
15
12
9
+
–
V
V
= 0.5 • (IN + IN ) = 2.5V
INCM
CC
= 5V
REF+ = 5V
REF– = GND
F
= GND
O
REF
A
6
C
= 10μF
3
T
= 25°C
0
R
= 1k
= 5k
SOURCE
–3
–6
–9
–12
–15
R
SOURCE
R
= 10k
SOURCE
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci-
tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typical better than
0.5%. Such a specification can also be easily achieved by
–0.5 –0.4 –0.3 –0.2–0.1 0 0.1 0.2 0.3 0.4 0.5
/V (V)
V
INDIF REFDIF
2435 F25
Figure 25. INL vs Differential Input Voltage (VIN = IN+ – IN–)
and Reference Source Resistance (RSOURCE at REF+ and
REF– for Large CREF Values (CREF ≥ 1μF)
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Output Data Rate
Third, the internal analog circuits are optimized for normal
operation; therefore an increase in the frequency of the
external oscillator will start to decrease the effectiveness
of the internal analog circuits. This will result in a progres-
sive degradation in the converter accuracy and linearity.
Typicalmeasuredperformancecurvesforoutputdatarates
up to 200 readings per second are shown in Figures 26 to
33. The degradation becomes more obvious above output
data rate of 150Hz, which corresponds to an external os-
cillatorof1.536MHz.Inordertoobtainthehighestpossible
level of accuracy from this converter at output data rates
above 150 readings per second, the user is advised to
maximize the power supply voltage used and to limit the
maximum ambient operating temperature. In certain cir-
cumstances, a reduction of the differential reference volt-
age may be beneficial.
When using its internal oscillator, the LTC2435 can pro-
duce up to 15 readings per second with a notch frequency
of 60Hz (FO = LOW) and 12.5 readings per second with a
notch frequency of 50Hz (FO = HIGH) and the LTC2435-1
can produce up to 13.6 readings per second with FO =
LOW. The actual output data rate will depend upon the
length of the sleep and data output phases which are
controlled by the user and which can be made insignifi-
cantly short. When operated with an external conversion
clock(FOconnectedtoanexternaloscillator),theLTC2435/
LTC2435-1 output data rate can be increased as desired.
The duration of the conversion phase is 10278/fEOSC. If
fEOSC = 153600Hz, the converter behaves as if the internal
oscillator is used and the notch is set at 60Hz. There is no
significant difference in the LTC2435/LTC2435-1 perfor-
mance between these two operation modes.
–300
V
V
V
= V
REFCM
INCM
CC
IN
An increase in fEOSC over the nominal 153600Hz will
translate into a proportional increase in the maximum
outputdatarate.Thissubstantialadvantageisnevertheless
accompanied by three potential effects, which must be
carefully considered.
= V
REF
= 5V
= 0V
= EXT OSC
–310
–320
–330
–340
–350
F
O
T
A
= 25°C
T
A
= 85°C
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent perfor-
mance degradation can be substantially reduced by rely-
ing upon the LTC2435/LTC2435-1’s exceptional common
mode rejection and by carefully eliminating common
mode to differential mode conversion sources in the input
circuit. The user should avoid single-ended input filters
and should maintain a very high degree of matching and
symmetry in the circuits driving the IN+ and IN– pins.
0
20 40 60 80 100 120 140 160 180 200
OUTPUT DATA RATE (READINGS/SEC)
2435 F26
Figure 26. Offset Error vs Output Data Rate and Temperature
–300
–320
–340
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (CIN, CREF) are used, the
previous section provides formulae for evaluating the
effect of the source resistance upon the converter perfor-
mance for any value of fEOSC. If small external input and/
or reference capacitors (CIN, CREF) are used, the effect of
the external source resistance upon the LTC2435/
LTC2435-1 typical performance can be inferred from
Figures 16, 17, 21 and 22 in which the horizontal axis is
T
= 25°C
A
T
–360
–380
–400
–420
–440
–460
–480
–500
= 85°C
A
V
V
O
= V
INCM
CC
REFCM
= 5V
REF
= V
F
= EXT OSC
80
100 120 140 160 180 200
0
20 40 60
OUTPUT DATA RATE (READINGS/SEC)
2435 F27
Figure 27. +FS Error vs Output Data Rate and Temperature
scaled by 153600/fEOSC
.
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–200
22
21
20
19
18
17
16
15
V
V
O
= V
INCM
CC
REFCM
= 5V
REF
= V
–220
–240
–260
–280
–300
–320
–340
–360
–380
–400
F
= EXT OSC
T
= 25°C
A
T
= 85°C
A
V
V
V
= V
= 5V
REF
REFCM
CC
INCM
IN
T
= 25°C
= V
A
= 0V
–
REF = GND
= EXT OSC
F
O
T
A
= 85°C
RES = LOG (V /NOISE
)
2
REF
RMS
80
100 120 140 160 180 200
0
20 40 60
0
20 40 60 80 100 120 140 160 180 200
OUTPUT DATA RATE (READINGS/SEC)
2435 F29
OUTPUT DATA RATE (READINGS/SEC)
2435 F28
Figure 28. –FS Error vs Output Data Rate and Temperature
Figure 29. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
21
20
19
50
V
V
= V
REFCM
INCM
40
30
= 0V
IN
–
REF = GND
= EXT OSC
= 25°C
F
O
A
T
20
T
= 25°C
A
10
18
17
V
= V
= 5V
REF
CC
0
V
V
= 2.7V
CC
–10
–20
–30
–40
–50
= 2.5V
REF
T
= 85°C
A
V
= V
= 5V
REF
REFCM
16 CC
V
= V
INCM
–
REF = GND
15
14
F
= EXT OSC
O
* RELATIVE TO OFFSET AT
NORMAL OUTPUT RATE
RES = LOG (V /INL
)
2
REF
MAX
80
100 120 140 160 180 200
0
20 40 60
0
20 40 60 80 100 120 140 160 180 200
OUTPUT DATA RATE (READINGS/SEC)
2435 F31
OUTPUT DATA RATE (READINGS/SEC)
2435 F30
Figure 30. Resolution (INLRMS ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 31. Offset Change* vs Output
Data Rate and Reference Voltage
22
21
21
20
V
= V
= 5V
REF
CC
V
= V
= 5V
REF
CC
20
19
18
17
16
15
19
18
17
16
15
14
V
= 2.7V
= 2.5V
V
V
= 2.7V
= 2.5V
CC
REF
CC
REF
V
V
V
= V
REFCM
V
V
= V
REFCM
= 0V
INCM
INCM
IN
REF = GND
= 0V
IN
–
–
REF = GND
= EXT OSC
= 25°C
F
F
= EXT OSC
O
A
O
T
T
= 25°C
A
RES = LOG (V /NOISE
)
RES = LOG (V /INL
)
2
REF
RMS
2
REF
MAX
0
20 40 60 80 100 120 140 160 180 200
OUTPUT DATA RATE (READINGS/SEC)
2435 F32
80
0
20 40 60
100 120 140 160 180 200
OUTPUT DATA RATE (READINGS/SEC)
2435 F33
Figure 32. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Reference Voltage
Figure 33. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Reference Voltage
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Normal Mode Rejection and Antialiasing
Through FO connection, the LTC2435 provides better than
110dB input differential mode rejection at 50Hz or 60Hz
2%. While for the LTC2435-1, it has a notch frequency of
about 55Hz with better than 70db rejection over 48Hz to
62.4Hz, which covers both 50Hz 2% and 60Hz 2%. In
order to achieve better rejection over the range of 48Hz to
62.4Hz,arunningaveragecanbeperformed.Byaveraging
two consecutive LTC2435-1 readings, a sinc1 notch is
combined with the sinc4 digital filter, yielding the fre-
quency response shown in Figure 37. The averaging
operation still keeps the output rate with the following
algorithm:
One of the advantages delta-sigma ADCs offer over con-
ventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2435/LTC2435-1 sig-
nificantly simplifies antialiasing filter requirements.
The sinc4 digital filter provides greater than 120dB normal
mode rejection at all frequencies except DC and integer
multiples of the modulator sampling frequency (fS). Inde-
pendent of the operating mode, fS = 256 • fN = 1024 •
f
OUTMAX wherefN isthenotchfrequencyandfOUTMAX isthe
maximumoutputdatarate. Intheinternaloscillatormode,
for the LTC2435, FS = 12800Hz with a 50Hz notch setting
and fS = 15360Hz with a 60Hz notch setting. For the
LTC2435-1, fS = 13980Hz (FO = LOW). In the external
oscillator mode, fS = fEOSC/10.
Result 1 = average (sample 0, sample 1)
Result 2 = average (sample 1, sample 2)
Result n = average (sample n-1, sample n)
The normal mode rejection performance is shown in
Figure 34. The regions of low rejection occurring at
integer multiples of fS have a very narrow bandwidth.
Magnified details of the normal mode rejection curves are
shown in Figure 35 (rejection near DC) and Figure 36
(rejection at fS = 256fN) where fN represents the notch
frequency. For the LTC2435, the bandwidth is 13.6Hz
(FO = GND) and 11.4Hz (FO = VCC). The Bandwidth is
12.4Hz for the LTC2435-1 (FO = GND).
The user can expect to achieve in practice this level of
performance using the internal oscillator as it is demon-
stratedbyFigures38to40.Typicalmeasuredvaluesofthe
normalmoderejectionoftheLTC2435-1operatingwithan
internal oscillator and a 54.6Hz notch setting are shown in
Figure38and39superimposedoverthetheoreticalcalcu-
lated curve. The same normal mode rejection perfor-
mance is obtained for the LTC2435 with the frequency
scaled to have the notch frequency at 60Hz (FO = GND) or
50Hz (FO = VCC).
0
0
–20
–40
F
O
= HIGH
–10
–20
–30
–40
–50
–60
–80
–60
–70
–80
–100
–120
–140
–90
–100
–110
–120
0
f
2f 3f 4f 5f 6f 7f 8f 9f 10f 11f 12f
S S S S S S S S S S S S
f /2
S
f
0
S
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
INPUT FREQUENCY
2435 F34a
2435 F34b
Figure 34a. Input Normal Mode Rejection,
Internal Oscillator and 50Hz Notch (LTC2435)
Figure 34b. Input Normal Mode Rejection, Internal
Oscillator and FO = Low or External Oscillator
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As a result of these remarkable normal mode specifica-
tions, minimal (if any) antialias filtering is required in front
of the LTC2435/LTC2435-1. If passive RC components
are placed in front of the LTC2435/LTC2435-1, the input
dynamic current should be considered (see Input Current
section). In cases where large effective RC time constants
are used, an external buffer amplifier may be required to
minimize the effects of dynamic input current.
posed over the more traditional normal mode rejection
ratio results obtained with a 5V peak-to-peak (full scale)
input signal. The same performance is obtained for the
LTC2435 with the frequency scaled to have the notch fre-
quency at 60Hz (FO = GND) or 50Hz (FO = VCC). It is clear
that the LTC2435/LTC2435-1 rejection performance is
maintained with no compromises in this extreme situa-
tion. When operating with large input signal levels, the
user must observe that such signals do not violate the
device absolute maximum ratings.
Traditionalhighorderdelta-sigmamodulators,whilepro-
viding very good linearity and resolution, suffer from
potential instabilities at large input signal levels. The pro-
prietary architecture used for the LTC2435/LTC2435-1
third order modulator resolves this problem and guaran-
tees a predictable stable behavior at input signal levels of
up to 150% of full scale. In many industrial applications,
it is not uncommon to have to measure microvolt level
signals superimposed over volt level perturbations and
LTC2435/LTC2435-1 are eminently suited for such tasks.
When the perturbation is differential, the specification of
interestisthenormalmoderejectionforlargeinputsignal
levels. With a reference voltage VREF = 5V, the LTC2435/
LTC2435-1 have a full-scale differential input range of 5V
peak-to-peak. Figure 40 shows measurement results for
the LTC2435-1 normal mode rejection ratio with a 7.5V
peak-to-peak (150% of full scale) input signal superim-
0
–20
–40
–60
–80
–100
–120
248 250 252 254 256 258 260 262 264
INPUT SIGNAL FREQUENCY (f )
N
2435 F36
Figure 36. Input Normal Mode Rejection
0
–20
–70
–80
NO AVERAGE
–90
–40
WITH
RUNNING
AVERAGE
–100
–110
–120
–130
–140
–60
–80
–100
–120
0
f
2f
3f
4f 5f
N
6f
7f
8f
N
56
60
62
48 50
52
54
58
N
N
N
N
N
N
INPUT SIGNAL FREQUENCY (f )
N
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2435 F35
2435 F37
Figure 35. Input Normal Mode Rejection
Figure 37. LTC2435-1 Input Normal Mode Rejection
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0
0
–20
MEASURED DATA
CALCULATED DATA
V
V
= 5V
= 5V
MEASURED DATA
CALCULATED DATA
V
V
= 5V
= 5V
CC
CC
REF
REF
–
–
–20
–40
REF = GND
REF = GND
V
V
F
= 2.5V
= 5V
= GND
V
V
F
= 2.5V
= 5V
INCM
INCM
IN(P-P)
IN(P-P)
–40
= GND
= 25°C
O
O
T
= 25°C
T
A
A
–60
–60
–80
–80
–100
–120
–100
–120
0
25 50 75 100 125 150 175 200 225
INPUT FREQUENCY (Hz)
0
25 50 75 100 125 150 175 200 225
INPUT FREQUENCY (Hz)
2435 F38
2435 F39
Figure 38. Input Normal Mode Rejection
vs Input Frequency (LTC2435-1)
Figure 39. Input Normal Mode Rejection
vs Input Frequency with Running Average
0
–20
V
V
= 5V
= 7.5V
(150% OF FULL SCALE)
V
V
= 5V
IN(P-P)
IN(P-P)
CC
= 5V
REF
–
REF = GND
V
= 2.5V
INCM
F
T
= GND
= 25°C
O
–40
A
–60
–80
–100
–120
0
25 50 75 100 125 150 175 200 225
INPUT FREQUENCY (Hz)
2435 F40
Figure 40. Measured Input Normal Mode
Rejection vs Input Frequency (fN = 54.6Hz)
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Sample Driver for LTC2435/LTC2435-1 SPI Interface
The listing in Figure 43 is a data collection program for the
LTC2435/LTC2435-1usingthePIC16F73microcontroller.
The microcontroller is configured to transfer data through
the SPI serial interface. Figure 42 shows the connection.
The LT1180A is a dual RS232 driver/receiver pair with
integral charge pump that generates RS232 voltage levels
from a single 5V supply.
Figure 41 shows the use of an LTC2435/LTC2435-1 with
a differential multiplexer. This is an inexpensive multi-
plexer that will contribute some error due to leakage if
used directly with the output from the bridge, or if
resistors are inserted as a protection mechanism from
overvoltage.Althoughthebridgeoutputmaybewithinthe
input range of the A/D and multiplexer in normal opera-
tion, some thought should be given to fault conditions
that could result in full excitation voltage at the inputs to
the multiplexer or ADC. The use of amplification prior to
the multiplexer will largely eliminate errors associated
with channel leakage developing error voltages in the
source impedance.
The program begins by declaring variables and allocating
memory locations to store the 24-bit conversion result.
The main sequence starts with pulling CS LOW. It then
waits for SDO to go LOW to start reading data. Three bytes
are read to the MCU and the LTC2435/LTC2435-1 will
automatically start a new conversion. CS is also raised to
HIGH to ensure that a new conversion is started. The
collected data are sent out through the serial port at 57600
baud. This can be captured with a terminal program and
analyzed with a spreadsheet using the HEX2DEC function.
The LTC2435/LTC2435-1 have a very simple serial inter-
face that makes interfacing to microprocessors and
microcontrollers very easy.
5V
5V
+
16
2
47μF
12
14
15
11
V
CC
3
4
+
–
REF
REF
LTC2435/
LTC2435-1
74HC4052
1
5
5
6
13
3
+
IN
–
IN
2
4
TO OTHER
DEVICES
GND
1, 7, 8, 9,
10, 15, 16
6
8
9
10
A0
A1
2435 F41
Figure 41. Use a Differential Multiplexer to Expand Channel Capability
V
CC
20
PIC16F73
RC2
RC3
RC4
X1
1
2
3
4
5
LT1180A
6
7
8
9
13
12
11
13
14
15
15
8
14
9
17
18
12
11
13
10
18
SCK
SDO
CS
RC6
RC7
T1IN
T1OUT
LTC2435/
LTC2435-1
T2IN
T2OUT
R1IN
R2IN
R1OUT
R2OUT
SHDN
17
V
C1
C2
V
CC
V
CC
CC
C3
8
19
3
7
2
+
+
C1
V
C5
4
5
–
–
C1
V
+
C2
C4
16
6
–
C2
GND
2435 F42
Figure 42. Connecting the LTC2435/LTC2435-1 to a PIC16F73 MCU Using the SPI Serial Interface
24351fb
35
LTC2435/LTC2435-1
U
W U U
APPLICATIO S I FOR ATIO
// Basic data collection program for the LTC2435 using the
// PIC16F73 microcontroller. Collects data as fast as possible
// and sends it out the serial port at 57600 baud as six
// hexadecimal characters, followed by a carriage return.
// This can be captured with a terminal program and analyzed
// with a spreadsheet using the HEX2DEC function (in Excel.)
//
// Written for the CCS compiler, version 3.049.
////////////////////////////////////////////////////////////////////
#include <16F73.h>
#byte SSPCON = 0x14
#byte SSPSTAT = 0x94
#bit CKE = SSPSTAT.6
#bit CKP = SSPCON.4
#bit SSPEN = SSPCON.5
#fuses HS,NOWDT,PUT
#use delay(clock=10000000)
// Synchronous serial port control
// registers.
// For baud rate calculation.
#use rs232(baud=57600,parity=N,xmit=PIN_C6,rcv=PIN_C7)
// Serial data is sent on pin C6.
#define CS_ PIN_C2
#define CLOCK PIN_C
#define SDO PIN_C4
// Chip select connected to pin C2
// Clock connected to pin C3
// SDO on the LTC2435 connected to pin C4
// (this is SDI on the PIC;
// Master In, Slave Out (MISO) is less ambiguous)
void main() {
// Basic configuration, no bearing on operation of LTC2435
setup_adc_ports(NO_ANALOGS);
setup_adc(ADC_CLOCK_DIV_2);
setup_counters(RTCC_INTERNAL,RTCC_DIV_2);
setup_timer_1(T1_DISABLED);
setup_timer_2(T2_DISABLED,0,1);
setup_ccp1(CCP_OFF);
setup_ccp2(CCP_OFF);
// LTC2435 is connected to the processor’s hardware SPI port.
// This sets the port such that data is shifted on clock falling edges and
// valid on rising edges. For a 10 MHz master clock, the SPI clock frequency
// wil be 2.5 MHz.
setup_spi(SPI_MASTER|SPI_L_TO_H|SPI_CLK_DIV_4|SPI_SS_DISABLED);
CKP = 0; // Set up clock edges - clock idles low, data changes on
CKE = 1; // falling edges, valid on rising edges.
24351fb
36
LTC2435/LTC2435-1
U
W
U U
APPLICATIO S I FOR ATIO
while(1)
{
output_low(CS_);
// Enable LTC2435
while(input(SDO)) { /* Wait for SDO to fall, indicating end of conversion.*/ }
printf(“%2X”,spi_read(0));
printf(“%2X”,spi_read(0));
printf(“%2X”,spi_read(0));
printf(“\r”);
// Read first byte, send 2 hex characters.
// Read second byte, send 2 hex characters.
/ Read third byte, send 2 hex characters.
// Send carriage return.
// Conversion actually started after last data byte was read,
// but raising CS_ ensures the loop will never lock up waiting for
// a low on SDO if a clock pulse is missed for some reason.
output_high(CS_);
}
}
Figure 43. A Sample Program for Data Collection from the
LTC2435/LTC2435-1 Using the PIC16F73 Microcontroller.
24351fb
37
LTC2435/LTC2435-1
U
W U U
APPLICATIO S I FOR ATIO
Correlated Double Sampling with the
LTC2435/LTC2435-1
low, determined by the ESR and inductance of the capaci-
tors above 10MHz. The conversion spikes that remain at
the output of other bipolar amplifiers pass through the
feedback network and often overdrive the input of the
amplifier, producing envelope detection. RFI may also be
present on the signal lines from the bridge; C3 and C4
provide RFI suppression at the signal input, as well as
suppressing transient voltages during bridge commuta-
tion.
TheTypicalApplicationonthebackpageofthisdatasheet
shows the LTC2435/LTC2435-1 in a correlated double
sampling circuit that achieves a noise floor of under
100nV. In this scheme, the polarity of the bridge is
alternatedeveryothersampleandtheresultistheaverage
of a pair of samples of opposite sign. This technique has
the benefit of canceling any fixed DC error components in
the bridge, amplifiers and the converter, as these will
alternate in polarity relative to the signal. Offset voltages
and currents, thermocouple voltages at junctions of dis-
similarmetalsandthelowerfrequencycomponentsof1/f
noise are virtually eliminated.
The wideband noise density of the LT1219 is 33nV/√Hz,
seemingly much noisier than the lowest noise amplifiers.
However, in the region just below the 1/f corner that is not
well suppressed by the correlated double sampling, the
average noise density is similar to the noise density of
many low noise amplifiers. If the amplifier is rolled off
below about 1500Hz, the total noise bandwidth is deter-
mined by the converter’s Sinc4 filter at about 12Hz. The
use of correlated double sampling involves averaging
even numbers of samples; hence, in this situation, two
samples would be averaged to give an input-referred
The LTC2435/LTC2435-1 have the virtue of being able to
digitize an input voltage that is outside the range defined
by the reference, thereby providing a simple means to
implement a ratiometric example of correlated double
sampling.
Thiscircuitusesabipolaramplifier(LT1219—U1andU2)
that has neither the lowest noise nor the highest gain. It
does, however, have an output stage that can effectively
suppress the conversion spikes from the LTC2435/
LTC2435-1. The LT1219 is a C-LoadTM stable amplifier
that, bydesign, needsatleast0.1μFoutputcapacitanceto
remain stable. The 0.1μF ceramic capacitors at the out-
puts(C1andC2)shouldbeplacedandroutedtominimize
lead inductance or their effectiveness in preventing enve-
lope detection in the input stage will be reduced. Alterna-
tively, several smaller capacitors could be placed so that
leadinductanceisfurtherreduced. Thisisaconsideration
because the frequency content of the conversion spikes
extends to 50MHz or more. The output impedance of
most op amps increases dramatically with frequency but
the effective output impedance of the LT1219 remains
noise level of about 100nVRMS
.
Level shift transistors Q4 and Q5 are included to allow
excitation voltages up to the maximum recommended for
the bridge. In the case shown, if a 10V supply is used, the
excitation voltage to the bridge is 8.5V and the outputs of
the bridge are above the supply rail of the ADC. U1 and U2
are also used to produce a level shift to bring the outputs
within the input range of the converter. This instrumenta-
tion amplifier topology does not require well-matched
resistors in order to produce good CMRR. However, the
use of R2 requires that R3 and R6 match well, as the
commonmodegainisapproximately–12dB. Ifthebridge
is composed of four equal 350Ω resistors, the differential
component associated with mismatch of R3 and R6 is
nearly constant with either polarity of excitation and, as
with offset, its contribution is canceled.
C-Load is a trademark of Linear Technology Corporation.
24351fb
38
LTC2435/LTC2435-1
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 .005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 .004
(0.38 0.10)
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
(0.203 – 0.305)
TYP
GN16 (SSOP) 0204
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
24351fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
39
LTC2435/LTC2435-1
U
TYPICAL APPLICATIO
Correlated Double Sampling Resolves 100nV
10V
ELIMINATE FOR 5V
1.5k
1.5k
DIFFERENCE
10V
OPERATION (CONNECT 2.7k
AMP
RESISTORS TO 100Ω
RESISTORS)
0.1μf
Q2
Q3
100Ω
7
3
2
+
–
100Ω
5k
U1
LT1219
6
R2
27k
22Ω
5
C1
22Ω
4
SHDN
0.1μF
5V
Q4
1k
Q5
5V
5V
R4
499Ω
R3 10k
1000pF
1000pF
2.7k
2.7k
5
6
3
4
+
–
C3 2.2nF
C4 2.2nF
IN
350Ω
×4
R5
499Ω
R6 10k
10V
IN
LTC2435/
LTC2435-1
+
POL
REF
0.1μf
1k
74HC04
–
+
7
2
3
–
REF
5k
U2
6
LT1219
Q1
GND
5
C2
22Ω
4
0.1μF
SHDN
R1
33Ω
61.9Ω
0.1%
100Ω
SILICONIX Si9802DY (800) 554-5565
MMBD2907
MMBD3904
Q1:
Q2, Q3:
Q4, Q5:
30pF
30pF
22Ω
2435 F46
RELATED PARTS
PART NUMBER
LT1019
DESCRIPTION
Precision Bandgap Reference, 2.5V, 5V
COMMENTS
3ppm/°C Drift, 0.05% Max Initial Accuracy
80μA Supply Current, 0.5°C Initial Accuracy
LT1025
Micropower Thermocouple Cold Junction Compensator
LTC1043
Dual Precision Instrumentation Switched Capacitor
Building Block
Precise Charge, Balanced Switching, Low Power
LTC1050
LT1236A-5
LT1460
Precision Chopper Stabilized Op Amp
Precision Bandgap Reference, 5V
Micropower Series Reference
No External Components 5μV Offset, 1.6μV Noise
P-P
0.05% Max Initial Accuracy, 5ppm/°C Drift
0.075% Max Initial Accuracy, 10ppm/°C Max Drift,
LTC2400
24-Bit, No Latency ΔΣ ADC in SO-8
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA
0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA
LTC2401/LTC2402 1-/2-Channel, 24-Bit, No Latency ΔΣ ADCs in MSOP
LTC2404/LTC2408 4-/8-Channel, 24-Bit, No Latency ΔΣ ADCs with Differential Inputs 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA
LTC2410
24-Bit, No Latency ΔΣ ADC with Differential Inputs
800nV
Noise, Pin Compatible with LTC2435
RMS
LTC2411/
24-Bit, No Latency ΔΣ ADC with Differential Inputs in MSOP
1.45μV
RMS
Noise, 4ppm INL,
Simultaneous 50Hz/60Hz Rejection (LTC2411-1)
Simultaneous 50Hz/60Hz Rejection, 800nV Noise
LTC2411-1
LTC2413
24-Bit, No Latency ΔΣ ADC with Differential Inputs
24-Bit, No Latency ΔΣ ADC with 15Hz Output Rate
RMS
LTC2415/
LTC2415-1
Pin Compatible with the LTC2435/LTC2435-1
LTC2414/LTC2418 8-/16-Channel 24-Bit, No Latency ΔΣ ADC
LTC2420 20-Bit, No Latency ΔΣ ADC in SO-8
0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200μA
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400
2.8μV Noise, SSOP-16/MSOP Package
LTC2430/LTC2431 20-Bit, No Latency ΔΣ ADC with Differential Inputs
24351fb
LT 0807 REV B • PRINTED IN USA
40 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2001
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