LTC2440CGN [Linear]
24-Bit High Speed Differential delta-sigma ADC with Selectable Speed/Resolution; 24位高速差分Δ-Σ ADC，具有可选速度/分辨率
| 型号： | LTC2440CGN |
| 厂家： | 
Linear |
| 描述： | 24-Bit High Speed Differential delta-sigma ADC with Selectable Speed/Resolution |
| 文件： | 总28页 (文件大小：302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2440
24-Bit High Speed
Differential ∆Σ ADC with
Selectable Speed/Resolution
U
DESCRIPTIO
FEATURES
■
Up to 3.5kHz Output Rate
TheLTC®2440isahighspeed24-bitNoLatency∆ΣTM ADC
with 5ppm INL and 5µV offset. It uses proprietary delta-
sigma architecture enabling variable speed and resolution
withnolatency.Tenspeed/resolutioncombinations(6.9Hz/
200nVRMS to 3.5kHz/25µVRMS) are programmed through
asimpleserialinterface. Alternatively, bytyingasinglepin
HIGH or LOW, a fast (880Hz/2µVRMS) or ultralow noise
(6.9Hz, 200nVRMS, 50/60Hz rejection) speed/resolution
combination can be easily selected. The accuracy (offset,
full-scale, linearity, drift) and power dissipation are inde-
pendent of the speed selected. Since there is no latency,
a speed/resolution change may be made between conver-
sions with no degradation in performance.
■
Selectable Speed/Resolution
■
2µVRMS Noise at 880Hz Output Rate
■
200nVRMS Noise at 6.9Hz Output Rate with
Simultaneous 50/60Hz Rejection
■
0.0005% INL, No Missing Codes
■
Autosleep Enables 20µA Operation at 6.9Hz
■
<5µV Offset (4.5V < VCC < 5.5V, –40°C to 85°C)
■
Differential Input and Differential Reference with
GND to VCC Common Mode Range
■
No Latency, Each Conversion is Accurate Even After
an Input Step
■
Internal Oscillator—No External Components
■
Pin Compatible with the LTC2410
Following each conversion cycle, the LTC2440 automati-
cally enters a low power sleep state. Power dissipation
may be reduced by increasing the duration of this sleep
state. For example, running at the 3.5kHz conversion
speed but reading data at a 100Hz rate draws 240µA
average current (1.1mW) while reading data at a 7Hz
outputratedrawsonly25µA(125µW).TheLTC2440com-
municates through a flexible 3-wire or 4-wire digital inter-
face that is compatible with the LTC2410 and is available
in a narrow 16-lead SSOP package.
■
24-Bit ADC in Narrow 16-Lead SSOP Package
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APPLICATIO S
■
High Speed Multiplexing
Weight Scales
■
■
Auto Ranging 6-Digit DVMs
■
Direct Temperature Measurement
■
High Speed Data Acquisition
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ is a trademark of Linear Technology Corporation.
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TYPICAL APPLICATIO
Speed vs RMS Noise
100
Simple 24-Bit 2-Speed Acquisition System
V
V
V
= 5V
CC
= 5V
IN
REF
+
–
4.5V TO 5.5V
= V = 0V
IN
10
1
2
15
V
BUSY
CC
2µV AT 880Hz
LTC2440
3
4
5
6
14
13
12
+
F
O
REF
REFERENCE VOLTAGE
200nV AT 6.9Hz
(50/60Hz REJECTION)
0.1V TO V
–
CC
REF
SCK
SDO
CS
V
CC
3-WIRE
+
IN
ANALOG INPUT
6.9Hz, 200nV NOISE,
50/60Hz REJECTION
SPI INTERFACE
11
7
–0.5V
TO 0.5V
–
REF
REF
IN
10-SPEED SERIAL
PROGRAMMABLE
SDI
EXT
0.1
1, 8, 9, 16
10
1
10
100
1000
10000
GND
880Hz OUTPUT RATE,
2µV NOISE
CONVERSION RATE (Hz)
2440 TA01
2440 TA01
2440 TA02
sn2440, 2440fas
1
LTC2440
W W
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W
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ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Notes 1, 2)
TOP VIEW
ORDER PART NUMBER
Supply Voltage (VCC) to GND.......................–0.3V to 6V
Analog Input Pins Voltage
to GND.................................... –0.3V to (VCC + 0.3V)
Reference Input Pins Voltage
to GND.................................... –0.3V to (VCC + 0.3V)
Digital Input Voltage to GND........ –0.3V to (VCC + 0.3V)
Digital Output Voltage to GND ..... –0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2440C ............................................... 0°C to 70°C
LTC2440I............................................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
GND
LTC2440CGN
LTC2440IGN
BUSY
V
CC
+
F
REF
REF
IN
O
–
+
–
SCK
SDO
CS
IN
GN PART MARKING
EXT
GND
SDI
GND
2440
2440I
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 110°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
Integral Nonlinearity
0.1V ≤ V ≤ V , –0.5 • V ≤ V ≤ 0.5 • V , (Note 5)
●
●
24
Bits
REF
CC
REF
IN
REF
+
–
V
= 5V, REF = 5V, REF = GND, V
= 2.5V, (Note 6)
5
3
15
5
ppm of V
ppm of V
CC
INCM
REF
REF
+
–
REF = 2.5V, REF = GND, V
= 1.25V, (Note 6)
INCM
+
–
Offset Error
2.5V ≤ REF ≤ V , REF = GND,
●
2.5
µV
CC
+
–
GND ≤ IN = IN ≤ V (Note 12)
CC
+
–
Offset Error Drift
2.5V ≤ REF ≤ V , REF = GND,
20
nV/°C
CC
+
–
GND ≤ IN = IN ≤ V
CC
+
–
+
–
Positive Full-Scale Error
Positive Full-Scale Error Drift
Negative Full-Scale Error
Negative Full-Scale Error Drift
Total Unadjusted Error
REF = 5V, REF = GND, IN = 3.75V, IN = 1.25V
●
●
10
10
30
50
ppm of V
ppm of V
REF
REF
+
–
+
–
REF = 2.5V, REF = GND, IN = 1.875V, IN = 0.625V
+
–
2.5V ≤ REF ≤ V , REF = GND,
IN = 0.75REF , IN = 0.25 • REF
0.2
ppm of V /°C
REF
CC
+
+
–
+
+
–
+
–
REF = 5V, REF = GND, IN = 1.25V, IN = 3.75V
●
●
10
10
30
50
ppm of V
ppm of V
REF
REF
+
–
+
–
REF = 2.5V, REF = GND, IN = 0.625V, IN = 1.875V
+
–
2.5V ≤ REF ≤ V , REF = GND,
IN = 0.25 • REF , IN = 0.75 • REF
0.2
ppm of V /°C
REF
CC
+
+
–
+
+
–
5V ≤ V ≤ 5.5V, REF = 2.5V, REF = GND, V
= 1.25V
15
15
15
ppm of V
ppm of V
ppm of V
CC
INCM
REF
REF
REF
+
–
5V ≤ V ≤ 5.5V, REF = 5V, REF = GND, V
= 2.5V
CC
INCM
+
–
REF = 2.5V, REF = GND, V
= 1.25V, (Note 6)
INCM
+
–
Input Common Mode Rejection DC 2.5V ≤ REF ≤ V , REF = GND,
120
dB
CC
–
+
GND ≤ IN = IN ≤ V
CC
sn2440, 2440fas
2
LTC2440
U
U
U
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A ALOG I PUT A D REFERE CE The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
+
IN
Absolute/Common Mode IN Voltage
●
●
●
GND – 0.3V
GND – 0.3V
V
V
+ 0.3V
V
V
V
CC
CC
–
–
IN
Absolute/Common Mode IN Voltage
+ 0.3V
/2
V
Input Differential Voltage Range
–V /2
REF
V
IN
REF
+
–
(IN – IN )
+
–
+
REF
REF
Absolute/Common Mode REF Voltage
●
●
●
0.1
GND
0.1
V
V
V
V
CC
–
Absolute/Common Mode REF Voltage
V
– 0.1V
CC
V
Reference Differential Voltage Range
V
CC
REF
+
–
(REF – REF )
+
C
C
C
C
IN Sampling Capacitance
3.5
3.5
3.5
3.5
10
pF
pF
pF
pF
nA
S(IN+)
–
IN Sampling Capacitance
S(IN–)
+
REF Sampling Capacitance
S(REF+)
–
REF Sampling Capacitance
S(REF–)
+
–
I
Leakage Current, Inputs and Reference
CS = V , IN = GND, IN = GND,
●
–100
100
DC_LEAK(IN+, IN–,
CC
+
–
REF = 5V, REF = GND
REF+, REF–)
I
Average Input/Reference Current
During Sampling
Varies, See Applications Section
SAMPLE(IN+, IN–,
REF+, REF–)
U
U
DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
4.5V ≤ V ≤ 5.5V
MIN
TYP
MAX
UNITS
V
V
V
V
High Level Input Voltage
●
●
●
●
●
●
2.5
V
IH
IL
IH
IL
CC
CS, F
O
Low Level Input Voltage
CS, F
4.5V ≤ V ≤ 5.5V
0.8
V
V
CC
O
High Level Input Voltage
SCK
4.5V ≤ V ≤ 5.5V (Note 8)
2.5
CC
Low Level Input Voltage
SCK
4.5V ≤ V ≤ 5.5V (Note 8)
0.8
10
10
V
CC
I
I
Digital Input Current
0V ≤ V ≤ V
CC
–10
–10
µA
µA
pF
pF
V
IN
IN
CS, F
O
Digital Input Current
SCK
0V ≤ V ≤ V (Note 8)
IN
IN
CC
C
C
V
V
V
V
Digital Input Capacitance
10
10
IN
CS, F
O
Digital Input Capacitance
SCK
(Note 8)
IN
High Level Output Voltage
SDO, BUSY
I = –800µA
O
●
●
●
●
●
V
V
– 0.5V
– 0.5V
OH
OL
OH
OL
CC
CC
Low Level Output Voltage
SDO, BUSY
I = 1.6mA
O
0.4V
V
High Level Output Voltage
SCK
I = –800µA (Note 9)
O
V
Low Level Output Voltage
SCK
I = 1.6mA (Note 9)
O
0.4V
10
V
I
Hi-Z Output Leakage
SDO
–10
µA
OZ
sn2440, 2440fas
3
LTC2440
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POWER REQUIRE E TS
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
Supply Voltage
Supply Current
CONDITIONS
MIN
TYP
MAX
UNITS
V
CC
●
4.5
5.5
V
I
CC
Conversion Mode
Sleep Mode
CS = 0V (Note 7)
●
●
8
8
11
30
mA
µA
CS = V (Note 7)
CC
W U
TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
0.1
25
TYP
MAX
20
UNITS
MHz
ns
f
t
t
t
External Oscillator Frequency Range
External Oscillator High Period
External Oscillator Low Period
Conversion Time
●
●
●
EOSC
HEO
10000
10000
25
ns
LEO
OSR = 256 (SDI = 0)
OSR = 32768 (SDI = 1)
●
●
0.99
126
1.13
145
1.33
170
ms
ms
CONV
40 • OSR + 170
External Oscillator (Note 10, 13)
●
●
ms
f
(kHz)
EOSC
f
Internal SCK Frequency
Internal Oscillator (Note 9)
External Oscillator (Notes 9, 10)
0.8
45
0.9
EOSC
1
MHz
Hz
ISCK
f
/10
D
ISCK
Internal SCK Duty Cycle
(Note 9)
(Note 8)
(Note 8)
(Note 8)
●
●
●
●
55
20
%
MHz
ns
f
t
t
t
External SCK Frequency Range
External SCK Low Period
ESCK
25
25
LESCK
External SCK High Period
ns
HESCK
DOUT_ISCK
Internal SCK 32-Bit Data Output Time
Internal Oscillator (Notes 9, 11)
External Oscillator (Notes 9, 10)
●
●
41.6
35.3
EOSC
30.9
µs
s
320/f
t
t
t
t
t
t
t
t
t
t
External SCK 32-Bit Data Output Time
CS ↓ to SDO Low Z
CS ↑ to SDO High Z
CS ↓ to SCK ↓
CS ↓ to SCK ↑
SCK ↓ to SDO Valid
(Note 8)
●
●
●
32/f
s
ns
ns
µs
ns
ns
ns
ns
ns
ns
DOUT_ESCK
ESCK
(Note 12)
(Note 12)
(Note 9)
0
0
25
25
1
2
5
3
(Notes 8, 12)
●
●
●
●
●
●
25
4
25
KQMAX
SDO Hold After SCK ↓
SCK Set-Up Before CS ↓
SDI Setup Before SCK ↑
SDI Hold After SCK ↑
(Note 5)
15
50
10
10
KQMIN
5
7
8
Note 5
Note 5
Note 1: Absolute Maximum Ratings are those values beyond which the life
Note 7: The converter uses the internal oscillator.
of the device may be impaired.
Note 8: The converter is in external SCK mode of operation such that the
Note 2: All voltage values are with respect to GND.
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is f
and is expressed in Hz.
ESCK
Note 3: V = 4.5 to 5.5V unless otherwise specified.
CC
+
–
+
–
V
V
= REF – REF , V
= IN – IN , V
= (REF + REF )/2;
Note 9: The converter is in internal SCK mode of operation such that the
SCK pin is used as a digital output. In this mode of operation, the SCK pin
REF
REFCM
+
–
+
–
= (IN + IN )/2.
IN
INCM
has a total equivalent load capacitance of C
= 20pF.
LOAD
Note 4: F pin tied to GND or to external conversion clock source with
O
f
= 10MHz unless otherwise specified.
Note 10: The external oscillator is connected to the F pin. The external
EOSC
O
oscillator frequency, f
, is expressed in kHz.
EOSC
Note 5: Guaranteed by design, not subject to test.
Note 11: The converter uses the internal oscillator. F = 0V.
Note 12: Guaranteed by design and test correlation.
Note 13: There is an internal reset that adds an additional 1µs (typical) to
the conversion time.
O
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
sn2440, 2440fas
4
LTC2440
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TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity fOUT = 3.5kHz
Integral Nonlinearity fOUT = 1.76kHz
Integral Nonlinearity fOUT = 880Hz
10
5
10
5
10
5
V
V
V
V
= 5V
= 5V
V
O
= 2.5V
INCM
V
V
V
V
= 5V
= 5V
V
F
A
= 2.5V
V
V
V
V
= 5V
= 5V
V
O
= 2.5V
INCM
CC
CC
INCM
O
CC
F
= GND
= GND
F
= GND
REF
REF
REF
REF
REF
REF
REF
REF
REF
+
–
+
–
+
–
= 5V
T = 25°C
A
= 5V
T
= 25°C
= 5V
T = 25°C
A
= GND
= GND
= GND
0
0
0
–5
–5
–5
–10
–10
–10
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
V
(V)
V
(V)
V
IN
(V)
IN
IN
2440 G02
2440 G01
2440 G03
Integral Nonlinearity fOUT = 440Hz
Integral Nonlinearity fOUT = 220Hz
Integral Nonlinearity fOUT = 110Hz
10
5
10
5
10
5
V
V
V
V
= 5V
= 5V
V
O
= 2.5V
INCM
V
V
V
V
= 5V
= 5V
V
F
A
= 2.5V
V
V
V
V
= 5V
= 5V
V
O
= 2.5V
INCM
CC
CC
INCM
O
CC
F
= GND
= GND
F
= GND
REF
REF
REF
REF
REF
REF
REF
REF
REF
+
–
+
–
+
–
= 5V
T = 25°C
A
= 5V
T
= 25°C
= 5V
T = 25°C
A
= GND
= GND
= GND
0
0
0
–5
–5
–5
–10
–10
–10
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2 2.5
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
V
(V)
V
(V)
V
IN
(V)
IN
IN
2440 G06
2440 G04
2440 G05
Integral Nonlinearity fOUT = 55Hz
Integral Nonlinearity fOUT = 27.5Hz
Integral Nonlinearity fOUT = 13.75Hz
10
5
10
5
10
5
V
V
V
V
= 5V
V
= 2.5V
V
V
V
V
= 5V
V
= 2.5V
V
V
V
V
= 5V
V
O
= 2.5V
CC
INCM
CC
INCM
CC
INCM
= 5V
F
= GND
= 5V
F
= GND
= 5V
F = GND
REF
REF
REF
O
REF
REF
REF
O
REF
REF
REF
+
–
+
–
+
–
= 5V
= GND
T
= 25°C
= 5V
= GND
T
= 25°C
= 5V
= GND
T = 25°C
A
A
A
0
0
0
–5
–5
–5
–10
–10
–10
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
V
(V)
V
(V)
V
IN
(V)
IN
IN
2440 G07
2440 G08
2440 G09
sn2440, 2440fas
5
LTC2440
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Integral Nonlinearity
Integral Nonlinearity fOUT = 6.875Hz
vs Conversion Rate
Integral Nonlinearity vs VINCM
10
5
10
5
10.0
7.5
5.0
2.5
V
V
V
V
= 5V
= 5V
V
= 2.5V
INCM
V
V
V
V
= 5V
= 5V
–2.5V ≤ V ≤ 2.5V
CC
CC
IN
F
= GND
V
F
= 2.5V
REF
REF
REF
O
REF
REF
REF
INCM
+
–
+
–
= 5V
T
= 25°C
V
= 3.75V
= 5V
= GND
A
INCM
O
= GND
= GND
T = 25°C
A
V
= 2.5V
INCM
0
0
V
= 1.25V
INCM
–5
–5
0
–10
–10
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
0
500 1000 1500 2000 2500 3000 3500
CONVERSION RATE (Hz)
–1.25
–0.75 –0.25
0.25
(V)
0.75
1.25
V
(V)
V
IN
IN
2440 G10
2440 G11
2440 G12
Integral Nonlinearity
vs Temperature
Integral Nonlinearity
vs Temperature
–Full-Scale Error vs VREF
10
5
10
5
20
10
V
V
V
V
= 5V
V
= 1.25V
V
V
V
V
= 5V
V
= 2.5V
CC
INCM
CC
INCM
= 2.5V
OSR = 32768
= GND
= 5V
OSR = 32768
F = GND
O
REF
REF
REF
REF
REF
REF
+
–
+
–
= 2.5V
= GND
F
= 5V
= GND
O
T
= –55°C
A
T
= 125°C
A
T
= 125°C
A
0
0
0
T
= 25°C
A
T
= 25°C
A
T
= –25°C
A
–5
–5
–10
–20
–10
–10
–1.25
–0.75 –0.25
0.25
(V)
0.75
1.25
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
0
1
3
4
5
2
V
V
(V)
V
(V)
REF
IN
IN
2440 G13
2440 G14
2440 G15
+Full-Scale Error vs VREF
–Full-Scale Error vs VCC
+Full-Scale Error vs VCC
20
10
10
9
8
7
6
5
4
3
2
1
0
0
–1
V
V
V
V
= 2.5V
OSR = 32768
REF
REF
REF
+
= 2.5V
= GND
= 1.25V
F
= GND
O
–
T
= 25°C
A
–2
–3
INCM
–4
–5
–6
–7
–8
–9
–10
0
–10
–20
V
V
V
V
= 2.5V
OSR = 32768
REF
REF
REF
+
= 2.5V
= GND
= 1.25V
F
= GND
O
–
T
= 25°C
A
INCM
0
1
2
3
4
5
4.5
4.7
4.9
V
5.1
(V)
5.3
5.5
4.5
4.7
4.9
V
CC
5.1
(V)
5.3
5.5
V
(V)
REF
CC
2440 G16
2440 G17
2440 G18
sn2440, 2440fas
6
LTC2440
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TYPICAL PERFOR A CE CHARACTERISTICS
Negative Full-Scale Error
vs Temperature
Positive Full-Scale Error
vs Temperature
Offset Error vs VCC
20
15
20
15
5.0
2.5
V
V
V
V
V
= 4.5V
= 4.5V
V
V
V
V
V
= 5.5V, 5V
= 5V
V
V
V
V
= 2.5V
OSR = 32768
CC
CC
REF
REF
+
= 2.5V
F
= GND
REF
REF
REF
REF
REF
REF
O
+
–
+
–
–
= 4.5V
= GND
= 2.25V
= 5V
= GND
T
= 25°C
A
REF
+
–
= GND
= 2.5V
= V = GND
IN
IN
10
10
INCM
INCM
4.5V
5.5V
OSR = 32768 OSR = 32768
= GND
5
5
F
F
= GND
O
O
0
0
0
V
V
V
V
V
= 4.5V
V
V
V
V
V
= 5.5V, 5V
CC
CC
5.5V
5V
–5
–10
–15
–20
–5
–10
–15
–20
= 4.5V
= 5V
REF
REF
REF
REF
REF
REF
+
–
+
–
5V
4.5V
= 4.5V
= GND
= 2.25V
= 5V
= GND
= 2.5V
–2.5
INCM
INCM
OSR = 32768 OSR = 32768
= GND
F
F
= GND
O
O
–5.0
35
–55
–25
5
65
95
125
35
–55
–25
5
65
95
125
4.5
4.7
4.9
5.1
5.3
5.5
TEMPERATURE (°C)
TEMPERATURE (°C)
V
(V)
CC
2440 G19
2440 G20
2440 G21
Offset Error vs Conversion Rate
Offset Error vs VINCM
RMS Noise vs Temperature
3.5
3.0
2.5
2.0
1.5
1.0
0.5
5.0
2.5
0
5.0
2.5
+
–
+
–
V
V
V
V
= 5V
V
= V = GND
CC
IN IN
V
V
V
V
= 5V
V
= V = V
IN IN INCM
CC
= 5V
F
= GND
= 25°C
REF
REF
REF
O
= 5V
OSR = 32768
= GND
= 25°C
REF
REF
REF
+
–
+
–
= 5V
= GND
T
A
= 5V
= GND
F
O
T
A
V
CC
V
CC
V
CC
= 4.5V
= 5V
= 5.5V
0
V
V
V
V
V
= 4.5V
V
V
V
V
V
= 5.5V, 5V
CC
CC
= 2.5V
= 5V
REF
REF
REF
REF
REF
REF
+
–
+
–
= 2.5V
= 5V
–2.5
–2.5
–5.0
= GND
= GND
+
–
+
–
= V = GND
= V = GND
IN
IN
IN
IN
OSR = 256
OSR = 256
F
O
= GND
F = GND
O
–5.0
0
500 1000 1500 2000 2500 3000 3500
CONVERSION RATE (Hz)
–55
5
35
65
95
125
–25
0
1
2
3
4
5
TEMPERATURE (°C)
V
(V)
INCM
2440 G22
2440 G24
2440 G23
INL vs Output Rate
(OSR = 128) External Clock Sweep
10MHz to 20MHz
RMS Noise vs Output Rate
(OSR = 128) External Clock Sweep
10MHz to 20MHz
Offset Error vs Temperature
5.0
2.5
20
18
16
14
12
10
8
5
4
3
2
1
0
V
= 5V
V
CC
EXTERNAL CLOCK 10MHz
V
= 5.5V
V
V
= 4.5V
CC
CC
(OR INTERNAL OSCILLATOR)
EXTERNAL
CLOCK 20MHz
0
= 4.5V
= 5.5V, 5V
CC
CC
V
V
V
V
= 2.5V
V
V
V
V
= 5V
REF
REF
REF
REF
REF
REF
+
–
+
–
6
= 2.5V
= 5V
–2.5
–5.0
= GND
= GND
V
= V = 5V
CC
V
= V = 5V
REF CC
4
REF
+
–
+
–
= V = GND
= V = GND
IN
IN
IN
IN
TEMP = 25°C
SWEEP (V – V /2) TO V /2
TEMP = 25°C
OSR = 256
OSR = 256
2
V
± V /2
IN
REF
REF
IN
REF
F
O
= GND
F = GND
O
0
2000
–55
5
35
65
95
125
–25
2500
3000
3500
4000
2000
2500
3000
3500
4000
TEMPERATURE (°C)
OUTPUT RATE (Hz)
OUTPUT RATE (Hz)
2440 G25
2440 G26
2440 G27
sn2440, 2440fas
7
LTC2440
U
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PI FU CTIO S
selected. The device generates its own SCK signal and
outputs this on the SCK pin. A framing signal BUSY
(Pin 15) goes low indicating data is being output.
GND (Pins 1, 8, 9, 16): Ground. Multiple ground pins
internally connected for optimum ground current flow and
VCC decoupling. Connect each one of these pins to a ground
plane through a low impedance connection. All four pins
must be connected to ground for proper operation.
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
VCC (Pin 2): Positive Supply Voltage. Bypass to GND
(Pin 1) with a 10µF tantalum capacitor in parallel with
0.1µF ceramic capacitor as close to the part as possible.
REF+ (Pin 3), REF– (Pin 4): Differential Reference Input.
ThevoltageonthesepinscanhaveanyvaluebetweenGND
and VCC as long as the reference positive input, REF+, is
maintained more positive than the reference negative
input, REF –, by at least 0.1V.
IN+ (Pin 5), IN– (Pin 6): Differential Analog Input. The
voltage on these pins can have any value between
GND – 0.3V and VCC + 0.3V. Within these limits the con-
verter bipolar input range (VIN = IN+ – IN–) extends from
–0.5 • (VREF) to 0.5 • (VREF). Outside this input range the
converter produces unique overrange and underrange
output codes.
SDO (Pin 12): Three-State Digital Output. During the Data
Output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = VCC) the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output.
TheconversionstatuscanbeobservedbypullingCSLOW.
SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as digital input for the external serial interface
clock during the Data Output period. The Serial Clock
Operation mode is determined by the logic level applied to
the EXT pin.
SDI(Pin7):SerialDataInput.Thispinisusedtoselectthe
speed/resolution of the converter. If SDI is grounded (pin
compatible with LTC2410) the device outputs data at
880Hz with 21 bits effective resolution. By tying SDI
HIGH, the converter enters the ultralow noise mode
(200nVRMS)withsimultaneous50/60Hzrejectionat6.9Hz
output rate. SDI may be driven logic HIGH or LOW
anytime during the conversion or sleep state in order to
change the speed/resolution. The conversion immedi-
ately following the data output cycle will be valid and
performed at the newly selected output rate/resolution.
SDI may also be programmed by a serial input data
stream under control of SCK during the data output cycle.
Oneoftenspeed/resolutionranges(from6.9Hz/200nVRMS
to 3.5kHz/21µVRMS) may be selected. The first conver-
sion following a new selection is valid and performed at
the newly selected speed/resolution.
FO (Pin 14): Frequency Control Pin. Digital input that con-
trols the internal conversion clock. When FO is connected
to VCC or GND, the converter uses its internal oscillator
runningat9MHz. Theconversionrateisdeterminedbythe
selected OSR such that tCONV (in ms) = (40 • OSR + 170)/
9000(tCONV =1.137msatOSR=256,tCONV=146msatOSR
= 32768). The first null is located at 8/tCONV, 7kHz at OSR
= 256 and 55Hz (simultaneous 50/60Hz) at OSR = 32768.
When FO is driven by an oscillator with frequency fEOSC (in
kHz), the conversion time becomes tCONV = (40 • OSR +
170)/fEOSC (in ms) and the first null remains 8/tCONV
.
BUSY (Pin 15): Conversion in Progress Indicator. For
compatibility with the LTC2410, this pin should not be tied
to ground. This pin is HIGH while the conversion is in
progress and goes LOW indicating the conversion is
completeanddataisready.Itremainslowduringthesleep
anddataoutputstates.Attheconclusionofthedataoutput
state,itgoesHIGHindicatinganewconversionhasbegun.
EXT (Pin 10): Internal/External SCK Selection Pin. This
pinisusedtoselectinternalorexternalSCKforoutputting
data. IfEXTistiedlow(pincompatiblewiththeLTC2410),
the device is in the external SCK mode and data is shifted
out the device under the control of a user applied serial
clock. If EXT is tied high, the internal serial clock mode is
sn2440, 2440fas
8
LTC2440
U
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FU CTIO AL BLOCK DIAGRA
INTERNAL
OSCILLATOR
V
CC
GND
AUTOCALIBRATION
AND CONTROL
F
O
(INT/EXT)
+
IN
IN
+
–
–
∫
∫
∫
SDO
∑
ADC
SCK
CS
SERIAL
INTERFACE
DECIMATING FIR
SDI
BUSY
EXT
2440 F01
DAC
–
+
+
–
REF
REF
Figure 1. Functional Block Diagram
V
TEST CIRCUITS
CC
1.69k
SDO
SDO
C
= 20pF
1.69k
C
LOAD
= 20pF
LOAD
Hi-Z TO V
Hi-Z TO V
OL
OL
OH
OH
V
V
TO V
V
TO V
OH
OL
OL
OH
TO Hi-Z
2440 TA04
V
TO Hi-Z
2440 TA03
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APPLICATIO S I FOR ATIO
CONVERTER OPERATION
CONVERT
SLEEP
Converter Operation Cycle
The LTC2440 is a high speed, delta-sigma analog-to-
digital converter with an easy to use 4-wire serial interface
(seeFigure1). Itsoperationismadeupofthreestates. The
converter operating cycle begins with the conversion,
followed by the low power sleep state and ends with the
data output (see Figure 2). The 4-wire interface consists
of serial data input (SDI), serial data output (SDO), serial
clock (SCK) and chip select (CS). The interface, timing,
FALSE
CS = LOW
AND
SCK
TRUE
DATA OUTPUT
2440 F02
Figure 2. LTC2440 State Transition Diagram
sn2440, 2440fas
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LTC2440
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APPLICATIO S I FOR ATIO
Power-Up Sequence
operation cycle and data out format is compatible with the
LTC2410.
The LTC2440 automatically enters an internal reset state
when the power supply voltage VCC drops below
approximately2.2V. Thisfeatureguaranteestheintegrity
of the conversion result and of the serial interface mode
selection.
Initially, the LTC2440 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
While in this sleep state, power consumption is reduced
below 10µA. The part remains in the sleep state as long as
CS is HIGH. The conversion result is held indefinitely in a
staticshiftregisterwhiletheconverterisinthesleepstate.
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 0.5ms. The POR
signal clears all internal registers. Following the POR
signal, the LTC2440 starts a normal conversion cycle and
followsthesuccessionofstatesdescribedabove. Thefirst
conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (4.5V to 5.5V) before
the end of the POR time interval.
Once CS is pulled LOW, the device begins outputting the
conversion result. There is no latency in the conversion
result. The data output corresponds to the conversion just
performed. This result is shifted out on the serial data out
pin (SDO) under the control of the serial clock (SCK). Data
is updated on the falling edge of SCK allowing the user to
reliably latch data on the rising edge of SCK (see Figure 3).
The data output state is concluded once 32-bits are read
outoftheADCorwhenCSisbroughtHIGH. Thedeviceau-
tomaticallyinitiatesanewconversionandthecyclerepeats.
Reference Voltage Range
This converter accepts a truly differential external refer-
ence voltage. The absolute/common mode voltage speci-
ficationfortheREF+ andREF– pinscoverstheentirerange
from GND to VCC. For correct converter operation, the
REF+ pin must always be more positive than the REF– pin.
Through timing control of the CS, SCK and EXT pins, the
LTC2440 offers several flexible modes of operation
(internal or external SCK). These various modes do not
require programming configuration registers; moreover,
they do not disturb the cyclic operation described above.
These modes of operation are described in detail in the
Serial Interface Timing Modes section.
The LTC2440 can accept a differential reference voltage
from 0.1V to VCC. The converter output noise is deter-
mined by the thermal noise of the front-end circuits, and
as such, its value in microvolts is nearly constant with
reference voltage. A decrease in reference voltage will not
significantly improve the converter’s effective resolution.
On the other hand, a reduced reference voltage will im-
prove the converter’s overall INL performance.
Ease of Use
The LTC2440 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle.Thereisaone-to-onecorrespondencebetweenthe
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy. Speed/resolution ad-
justmentsmaybemadeseamlesslybetweentwoconver-
sions without settling errors.
Input Voltage Range
The analog input is truly differential with an absolute/
common mode range for the IN+ and IN– input pins
extending from GND – 0.3V to VCC + 0.3V. Outside
these limits, the ESD protection devices begin to turn on
and the errors due to input leakage current increase
rapidly. Within these limits, the LTC2440 converts the
bipolar differential input signal, VIN = IN+ – IN–, from
The LTC2440 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation de-
scribed above. The advantage of continuous calibration is
extreme stability of offset and full-scale readings with re-
specttotime,supplyvoltagechangeandtemperaturedrift.
–FS = –0.5 • VREF to +FS = 0.5 • VREF where VREF
=
sn2440, 2440fas
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LTC2440
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APPLICATIO S I FOR ATIO
REF+ – REF–. Outside this range, the converter indicates
the overrange or the underrange condition using distinct
output codes.
indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0,
this bit is LOW.
Bit 28 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 29 also
provides the underrange or overrange indication. If both
Bit 29 and Bit 28 are HIGH, the differential input voltage is
above +FS. If both Bit 29 and Bit 28 are LOW, the
differential input voltage is below –FS.
Output Data Format
TheLTC2440serialoutputdatastreamis32-bitslong.The
first3-bitsrepresentstatusinformationindicatingthesign
and conversion state. The next 24-bits are the conversion
result, MSB first. The remaining 5-bits are sub LSBs
beyond the 24-bit level that may be included in averaging
or discarded without loss of resolution. In the case of
ultrahigh resolution modes, more than 24 effective bits of
performance are possible (see Table 3). Under these
conditions, sub LSBs are included in the conversion result
and represent useful information beyond the 24-bit level.
The third and fourth bit together are also used to indicate
an underrange condition (the differential input voltage is
below –FS) or an overrange condition (the differential
inputvoltageisabove+FS).Forinputconditionsinexcess
of twice full scale (|VIN| ≥ VREF), the converter may
indicate either overrange or underrange. Once the input
returns to the normal operating range, the conversion
resultisimmediatelyaccuratewithinthespecificationsof
the device.
The function of these bits is summarized in Table 1.
Table 1. LTC2440 Status Bits
Bit 31 Bit 30 Bit 29 Bit 28
Input Range
EOC
DMY
SIG MSB
V
≥ 0.5 • V
0
0
0
0
0
1
1
0
0
1
0
1
0
IN
REF
0V ≤ V < 0.5 • V
0
IN
REF
–0.5 • V ≤ V < 0V
0
REF
IN
V
< –0.5 • V
0
IN
REF
Bits ranging from 28 to 5 are the 24-bit conversion result
MSB first.
Bit 5 is the Least Significant Bit (LSB).
Bits ranging from 4 to 0 are sub LSBs below the 24-bit
level. Bits 4 to bit 0 may be included in averaging or
discarded without loss of resolution.
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
DataisshiftedoutoftheSDOpinundercontroloftheserial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance.
In order to shift the conversion result out of the device, CS
mustfirstbedrivenLOW. EOCisseenattheSDOpinofthe
deviceonceCSispulledLOW.EOCchangesrealtimefrom
HIGH to LOW at the completion of a conversion. This
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign
CS
BIT 31
EOC
BIT 30
“0”
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 5
BIT 0
SDO
LSB
24
Hi-Z
SCK
1
2
3
4
5
26
27
32
BUSY
2440 F03
SLEEP
DATA OUTPUT
CONVERSION
Figure 3. Output Data Timing
sn2440, 2440fas
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LTC2440
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APPLICATIO S I FOR ATIO
signal may be used as an interrupt for an external
microcontroller. Bit 31 (EOC) can be captured on the first
risingedgeofSCK. Bit30isshiftedoutofthedeviceonthe
first falling edge of SCK. The final data bit (Bit 0) is shifted
out on the falling edge of the 31st SCK and may be latched
on the rising edge of the 32nd SCK pulse. On the falling
edgeofthe32ndSCKpulse,SDOgoesHIGHindicatingthe
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
AslongasthevoltageontheIN+ andIN–pinsismaintained
within the –0.3V to (VCC + 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 • VREF to
+FS=0.5•VREF.Fordifferentialinputvoltagesgreaterthan
+FS, the conversion result is clamped to the value corre-
sponding to the +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 13) is used to
synchronizethedatatransfer.Eachbitofdataisshiftedout
the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
outputandtheLTC2440createsitsownserialclock. Inthe
External SCK mode of operation, the SCK pin is used as
input.TheinternalorexternalSCKmodeisselectedbytying
EXT (Pin 10) LOW for external SCK and HIGH for internal
SCK.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 12), provides the
result of the last conversion as a serial bit stream (MSB
first) during the data output state. In addition, the SDO pin
is used as an end of conversion indicator during the
conversion and sleep states.
When CS (Pin 11) is HIGH, the SDO driver is switched to
a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
duringtheconversionphase, theEOCbitappearsHIGHon
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS = LOW.
SERIAL INTERFACE PINS
The LTC2440 transmits the conversion results and re-
ceives the start of conversion command through a
synchronous 2-wire, 3-wire or 4-wire interface. During
the conversion and sleep states, this interface can be
used to assess the converter status and during the data
output state it is used to read the conversion result and
program the speed/resolution.
Table 2. LTC2440 Output Data Format
Differential Input Voltage
Bit 31
EOC
Bit 30
DMY
Bit 29
SIG
Bit 28
MSB
Bit 27
Bit 26
Bit 25
…
Bit 0
V
IN
*
V * ≥ 0.5 • V **
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
…
…
…
…
…
…
…
…
…
…
0
1
0
1
0
1
0
1
0
1
IN
REF
0.5 • V ** – 1LSB
REF
0.25 • V **
REF
0.25 • V ** – 1LSB
REF
0
–1LSB
–0.25 • V **
REF
–0.25 • V ** – 1LSB
REF
–0.5 • V **
REF
V * < –0.5 • V **
0
1
1
IN
REF
+
–
+
–
*The differential input voltage V = IN – IN . **The differential reference voltage V = REF – REF .
IN
REF
sn2440, 2440fas
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LTC2440
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APPLICATIO S I FOR ATIO
Serial Data Input (SDI)—Serial Input Speed Selection
Chip Select Input (CS)
SDImayalsobeprogrammedbyaserialinputdatastream
under control of SCK during the data output cycle, see
Figure 4. One of ten speed/resolution ranges (from 6.9Hz/
200nVRMS to 3.5kHz/21µVRMS) may be selected, see
Table 3. The conversion following a new selection is valid
and performed at the newly selected speed/resolution.
The active LOW chip select, CS (Pin 11), is used to test the
conversionstatusandtoenablethedataoutputtransferas
described in the previous sections.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2440 will abort any serial data
transfer in progress and start a new conversion cycle
anytime a LOW-to-HIGH transition is detected at the CS
pin after the converter has entered the data output state
(i.e., after the fifth falling edge of SCK occurs with
CS = LOW).
BUSY
The BUSY output (Pin 15) is used to monitor the state of
conversion, data output and sleep cycle. While the part is
converting, the BUSY pin is HIGH. Once the conversion is
complete, BUSY goes LOW indicating the conversion is
complete and data out is ready. The part now enters the
LOW power sleep state. BUSY remains LOW while data is
shifted out of the device. It goes HIGH at the conclusion of
the data output cycle indicating a new conversion has
begun.Thisrisingedgemaybeusedtoflagthecompletion
of the data read cycle.
Serial Data Input (SDI)—Logic Level Speed Selection
The serial data input (SDI, Pin 7) is used to select the
speed/resolution of the LTC2440. A simple 2-speed con-
trol is selectable by either driving SDI HIGH or LOW. If SDI
is grounded (pin compatible with LTC2410) the device
outputs data at 880Hz with 21 bits effective resolution. By
tying SDI HIGH, the converter enters the ultralow noise
mode(200nVRMS)withsimultaneous50/60Hzrejectionat
6.9Hz output rate. SDI may be driven logic HIGH or LOW
anytime during the conversion or sleep state in order to
changethespeed/resolution. Theconversionimmediately
following the data output cycle will be valid and performed
at the newly selected output rate/resolution.
SERIAL INTERFACE TIMING MODES
The LTC2440’s 2-wire, 3-wire or 4-wire interface is SPI
and MICROWIRE compatible. This interface offers several
flexible modes of operation. These include internal/exter-
nal serial clock, 2-wire or 3-wire I/O, single cycle conver-
sion and autostart. The following sections describe each
of these serial interface timing modes in detail. In all these
cases, the converter can use the internal oscillator (FO =
LOW)oranexternaloscillatorconnectedtotheFO pin. See
Table 4 for a summary.
Changing SDI logic state during the data output cycle
should be avoided as speed resolution other than 6.9Hz or
880Hz may be selected. For example, if SDI is changed
from logic 0 to logic 1 after the second rising edge of SCK,
the conversion rate will change from 880Hz to 55Hz (the
following values are listed in Table 3: OSR4 = 0, OSR3 = 0,
OSR2 = 1, OSR1 = 1 and OSR0 = 1). If SDI remains HIGH,
the conversion rate will switch to the desired 6.9Hz speed
immediately following the conversion at 55Hz. The 55Hz
rate conversion cycle will be a valid result as well as the
first 6.9Hz result. On the other hand, if SDI is changed to
a 1 anytime before the first rising edge of SCK, the
following conversion rate will become 6.9Hz. If SDI is
changed to a 1 after the 5th rising edge of SCK, the next
conversion will remain 880Hz while all subsequent con-
versions will be at 6.9Hz.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 5.
The serial clock mode is selected by the EXT pin. To select
the external serial clock mode, EXT must be tied low.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
sn2440, 2440fas
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LTC2440
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CS
SCK
SDI
OSR4*
OSR3
OSR2
OSR1
OSR0
BIT 31
EOC
BIT 30
“0”
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 25
BIT 1
BIT 0
LSB
Hi-Z
Hi-Z
SDO
BUSY
2440 F04
*OSR4 BIT MUST BE AT FIRST SCK RISING EDGE DURING SERIAL DATA OUT CYCLE
Figure 4. SDI Speed/Resolution Programming
Table 3. SDI Speed/Resolution Programming
CONVERSION RATE
INTERNAL
EXTERNAL
RMS
OSR4 OSR3 OSR2 OSR1 OSR0 9MHz CLOCK 10.24MHz CLOCK NOISE ENOB OSR
X
X
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
3.52kHz
1.76kHz
880Hz
880Hz
440Hz
220Hz
110Hz
55Hz
4kHz
2kHz
23µV
17
64
3.5µV 20
2µV 21.3
2µV 21.3
1.4µV 21.8
1µV 22.4
750nV 22.9
510nV 23.4
375nV 24
128
1kHz
256*
256
X
X
X
X
X
X
X
X
1kHz
500Hz
250Hz
125Hz
62.5Hz
31.25Hz
15.625Hz
7.8125Hz
512
1024
2048
4096
8192
27.5Hz
13.75Hz
6.875Hz
250nV 24.4 16384
200nV 24.6 32768**
**Address allows tying SDI HIGH *Additional address to allow tying SDI LOW
Table 4. LTC2440 Interface Timing Modes
Conversion
Cycle
Control
Data
Output
Control
Connection
and
Waveforms
SCK
Source
Configuration
External SCK, Single Cycle Conversion
External SCK, 2-Wire I/O
External
External
Internal
Internal
CS and SCK
SCK
CS and SCK
SCK
Figures 5, 6
Figure 7
Internal SCK, Single Cycle Conversion
Internal SCK, 2-Wire I/O, Continuous Conversion
CS ↓
CS ↓
Figures 8, 9
Figure 10
Continuous
Internal
sn2440, 2440fas
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4.5V TO 5.5V
1µF
2
15
V
BUSY
CC
LTC2440
REF
3
4
5
6
14
13
12
11
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
+
F
O
REFERENCE VOLTAGE
0.1V TO V
–
CC
SCK
SDO
CS
REF
+
3-WIRE
SPI INTERFACE
IN
ANALOG INPUT RANGE
–0.5V
TO 0.5V
–
REF
REF
V
IN
CC
200nV NOISE, 50/60Hz REJECTION
7
10-SPEED/RESOLUTION PROGRAMMABLE
SDI
EXT
2µV NOISE, 880Hz OUTPUT RATE
1, 8, 9, 16
10
GND
CS
TEST EOC
TEST EOC
TEST EOC
BIT 31
EOC
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 5
LSB
BIT 0
SDO
SUB LSB
Hi-Z
Hi-Z
Hi-Z
SCK
(EXTERNAL)
BUSY
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
2440 F05
Figure 5. External Serial Clock, Single Cycle Operation
EOC = 1 (BUSY = 1) while a conversion is in progress and
EOC = 0 (BUSY = 0) if the device is in the sleep state.
IndependentofCS,thedeviceautomaticallyentersthelow
power sleep state once the conversion is complete.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CSHIGHanytimebetweenthefifthfallingedge(SDImust
be properly loaded each cycle) and the 32nd falling edge
of SCK, see Figure 6. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 32-bits of output data, aborting an invalid conversion
cycle or synchronizing the start of a conversion.
When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift regis-
ter. The device remains in the sleep state until the first
rising edge of SCK is seen. Data isshifted out the SDO pin
oneachfallingedgeofSCK.Thisenablesexternalcircuitry
to latch the output on the rising edge of SCK. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result can be latched on the 32nd rising
edge of SCK. On the 32nd falling edge of SCK, the device
begins a new conversion. SDO goes HIGH (EOC = 1) and
BUSY goes HIGH indicating a conversion is in progress.
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 7. CS
may be permanently tied to ground, simplifying the user
interface or isolation barrier. The external serial clock
mode is selected by tying EXT LOW.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z
and BUSY monitored for the completion of a conversion.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status on the SDO pin.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. Conversely, BUSY (Pin 15) may be used
tomonitorthestatusoftheconversioncycle.EOCorBUSY
may be used as an interrupt to an external controller
sn2440, 2440fas
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4.5V TO 5.5V
1µF
2
15
V
BUSY
CC
LTC2440
REF
3
14
13
12
11
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
+
F
O
REFERENCE VOLTAGE
0.1V TO V
4
5
6
–
CC
SCK
SDO
CS
REF
+
3-WIRE
SPI INTERFACE
IN
ANALOG INPUT RANGE
–0.5V
TO 0.5V
–
REF
REF
V
IN
CC
200nV NOISE, 50/60Hz REJECTION
7
10-SPEED/RESOLUTION PROGRAMMABLE
SDI
EXT
2µV NOISE, 880Hz OUTPUT RATE
1, 8, 9, 16
10
GND
CS
TEST EOC
TEST EOC
TEST EOC
BIT 0
EOC
BIT 31
EOC
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 9
BIT 8
SDO
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
5
SCK
(EXTERNAL)
BUSY
SLEEP
CONVERSION
DATA OUTPUT
SLEEP
DATA OUTPUT
CONVERSION
2410 F06
Figure 6. External Serial Clock, Reduced Data Output Length
4.5V TO 5.5V
1µF
2
15
V
BUSY
CC
LTC2440
REF
3
4
5
6
14
13
12
11
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
+
F
O
REFERENCE VOLTAGE
0.1V TO V
–
CC
SCK
SDO
CS
REF
+
3-WIRE
SPI INTERFACE
IN
ANALOG INPUT RANGE
–0.5V
TO 0.5V
–
REF
REF
V
IN
CC
200nV NOISE, 50/60Hz REJECTION
7
10-SPEED/RESOLUTION PROGRAMMABLE
SDI
EXT
2µV NOISE, 880Hz OUTPUT RATE
1, 8, 9, 16
10
GND
CS
BIT 31
EOC
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 5
LSB
BIT 0
SDO
24
SCK
(EXTERNAL)
BUSY
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
2440 F07
Figure 7. External Serial Clock, CS = 0 Operation (2-Wire)
sn2440, 2440fas
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Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state. Alternatively,
BUSY (Pin 15) may be used to monitor the status of the
conversion in progress. BUSY is HIGH during the conver-
sionandgoesLOWattheconclusion.ItremainsLOWuntil
the result is read from the device.
indicating the conversion result is ready. EOC = 1
(BUSY = 1) while the conversion is in progress and
EOC = 0 (BUSY = 0) once the conversion enters the low
power sleep state. On the falling edge of EOC/BUSY, the
conversion result is loaded into an internal static shift
register. The device remains in the sleep state until the
first rising edge of SCK. Data is shifted out the SDO pin
on each falling edge of SCK enabling external circuitry to
latch data on the rising edge of SCK. EOC can be latched
on the first rising edge of SCK. On the 32nd falling edge
of SCK, SDO and BUSY go HIGH (EOC = 1) indicating a
new conversion has begun.
WhentestingEOC,iftheconversioniscomplete(EOC=0),
thedevicewillexitthesleepstateandenterthedataoutput
state if CS remains LOW. In order to prevent the device
from exiting the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time tEOCtest after the falling edge of CS
(if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW
during the falling edge of EOC). The value of tEOCtest is
500ns. If CS is pulled HIGH before time tEOCtest, the device
remains in the sleep state. The conversion result is held in
the internal static shift register.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
In order to select the internal serial clock timing mode, the
EXT pin must be tied HIGH.
If CS remains LOW longer than tEOCtest, the first rising
edge of SCK will occur and the conversion result is serially
shiftedoutoftheSDOpin. Thedataoutputcyclebeginson
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
4.5V TO 5.5V
1µF
2
15
V
CC
BUSY
LTC2440
+
3
14
13
12
11
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
REF
REF
F
O
REFERENCE VOLTAGE
4
–
0.1V TO V
CC
SCK
SDO
CS
5
6
3-WIRE
SPI INTERFACE
+
IN
ANALOG INPUT RANGE
–0.5V
TO 0.5V
–
REF
REF
V
IN
CC
200nV NOISE, 50/60Hz REJECTION
7
10-SPEED/RESOLUTION PROGRAMMABLE
SDI
EXT
2µV NOISE, 880Hz OUTPUT RATE
1, 8, 9, 16
10
GND
V
CC
<t
EOCtest
CS
TEST EOC
TEST EOC
BIT 31
EOC
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 5
LSB
BIT 0
SDO
24
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCK
(INTERNAL)
BUSY
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
2440 F08
Figure 8. Internal Serial Clock, Single Cycle Operation
sn2440, 2440fas
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this first rising edge of SCK and concludes after the 32nd
rising edge. Data is shifted out the SDO pin on each falling
edgeofSCK.Theinternallygeneratedserialclockisoutput
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latchedonthefirstrisingedgeofSCKandthelastbitofthe
conversionresultonthe32ndrisingedgeofSCK. Afterthe
32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH and a new conversion starts.
This is useful for systems not requiring all 32-bits of
output data, aborting an invalid conversion cycle, or
synchronizing the start of a conversion.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground, simpli-
fying the user interface or isolation barrier. The internal
serial clock mode is selected by tying EXT HIGH.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 9. In order to properly select the OSR
for the conversion following a data abort, five SCK rising
edges must be seen prior to performing a data out abort
(pullingCSHIGH). IfCSispulledhighpriortothefifthSCK
falling edge, the OSR selected depends on the number of
SCK signals seen prior to data abort, where subsequent
nonaborted conversion cycles return to the programmed
OSR. On the rising edge of CS, the device aborts the data
output state and immediately initiates a new conversion.
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1) and BUSY = 1. Once the
conversion is complete, SCK, BUSY and SDO go LOW
(EOC = 0) indicating the conversion has finished and the
device has entered the low power sleep state. The part
remains in the sleep state a minimum amount of time
(≈500ns) then immediately begins outputting data. The
dataoutputcyclebeginsonthefirstrisingedgeofSCKand
4.5V TO 5.5V
1µF
15
2
V
CC
BUSY
LTC2440
REF
3
14
13
12
11
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
+
F
O
REFERENCE VOLTAGE
4
–
0.1V TO V
CC
SCK
SDO
CS
REF
+
5
6
3-WIRE
SPI INTERFACE
IN
ANALOG INPUT RANGE
–0.5V TO 0.5V
–
REF REF
V
IN
CC
200nV NOISE, 50/60Hz REJECTION
7
10-SPEED/RESOLUTION PROGRAMMABLE
SDI
EXT
2µV NOISE, 880Hz OUTPUT RATE
1, 8, 9, 16
10
GND
V
CC
>t
EOCtest
<t
EOCtest
CS
TEST EOC
TEST EOC
TEST EOC
BIT 0
BIT 31
EOC
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 8
SDO
EOC
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
5
SCK
(INTERNAL)
BUSY
SLEEP
CONVERSION
DATA OUTPUT
SLEEP
DATA OUTPUT
CONVERSION
2440 F09
Figure 9. Internal Serial Clock, Reduced Data Output Length
sn2440, 2440fas
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4.5V TO 5.5V
1µF
15
2
BUSY
V
CC
LTC2440
REF
3
4
5
6
14
13
12
11
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
+
F
O
REFERENCE VOLTAGE
–
0.1V TO V
CC
SCK
SDO
CS
REF
+
2-WIRE
SPI INTERFACE
IN
ANALOG INPUT RANGE
–0.5V TO 0.5V
–
REF
REF
V
IN
CC
200nV NOISE, 50/60Hz REJECTION
7
10-SPEED/RESOLUTION PROGRAMMABLE
SDI
EXT
2µV NOISE, 880Hz OUTPUT RATE
1, 8, 9, 16
10
GND
V
CC
CS
BIT 31
EOC
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 5
LSB
BIT 0
SDO
24
SCK
(INTERNAL)
BUSY
CONVERSION
DATA OUTPUT
CONVERSION
2410 F10
SLEEP
Figure 10. Internal Serial Clock, Continuous Operation
fN = fS/OSR, see Figure 11 and Table 5. The rejection at the
endsafterthe32ndrisingedge.DataisshiftedouttheSDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
EOC can be latched on the first rising edge of SCK and the
last bit of the conversion result can be latched on the 32nd
rising edge of SCK. After the 32nd rising edge, SDO goes
HIGH(EOC=1)indicatinganewconversionisinprogress.
SCK remains HIGH during the conversion.
frequency fN ±14% is better than 80dB, see Figure 12.
If FO is grounded, fS is set by the on-chip oscillator at
1.8MHz±5%(oversupplyandtemperaturevariations). At
an OSR of 32,768, the first NULL is at fN = 55Hz and the no
latency output rate is fN/8 = 6.9Hz. At the maximum OSR,
0
–20
–40
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over con-
ventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2440 significantly
simplifies antialiasing filter requirements.
–60
–80
–100
–120
–140
TheLTC2440’sspeed/resolutionisdeterminedbytheover
sample ratio (OSR) of the on-chip digital filter. The OSR
ranges from 64 for 3.5kHz output rate to 32,768 for 6.9Hz
output rate. The value of OSR and the sample rate fS
determine the filter characteristics of the device. The first
NULL of the digital filter is at fN and multiples of fN where
60
120
240
0
180
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2440 F11
Figure 11. LTC2440 Normal Mode Rejection (Internal Oscillator)
sn2440, 2440fas
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Table 5. OSR vs Notch Frequency (fN) with Internal Oscillator
the noise performance of the device is 200nVRMS with
better than 80dB rejection of 50Hz ±2% and 60Hz ±2%.
Since the OSR is large (32,768) the wide band rejection is
extremely large and the antialiasing requirements are
simple. The first multiple of fS occurs at 55Hz • 32,768 =
1.8MHz, see Figure 13.
Running at 9MHz
OSR
NOTCH (f )
N
64
28.16kHz
14.08kHz
7.04kHz
3.52kHz
1.76kHz
880Hz
128
256
512
The first NULL becomes fN = 7.04kHz with an OSR of 256
(an output rate of 880Hz) and FO grounded. While the
NULL has shifted, the sample rate remains constant. As a
result of constant modulator sampling rate, the linearity,
offset and full-scale performance remains unchanged as
does the first multiple of fS.
1024
2048
4096
440Hz
8192
16384
220Hz
110Hz
32768*
55Hz
*Simultaneous 50/60 rejection
–80
–90
0
–20
–40
–100
–110
–120
–130
–140
–60
1.8MHz
–80
–100
REJECTION > 120dB
–120
–140
57 59
47 49 51 53 55
61 63
1000000
2000000
0
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2440 F12
1440 F13
Figure 12. LTC2440 Normal Mode Rejection (Internal Oscillator)
Figure 13. LTC2440 Normal Mode Rejection (Internal Oscillator)
sn2440, 2440fas
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The sample rate fS and NULL fN, my also be adjusted by
driving the FO pin with an external oscillator. The sample
rate is fS = fEOSC/5, where fEOSC is the frequency of the
clock applied to FO. Combining a large OSR with a reduced
sample rate leads to notch frequencies fN near DC while
maintaining simple antialiasing requirements. A 100kHz
clock applied to FO results in a NULL at 0.6Hz plus all
harmonics up to 20kHz, see Figure 14. This is useful in
applications requiring digitalization of the DC component
of a noisy input signal and eliminates the need of placing
a 0.6Hz filter in front of the ADC.
Reduced Power Operation
In addition to adjusting the speed/resolution of the
LTC2440, the speed/resolution/power dissipation may
also be adjusted using the automatic sleep mode. During
the conversion cycle, the LTC2440 draws 8mA supply
current independent of the programmed speed. Once the
conversion cycle is completed, the device automatically
enters a low power sleep state drawing 8µA. The device
remains in this state as long as CS is HIGH and data is not
shifted out. By adjusting the duration of the sleep state
(hold CS HIGH longer) and the duration of the conversion
cycle (programming OSR) the DC power dissipation can
be reduced, see Figure 16.
An external oscillator operating from 100kHz to 20MHz
can be implemented using the LTC1799 (resistor set
SOT-23 oscillator), see Figure 22. By floating pin 4 (DIV)
of the LTC1799, the output oscillator frequency is:
For example, if the OSR is programmed at the fastest rate
(OSR = 64, tCONV = 0.285ms) and the sleep state is 10ms,
the effective output rate is approximately 100Hz while the
average supply current is reduced to 240µA. By further
extending the sleep state to 100ms, the effective output
rate of 10Hz draws on average 30µA. Noise, power, and
speed can be optimized by adjusting the OSR (Noise/
Speed) and sleep mode duration (Power).
⎛
⎜
10k
⎝10•RSET
⎞
fOSC = 10MHz •
⎟
⎠
The normal mode rejection characteristic shown in Fig-
ure 14 is achieved by applying the output of the LTC1799
(with RSET = 100k) to the FO pin on the LTC2440 with SDI
tied HIGH (OSR = 32768).
0
–20
–40
–60
–80
–100
–120
–140
2
4
6
10
0
8
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2440 F14
Figure 14. LTC2440 Normal Mode Rejection
(External Oscillator at 90kHz)
sn2440, 2440fas
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CONVERTER
SLEEP
CONVERT
SLEEP
CONVERT
SLEEP
STATE
DATA
OUT
DATA
OUT
CS
SUPPLY
CURRENT
8µA
8mA
8µA
8mA
8µA
2440 F15
Figure 15. Reduced Power Timing Mode
LTC2440 Input Structure
When using the internal oscillator, fSW is 1.8MHz and the
equivalent resistance is approximately 110kΩ.
Modern delta sigma converters have switched capacitor
front ends that repeatedly sample the input voltage over
sometimeperiod.Thesamplingprocessproducesasmall
current pulse at the input and reference terminals as the
capacitors are charged. The LTC2440 switches the input
and reference to a 5pF sample capacitor at a frequency
of 1.8MHz. A simplified equivalent circuit is shown in
Figure 16.
Driving the Input and Reference
Because of the small current pulses, excessive lead length
at the analog or reference input may allow reflections or
ringing to occur, affecting the conversion accuracy. The
keytopreservingtheaccuracyoftheLTC2440iscomplete
settling of these sampling glitches at both the input and
reference terminals. There are several recommended
methods of doing this.
The average input and reference currents can be ex-
pressed in terms of the equivalent input resistance of the
sample capacitor, where:
Req = 1/(fSW • Ceq)
V
CC
I
+
+
REF
R
R
(TYP)
SW
I
I
LEAK
500Ω
V
REF
LEAK
V
CC
I
+
IN
(TYP)
500Ω
SW
I
I
LEAK
V
+
IN
C
EQ
LEAK
5pF
(TYP)
V
CC
(C = 3.5pF SAMPLE CAP + PARASITICS)
EQ
I
–
–
IN
IN
R
R
(TYP)
SW
I
I
LEAK
LEAK
500Ω
V
V
CC
I
–
–
REF
(TYP)
500Ω
SW
I
I
LEAK
LEAK
2440 F16
V
REF
SWITCHING FREQUENCY
f
f
= 1.8MHz INTERNAL OSCILLATOR
EOSC
SW
SW
= f
/5 EXTERNAL OSCILLATOR
Figure 16. LTC2440 Input Structure
sn2440, 2440fas
22
LTC2440
U
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APPLICATIO S I FOR ATIO
Direct Connection to Low Impedance Sources
Buffering the LTC2440
If the ADC can be located physically close to the sensor, it
canbedirectlyconnectedtosensorsorothersourceswith
impedances up to 350Ω with no other components re-
quired (see Figure 17).
Manyapplicationswillrequirebuffering,particularlywhere
high impedance sources are involved or where the device
being measured is located some distance from the
LTC2440. WhenbufferingtheLTC2440afewsimplesteps
should be followed.
4.5V to 5.5V
Figure19showsanetworksuitableforcouplingtheinputs
of a LTC2440 to a LTC2051 chopper-stabilized op amp.
The 3µV offset and low noise of the LTC2051 make it a
good choice for buffering the LTC2440. Many other op
ampswillwork, withvaryingperformancecharacteristics.
1µF
+
+
–
REF
IN
IN
LTC2440
–
REF
The LTC2051 is configured to be able to drive the 1µF
capacitors at the inputs of the LTC2440. The 1µF capaci-
tors should be located close to the ADC input pins.
2440 F17
Figure 17. Direct Connection to Low Impedance (<350Ω) Source
The measured total unadjusted error of Figure 19 is well
within the specifications of the LTC2440 by itself. Most
autozero amplifiers will degrade the overall resolution to
some degree because of the extremely low input noise of
the LTC2440, however the LTC2051 is a good general
purpose buffer. The measured input referred noise of two
LTC2051s buffering both LTC2440 inputs is approxi-
matelydoublethatoftheLTC2440byitself, whichreduces
the effective resolution by 1-bit for all oversample ratios.
Adding gain to the LTC2051 will increase gain and offset
errors and will not appreciably increase the overall resolu-
tion, so it has limited benefit.
is Possible if the Sensor is Located Close to the ADC.
Longer Connections to Low Impedance Sources
If longer lead lengths are unavoidable, adding an input
capacitor close to the ADC input pins will average the
charging pulses and prevent reflections or ringing (see
Figure 18). Averaging the current pulses results in a DC
input current that should be taken into account. The
resulting 110kΩ input impedance willresultinagainerror
of 0.44% for a 350Ω bridge (within the full scale specs of
many bridges) and a very low 12.6ppm error for a 2Ω
thermocouple connection.
Procedure For Coupling Any Amplifier to the LTC2440
4.5V to 5.5V
The LTC2051 is suitable for a wide range of DC and low
frequency measurement applications. If another amplifier
is to be selected, a general procedure for evaluating the
suitability of an amplifier for use with the LTC2440 is
suggested here:
1µF
1µF
+
+
–
V
V
REF
CC
IN
IN
LTC2440
GND
1. Perform a thorough error and noise analysis on the
amplifier and gain setting components to verify that the
amplifier will perform as intended.
REMOTE
THERMOCOUPLE
1µF
2440 F18
Figure 18. Input Capacitors Allow Longer Connection Between
the Low Impedance Source and the ADC.
2. Measure the large signal response of the overall circuit.
The capacitive load may affect the maximum slew rate of
the amplifier. Verify that the slew rate is adequate for the
sn2440, 2440fas
23
LTC2440
U
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APPLICATIO S I FOR ATIO
fastest expected input signal. Figure 20 shows the large
signal response of the circuit in Figure 19.
For more information on testing high linearity ADCs, refer
to Linear Technology Design Solutions 11.
3. Measure noise performance of the complete circuit. A
good technique is to build one amplifier for each input,
even if only one will be used in the end application. Bias
both amplifier outputs to midscale, with the inputs tied
together. Verify that the noise is as expected, taking into
account the bandwidth of the LTC2440 inputs for the OSR
being used, the amplifier’s broadband voltage noise and
1/f corner (if any) and any additional noise due to the
amplifier’s current noise and source resistance.
Input Bandwidth and Frequency Rejection
The combined effect of the internal SINC4 digital filter and
the digital and analog autocalibration circuits determines
the LTC2440 input bandwidth and rejection characteris-
tics. Thedigitalfilter’sresponsecanbeadjustedbysetting
theoversampleratio(OSR)throughtheSPIinterfaceorby
supplying an external conversion clock to the FO pin.
Table 6 lists the properties of the LTC2440 with various
8-12V
5V
LT1236-5
4.7µF
0.01µF
10µF
15
V
CC
BUSY
14
+
5k
F
O
REF
LTC2440
–
R1
13
12
11
4
C1
0.1µF
SCK
SDO
CS
REF
0.01µF
–
+
10Ω
5
6
+
IN
C2
R2
7
–
IN+
IN
1µF
SDI
EXT
1
/
LTC2051HV
C4
2
1, 8, 9, 16
10
5k
R4
2440 F19
0.01µF
–
+
10Ω
C5
R5
IN–
1µF
1
/
LTC2051HV
2
C2, C5 TAIYO YUDEN JMK107BJ105MA
Figure 19. Buffering the LTC2440 from High Impedance Sources Using A Chopper Amplifier
100µs/DIV
5ns/DIV
2440 F20
2440 F21
Figure 20. Large Signal Input Settling Time Indicates Completed
Settling with Selected Load Capacitance.
Figure 21. Dynamic Input Current is Attenuated by Load
Capacitance and Completly Settled Before the Next Conversion
Sample Resulting in No Reduction in Performance.
sn2440, 2440fas
24
LTC2440
U
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APPLICATIO S I FOR ATIO
combinations of oversample ratio and clock frequency.
Understanding these properties is the key to fine tuning
the characteristics of the LTC2440 to the application.
multiples (up to the modulator sample rate of 1.8MHz)
exceeds 120dB. This is 8 times the maximum conversion
rate.
Maximum Conversion Rate
Effective Noise Bandwidth
The maximum conversion rate is the fastest possible rate
at which conversions can be performed.
The LTC2440 has extremely good input noise rejection
from the first notch frequency all the way out to the
modulator sample rate (typically 1.8MHz). Effective noise
bandwidthisameasureofhowtheADCwillrejectwideband
input noise up to the modulator sample rate. The example
onthefollowingpageshowshowthenoiserejectionofthe
LTC2440 reduces the effective noise of an amplifier driv-
ing its input.
First Notch Frequency
This is the first notch in the SINC4 portion of the digital
filter and depends on the fo clock frequency and the
oversample ratio. Rejection at this frequency and its
Table 6
Oversample Ratio ADC
ENOB
REF
Maximum Conversion Rate
First Notch Frequency
Effective Noise BW
–3dB point(Hz)
(OSR)
Noise* (V = 5V)*
Internal
External
Internal
External
Internal
External
Internal
External
9MHz clock
f
9MHz clock
f
9MHz clock
f
9MHz clock
1696
848
f
o
o
o
o
64
128
23µV
3.5µV
2µV
17
3515.6
1757.8
878.9
439.5
219.7
109.9
54.9
F /2560
28125
14062.5
7031.3
3515.6
1757.8
878.9
F /320
3148
1574
787
F /2850
F /5310
o
o
o
o
20
F /5120
F /640
F /5700
F /10600
o
o
o
o
256
21.3
21.8
22.4
22.9
23.4
24
F /10240
F /1280
F /11400
424
F /21200
o
o
o
o
512
1.4µV
1µV
F /20480
F /2560
394
F /22800
212
F /42500
o
o
o
o
1024
2048
4096
8192
16384
32768
F /40960
F /5120
197
F /45700
106
F /84900
o
o
o
o
750nV
510nV
375nV
250nV
200nV
F /81920
F /1020
98.4
49.2
24.6
12.4
6.2
F /91400
53
F /170000
o
o
o
o
F /163840
439.5
F /2050
F /183000
26.5
13.2
6.6
F /340000
o
o
o
o
27.5
F /327680
219.7
F /4100
F /366000
F /679000
o
o
o
o
24.4
24.6
13.7
F /655360
109.9
F /8190
F /731000
F /1358000
o
o
o
o
6.9
F /1310720
54.9
F /16380
F /1463000
3.3
F /2717000
o
o
o
o
*ADC noise increases by approximately √2 when OSR is decreased by a factor of 2 for OSR 32768 to OSR 256. The ADC noise at OSR 128 and OSR 64
include effects from internal modulator quantization noise.
sn2440, 2440fas
25
LTC2440
U
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APPLICATIO S I FOR ATIO
Example:
ThetotalnoiseistheRMSsumofthisnoisewiththe200nV
noise of the ADC at OSR = 32768.
If an amplifier (e.g. LT1219) driving the input of an
LTC2440 has wideband noise of 33nV/√Hz, band-limited
to 1.8MHz, the total noise entering the ADC input is:
√82nV2 + 2µV2 = 216nV.
In this way, the digital filter with its variable oversampling
ratio can greatly reduce the effects of external noise
sources.
33nV/√Hz • √1.8MHz = 44.3µV.
When the ADC digitizes the input, its digital filter filters out
the wideband noise from the input signal. The noise
reduction depends on the oversample ratio which defines
the effective bandwidth of the digital filter.
Using Non-Autozeroed Amplifiers for Lowest Noise
Applications
Ultralow noise applications may require the use of low
noise bipolar amplifiers that are not autozeroed. Because
the LTC2440 has such exceptionally low offset, offset drift
and 1/f noise, the offset drift and 1/f noise in the amplifiers
may need to be compensated for to retain the system
performance of which the ADC is capable.
At an oversample of 256, the noise bandwidth of the ADC
is 787Hz which reduces the total amplifier noise to:
33nV/√Hz • √787Hz = 0.93µV.
The total noise is the RMS sum of this noise with the 2µV
noise of the ADC at OSR=256.
The circuit of Figure 23 uses low noise bipolar amplifiers
and correlated double sampling to achieve a resolution of
14nV, or 19 effective bits over a 10mV span. Each mea-
surement is the difference between two ADC readings
taken with opposite polarity bridge excitation. This can-
cels 1/f noise below 3.4Hz and eliminates errors due to
parasitic thermocouples. Allow 750µs settling time after
switching excitation polarity.
√0.93µV2 + 2uV2 = 2.2µV.
Increasing the oversampling ratio to 32768 reduces the
noise bandwidth of the ADC to 6.2Hz which reduces the
total amplifier noise to:
33nV/√Hz • √6.2Hz = 82nV.
sn2440, 2440fas
26
LTC2440
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ± .0015
.0250 TYP
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
× 45°
.053 – .068
(1.351 – 1.727)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
(0.203 – 0.305)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
GN16 (SSOP) 0502
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
U
TYPICAL APPLICATIO S
4.5V TO 5.5V
1µF
2
15
V
BUSY
CC
LTC1799
R
LTC2440
SET
50Ω
5
4
1
14
13
12
11
3
+
+
F
V
REF
OUT
O
REFERENCE VOLTAGE
0.1V TO V
4
5
6
–
CC
SCK
SDO
CS
REF
0.1µF
3-WIRE
SPI INTERFACE
+
2
3
IN
ANALOG INPUT RANGE
GND
SET
–0.5V
TO 0.5V
–
REF
REF
IN
7
V
CC
SDI
1, 8, 9, 16
10
NC
DIV
GND
EXT
2440 TA05
Figure 22. Simple External Clock Source
sn2440, 2440fas
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection ofits circuits as described herein willnotinfringe on existing patentrights.
27
LTC2440
U
TYPICAL APPLICATIO S
V
REF
100k
3
V
+7V
REF
4
TOP_P
TOP_N
5,6,7,8
LT1461-5
10µF
0.1µF
2
+
10Ω
1
100k
2X LT1677
+
–
4
REF
0.047µF
1k 0.1%
+
IN
IN
1µF
1µF
LTC2440
100Ω 0.1%
1k 0.1%
–
–
0.047µF
REF
–
+
V
REF
10Ω
100k
4
3
2440 F22
BOTTOM_P
2X SILICONIX SI9801
BOTTOM_N
5,6,7,8
2
1
100k
Figure 23. Bridge Reversal Eliminates 1/f Noise and Offset Drift of a Low Noise, Non-autozeroed, Bipolar Amplifier.
Circuit Gives 14nV Noise Level or 19 Effective Bits Over a 10mV Span
RELATED PARTS
PART NUMBER
LT1025
DESCRIPTION
COMMENTS
Micropower Thermocouple Cold Junction Compensator
80µA Supply Current, 0.5°C Initial Accuracy
Precise Charge, Balanced Switching, Low Power
LTC1043
Dual Precision Instrumentation Switched Capacitor
Building Block
LTC1050
Precision Chopper Stabilized Op Amp
Precision Bandgap Reference, 5V
No External Components 5µV Offset, 1.6µV Noise
P-P
LT1236A-5
LT1461
0.05% Max, 5ppm/°C Drift
Micropower Series Reference, 2.5V
Ultraprecise 16-Bit SoftSpanTM DAC
16-Bit Rail-to-Rail Micropower DAC
Resistor Set SOT-23 Oscillator
0.04% Max, 3ppm/°C Max Drift
Six Programmable Output Ranges
±1LSB DNL, 600µA, Internal Reference, SO-8
Single Resistor Frequency Set
LTC1592
LTC1655
LTC1799
LTC2053
Rail-to-Rail Instrumentation Amplifier
24-Bit, No Latency ∆Σ ADC in SO-8
1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP
4-/8-Channel, 24-Bit, No Latency ∆Σ ADC
24-Bit, No Latency ∆Σ ADC
10µV Offset with 50nV/°C Drift, 2.5µV Noise 0.01Hz to 10Hz
P-P
LTC2400
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2401/LTC2402
LTC2404/LTC2408
LTC2410/LTC2413
LTC2411
800nV
Noise, 5ppm INL/Simultaneous 50Hz/60Hz Rejection
Noise, 6ppm INL
RMS
24-Bit, No Latency ∆Σ ADC in MSOP
1-/4-/8-Channel, 20-Bit, No Latency ∆Σ ADCs
1.45µV
RMS
LTC2420LTC2424/
LTC2428
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400/
LTC2404/LTC2408
SoftSpan is a trademark of Linear Technology Corporation.
sn2440, 2440fas
LT/TP 0105 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2002
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