LTC2440CGN#TR [Linear]
LTC2440 - 24-Bit High Speed Differential Delta Sigma ADC with Selectable Speed/Resolution; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C;
| 型号： | LTC2440CGN#TR |
| 厂家： | 
Linear |
| 描述： | LTC2440 - 24-Bit High Speed Differential Delta Sigma ADC with Selectable Speed/Resolution; Package: SSOP; Pins: 16; Temperature Range: 0°C to 70°C 光电二极管 转换器 |
| 文件： | 总28页 (文件大小：351K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2440
24-Bit High Speed
Differential Δ∑ ADC with
Selectable Speed/Resolution
DESCRIPTION
FEATURES
The LTC®2440 is a high speed 24-bit No Latency Δ∑TM
ADC with 5ppm INL and 5μV offset. It uses proprietary
delta-sigmaarchitectureenablingvariablespeedandreso-
lution with no latency. Ten speed/resolution combinations
n
Up to 3.5kHz Output Rate
n
Selectable Speed/Resolution
n
2μV
Noise at 880Hz Output Rate
RMS
RMS
200nV
n
Noise at 6.9Hz Output Rate with
Simultaneous 50/60Hz Rejection
0.0005% INL, No Missing Codes
(6.9Hz/200nV
to 3.5kHz/25μV ) are programmed
RMS
RMS
n
n
n
n
through a simple serial interface. Alternatively, by tying a
singlepinHIGHorLOW,afast(880Hz/2μV )orultralow
Autosleep Enables 20μA Operation at 6.9Hz
RMS
<5μV Offset (4.5V < V < 5.5V, –40°C to 85°C)
noise (6.9Hz, 200nV
, 50/60Hz rejection) speed/reso-
CC
RMS
Differential Input and Differential Reference with
lution combination can be easily selected. The accuracy
(offset, full-scale, linearity, drift) and power dissipation
are independent of the speed selected. Since there is no
latency, a speed/resolution change may be made between
conversions with no degradation in performance.
GND to V Common Mode Range
CC
n
No Latency, Each Conversion is Accurate Even After
an Input Step
n
n
n
Internal Oscillator—No External Components
Pin Compatible with the LTC2410
24-Bit ADC in Narrow 16-Lead SSOP Package
Following each conversion cycle, the LTC2440 automati-
cally enters a low power sleep state. Power dissipation
may be reduced by increasing the duration of this sleep
state.Forexample,runningatthe3.5kHzconversionspeed
but reading data at a 100Hz rate draws 240μA average
current (1.1mW) while reading data at a 7Hz output rate
draws only 25μA (125μW).The LTC2440 communicates
through a flexible 3-wire or 4-wire digital interface that is
compatible with the LTC2410 and is available in a narrow
16-lead SSOP package.
APPLICATIONS
n
High Speed Multiplexing
n
Weight Scales
n
Auto Ranging 6-Digit DVMs
n
Direct Temperature Measurement
n
High Speed Data Acquisition
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
No Latency Δ∑ is a trademark of Linear Technology Corporation. All other trademarks are
the property of their respective owners.
TYPICAL APPLICATION
Speed vs RMS Noise
100
Simple 24-Bit 2-Speed Acquisition System
V
V
V
= 5V
CC
= 5V
IN
REF
+
–
4.5V TO 5.5V
= V = 0V
IN
10
1
V
BUSY
CC
LTC2440
2μV AT 880Hz
+
f
REF
O
REFERENCE VOLTAGE
0.1V TO V
4
–
CC
200nV AT 6.9Hz
(50/60Hz REJECTION)
REF
SCK
SDO
CS
V
CC
3-WIRE
SPI INTERFACE
+
IN
ANALOG INPUT
–0.5V TO 0.5V
6.9Hz, 200nV NOISE,
50/60Hz REJECTION
–
REF
REF
IN
10-SPEED SERIAL
PROGRAMMABLE
SDI
0.1
EXT
GND
880Hz OUTPUT RATE,
2μV NOISE
1
10
100
1000
10000
CONVERSION RATE (Hz)
2440 TA01
2440 TA01
2440 TA02
2440fd
1
LTC2440
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1,2)
TOP VIEW
Supply Voltage (V ) to GND....................... –0.3V to 6V
CC
Analog Input Pins Voltage
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
GND
to GND......................................–0.3V to (V + 0.3V)
BUSY
V
CC
CC
+
f
O
Reference Input Pins Voltage
REF
–
SCK
SDO
CS
REF
to GND......................................–0.3V to (V + 0.3V)
CC
+
IN
Digital Input Voltage to GND .........–0.3V to (V + 0.3V)
CC
–
IN
Digital Output Voltage to GND.......–0.3V to (V + 0.3V)
CC
EXT
GND
SDI
Operating Temperature Range
GND
LTC2440C ............................................... 0°C to 70°C
LTC2440I .............................................–40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................. 300°C
GN PACKAGE
16-LEAD PLASTIC SSOP
T
= 125°C, θ = 110°C/W
JA
JMAX
ORDER INFORMATION
LEAD FREE FINISH
LTC2440CGN#PBF
LTC2440IGN#PBF
TAPE AND REEL
PART MARKING
2440
PACKAGE DESCRIPTION
Narrow 16-Lead SSOP
Narrow 16-Lead SSOP
TEMPERATURE RANGE
LTC2440CGN#TRPBF
LTC2440IGN#TRPBF
0°C to 70°C
2440I
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
Resolution (No Missing Codes)
Integral Nonlinearity
0.1V ≤ V ≤ V , –0.5 • V ≤ V ≤ 0.5 • V , (Note 5)
24
Bits
REF
CC
REF
IN
REF
+
–
V
= 5V, REF = 5V, REF = GND, V
= 2.5V, (Note 6)
5
3
15
5
ppm of V
CC
INCM
REF
REF
+
–
REF = 2.5V, REF = GND, V
= 1.25V, (Note 6)
ppm of V
INCM
+
–
+
–
l
Offset Error
2.5V ≤ REF ≤ V , REF = GND, GND ≤ IN = IN ≤ V (Note 12)
2.5
20
μV
CC
CC
+
–
+
–
Offset Error Drift
Positive Full-Scale Error
2.5V ≤ REF ≤ V , REF = GND, GND ≤ IN = IN ≤ V
nV/°C
CC
CC
+
+
–
+
–
l
l
REF = 5V, REF = GND, IN = 3.75V, IN = 1.25V
10
10
30
50
ppm of V
ppm of V
REF
REF
–
+
–
REF = 2.5V, REF = GND, IN = 1.875V, IN = 0.625V
+
–
+
+
–
+
Positive Full-Scale Error Drift
Negative Full-Scale Error
2.5V ≤ REF ≤ V , REF = GND, IN = 0.75REF , IN = 0.25 • REF
0.2
ppm of V /°C
REF
CC
+
–
+
–
l
l
REF = 5V, REF = GND, IN = 1.25V, IN = 3.75V
REF = 2.5V, REF = GND, IN = 0.625V, IN = 1.875V
10
10
30
50
ppm of V
ppm of V
REF
REF
+
–
+
–
+
–
+
+
–
+
Negative Full-Scale Error Drift
Total Unadjusted Error
2.5V ≤ REF ≤ V , REF = GND, IN = 0.25 • REF , IN = 0.75 • REF
0.2
ppm of V /°C
REF
CC
+
+
–
5V ≤ V ≤ 5.5V, REF = 2.5V, REF = GND, V
= 1.25V
= 2.5V
INCM
15
15
15
ppm of V
ppm of V
ppm of V
CC
CC
INCM
REF
REF
REF
–
5V ≤ V ≤ 5.5V, REF = 5V, REF = GND, V
+
–
REF = 2.5V, REF = GND, V
= 1.25V, (Note 6)
INCM
+
–
–
+
Input Common Mode Rejection DC 2.5V ≤ REF ≤ V , REF = GND, GND ≤ IN = IN ≤ V
120
dB
CC
CC
2440fd
2
LTC2440
ANALOG INPUT AND REFERENCE The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
+
l
l
l
l
l
l
IN
Absolute/Common Mode IN Voltage
GND – 0.3V
GND – 0.3V
V
V
+ 0.3V
V
V
V
V
V
V
CC
CC
–
–
IN
Absolute/Common Mode IN Voltage
+ 0.3V
/2
+
–
V
Input Differential Voltage Range (IN – IN )
–V /2
REF
V
IN
REF
+
–
+
REF
REF
Absolute/Common Mode REF Voltage
0.1
GND
0.1
V
CC
–
Absolute/Common Mode REF Voltage
V
– 0.1V
CC
+
V
Reference Differential Voltage Range (REF
V
CC
REF
–
– REF )
+
+
C
C
C
C
IN Sampling Capacitance
3.5
3.5
3.5
3.5
10
pF
pF
pF
pF
nA
S(IN )
–
–
IN Sampling Capacitance
S(IN )
+
+
REF Sampling Capacitance
S(REF )
–
–
REF Sampling Capacitance
S(REF )
+
–
+
–
l
I
Leakage Current, Inputs and Reference
CS = V , IN = GND, IN = GND,
–100
100
DC_LEAK(IN , IN ,
REF , REF )
CC
+
–
+
–
REF = 5V, REF = GND
+
–
I
Average Input/Reference Current During
Sampling
Varies, See Applications Section
SAMPLE(IN , IN ,
+
–
REF , REF )
DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
4.5V ≤ V ≤ 5.5V
MIN
TYP
MAX
UNITS
l
l
l
l
l
l
V
IN
V
IL
V
IN
V
IL
High Level Input Voltage
2.5
V
CC
CS, f , SDI
O
Low Level Input Voltage
4.5V ≤ V ≤ 5.5V
0.8
V
V
CC
CS, f , SDI
O
High Level Input Voltage
SCK
4.5V ≤ V ≤ 5.5V (Note 8)
2.5
CC
Low Level Input Voltage
SCK
4.5V ≤ V ≤ 5.5V (Note 8)
0.8
10
10
V
CC
I
I
Digital Input Current
0V ≤ V ≤ V
CC
–10
–10
μA
μA
pF
pF
V
IN
IN
CS, f
O
Digital Input Current
SCK
0V ≤ V ≤ V (Note 8)
IN
IN
CC
C
C
V
V
V
V
Digital Input Capacitance
10
10
IN
CS, f
O
Digital Input Capacitance
SCK
(Note 8)
IN
l
l
l
l
l
High Level Output Voltage
SDO, BUSY
I = –800μA
O
V
V
– 0.5V
– 0.5V
OH
OL
OH
OL
CC
CC
Low Level Output Voltage
SDO, BUSY
I = 1.6mA
O
0.4V
V
High Level Output Voltage
SCK
I = –800μA (Note 9)
O
V
Low Level Output Voltage
SCK
I = 1.6mA (Note 9)
O
0.4V
10
V
I
Hi-Z Output Leakage
SDO
–10
μA
OZ
2440fd
3
LTC2440
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
V
I
Supply Voltage
4.5
5.5
V
CC
Supply Current
Conversion Mode
Sleep Mode
CC
l
l
CS = 0V (Note 7)
8
8
11
30
mA
μA
CS = V (Note 7)
CC
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
f
t
t
t
External Oscillator Frequency Range
0.1
20
MHz
EOSC
External Oscillator High Period
External Oscillator Low Period
Conversion Time
25
25
10000
10000
ns
ns
HEO
LEO
l
l
l
OSR = 256 (SDI = 0)
0.99
126
1.13
145
1.33
170
ms
ms
CONV
OSR = 32768 (SDI = 1)
40 • OSR + 170
External Oscillator (Note 10, 13)
ms
f
(kHz)
EOSC
l
f
Internal SCK Frequency
Internal Oscillator (Note 9)
0.8
45
0.9
EOSC
1
ISCK
f
/10
External Oscillator (Notes 9, 10)
l
l
l
l
l
D
Internal SCK Duty Cycle
(Note 9)
(Note 8)
(Note 8)
(Note 8)
55
20
%
MHz
ns
ISCK
f
t
t
t
External SCK Frequency Range
External SCK Low Period
ESCK
25
25
LESCK
External SCK High Period
ns
HESCK
DOUT_ISCK
Internal SCK 32-Bit Data Output Time
Internal Oscillator (Notes 9, 11)
External Oscillator (Notes 9, 10)
30.9
35.3
41.6
μs
s
320/f
EOSC
l
l
l
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
t
t
External SCK 32-Bit Data Output Time
(Note 8)
32/f
s
ns
ns
μs
ns
ns
ns
ns
ns
ns
DOUT_ESCK
ESCK
↑
CS to SDO Low Z
(Note 12)
(Note 12)
(Note 9)
0
0
25
25
1
CS ↑ to SDO High Z
2
↑
↑
CS to SCK
5
3
↑
(Notes 8, 12)
25
CS to SCK ↑
4
↑
SCK to SDO Valid
SDO Hold After SCK
SCK Set-Up Before CS
25
KQMAX
↑
(Note 5)
15
50
10
10
KQMIN
↑
5
7
8
(Note 5)
(Note 5)
SDI Setup Before SCK ↑
SDI Hold After SCK ↑
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
Note 7: The converter uses the internal oscillator.
Note 8: The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
Note 2: All voltage values are with respect to GND.
SCK during the data output is f
and is expressed in Hz.
ESCK
Note 9: The converter is in internal SCK mode of operation such that the
Note 3: V = 4.5 to 5.5V unless otherwise specified.
CC
+
–
+
–
SCK pin is used as a digital output. In this mode of operation, the SCK pin
V
V
= REF – REF , V
= (REF + REF )/2;
= (IN + IN )/2.
REF
REFCM
+
–
+
–
has a total equivalent load capacitance of C
= 20pF.
LOAD
= IN – IN , V
IN
INCM
Note 10: The external oscillator is connected to the f pin. The external
O
Note 4: f pin tied to GND or to external conversion clock source with
O
oscillator frequency, f
, is expressed in kHz.
EOSC
f
= 10MHz unless otherwise specified.
EOSC
Note 11: The converter uses the internal oscillator. f = 0V.
O
Note 5: Guaranteed by design, not subject to test.
Note 12: Guaranteed by design and test correlation.
Note 13: There is an internal reset that adds an additional 1μs (typical) to
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
the conversion time.
2440fd
4
LTC2440
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity
Integral Nonlinearity fOUT = 3.5kHz
fOUT = 1.76kHz
Integral Nonlinearity fOUT = 880Hz
10
5
10
5
10
5
V
V
V
V
= 5V
= 5V
V
O
= 2.5V
INCM
V
V
V
V
= 5V
= 5V
V
f
A
= 2.5V
V
V
V
V
= 5V
= 5V
V
O
= 2.5V
INCM
CC
CC
INCM
O
CC
f
= GND
= GND
f
= GND
REF
REF
REF
REF
REF
REF
REF
REF
REF
+
–
+
–
+
–
= 5V
T = 25°C
A
= 5V
T
= 25°C
= 5V
T = 25°C
A
= GND
= GND
= GND
0
0
0
–5
–5
–5
–10
–10
–10
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
V
(V)
V
(V)
V
IN
(V)
IN
IN
2440 G03
2440 G01
2440 G02
Integral Nonlinearity fOUT = 440Hz
Integral Nonlinearity fOUT = 220Hz
Integral Nonlinearity fOUT = 110Hz
10
5
10
5
10
5
V
V
V
V
= 5V
= 5V
V
O
= 2.5V
INCM
V
V
V
V
= 5V
= 5V
V
f
A
= 2.5V
V
V
V
V
= 5V
= 5V
V
O
= 2.5V
INCM
CC
CC
INCM
O
CC
f
= GND
= GND
f
= GND
REF
REF
REF
REF
REF
REF
REF
REF
REF
+
–
+
–
+
–
= 5V
T = 25°C
A
= 5V
T
= 25°C
= 5V
T = 25°C
A
= GND
= GND
= GND
0
0
0
–5
–5
–5
–10
–10
–10
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
V
(V)
V
(V)
V
IN
(V)
IN
IN
2440 G06
2440 G04
2440 G05
Integral Nonlinearity
fOUT = 13.75Hz
Integral Nonlinearity fOUT = 55Hz
Integral Nonlinearity fOUT = 27.5Hz
10
5
10
5
10
5
V
V
V
V
= 5V
= 5V
V
O
= 2.5V
INCM
V
V
V
V
= 5V
= 5V
V
O
= 2.5V
INCM
CC
V
V
V
V
= 5V
= 5V
V
O
= 2.5V
INCM
CC
CC
f
= GND
f
= GND
REF
REF
REF
f
= GND
REF
REF
REF
REF
REF
REF
+
–
+
–
+
–
= 5V
T = 25°C
A
= 5V
T = 25°C
A
= 5V
T = 25°C
A
= GND
= GND
= GND
0
0
0
–5
–5
–5
–10
–10
–10
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
V
(V)
V
(V)
IN
V
(V)
IN
IN
2440 G08
2440 G07
2440 G09
2440fd
5
LTC2440
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity
OUT = 6.875Hz
Integral Nonlinearity
vs Conversion Rate
f
Integral Nonlinearity vs VINCM
10
5
10
5
10.0
7.5
5.0
2.5
V
V
V
V
= 5V
V
= 2.5V
V
V
V
V
= 5V
–2.5V ≤ V ≤ 2.5V
IN
CC
INCM
CC
= 5V
f
= GND
= 5V
V
= 2.5V
REF
REF
REF
O
REF
REF
REF
INCM
O
+
–
+
–
= 5V
= GND
T
= 25°C
= 5V
= GND
f
= GND
V
= 3.75V
A
INCM
T = 25°C
A
V
= 2.5V
INCM
0
0
V
= 1.25V
INCM
–5
–5
V
V
V
V
= 5V
OSR = 32768
CC
= 2.5V
f
= GND
T = 25°C
A
REF
REF
REF
O
+
–
= 2.5V
= GND
0
–10
–10
0
500 1000 1500 2000 2500 3000 3500
CONVERSION RATE (Hz)
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
0.75
4
2
2.5
–1.25
–0.75
–0.25
0.25
(V)
0.75
1.25
V
(V)
V
IN
IN
2440 G11
2440 G10
2440 G12
Integral Nonlinearity
vs Temperature
Integral Nonlinearity
vs Temperature
–Full-Scale Error vs VREF
10
5
10
5
20
10
V
V
V
V
= 5V
= 5V
V
= 2.5V
V
V
V
V
= 5V
V
= 1.25V
CC
INCM
CC
INCM
OSR = 32768
f = GND
O
= 2.5V
OSR = 32768
f = GND
O
REF
REF
REF
REF
REF
REF
+
–
+
–
= 5V
= 2.5V
= GND
= GND
T
= –55°C
A
T
= 125°C
A
T
= 125°C
A
0
0
0
T
= 25°C
A
T
= 25°C
A
T
= –25°C
A
–5
–5
–10
–20
–10
–10
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–1.25
–0.75
–0.25
0.25
(V)
1.25
1
3
0
2
4
5
V
(V)
V
V
(V)
IN
IN
REF
2440 G14
2440 G13
2440 G15
+Full-Scale Error vs VREF
–Full-Scale Error vs VCC
+Full-Scale Error vs VCC
10
9
8
7
6
5
4
3
2
1
0
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
20
10
V
V
V
V
= 2.5V
OSR = 32768
REF
REF
REF
+
= 2.5V
= GND
= 1.25V
f
= GND
= 25°C
O
A
–
T
INCM
0
–10
–20
V
V
V
V
= 2.5V
OSR = 32768
REF
REF
REF
+
= 2.5V
= GND
= 1.25V
f
= GND
= 25°C
O
A
–
T
INCM
4.5
4.7
4.9
V
5.1
(V)
5.3
5.5
4.5
4.7
4.9
V
5.1
(V)
5.3
5.5
0
1
2
3
5
V
(V)
CC
CC
REF
2440 G17
2440 G18
2440 G16
2440fd
6
LTC2440
TYPICAL PERFORMANCE CHARACTERISTICS
Negative Full-Scale Error
vs Temperature
Positive Full-Scale Error
vs Temperature
Offset Error vs VCC
20
15
20
15
5.0
2.5
V
V
V
V
V
= 4.5V
= 4.5V
V
V
V
V
V
= 5.5V, 5V
= 5V
V
V
V
V
= 2.5V
OSR = 32768
CC
CC
REF
REF
+
= 2.5V
f
= GND
T = 25°C
A
REF
REF
REF
REF
REF
REF
O
+
–
+
–
–
= 4.5V
= GND
= 2.25V
= 5V
= GND
REF
+
–
= GND
= 2.5V
= V = GND
IN
IN
10
10
INCM
INCM
4.5V
5.5V
OSR = 32768 OSR = 32768
= GND = GND
5
5
f
O
f
O
0
0
0
V
V
V
V
V
= 4.5V
V
V
V
V
V
= 5.5V, 5V
CC
CC
5.5V
5V
–5
–5
= 4.5V
= 5V
REF
REF
REF
REF
REF
REF
+
–
+
–
5V
4.5V
= 4.5V
= GND
= 2.25V
= 5V
= GND
= 2.5V
–10
–15
–20
–10
–15
–20
–2.5
INCM
INCM
OSR = 32768 OSR = 32768
= GND
f
O
f
O
= GND
–5.0
35
TEMPERATURE (°C)
–55
35
125
–55
–25
5
65
95
125
–25
5
65
95
4.5
4.7
4.9
5.1
5.3
5.5
TEMPERATURE (°C)
V
(V)
CC
2440 G19
2440 G20
2440 G21
Offset Error vs Conversion Rate
Offset Error vs VINCM
RMS Noise vs Temperature
5.0
2.5
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
5.0
2.5
+
–
+
–
V
V
V
V
= 5V
= 5V
V
f
A
= V = GND
IN IN
O
V
V
V
V
= 5V
= 5V
V
= V = V
CC
CC
IN IN INCM
= GND
= 25°C
OSR = 32768
= GND
T = 25°C
A
REF
REF
REF
REF
REF
REF
+
–
+
–
= 5V
T
= 5V
f
O
= GND
= GND
V
CC
V
CC
V
CC
= 4.5V
= 5V
= 5.5V
0
V
V
V
V
V
= 4.5V
V
V
V
V
V
= 5.5V, 5V
CC
CC
= 2.5V
= 5V
REF
REF
REF
REF
REF
REF
+
–
+
–
= 2.5V
= 5V
–2.5
–2.5
–5.0
= GND
= GND
+
–
+
–
= V = GND
= V = GND
IN
IN
IN
IN
OSR = 256
OSR = 256
f
O
= GND
f
O
= GND
–5.0
0
500 1000 1500 2000 2500 3000 3500
CONVERSION RATE (Hz)
–55
5
35
65
95
125
0
1
2
3
4
5
–25
TEMPERATURE (°C)
V
(V)
INCM
2440 G22
2440 G24
2440 G23
INL vs Output Rate
(OSR = 128) External Clock Sweep
10MHz to 20MHz
RMS Noise vs Output Rate
(OSR = 128) External Clock
Sweep 10MHz to 20MHz
Offset Error vs Temperature
5.0
2.5
20
18
16
14
12
10
8
5
4
3
2
1
0
V
= 5V
V
CC
EXTERNAL CLOCK 10MHz
V
= 5.5V
V
V
= 4.5V
CC
CC
(OR INTERNAL OSCILLATOR)
EXTERNAL
CLOCK 20MHz
0
= 4.5V
= 5.5V, 5V
CC
CC
V
V
V
V
= 2.5V
V
V
V
V
= 5V
REF
REF
REF
REF
REF
REF
+
–
+
–
6
= 2.5V
= 5V
–2.5
–5.0
= GND
= GND
V
= V = 5V
CC
V
= V = 5V
CC
4
REF
REF
+
–
+
–
= V = GND
= V = GND
IN
IN
IN
IN
TEMP = 25°C
TEMP = 25°C
/2
2
OSR = 256
OSR = 256
SWEEP (V – V /2) TO V /2
V
V
REF
IN
REF
REF
IN
f
O
= GND
f
O
= GND
0
2000
–55
5
35
65
95
125
–25
2500
3000
3500
4000
2000
2500
3000
3500
4000
TEMPERATURE (°C)
OUTPUT RATE (Hz)
OUTPUT RATE (Hz)
2440 G25
2440 G26
2440 G27
2440fd
7
LTC2440
PIN FUNCTIONS
GND (Pins 1, 8, 9, 16): Ground. Multiple ground pins
is selected. The device generates its own SCK signal and
outputsthisontheSCKpin.AframingsignalBUSY(Pin 15)
goes low indicating data is being output.
internallyconnectedforoptimumgroundcurrentflowand
V decoupling.Connecteachoneofthesepinstoaground
CC
plane through a low impedance connection. All four pins
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
must be connected to ground for proper operation.
V
(Pin 2): Positive Supply Voltage. Bypass to GND
CC
(Pin 1)witha10μFtantalumcapacitorinparallelwith0.1μF
ceramic capacitor as close to the part as possible.
+
–
REF (Pin 3), REF (Pin 4): Differential Reference Input.
The voltage on these pins can have any value between
+
GNDandV aslongasthereferencepositiveinput, REF ,
SDO (Pin 12): Three-State Digital Output. During the Data
CC
is maintained more positive than the reference negative
Output period, this pin is used as serial data output. When
–
input, REF , by at least 0.1V.
the chip select CS is HIGH (CS = V ) the SDO pin is in a
CC
high impedance state. During the Conversion and Sleep
periods,thispinisusedastheconversionstatusoutput.The
conversion status can be observed by pulling CS LOW.
+
–
IN (Pin 5), IN (Pin 6): Differential Analog Input. The
voltage on these pins can have any value between GND
– 0.3V and V + 0.3V. Within these limits the converter
CC
+
–
bipolar input range (V = IN – IN ) extends from –0.5
SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data Output
period.InExternalSerialClockOperationmode,SCKisused
as digital input for the external serial interface clock during
the Data Output period. The Serial Clock Operation mode is
determined by the logic level applied to the EXT pin.
IN
• (V ) to 0.5 • (V ). Outside this input range the
REF
REF
converter produces unique overrange and underrange
output codes.
SDI (Pin 7): Serial Data Input. This pin is used to select
the speed/resolution of the converter. If SDI is grounded
(pin compatible with LTC2410) the device outputs data at
880Hzwith21bitseffectiveresolution. BytyingSDIHIGH,
f (Pin 14): Frequency Control Pin. Digital input that con-
O
the converter enters the ultralow noise mode (200nV
)
RMS
trolstheinternalconversionclock.Whenf isconnectedto
O
with simultaneous 50/60Hz rejection at 6.9Hz output
rate. SDI may be driven logic HIGH or LOW anytime dur-
ing the conversion or sleep state in order to change the
speed/resolution. The conversion immediately following
the data output cycle will be valid and performed at the
newly selected output rate/resolution. SDI may also be
programmedbyaserialinputdatastreamundercontrolof
SCKduringthedataoutputcycle. Oneoftenspeed/resolu-
V orGND,theconverterusesitsinternaloscillatorrunning
CC
at 9MHz. The conversion rate is determined by the selected
OSR such that t
(in ms) = (40 • OSR + 170)/9000
CONV
(t
CONV
= 1.137ms at OSR = 256, t
= 146ms at OSR =
CONV
32768). The first null is located at 8/t
, 7kHz at OSR =
CONV
256 and 55Hz (simultaneous 50/60Hz) at OSR = 32768.
When f is driven by an oscillator with frequency f (in
O
EOSC
= (40 • OSR +
kHz), the conversion time becomes t
CONV
tion ranges (from 6.9Hz/200nV
to 3.5kHz/21μV
)
RMS
RMS
170)/f
(in ms) and the first null remains 8/t
.
may be selected. The first conversion following a new
selection is valid and performed at the newly selected
speed/resolution.
EOSC
CONV
BUSY (Pin 15): Conversion in Progress Indicator. For
compatibility with the LTC2410, this pin should not be
tied to ground. This pin is HIGH while the conversion
is in progress and goes LOW indicating the conversion
is complete and data is ready. It remains low during the
sleep and data output states. At the conclusion of the data
output state, it goes HIGH indicating a new conversion
EXT(Pin10):Internal/ExternalSCKSelectionPin. Thispin
is used to select internal or external SCK for outputting
data. If EXT is tied low (pin compatible with the LTC2410),
the device is in the external SCK mode and data is shifted
out the device under the control of a user applied serial
clock. If EXT is tied high, the internal serial clock mode
has begun.
2440fd
8
LTC2440
FUNCTIONAL BLOCK DIAGRAM
INTERNAL
OSCILLATOR
V
CC
GND
AUTOCALIBRATION
AND CONTROL
f
O
(INT/EXT)
+
IN
+
–
–
IN
SDO
ADC
SCK
CS
SERIAL
INTERFACE
DECIMATING FIR
SDI
BUSY
EXT
2440 F01
DAC
–
+
+
REF
–
REF
Figure 1. Functional Block Diagram
TEST CIRCUITS
V
CC
1.69k
SDO
SDO
1.69k
C
= 20pF
LOAD
C
= 20pF
LOAD
Hi-Z TO V
OH
OH
V
V
TO V
OL
OH
Hi-Z TO V
OL
OL
TO Hi-Z
2440 TA03
V
V
TO V
OH
OL
TO Hi-Z
2440 TA04
APPLICATIONS INFORMATION
CONVERTER OPERATION
CONVERT
SLEEP
Converter Operation Cycle
TheLTC2440isahighspeed,delta-sigmaanalog-to-digital
converter with an easy to use 4-wire serial interface (see
Figure 1). Its operation is made up of three states. The
converter operating cycle begins with the conversion,
followed by the low power sleep state and ends with the
data output (see Figure 2). The 4-wire interface consists
of serial data input (SDI), serial data output (SDO), serial
clock (SCK) and chip select (CS). The interface, timing,
operation cycle and data out format is compatible with
the LTC2410.
FALSE
CS = LOW
AND
SCK
TRUE
DATA OUTPUT
2440 F02
Figure 2. LTC2440 State Transition Diagram
2440fd
9
LTC2440
APPLICATIONS INFORMATION
Initially, the LTC2440 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
While in this sleep state, power consumption is reduced
below 10μA. The part remains in the sleep state as long
as CS is HIGH. The conversion result is held indefinitely
in a static shift register while the converter is in the sleep
state.
Power-Up Sequence
The LTC2440 automatically enters an internal reset state
when the power supply voltage V drops below ap-
proximately 2.2V. This feature guarantees the integrity
of the conversion result and of the serial interface mode
selection.
CC
WhentheV voltagerisesabovethiscriticalthreshold,the
CC
Once CS is pulled LOW, the device begins outputting the
conversion result. There is no latency in the conversion
result. The data output corresponds to the conversion
just performed. This result is shifted out on the serial data
out pin (SDO) under the control of the serial clock (SCK).
Data is updated on the falling edge of SCK allowing the
user to reliably latch data on the rising edge of SCK (see
Figure 3). The data output state is concluded once 32-bits
are read out of the ADC or when CS is brought HIGH. The
device automatically initiates a new conversion and the
cycle repeats.
converter creates an internal power-on-reset (POR) signal
with a duration of approximately 0.5ms. The POR signal
clears all internal registers. Following the POR signal, the
LTC2440 starts a normal conversion cycle and follows the
successionofstatesdescribedabove.Thefirstconversion
result following POR is accurate within the specifications
of the device if the power supply voltage is restored within
the operating range (4.5V to 5.5V) before the end of the
POR time interval.
Reference Voltage Range
Through timing control of the CS, SCK and EXT pins,
the LTC2440 offers several flexible modes of operation
(internal or external SCK). These various modes do not
require programming configuration registers; moreover,
they do not disturb the cyclic operation described above.
These modes of operation are described in detail in the
Serial Interface Timing Modes section.
Thisconverteracceptsatrulydifferentialexternalreference
voltage.Theabsolute/commonmodevoltagespecification
+
–
for the REF and REF pins covers the entire range from
+
GND to V . For correct converter operation, the REF pin
CC
–
must always be more positive than the REF pin.
The LTC2440 can accept a differential reference voltage
from0.1VtoV .Theconverteroutputnoiseisdetermined
CC
by the thermal noise of the front-end circuits, and as such,
its value in microvolts is nearly constant with reference
voltage. A decrease in reference voltage will not signifi-
cantly improve the converter’s effective resolution. On the
other hand, a reduced reference voltage will improve the
converter’s overall INL performance.
Ease of Use
The LTC2440 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy. Speed/resolution adjust-
ments may be made seamlessly between two conversions
without settling errors.
Input Voltage Range
Theanaloginputistrulydifferentialwithanabsolute/com-
+
–
The LTC2440 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
theuserandhasnoeffectonthecyclicoperationdescribed
above. Theadvantageofcontinuouscalibrationisextreme
stability of offset and full-scale readings with respect to
time, supply voltage change and temperature drift.
mon mode range for the IN and IN input pins extending
from GND – 0.3V to V + 0.3V. Outside these limits, the
CC
ESD protection devices begin to turn on and the errors
due to input leakage current increase rapidly. Within these
limits, the LTC2440 converts the bipolar differential input
+
–
signal, V = IN – IN , from –FS = –0.5 • V
to +FS =
IN
REF
2440fd
10
LTC2440
APPLICATIONS INFORMATION
+
–
0.5 • V where V = REF – REF . Outside this range, indicator (SIG). If V is >0, this bit is HIGH. If V is <0,
REF
REF
IN
IN
this bit is LOW.
the converter indicates the overrange or the underrange
condition using distinct output codes.
Bit28(fourthoutputbit)isthemostsignificantbit(MSB)of
the result. This bit in conjunction with Bit 29 also provides
the underrange or overrange indication. If both Bit 29 and
Bit 28 are HIGH, the differential input voltage is above +FS.
If both Bit 29 and Bit 28 are LOW, the differential input
voltage is below –FS.
Output Data Format
The LTC2440 serial output data stream is 32-bits long.
The first 3-bits represent status information indicating
the sign and conversion state. The next 24-bits are the
conversion result, MSB first. The remaining 5-bits are
sub LSBs beyond the 24-bit level that may be included in
averaging or discarded without loss of resolution. In the
case of ultrahigh resolution modes, more than 24 effec-
tive bits of performance are possible (see Table 3). Under
these conditions, sub LSBs are included in the conversion
result and represent useful information beyond the 24-bit
level. The third and fourth bit together are also used to
indicate an underrange condition (the differential input
voltage is below –FS) or an overrange condition (the dif-
ferential input voltage is above +FS). For input conditions
The function of these bits is summarized in Table 1.
Table 1. LTC2440 Status Bits
Bit 31
Bit 30
DMY
Bit 29
SIG
Bit 28
MSB
Input Range
≥ 0.5 • V
EOC
V
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
IN
REF
0V ≤ V < 0.5 • V
IN
REF
–0.5 • V ≤ V < 0V
REF
IN
V
IN
< –0.5 • V
REF
Bits ranging from 28 to 5 are the 24-bit conversion result
MSB first.
in excess of twice full scale (|V | ≥ V ), the converter
IN
REF
may indicate either overrange or underrange. Once the
inputreturnstothenormaloperatingrange,theconversion
result is immediately accurate within the specifications of
the device.
Bit 5 is the Least Significant Bit (LSB).
Bits ranging from 4 to 0 are sub LSBs below the 24-bit
level. Bits 4 to bit 0 may be included in averaging or dis-
carded without loss of resolution.
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Data is shifted out of the SDO pin under control of the
serial clock (SCK), see Figure 3. Whenever CS is HIGH,
SDO remains high impedance.
In order to shift the conversion result out of the device,
CS must first be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes real
time from HIGH to LOW at the completion of a conversion.
This signal may be used as an interrupt for an external
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign
CS
BIT 31
BIT 30
“0”
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 5
BIT 0
SDO
LSB
24
EOC
Hi-Z
SCK
1
2
3
4
5
26
27
32
BUSY
SLEEP
DATA OUTPUT
CONVERSION
2440 F03
Figure 3. Output Data Timing
2440fd
11
LTC2440
APPLICATIONS INFORMATION
Serial Clock Input/Output (SCK)
microcontroller. Bit 31 (EOC) can be captured on the first
rising edge of SCK. Bit 30 is shifted out of the device on
the first falling edge of SCK. The final data bit (Bit 0) is
shifted out on the falling edge of the 31st SCK and may
be latched on the rising edge of the 32nd SCK pulse. On
the falling edge of the 32nd SCK pulse, SDO goes HIGH
indicating the initiation of a new conversion cycle. This
bit serves as EOC (Bit 31) for the next conversion cycle.
Table 2 summarizes the output data format.
The serial clock signal present on SCK (Pin 13) is used to
synchronizethedatatransfer. Eachbitofdataisshiftedout
the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2440 creates its own serial clock. In
the External SCK mode of operation, the SCK pin is used
as input. The internal or external SCK mode is selected
by tying EXT (Pin 10) LOW for external SCK and HIGH
for internal SCK.
+
–
As long as the voltage on the IN and IN pins is main-
tainedwithinthe–0.3Vto(V +0.3V)absolutemaximum
CC
operating range, a conversion result is generated for any
Serial Data Output (SDO)
differential input voltage V from –FS = –0.5 • V
to
IN
REF
The serial data output pin, SDO (Pin 12), provides the
result of the last conversion as a serial bit stream (MSB
first) during the data output state. In addition, the SDO
pin is used as an end of conversion indicator during the
conversion and sleep states.
+FS = 0.5 • V . For differential input voltages greater
REF
than +FS, the conversion result is clamped to the value
corresponding to the +FS + 1LSB. For differential input
voltages below –FS, the conversion result is clamped to
the value corresponding to –FS – 1LSB.
When CS (Pin 11) is HIGH, the SDO driver is switched
to a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH
on the SDO pin. Once the conversion is complete, EOC
goes LOW. The device remains in the sleep state until the
first rising edge of SCK occurs while CS = LOW.
SERIAL INTERFACE PINS
TheLTC2440transmitstheconversionresultsandreceives
the start of conversion command through a synchronous
2-wire, 3-wire or 4-wire interface. During the conversion
and sleep states, this interface can be used to assess
the converter status and during the data output state it
is used to read the conversion result and program the
speed/resolution.
Table 2. LTC2440 Output Data Format
Differential Input Voltage
V *
Bit 31
Bit 30
DMY
Bit 29
SIG
Bit 28
EOC
MSB
Bit 27
Bit 26
Bit 25
…
…
…
Bit 0
IN
V * ≥ 0.5 • V **
0
0
0
0
1
1
1
0
0
1
0
1
0
1
0
1
IN
REF
0.5 • V ** – 1LSB
REF
0.25 • V **
0
0
0
0
1
1
0
0
1
0
0
1
0
1
…
…
0
1
REF
0.25 • V ** – 1LSB
REF
0
0
0
0
0
1
0
0
1
0
1
0
1
0
1
…
…
0
1
–1LSB
–0.25 • V **
0
0
0
0
0
0
1
1
1
0
0
1
0
1
…
…
0
1
REF
–0.25 • V ** – 1LSB
REF
–0.5 • V **
0
0
0
0
0
1
0
0
0
1
0
1
…
…
0
1
REF
V * < –0.5 • V **
IN
0
1
REF
+
–
+
–
*The differential input voltage V = IN – IN . **The differential reference voltage V = REF – REF .
IN
REF
2440fd
12
LTC2440
APPLICATIONS INFORMATION
Chip Select Input (CS)
Serial Data Input (SDI)—Serial Input Speed Selection
SDI may also be programmed by a serial input data
stream under control of SCK during the data output cycle,
see Figure 4. One of ten speed/resolution ranges (from
The active LOW chip select, CS (Pin 11), is used to test the
conversion status and to enable the data output transfer
as described in the previous sections.
6.9Hz/200nV
to3.5kHz/21μV
)maybeselected,see
RMS
RMS
In addition, the CS signal can be used to trigger a new con-
versioncyclebeforetheentireserialdatatransferhasbeen
completed. The LTC2440 will abort any serial data transfer
in progress and start a new conversion cycle anytime a
LOW-to-HIGH transition is detected at the CS pin after the
converter has entered the data output state (i.e., after the
fifth falling edge of SCK occurs with CS = LOW).
Table 3. The conversion following a new selection is valid
and performed at the newly selected speed/resolution.
BUSY
The BUSY output (Pin 15) is used to monitor the state of
conversion, data output and sleep cycle. While the part is
converting, the BUSY pin is HIGH. Once the conversion is
complete, BUSY goes LOW indicating the conversion is
complete and data out is ready. The part now enters the
LOW power sleep state. BUSY remains LOW while data is
shifted out of the device. It goes HIGH at the conclusion
of the data output cycle indicating a new conversion has
begun. This rising edge may be used to flag the comple-
tion of the data read cycle.
Serial Data Input (SDI)—Logic Level Speed Selection
The serial data input (SDI, Pin 7) is used to select the
speed/resolutionoftheLTC2440.Asimple2-speedcontrol
is selectable by either driving SDI HIGH or LOW. If SDI
is grounded (pin compatible with LTC2410) the device
outputs data at 880Hz with 21 bits effective resolution. By
tying SDI HIGH, the converter enters the ultralow noise
mode(200nV
)withsimultaneous50/60Hzrejectionat
RMS
SERIAL INTERFACE TIMING MODES
6.9Hz output rate. SDI may be driven logic HIGH or LOW
anytime during the conversion or sleep state in order to
changethespeed/resolution. Theconversionimmediately
following the data output cycle will be valid and performed
at the newly selected output rate/resolution.
The LTC2440’s 2-wire, 3-wire or 4-wire interface is SPI
andMICROWIREcompatible. Thisinterfaceoffersseveral
flexiblemodesofoperation.Theseincludeinternal/external
serial clock, 2-wire or 3-wire I/O, single cycle conversion
and autostart. The following sections describe each of
these serial interface timing modes in detail. In all these
Changing SDI logic state during the data output cycle
should be avoided as speed resolution other than 6.9Hz
or 880Hz may be selected. For example, if SDI is changed
from logic 0 to logic 1 after the second rising edge of SCK,
the conversion rate will change from 880Hz to 55Hz (the
following values are listed in Table 3: OSR4 = 0, OSR3 = 0,
OSR2 = 1, OSR1 = 1 and OSR0 = 1). If SDI remains HIGH,
the conversion rate will switch to the desired 6.9Hz speed
immediately following the conversion at 55Hz. The 55Hz
rate conversion cycle will be a valid result as well as the
first 6.9Hz result. On the other hand, if SDI is changed to a
1 anytime before the first rising edge of SCK, the following
conversion rate will become 6.9Hz. If SDI is changed to
a 1 after the 5th rising edge of SCK, the next conversion
will remain 880Hz while all subsequent conversions will
be at 6.9Hz.
cases, the converter can use the internal oscillator (f =
O
LOW) or an external oscillator connected to the f pin.
O
See Table 4 for a summary.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift
out the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 5.
The serial clock mode is selected by the EXT pin. To select
the external serial clock mode, EXT must be tied low.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
2440fd
13
LTC2440
APPLICATIONS INFORMATION
CS
SCK
SDI
OSR4*
OSR3
OSR2
OSR1
OSR0
BIT 31
EOC
BIT 30
“0”
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 25
BIT 1
BIT 0
LSB
Hi-Z
Hi-Z
SDO
BUSY
2440 F04
*OSR4 BIT MUST BE AT FIRST SCK RISING EDGE DURING SERIAL DATA OUT CYCLE
Figure 4. SDI Speed/Resolution Programming
Table 3. SDI Speed/Resolution Programming
CONVERSION RATE
INTERNAL
EXTERNAL
RMS
OSR4
OSR3
OSR2
OSR1
OSR0
9MHz CLOCK
3.52kHz
1.76kHz
880Hz
10.24MHz CLOCK
NOISE
23μV
3.5μV
2μV
ENOB
OSR
64
X
X
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
4kHz
2kHz
17
20
128
1kHz
21.3
21.3
21.8
22.4
22.9
23.4
24
256*
256
X
X
X
X
X
X
X
X
880Hz
1kHz
2μV
440Hz
500Hz
250Hz
125Hz
62.5Hz
31.25Hz
15.625Hz
7.8125Hz
1.4μV
1μV
512
220Hz
1024
2048
4096
8192
110Hz
750nV
510nV
375nV
250nV
200nV
55Hz
27.5Hz
13.75Hz
6.875Hz
24.4
24.6
16384
32768**
**Address allows tying SDI HIGH *Additional address to allow tying SDI LOW
Table 4. LTC2440 Interface Timing Modes
Conversion
Cycle
Control
Data
Connection
SCK
Source
Output
and
Configuration
Control
Waveforms
External SCK, Single Cycle Conversion
External SCK, 2-Wire I/O
External
External
Internal
Internal
CS and SCK
CS and SCK
Figures 5, 6
Figure 7
SCK
SCK
↑
↑
Internal SCK, Single Cycle Conversion
Internal SCK, 2-Wire I/O, Continuous Conversion
CS
CS
Figures 8, 9
Figure 10
Continuous
Internal
2440fd
14
LTC2440
APPLICATIONS INFORMATION
4.5V TO 5.5V
1μF
2
15
V
CC
BUSY
LTC2440
REF
3
14
13
12
11
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
+
f
O
REFERENCE VOLTAGE
0.1V TO V
4
5
6
–
CC
SCK
SDO
CS
REF
+
3-WIRE
SPI INTERFACE
IN
ANALOG INPUT RANGE
–0.5V
TO 0.5V
–
REF
REF
V
IN
CC
200nV NOISE, 50/60Hz REJECTION
7
10-SPEED/RESOLUTION PROGRAMMABLE
2μV NOISE, 880Hz OUTPUT RATE
SDI
1, 8, 9, 16
10
GND
EXT
CS
TEST EOC
TEST EOC
TEST EOC
BIT 31
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 5
LSB
BIT 0
SUB LSB
SDO
EOC
Hi-Z
Hi-Z
Hi-Z
SCK
(EXTERNAL)
BUSY
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
2440 F05
Figure 5. External Serial Clock, Single Cycle Operation
EOC = 1 (BUSY = 1) while a conversion is in progress
and EOC = 0 (BUSY = 0) if the device is in the sleep state.
IndependentofCS,thedeviceautomaticallyentersthelow
power sleep state once the conversion is complete.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the fifth falling edge (SDI must
be properly loaded each cycle) and the 32nd falling edge
of SCK, see Figure 6. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 32-bits of output data, aborting an invalid conversion
cycle or synchronizing the start of a conversion.
When the device is in the sleep state (EOC = 0), its con-
version result is held in an internal static shift register.
The device remains in the sleep state until the first rising
edge of SCK is seen. Data is shifted out the SDO pin on
each falling edge of SCK. This enables external circuitry
to latch the output on the rising edge of SCK. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result can be latched on the 32nd rising
edge of SCK. On the 32nd falling edge of SCK, the device
begins a new conversion. SDO goes HIGH (EOC = 1) and
BUSY goes HIGH indicating a conversion is in progress.
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface.
The conversion result is shifted out of the device by an
externally generated serial clock (SCK) signal, see Figure
7. CS may be permanently tied to ground, simplifying the
user interface or isolation barrier. The external serial clock
mode is selected by tying EXT LOW.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z
and BUSY monitored for the completion of a conversion.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status on the SDO pin.
Since CS is tied LOW, the end-of-conversion (EOC) can
be continuously monitored at the SDO pin during the
convert and sleep states. Conversely, BUSY (Pin 15) may
be used to monitor the status of the conversion cycle.
EOC or BUSY may be used as an interrupt to an external
2440fd
15
LTC2440
APPLICATIONS INFORMATION
4.5V TO 5.5V
1μF
2
15
V
BUSY
CC
LTC2440
REF
3
4
5
6
14
13
12
11
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
+
f
O
REFERENCE VOLTAGE
–
0.1V TO V
CC
SCK
SDO
CS
REF
+
3-WIRE
SPI INTERFACE
IN
ANALOG INPUT RANGE
–0.5V
TO 0.5V
–
REF
REF
V
IN
CC
200nV NOISE, 50/60Hz REJECTION
7
10-SPEED/RESOLUTION PROGRAMMABLE
2μV NOISE, 880Hz OUTPUT RATE
SDI
1, 8, 9, 16
10
GND
EXT
CS
TEST EOC
TEST EOC
TEST EOC
BIT 0
BIT 31
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 9
BIT 8
SDO
EOC
EOC
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
5
SCK
(EXTERNAL)
BUSY
SLEEP
CONVERSION
DATA OUTPUT
SLEEP
DATA OUTPUT
CONVERSION
2410 F06
Figure 6. External Serial Clock, Reduced Data Output Length
4.5V TO 5.5V
1μF
2
15
V
CC
BUSY
LTC2440
REF
3
4
5
6
14
13
12
11
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
+
f
O
REFERENCE VOLTAGE
0.1V TO V
–
CC
SCK
SDO
CS
REF
+
3-WIRE
SPI INTERFACE
IN
ANALOG INPUT RANGE
–0.5V
TO 0.5V
–
REF
REF
V
IN
CC
200nV NOISE, 50/60Hz REJECTION
7
10-SPEED/RESOLUTION PROGRAMMABLE
2μV NOISE, 880Hz OUTPUT RATE
SDI
1, 8, 9, 16
10
GND
EXT
CS
BIT 31
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 5
LSB
BIT 0
SDO
EOC
24
SCK
(EXTERNAL)
BUSY
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
2440 F07
Figure 7. External Serial Clock, CS = 0 Operation (2-Wire)
2440fd
16
LTC2440
APPLICATIONS INFORMATION
controller indicating the conversion result is ready. EOC
= 1 (BUSY = 1) while the conversion is in progress and
EOC = 0 (BUSY = 0) once the conversion enters the low
power sleep state. On the falling edge of EOC/BUSY, the
conversion result is loaded into an internal static shift
register. The device remains in the sleep state until the
first rising edge of SCK. Data is shifted out the SDO pin
on each falling edge of SCK enabling external circuitry to
latch data on the rising edge of SCK. EOC can be latched
on the first rising edge of SCK. On the 32nd falling edge
of SCK, SDO and BUSY go HIGH (EOC = 1) indicating a
new conversion has begun.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state. Alterna-
tively, BUSY (Pin 15) may be used to monitor the status
of the conversion in progress. BUSY is HIGH during the
conversion and goes LOW at the conclusion. It remains
LOW until the result is read from the device.
When testing EOC, if the conversion is complete (EOC =
0), the device will exit the sleep state and enter the data
output state if CS remains LOW. In order to prevent the
device from exiting the low power sleep state, CS must
be pulled HIGH before the first rising edge of SCK. In the
internal SCK timing mode, SCK goes HIGH and the device
Internal Serial Clock, Single Cycle Operation
beginsoutputtingdataattimet
afterthefallingedge
after EOC goes LOW (if CS is
EOCtest
This timing mode uses an internal serial clock to shift out
theconversionresultandaCSsignaltomonitorandcontrol
the state of the conversion cycle, see Figure 8.
of CS (if EOC = 0) or t
EOCtest
LOW during the falling edge of EOC). The value of t
EOCtest
, the
is 500ns. If CS is pulled HIGH before time tE
OCtest
device remains in the sleep state. The conversion result
is held in the internal static shift register.
In order to select the internal serial clock timing mode,
the EXT pin must be tied HIGH.
If CS remains LOW longer than t
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins
, the first rising
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
EOCtest
4.5V TO 5.5V
1μF
2
15
V
CC
BUSY
LTC2440
REF
3
14
13
12
11
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
+
f
O
REFERENCE VOLTAGE
4
–
0.1V TO V
CC
SCK
SDO
CS
REF
+
5
6
3-WIRE
SPI INTERFACE
IN
ANALOG INPUT RANGE
–0.5V
TO 0.5V
–
REF
REF
V
IN
CC
200nV NOISE, 50/60Hz REJECTION
7
10-SPEED/RESOLUTION PROGRAMMABLE
2μV NOISE, 880Hz OUTPUT RATE
SDI
1, 8, 9, 16
10
GND
EXT
V
CC
<t
EOCtest
CS
TEST EOC
TEST EOC
BIT 31
EOC
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 5
LSB
BIT 0
SDO
24
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCK
(INTERNAL)
BUSY
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
2440 F08
Figure 8. Internal Serial Clock, Single Cycle Operation
2440fd
17
LTC2440
APPLICATIONS INFORMATION
on this first rising edge of SCK and concludes after the
32nd rising edge. Data is shifted out the SDO pin on each
falling edge of SCK. The internally generated serial clock
is output to the SCK pin. This signal may be used to shift
the conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result on the 32nd rising edge of SCK.
After the 32nd rising edge, SDO goes HIGH (EOC = 1),
SCK stays HIGH and a new conversion starts.
new conversion. This is useful for systems not requiring
all 32-bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. Theconversionresultisshiftedoutofthedevice
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground, sim-
plifying the user interface or isolation barrier. The internal
serial clock mode is selected by tying EXT HIGH.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pull-
ing CS HIGH anytime between the first and 32nd rising
edge of SCK, see Figure 9. In order to properly select the
OSR for the conversion following a data abort, five SCK
rising edges must be seen prior to performing a data out
abort (pulling CS HIGH). If CS is pulled high prior to the
fifth SCK falling edge, the OSR selected depends on the
number of SCK signals seen prior to data abort, where
subsequent nonaborted conversion cycles return to the
programmed OSR. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1) and BUSY = 1. Once the
conversioniscomplete,SCK,BUSYandSDOgoLOW(EOC
= 0) indicating the conversion has finished and the device
has entered the low power sleep state. The part remains in
the sleep state a minimum amount of time (≈500ns) then
immediately begins outputting data. The data output cycle
begins on the first rising edge of SCK and ends after the
32nd rising edge. Data is shifted out the SDO pin on each
4.5V TO 5.5V
1μF
15
2
V
CC
BUSY
LTC2440
REF
3
14
13
12
11
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
+
f
O
REFERENCE VOLTAGE
4
–
0.1V TO V
CC
SCK
SDO
CS
REF
+
5
6
3-WIRE
SPI INTERFACE
IN
ANALOG INPUT RANGE
–0.5V TO 0.5V
–
REF
REF
V
IN
CC
200nV NOISE, 50/60Hz REJECTION
7
10-SPEED/RESOLUTION PROGRAMMABLE
2μV NOISE, 880Hz OUTPUT RATE
SDI
EXT
1, 8, 9, 16
10
GND
V
CC
>t
<t
EOCtest
EOCtest
CS
TEST EOC
TEST EOC
TEST EOC
BIT 0
BIT 31
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 8
SDO
EOC
EOC
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
5
SCK
(INTERNAL)
BUSY
SLEEP
CONVERSION
DATA OUTPUT
SLEEP
DATA OUTPUT
CONVERSION
2440 F09
Figure 9. Internal Serial Clock, Reduced Data Output Length
2440fd
18
LTC2440
APPLICATIONS INFORMATION
4.5V TO 5.5V
1μF
15
2
BUSY
V
CC
LTC2440
REF
3
14
13
12
11
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
+
f
O
REFERENCE VOLTAGE
0.1V TO V
4
5
6
–
CC
SCK
SDO
CS
REF
+
2-WIRE
SPI INTERFACE
IN
ANALOG INPUT RANGE
–0.5V TO 0.5V
–
REF
REF
V
CC
IN
200nV NOISE, 50/60Hz REJECTION
10-SPEED/RESOLUTION PROGRAMMABLE
2μV NOISE, 880Hz OUTPUT RATE
7
SDI
1, 8, 9, 16
10
GND
EXT
V
CC
CS
BIT 31
BIT 30
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 5
LSB
BIT 0
SDO
EOC
24
SCK
(INTERNAL)
BUSY
CONVERSION
DATA OUTPUT
CONVERSION
2410 F10
SLEEP
Figure 10. Internal Serial Clock, Continuous Operation
falling edge of SCK. The internally generated serial clock
is output to the SCK pin. This signal may be used to shift
the conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result can be latched on the 32nd rising
edge of SCK. After the 32nd rising edge, SDO goes HIGH
(EOC = 1) indicating a new conversion is in progress. SCK
remains HIGH during the conversion.
rejection at the frequency f 14% is better than 80dB,
N
see Figure 12.
If f is grounded, f is set by the on-chip oscillator at
O
S
1.8MHz 5% (over supply and temperature variations). At
an OSR of 32,768, the first NULL is at f = 55Hz and the
N
no latency output rate is f /8 = 6.9Hz. At the maximum
N
0
–20
–40
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital filtering. Combined
with a large oversampling ratio, the LTC2440 significantly
simplifies antialiasing filter requirements.
–60
–80
–100
–120
–140
The LTC2440’s speed/resolution is determined by the
over sample ratio (OSR) of the on-chip digital filter. The
OSR ranges from 64 for 3.5kHz output rate to 32,768
for 6.9Hz output rate. The value of OSR and the sample
60
120
240
0
180
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
rate f determine the filter characteristics of the device.
S
2440 F11
The first NULL of the digital filter is at f and multiples
N
Figure 11. LTC2440 Normal Mode Rejection (Internal Oscillator)
of f where f = f /OSR, see Figure 11 and Table 5. The
N
N
S
2440fd
19
LTC2440
APPLICATIONS INFORMATION
OSR,thenoiseperformanceofthedeviceis200nV
with
Table 5. OSR vs Notch Frequency (f ) with Internal Oscillator
RMS
N
Running at 9MHz
better than 80dB rejection of 50Hz 2% and 60Hz 2%.
Since the OSR is large (32,768) the wide band rejection
is extremely large and the antialiasing requirements are
OSR
NOTCH (f )
N
64
28.16kHz
14.08kHz
7.04kHz
3.52kHz
1.76kHz
880Hz
128
simple. The first multiple of f occurs at 55Hz • 32,768 =
S
256
1.8MHz, see Figure 13.
512
The first NULL becomes f = 7.04kHz with an OSR of 256
N
1024
(anoutputrateof880Hz)andf grounded.WhiletheNULL
O
2048
has shifted, the sample rate remains constant. As a result
of constant modulator sampling rate, the linearity, offset
and full-scale performance remains unchanged as does
4096
440Hz
8192
16384
220Hz
110Hz
the first multiple of f .
S
32768*
55Hz
*Simultaneous 50/60 rejection
0
–20
–40
–80
–90
–100
–110
–120
–130
–140
–60
–80
1.8MHz
–100
–120
REJECTION > 120dB
1000000
–140
0
57 59
2000000
47 49 51 53 55
61 63
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2440 F12
1440 F13
Figure 12. LTC2440 Normal Mode Rejection (Internal Oscillator)
Figure 13. LTC2440 Normal Mode Rejection (Internal Oscillator)
2440fd
20
LTC2440
APPLICATIONS INFORMATION
The sample rate f and NULL f , my also be adjusted by
Reduced Power Operation
S
N
driving the f pin with an external oscillator. The sample
O
In addition to adjusting the speed/resolution of the
LTC2440, the speed/resolution/power dissipation may
also be adjusted using the automatic sleep mode. During
the conversion cycle, the LTC2440 draws 8mA supply
current independent of the programmed speed. Once the
conversion cycle is completed, the device automatically
enters a low power sleep state drawing 8μA. The device
remains in this state as long as CS is HIGH and data is not
shifted out. By adjusting the duration of the sleep state
(hold CS HIGH longer) and the duration of the conversion
cycle (programming OSR) the DC power dissipation can
be reduced, see Figure 16.
rate is f = f
/5, where f
O
is the frequency of the
S
EOSC
EOSC
clock applied to f . Combining a large OSR with a reduced
sample rate leads to notch frequencies f near DC while
N
maintaining simple antialiasing requirements. A 100kHz
clock applied to f results in a NULL at 0.6Hz plus all
O
harmonics up to 20kHz, see Figure 14. This is useful in
applications requiring digitalization of the DC component
of a noisy input signal and eliminates the need of placing
a 0.6Hz filter in front of the ADC.
Anexternaloscillatoroperatingfrom100kHzto20MHzcan
be implemented using the LTC1799 (resistor set SOT-23
oscillator), see Figure 22. By floating pin 4 (DIV) of the
LTC1799, the output oscillator frequency is:
For example, if the OSR is programmed at the fastest rate
(OSR = 64, t
= 0.285ms) and the sleep state is 10ms,
CONV
the effective output rate is approximately 100Hz while the
average supply current is reduced to 240μA. By further
extending the sleep state to 100ms, the effective output
rate of 10Hz draws on average 30μA. Noise, power, and
speedcanbeoptimizedbyadjustingtheOSR(Noise/Speed)
and sleep mode duration (Power).
⎛
⎜
10k
⎝10•RSET
⎞
fOSC = 10MHz •
⎟
⎠
The normal mode rejection characteristic shown in Fig-
ure 14 is achieved by applying the output of the LTC1799
(with R = 100k) to the f pin on the LTC2440 with SDI
SET
O
tied HIGH (OSR = 32768).
0
–20
–40
–60
–80
–100
–120
–140
2
4
6
10
0
8
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2440 F14
Figure 14. LTC2440 Normal Mode Rejection
(External Oscillator at 90kHz)
2440fd
21
LTC2440
APPLICATIONS INFORMATION
CONVERTER
SLEEP
CONVERT
SLEEP
CONVERT
SLEEP
STATE
DATA
OUT
DATA
OUT
CS
SUPPLY
CURRENT
8μA
8mA
8μA
8μA
8mA
2440 F15
Figure 15. Reduced Power Timing Mode
When using the internal oscillator, f is 1.8MHz and the
LTC2440 Input Structure
SW
equivalent resistance is approximately 110kΩ.
Modern delta sigma converters have switched capacitor
front ends that repeatedly sample the input voltage over
sometimeperiod. Thesamplingprocessproducesasmall
current pulse at the input and reference terminals as the
capacitors are charged. The LTC2440 switches the input
and reference to a 5pF sample capacitor at a frequency
of 1.8MHz. A simplified equivalent circuit is shown in
Figure 16.
Driving the Input and Reference
Because of the small current pulses, excessive lead length
at the analog or reference input may allow reflections or
ringing to occur, affecting the conversion accuracy. The
key to preserving the accuracy of the LTC2440 is complete
settling of these sampling glitches at both the input and
reference terminals. There are several recommended
methods of doing this.
Theaverageinputandreferencecurrentscanbeexpressed
in terms of the equivalent input resistance of the sample
capacitor, where:
Req = 1/(f • Ceq)
SW
V
CC
I
+
+
REF
R
R
(TYP)
SW
I
I
LEAK
500Ω
V
REF
LEAK
V
CC
I
+
IN
(TYP)
500Ω
SW
I
I
LEAK
LEAK
V
+
IN
C
EQ
5pF
(TYP)
V
CC
(C = 3.5pF SAMPLE CAP + PARASITICS)
EQ
I
–
–
IN
R
R
(TYP)
SW
I
I
LEAK
LEAK
500Ω
V
IN
V
CC
I
–
–
REF
(TYP)
500Ω
SW
I
I
LEAK
LEAK
2440 F16
V
REF
SWITCHING FREQUENCY
f
f
= 1.8MHz INTERNAL OSCILLATOR
EOSC
SW
SW
= f
/5 EXTERNAL OSCILLATOR
Figure 16. LTC2440 Input Structure
2440fd
22
LTC2440
APPLICATIONS INFORMATION
Direct Connection to Low Impedance Sources
Buffering the LTC2440
Many applications will require buffering, particularly
where high impedance sources are involved or where the
device being measured is located some distance from the
LTC2440. When buffering the LTC2440 a few simple steps
should be followed.
If the ADC can be located physically close to the sensor,
it can be directly connected to sensors or other sources
with impedances up to 350Ω with no other components
required (see Figure 17).
4.5V to 5.5V
Figure19showsanetworksuitableforcouplingtheinputs
ofaLTC2440toaLTC2051chopper-stabilizedopamp. The
3μV offset and low noise of the LTC2051 make it a good
choice for buffering the LTC2440. Many other op amps
will work, with varying performance characteristics.
1μF
+
+
–
REF
IN
IN
LTC2440
–
The LTC2051 is configured to be able to drive the 1μF ca-
pacitors at the inputs of the LTC2440. The 1μF capacitors
should be located close to the ADC input pins.
REF
2440 F17
The measured total unadjusted error of Figure 19 is well
within the specifications of the LTC2440 by itself. Most
autozero amplifiers will degrade the overall resolution to
some degree because of the extremely low input noise
of the LTC2440, however the LTC2051 is a good general
purpose buffer. The measured input referred noise of two
LTC2051sbufferingbothLTC2440inputsisapproximately
double that of the LTC2440 by itself, which reduces the ef-
fectiveresolutionby1-bitforalloversampleratios.Adding
gain to the LTC2051 will increase gain and offset errors
and will not appreciably increase the overall resolution,
so it has limited benefit.
Figure 17. Direct Connection to Low Impedance (<350Ω) Source
is Possible if the Sensor is Located Close to the ADC.
Longer Connections to Low Impedance Sources
If longer lead lengths are unavoidable, adding an input
capacitor close to the ADC input pins will average the
charging pulses and prevent reflections or ringing (see
Figure 18). Averaging the current pulses results in a DC
input current that should be taken into account. The re-
sulting 110kΩ input impedance will result in a gain error
of 0.44% for a 350Ω bridge (within the full scale specs
of many bridges) and a very low 12.6ppm error for a 2Ω
thermocouple connection.
Procedure For Coupling Any Amplifier to the LTC2440
The LTC2051 is suitable for a wide range of DC and low
frequency measurement applications. If another ampli-
fier is to be selected, a general procedure for evaluating
the suitability of an amplifier for use with the LTC2440 is
suggested here:
4.5V to 5.5V
1μF
1μF
+
+
V
V
REF
CC
IN
IN
LTC2440
GND
1. Perform a thorough error and noise analysis on the
amplifier and gain setting components to verify that the
amplifier will perform as intended.
–
REMOTE
THERMOCOUPLE
1μF
2440 F18
2. Measure the large signal response of the overall circuit.
The capacitive load may affect the maximum slew rate of
the amplifier. Verify that the slew rate is adequate for the
Figure 18. Input Capacitors Allow Longer Connection
Between the Low Impedance Source and the ADC.
2440fd
23
LTC2440
APPLICATIONS INFORMATION
fastest expected input signal. Figure 20 shows the large
signal response of the circuit in Figure 19.
For more information on testing high linearity ADCs, refer
to Linear Technology Design Solutions 11.
3. Measure noise performance of the complete circuit. A
good technique is to build one amplifier for each input,
even if only one will be used in the end application. Bias
both amplifier outputs to midscale, with the inputs tied
together. Verify that the noise is as expected, taking into
account the bandwidth of the LTC2440 inputs for the OSR
being used, the amplifier’s broadband voltage noise and
1/f corner (if any) and any additional noise due to the
amplifier’s current noise and source resistance.
Input Bandwidth and Frequency Rejection
4
The combined effect of the internal SINC digital filter and
the digital and analog autocalibration circuits determines
theLTC2440inputbandwidthandrejectioncharacteristics.
The digital filter’s response can be adjusted by setting the
oversample ratio (OSR) through the SPI interface or by
supplying an external conversion clock to the f pin.
O
8-12V
5V
LT1236-5
4.7μF
0.01μF
10μF
15
V
CC
BUSY
14
+
5k
f
O
REF
LTC2440
–
R1
13
12
11
4
C1
0.1μF
SCK
SDO
CS
REF
0.01μF
–
+
10Ω
R2
5
6
+
IN
C2
7
–
IN+
IN
1μF
SDI
EXT
1
/
2
LTC2051HV
C4
1, 8, 9, 16
10
5k
R4
0.01μF
2440 F19
–
+
10Ω
R5
C5
IN–
1μF
1
/
2
LTC2051HV
C2, C5 TAIYO YUDEN JMK107BJ105MA
Figure 19. Buffering the LTC2440 from High Impedance Sources Using a Chopper Amplifier
5ns/DIV
100μs/DIV
2440 F21
2440 F20
Figure 20. Large Signal Input Settling Time Indicates
Completed Settling with Selected Load Capacitance.
Figure 21. Dynamic Input Current is Attenuated by Load
Capacitance and Completely Settled Before the Next Conversion
Sample Resulting in No Reduction in Performance.
2440fd
24
LTC2440
APPLICATIONS INFORMATION
Table 6 lists the properties of the LTC2440 with various
combinations of oversample ratio and clock frequency.
Understanding these properties is the key to fine tuning
the characteristics of the LTC2440 to the application.
the modulator sample rate of 1.8MHz) exceeds 120dB.
This is 8 times the maximum conversion rate.
Effective Noise Bandwidth
TheLTC2440hasextremelygoodinputnoiserejectionfrom
the first notch frequency all the way out to the modulator
sample rate (typically 1.8MHz). Effective noise bandwidth
is a measure of how the ADC will reject wideband input
noise up to the modulator sample rate. The example on
the following page shows how the noise rejection of the
LTC2440 reduces the effective noise of an amplifier driv-
ing its input.
Maximum Conversion Rate
The maximum conversion rate is the fastest possible rate
at which conversions can be performed.
First Notch Frequency
4
ThisisthefirstnotchintheSINC portionofthedigitalfilter
anddependsonthefoclockfrequencyandtheoversample
ratio. Rejection at this frequency and its multiples (up to
Table 6
Maximum Conversion Rate
Oversample
First Notch Frequency
Effective Noise BW
–3dB Point (Hz)
Internal
9MHz cloc
28125
Internal
External
fO
External
fO
Internal
External
fO
Internal
External
fO
Ratio
ADC
ENOB
(OSR)
Noise* (V = 5V)*
9MHz clock
k
9MHz clock
9MHz clock
1696
848
REF
64
23μV
3.5μV
2μV
17
3515.6
1757.8
878.9
439.5
219.7
109.9
54.9
f /2560
f /320
O
3148
1574
787
f /2850
f /5310
O
O
O
128
20
f /5120
O
14062.5
7031.3
3515.6
1757.8
878.9
439.5
219.7
109.9
54.9
f /640
f /5700
O
f /10600
O
O
256
21.3
21.8
22.4
22.9
23.4
24
f /10240
O
f /1280
O
f /11400
O
424
f /21200
O
512
1.4μV
1μV
f /20480
O
f /2560
O
394
f /22800
O
212
f /42500
O
1024
2048
4096
8192
16384
32768
f /40960
O
f /5120
O
197
f /45700
O
106
f /84900
O
750nV
510nV
375nV
250nV
200nV
f /81920
O
f /1020
O
98.4
49.2
24.6
12.4
6.2
f /91400
53
f /170000
O
O
f /163840
O
f /2050
O
f /183000
O
26.5
13.2
6.6
f /340000
O
27.5
f /327680
O
f /4100
O
f /366000
O
f /679000
O
24.4
24.6
13.7
f /655360
O
f /8190
O
f /731000
O
f /1358000
O
6.9
f /1310720
O
f /16380
O
f /1463000
O
3.3
f /2717000
O
*ADC noise increases by approximately √2 when OSR is decreased by a factor of 2 for OSR 32768 to OSR 256. The ADC noise at OSR 128 and OSR 64
include effects from internal modulator quantization noise.
2440fd
25
LTC2440
APPLICATIONS INFORMATION
Example:
The total noise is the RMS sum of this noise with the
200nV noise of the ADC at OSR = 32768.
Ifanamplifier(e.g.LT1219)drivingtheinputofanLTC2440
haswidebandnoiseof33nV/√Hz, band-limitedto1.8MHz,
the total noise entering the ADC input is:
2
2
√82nV + 2μV = 216nV.
In this way, the digital filter with its variable oversampling
ratio can greatly reduce the effects of external noise
sources.
33nV/√Hz • √1.8MHz = 44.3μV.
When the ADC digitizes the input, its digital filter filters
out the wideband noise from the input signal. The noise
reduction depends on the oversample ratio which defines
the effective bandwidth of the digital filter.
Using Non-Autozeroed Amplifiers for Lowest Noise
Applications
Ultralow noise applications may require the use of low
noise bipolar amplifiers that are not autozeroed. Because
the LTC2440 has such exceptionally low offset, offset drift
and 1/f noise, the offset drift and 1/f noise in the ampli-
fiers may need to be compensated for to retain the system
performance of which the ADC is capable.
At an oversample of 256, the noise bandwidth of the ADC
is 787Hz which reduces the total amplifier noise to:
33nV/√Hz • √787Hz = 0.93μV.
The total noise is the RMS sum of this noise with the 2μV
noise of the ADC at OSR=256.
The circuit of Figure 23 uses low noise bipolar amplifiers
and correlated double sampling to achieve a resolution of
14nV,or19effectivebitsovera10mVspan.Eachmeasure-
ment is the difference between two ADC readings taken
with opposite polarity bridge excitation. This cancels 1/f
noise below 3.4Hz and eliminates errors due to parasitic
thermocouples. Allow 750μs settling time after switching
excitation polarity.
2
2
√0.93μ/V + 2μV = 2.2μV.
Increasing the oversampling ratio to 32768 reduces the
noise bandwidth of the ADC to 6.2Hz which reduces the
total amplifier noise to:
33nV/√Hz • √6.2Hz = 82nV.
2440fd
26
LTC2440
PACKAGE DESCRIPTION
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ± .0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
TYPICAL APPLICATIONS
4.5V TO 5.5V
1μF
2
15
V
BUSY
CC
LTC1799
R
LTC2440
SET
50Ω
5
4
1
2
14
13
12
11
3
+
+
f
V
REF
OUT
O
REFERENCE VOLTAGE
0.1V TO V
4
5
6
–
CC
SCK
SDO
CS
REF
0.1μF
3-WIRE
SPI INTERFACE
+
IN
ANALOG INPUT RANGE
GND
SET
–0.5V
TO 0.5V
–
REF
REF
IN
7
V
CC
SDI
3
1, 8, 9, 16
10
NC
DIV
GND
EXT
2440 TA05
Figure 22. Simple External Clock Source
2440fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC2440
TYPICAL APPLICATION
V
REF
100k
3
V
+7V
REF
4
TOP_P
TOP_N
5,6,7,8
LT1461-5
10μF
0.1μF
2
+
10Ω
1
100k
2X LT1677
+
–
4
REF
0.047μF
1k 0.1%
+
IN
IN
1μF
1μF
LTC2440
100Ω 0.1%
1k 0.1%
10Ω
–
–
0.047μF
REF
–
+
V
REF
100k
4
3
2440 F22
BOTTOM_P
2X SILICONIX SI9801
BOTTOM_N
5,6,7,8
2
1
100k
Figure 23. Bridge Reversal Eliminates 1/f Noise and Offset Drift of a Low Noise, Non-Autozeroed,
Bipolar Amplifier. Circuit Gives 14nV Noise Level or 19 Effective Bits over a 10mV Span
RELATED PARTS
PART NUMBER
LT1025
DESCRIPTION
COMMENTS
Micropower Thermocouple Cold Junction Compensator
80μA Supply Current, 0.5°C Initial Accuracy
Precise Charge, Balanced Switching, Low Power
LTC1043
Dual Precision Instrumentation Switched Capacitor
Building Block
LTC1050
LT1236A-5
LT1461
Precision Chopper Stabilized Op Amp
Precision Bandgap Reference, 5V
Micropower Series Reference, 2.5V
Ultraprecise 16-Bit SoftSpanTM DAC
16-Bit Rail-to-Rail Micropower DAC
Resistor Set SOT-23 Oscillator
No External Components 5μV Offset, 1.6μV Noise
P-P
0.05% Max, 5ppm/°C Drift
0.04% Max, 3ppm/°C Max Drift
Six Programmable Output Ranges
1LSB DNL, 600μA, Internal Reference, SO-8
Single Resistor Frequency Set
LTC1592
LTC1655
LTC1799
LTC2053
LTC2400
Rail-to-Rail Instrumentation Amplifier
24-Bit, No Latency Δ∑ ADC in SO-8
10μV Offset with 50nV/°C Drift, 2.5μV Noise 0.01Hz to 10Hz
P-P
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA
0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA
LTC2401/LTC2402 1-/2-Channel, 24-Bit, No Latency Δ∑ ADC in MSOP
LTC2404/LTC2408 4-/8-Channel, 24-Bit, No Latency Δ∑ ADC
LTC2410/LTC2413 24-Bit, No Latency Δ∑ ADC
800nV
Noise, 5ppm INL/Simultaneous 50Hz/60Hz Rejection
Noise, 6ppm INL
RMS
LTC2411
24-Bit, No Latency Δ∑ ADC in MSOP
1.45μV
RMS
LTC2420LTC2424/ 1-/4-/8-Channel, 20-Bit, No Latency Δ∑ ADCs
LTC2428
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400/
LTC2404/LTC2408
SoftSpan is a trademark of Linear Technology Corporation.
2440fd
LT 1008 REV D • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
© LINEAR TECHNOLOGY CORPORATION 2002
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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