LTC2461CDDPBF_技术文档

LTC2461/LTC2463

2

Ultra-Tiny, 16-Bit I C ΔΣ

ADCs with 10ppm/°C Max

Precision Reference

FEATURES

DESCRIPTION

The LTC^®2461/LTC2463 are ultra tiny, 16-Bit analog-to-

digital converters with an integrated precision reference.

They use a single 2.7V to 5.5V supply and communicate

through an I²C Interface. The LTC2461 is single-ended

with a 0V to 1.25V input range and the LTC2463 is dif-

ferential with a 1.25V input range. Both ADCs include a

1.25V integrated reference with 2ppm/°C drift perfor-

mance and 0.1% initial accuracy. The converters are

available in a 12-pin 3mm × 3mm DFN package or an

MSOP-12 package. They include an integrated oscillator

and perform conversions with no latency for multiplexed

applications. TheLTC2461/LTC2463includeaproprietary

input sampling scheme that reduces the average input

current several orders of magnitude when compared to

conventional delta sigma converters.

n

16-Bit Resolution, No Missing Codes

n

Internal Reference, High Accuracy 10ppm/°C (Max)

n

Single-Ended (LTC2461) or Differential (LTC2463)

n

2LSB Offset Error (Typ)

n

0.01% Gain Error (Typ)

n

60 Conversions Per Second

n

Single Conversion Settling Time for Multiplexed

Applications

n

1.5mA Supply Current

n

200nA Sleep Current

n

Internal Oscillator—No External Components

Required

2

n

2-Wire I C Interface with Two Addresses Plus One

Global Address for Synchronization

n

Ultra-Tiny, 12-Lead, 3mm × 3mm DFN and MSOP

Packages

Following a single conversion, the LTC2461/LTC2463

automatically power down the converter and can also be

conﬁgured to power down the reference. When both the

ADC and reference are powered down, the supply current

is reduced to 200nA.

APPLICATIONS

n

System Monitoring

n

Environmental Monitoring

n

Direct Temperature Measurements

The LTC2461/LTC2463 can sample at 60 conversions per

second and, due to the very large oversampling ratio,

have extremely relaxed antialiasing requirements. Both

includecontinuousinternaloffsetandfullscalecalibration

algorithmswhicharetransparenttotheuser, ensuringac-

curacy over time and the operating temperature range.

n

Instrumentation

Data Acquisition

Embedded ADC Upgrades

n

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 6208279, 6411242, 7088280, 7164378.

TYPICAL APPLICATION

V_REFvs Temperature

1.2520

2.7V TO 5.5V

1.2515

1.2510

1.2505

1.2500

1.2495

1.2490

1.2485

1.2480

0.1μF

COMP

0.1μF

10μF

0.1μF

10k

REFOUT

V

CC

SCL

SDA

GND

+

–

IN

2

10k

I C

INTERFACE

LTC2463

A0

IN

0.1μF

–

REF

R

24613 TA01a

–50 –30 –10 10

30

50

70

90

TEMPERATURE (°C)

24613 TA01b

24613f

1

LTC2461/LTC2463

ABSOLUTE MAXIMUM RATINGS

(Notes 1, 2)

Supply Voltage (V ) ................................... –0.3V to 6V

Storage Temperature Range .................. –65°C to 150°C

Operating Temperature Range

CC

Analog Input Voltage

+

–

(V , V , V , V ,

IN REF

LTC2461C/LTC2463C............................... 0°C to 70°C

LTC2461I/LTC2463I .............................–40°C to 85°C

IN

V

, V

)...........................–0.3V to (V + 0.3V)

COMP REFOUT CC

Digital Voltage

(V , V , V )..........................–0.3V to (V + 0.3V)

SDA SCL A0

CC

PIN CONFIGURATION

LTC2463

TOP VIEW

1

2

3

4

5

6

V

12

CC

REFOUT

COMP

A0

1

2

3

4

5

6

REFOUT

COMP

A0

12 V

CC

11 GND

–

11 GND

IN

10

9

–

10 IN

13

+

GND

SCL

GND

SCL

SDA

9

8

7

IN

–

REF

8

REF

GND

7

GND

SDA

MS PACKAGE

12-LEAD PLASTIC MSOP

DD PACKAGE

12-LEAD (3mm s 3mm) PLASTIC DFN

T

JMAX

= 125°C, θ = 135°C/W

T

= 125°C, θ = 43°C/W

JA

JMAX

EXPOSED PAD (PIN 13)

LTC2461

TOP VIEW

1

12

V

CC

REFOUT

COMP

A0

1

2

3

4

5

6

REFOUT

COMP

A0

12 V

CC

11 GND

10 GND

2

3

4

5

6

11 GND

GND

IN

10

9

13

GND

SCL

GND

SCL

SDA

9

8

7

IN

REF

GND

–

REF

8

7

GND

SDA

MS PACKAGE

12-LEAD PLASTIC MSOP

DD PACKAGE

12-LEAD (3mm s 3mm) PLASTIC DFN

T

JMAX

= 125°C, θ = 135°C/W

T

= 125°C, θ = 43°C/W

JA

JMAX

EXPOSED PAD (PIN 13)

ORDER INFORMATION

LEAD FREE FINISH

LTC2461CDD#PBF

LTC2461IDD#PBF

LTC2461CMS#PBF

LTC2461IMS#PBF

LTC2463CDD#PBF

LTC2463IDD#PBF

LTC2463CMS#PBF

LTC2463IMS#PBF

TAPE AND REEL

PART MARKING*

LFGF

PACKAGE DESCRIPTION

TEMPERATURE RANGE

0°C to 70°C

LTC2461CDD#TRPBF

LTC2461IDD#TRPBF

LTC2461CMS#TRPBF

LTC2461IMS#TRPBF

LTC2463CDD#TRPBF

LTC2463IDD#TRPBF

LTC2463CMS#TRPBF

LTC2463IMS#TRPBF

12-Lead Plastic (3mm × 3mm) DFN

12-Lead Plastic MSOP

LFGF

–40°C to 85°C

0°C to 70°C

2461

12-Lead Plastic MSOP

–40°C to 85°C

0°C to 70°C

LFGG

12-Lead Plastic (3mm × 3mm) DFN

12-Lead Plastic MSOP

LFGG

–40°C to 85°C

0°C to 70°C

2463

12-Lead Plastic MSOP

–40°C to 85°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

24613f

2

LTC2461/LTC2463

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. (Note 2)

PARAMETER

CONDITIONS

(Note 3)

MIN

TYP

MAX

UNITS

Bits

l

Resolution (No Missing Codes)

Integral Nonlinearity

Offset Error

16

(Note 4)

1

8

LSB

LTC2461, 30Hz, LTC2463

LTC2461, 60Hz

2

5

15

LSB

Offset Error Drift

Gain Error

0.02

0.01

LSB/°C

l

Includes Contributions of ADC and Internal Reference

0.25 % of FS

Gain Error Drift

Includes Contributions of ADC and Internal Reference

C-Grade

I-Grade

2

5

10

ppm/°C

Transition Noise

2.2

80

μV

RMS

Power Supply Rejection DC

dB

The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise

ANALOG INPUTS

speciﬁcations are at T_A= 25°C.

SYMBOL

PARAMETER

CONDITIONS

LTC2463

MIN

0

TYP

MAX

UNITS

V

+

l

V

C

Positive Input Voltage Range

Negative Input Voltage Range

Input Voltage Range

V

REF

V

REF

V

REF

IN

–

LTC2463

0

V

LTC2461

0

V

+

–

+

–

+

–

, V

UR

, V

UR

Overrange/Underrange Voltage, IN

V

IN

V

IN

= 0.625V (See Figure 3)

8

LSB

pF

OR

IN

+

Overrange/Underrange Voltage, IN–

+

–

IN , IN , IN Sampling Capacitance

0.35

+

–

l

+

–

I

IN , IN DC Leakage Current (LTC2463)

IN DC Leakage Current (LTC2461)

V

IN

V

IN

= GND or V (Note 8)

–10

1

10

nA

DC_LEAK(IN , IN , IN)

CC

= GND or V (Note 8)

CC

I

Input Sampling Current (Note 5)

REFOUT Output Voltage

50

nA

V

CONV

l

V

1.247

1.25

1.253

10

REF

REFOUT Voltage Temperature Coefﬁcient (Note 9)

C-Grade

I-Grade

2

5

ppm/°C

Reference Line Regulation

2.7V ≤ V ≤ 5.5V

–90

dB

mA

CC

l

Reference Short Circuit Current

COMP Pin Short Circuit Current

Reference Load Regulation

Reference Output Noise Density

V

CC

V

CC

= 5.5, Forcing REFOUT to GND

35

= 5.5, Forcing REFOUT to GND

200

μA

2.7V ≤ V ≤ 5.5V, I

= 100ꢀA Sourcing

= 0.1ꢀF, At f = 1kHz

3.5

30

mV/mA

nV/√Hz

CC

OUT

C = 0.1ꢀF, C

COMP REFOUT

The l denotes the speciﬁcations which apply over the full operating temperature

POWER REQUIREMENTS

range, otherwise speciﬁcations are at T_A= 25°C.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Supply Voltage

2.7

5.5

V

CC

I

Supply Current

Conversion

Nap

CC

l

1.5

800

0.2

2.5

1500

2

mA

μA

Sleep

24613f

3

LTC2461/LTC2463

I²C INPUTS AND OUTPUTS

The l denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at T_A= 25°C. (Notes 2, 7)

SYMBOL

PARAMETER

CONDITIONS

MIN

0.7V

TYP

MAX

UNITS

V

l

V

High Level Input Voltage

IH

IL

CC

Low Level Input Voltage

0.3V

10

V

CC

I

Digital Input Current

–10

μA

V

I

V

Hysteresis of Schmidt Trigger Inputs

Low Level Output Voltage (SDA)

Input Leakage

(Note 3)

I = 3mA

0.05V

HYS

OL

CC

0.4

1

V

I

0.1V ≤ V ≤ 0.9V

CC

μA

pF

V

IN

CC

IN

C

V

Capacitance for Each I/O Pin

Capacitance Load for Each Bus Line

High Level Input Voltage for Address Pin

Low Level Input Voltage for Address Pin

10

I

400

B

0.95V

IH(A0)

IL(A0)

CC

0.05V

V

CC

I²C TIMING CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

temperature range, otherwise speciﬁcations are at T_A= 25°C. (Notes 2, 7)

SYMBOL

PARAMETER

CONDITIONS

MIN

13

TYP

MAX

23

UNITS

ms

kHz

μs

l

t

f

t

Conversion Time

16.6

CONV

SCL

SCL Clock Frequency

0

400

Hold Time (Repeated) START Condition

LOW Period of the SCL Pin

HIGH Period of the SCL Pin

Set-Up Time for a Repeated START Condition

Data Hold Time

0.6

HD(SDA,STA)

LOW

1.3

μs

0.6

μs

HIGH

0.6

μs

SU(STA)

HD(DAT)

SU(DAT)

r

0

0.9

μs

Data Set-Up Time

100

ns

Rise Time for SDA, SCL Signals

Fall Time for SDA, SCL Signals

Set-Up Time for STOP Condition

Bus Free Time Between a Stop and Start Condition

(Note 6)

20 + 0.1C

0.6

300

ns

B

ns

f

B

μs

SU(STO)

BUF

1.3

μs

Output Fall Time V

to V

Bus Load C = 10pF to

20 + 0.1C

250

50

ns

OF

IHMIN

ILMAX

B

400pF (Note 6)

l

t

SP

Input Spike Suppression

ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 5: Input sampling current is the average input current drawn from

the input sampling network while the LTC2461/LTC2463 are converting.

Note 6: C = capacitance of one bus line in pF.

B

Note 7: All values refer to V

) and V

levels.

IH(MIN

IL(MAX)

Note 2: All voltage values are with respect to GND. V = 2.7V to 5.5V

CC

Note 8: A positive current is ﬂowing into the DUT pin.

Note 9: Voltage temperature coefﬁcient is calculated by dividing the

maximum change in output voltage by the speciﬁed temperature range.

unless otherwise speciﬁed.

Note 3: Guaranteed by design, not subject to test.

Note 4: Integral nonlinearity is deﬁned as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

Guaranteed by design and test correlation.

24613f

4

LTC2461/LTC2463

TYPICAL PERFORMANCE CHARACTERISTICS (T_A= 25°C, unless otherwise noted)

Integral Nonlinearity (V_CC= 5.5V)

Integral Nonlinearity (V_CC= 2.7V)

INL vs Temperature

3

2

3

2

3

2

V

= 5.5V, 4.1V, 2.7V

T

= –45°C, 25°C, 90°C

T = –45°C, 25°C, 90°C

A

CC

A

1

0

–1

–2

–3

–1

–2

–3

–1

–2

–3

–1.25

–0.75

–0.25

0.25

0.75

1.25

–1.25

–0.75

–0.25

0.25

0.75

1.25

–55 –35 –15

5

25 45 65 85 105 125

DIFFERENTIAL INPUT VOLTAGE (V)

TEMPERATURE (°C)

24613 G03

24613 G01

24613 G02

Offset Error vs Temperature

ADC Gain Error vs Temperature

Transition Noise vs Temperature

25

20

15

10

5

10

9

8

7

6

5

4

3

2

1

0

5

4

V

= 5.5V

CC

V

= 5.5V

CC

3

2

V

= 4.1V

CC

1

V

= 2.7V

0

CC

–1

–2

–3

–4

–5

V

= 4.1V

= 2.7V

CC

V

= 2.7V

= 5.5V

30

CC

V

CC

0

–50

–25

0

25

50

75

100

–50 –30 –10 10

50

70

90

–50 –30 –10 10

30

50

70

90

TEMPERATURE (°C)

24613 G05

24613 G06

24613 G04

Conversion Mode Power Supply

Current vs Temperature

Sleep Mode Power Supply

Current vs Temperature

V

_REFvs Temperature

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

350

300

250

200

150

100

50

1.2508

1.2507

1.2506

1.2505

1.2504

1.2503

1.2502

= 5V

CC

V

= 5.5V

CC

V

= 5.5V

CC

V

= 4.1V

CC

V

= 2.7V

V

= 4.1V

CC

V

= 2.7V

30

CC

0

–50 –30 –10 10

30

50

70

90

–50 –30 –10 10

50

70

90

–50 –30 –10 10

30

50

70

90

TEMPERATURE (°C)

24613 G07

24613 G08

24613 G09

24613f

5

LTC2461/LTC2463

TYPICAL PERFORMANCE CHARACTERISTICS (T_A= 25°C, unless otherwise noted)

Power Supply Rejection

vs Frequency at V_CC

Conversion Time vs Temperature

V_REFvs V_CC

0

–20

21

20

19

18

17

16

15

14

1.24892

1.24891

1.24890

1.24889

1.24888

1.24887

1.24886

1.24885

1.24884

T

= 25°C

CC

T

= 25°C

A

V

= 4.1V

–40

V

= 5V, 4.1V, 3V

CC

–60

–80

–100

–120

1

10 100 1k 10k 100k 1M 10M

–50

–25

0

25

50

75

100

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

FREQUENCY AT V (Hz)

CC

TEMPERATURE (°C)

V

CC

(V)

24613 G10

24613 G11

24613 G12

24613f

6

LTC2461/LTC2463

PIN FUNCTIONS

2

REFOUT (Pin 1): Reference Output Pin. Nominally 1.25V,

this voltage sets the fullscale input range of the ADC. For

noise and reference stability connect to a 0.1μF capacitor

tied to GND. This capacitor value must be less than or

equal to the capacitor tied to the reference compensation

pin (COMP). REFOUT cannot be overdriven by an external

reference. For applications that require an input range

greater than 0V to 1.25V, please refer to the LTC2451/

LTC2453.

SDA (Pin 6): Bidirectional Serial Data Line of the I C Inter-

face. The conversion result is output through the SDA pin.

The pin is high impedance unless the LTC2461/LTC2463

is in the data output mode. While the LTC2461/LTC2463

is in the data output mode, SDA is an open drain pull

down (which requires an external 1.7k pull-up resistor

to V ).

CC

–

REF (Pin 8): Negative Reference Input to the ADC. The

voltage on this pin sets the zero input to the ADC. This

pin should tie directly to ground or the ground sense of

the input sensor.

COMP (Pin 2): Internal Reference Compensation Pin. For

low noise and reference stability, tie a 0.1ꢀF capacitor to

GND.

+

IN (LTC2463), IN (LTC2461) (Pin 9): Positive input volt-

age for the LTC2463 differential device. ADC input for the

LTC2461 single-ended device.

A0 (Pin 3): Chip Address Control Pin. The A0 pin can be

tied to GND or V . If A0 is tied to GND, the LTC2461/

CC

2

LTC2463 I C address is 0010100. If A0 is tied to V , the

–

CC

IN (LTC2463), GND (LTC2461) (Pin 10): Negative input

voltage for the LTC2463 differential device. GND for the

LTC2461 single-ended device.

2

LTC2461/LTC2463 I C address is 1010100.

GND (Pins 4, 7, 11): Ground. Connect directly to the

ground plane through a low impedance connection.

V

CC

(Pin12):PositiveSupplyVoltage. BypasstoGNDwith

2

SCL (Pin 5): Serial Clock Input of the I C Interface. The

a 10ꢀF capacitor in parallel with a low-series-inductance

LTC2461/LTC2463 can only act as a slave and the SCL pin

only accepts external serial clock. Data is shifted into the

SDA pin on the rising edges of SCL and output through

the SDA pin on the falling edges of SCL.

0.1ꢀF capacitor located as close to pin 12 as possible.

Exposed Pad (Pin 13 – DFN Package): Ground. Connect

directly to the ground plane through a low impedance

connection.

24613f

7

LTC2461/LTC2463

BLOCK DIAGRAM

1

2

12

REFOUT

COMP

V

CC

2

3

5

6

INTERNAL

A0

SCL

SDA

$3 A/D

CONVERTER

I C

REFERENCE

9

+

INTERFACE

IN

(IN)

DECIMATING

SINC FILTER

–

$3 A/D

CONVERTER

10

–

IN

INTERNAL

OSCILLATOR

(GND)

–

REF

GND

4, 7, 11, 13 (DD PACKAGE)

8

24613 BD

( ) PARENTHESIS INDICATE LTC2461

Figure 1. Functional Block Diagram

APPLICATIONS INFORMATION

CONVERTER OPERATION

POWER-ON RESET

CONVERT

Converter Operation Cycle

The LTC2461/LTC2463 are low power, delta sigma, ana-

2

SLEEP/NAP

log to digital converters with a simple I C interface (see

Figure 1). The LTC2463 has a fully differential input while

the LTC2461 is single-ended. Both are pin and software

compatible. Their operation is composed of three distinct

states: CONVERT, SLEEP/NAP, and DATA INPUT/OUTPUT

(see Figure 2). The operation begins with the CONVERT

state. Once the conversion is ﬁnished, the converter auto-

matically powers down (NAP) or, under user control, both

the converter and reference are powered down (SLEEP).

The conversion result is held in a static register while the

device is in this state. The cycle concludes with the DATA

INPUT/OUTPUT state. Once all 16-bits are read the device

begins a new conversion.

READ/WRITE

NO

ACKNOWLEDGE

YES

DATA INPUT/OUTPUT

STOP

OR

READ 16 BITS

NO

YES

24613 F02

TheCONVERTstatedurationisdeterminedbytheLTC2461/

LTC2463 conversion time (nominally 16.6 milliseconds).

Oncestarted, thisoperationcannotbeabortedexceptbya

Figure 2. LTC2461/LTC2463 State Transition Diagram

low power supply condition (V < 2.1V) which generates

CC

read/write is acknowledged. Following this condition, the

ADC transitions into the DATA INPUT/OUTPUT state.

an internal power-on reset signal.

Afterthecompletionofaconversion,theLTC2461/LTC2463

enterstheSLEEP/NAPstateandremainsthereuntilavalid

While in the SLEEP/NAP state, the LTC2461/LTC2463’s

converters are powered down. This reduces the supply

24613f

8

LTC2461/LTC2463

APPLICATIONS INFORMATION

current by approximately 50%. While in the Nap state,

the reference remains powered up. To power down the

reference in addition to the converter, the user can select

the SLEEP mode during the DATA INPUT/OUTPUT state.

Once the next conversion is complete, SLEEP state is

entered and power is reduced to 200nA. The reference

is powered up once a valid read/write is acknowledged.

The reference startup time is 12ms (if the reference and

compensation capacitor values are both 0.1ꢀF).

The LTC2461/LTC2463 perform offset calibrations every

conversion cycle. This calibration is transparent to the

user and has no effect upon the cyclic operation described

previously. The advantage of continuous calibration is

stability of the ADC performance with respect to time and

temperature.

TheLTC2461/LTC2463includeaproprietaryinputsampling

scheme that reduces the average input current by several

orders of magnitude when compared to traditional delta-

sigma architectures. This allows external ﬁlter networks

to interface directly to the LTC2461/LTC2463. Since the

average input sampling current is 50nA, an external RC

lowpass ﬁlter using 1kΩ and 0.1μF results in <1LSB

additional error. Additionally, there is negligible leakage

Power-Up Sequence

When the power supply voltage (V ) applied to the con-

CC

verter is below approximately 2.1V, the ADC performs a

power-on reset. This feature guarantees the integrity of

the conversion result.

+

–

current between IN and IN .

WhenV risesabovethiscriticalthreshold, theconverter

CC

Input Voltage Range (LTC2461)

generates an internal power-on reset (POR) signal for

approximately 0.5ms. The POR signal clears all internal

registers.FollowingthePORsignal,theLTC2461/LTC2463

startaconversioncycleandfollowthesuccessionofstates

shown in Figure 2. The reference startup time following a

Ignoring offset and full-scale errors, the LTC2461 will

theoretically output an “all zero” digital result when the

input is at ground (a zero scale input) and an “all one”

digital result when the input is at V (V

= 1.25V).

REF REFOUT

In an underrange condition, for all input voltages below

zeroscale,theconverterwillgeneratetheoutputcode0.In

an overrange condition, for all input voltages greater than

POR is 12ms (C

= C

= 0.1ꢀF). The ﬁrst conver-

COMP

REFOUT

sion following power-up will be invalid since the reference

voltage has not completely settled. The ﬁrst conversion

following power up can be discarded using the data abort

command or simply read and ignored. The following con-

versions are accurate to the device speciﬁcations.

V

, the converter will generate the output code 65535.

REF

For applications that require an input range greater than

0V to 1.25V, please refer to the LTC2451.

Input Voltage Range (LTC2463)

Ease of Use

AsmentionedintheOutputDataFormatsection,theoutput

The LTC2461/LTC2463 data output has no latency, ﬁlter

settling delay or redundant results associated with the

conversion cycle. There is a one-to-one correspondence

between the conversion and the output data. Therefore,

multiplexing multiple analog input voltages requires no

special actions.

+

–

code is given as 32768 • (V – V )/V + 32768. For

IN

REF

+

–

(V – V ) ≥ V , the output code is clamped at 65535

(all ones). For (V – V ) ≤ –V , the output code is

IN

REF

IN

+

–

IN

REF

clamped at 0 (all zeroes).

The LTC2463 includes a proprietary architecture that

can, typically, digitize each input up to 8 LSBs above

24613f

9

LTC2461/LTC2463

APPLICATIONS INFORMATION

2

V

and below GND, if the differential input is within

REF

the data line is free, it is HIGH. Data on the I C bus can be

REF

V

. As an example (Figure 3), if the user desires to

transferredatratesupto100kbits/sintheStandard-Mode

and up to 400kbits/s in the Fast-Mode.

measure a signal slightly below ground, the user could

–

+

set V = GND. If V = GND, the output code would be

IN

UponenteringtheDATAINPUT/OUTPUTstate,SDAoutputs

the sign (D15) of the conversion result. During this state,

the ADC shifts the conversion result serially through the

SDA output pin under the control of the SCL input pin.

There is no latency in generating this data and the result

corresponds to the last completed conversion. A new bit

of data appears at the SDA pin following each falling edge

detectedattheSCLinputpinandappearsfromMSBtoLSB.

The user can reliably latch this data on every rising edge

of the external serial clock signal driving the SCL pin.

+

approximately32768.IfV = GND –8LSB =–0.305mV,

IN

the output code would be approximately 32760. For ap-

plications that require an input range greater than 1.25V,

please refer to the LTC2453.

20

16

12

8

4

0

2

Each device on the I C bus is recognized by a unique

–4

address stored in that device and can operate either as

a transmitter or receiver, depending on the function of

the device. In addition to transmitters and receivers,

devices can also be considered as masters or slaves when

performing data transfers. A master is the device which

initiates a data transfer on the bus and generates the

clock signals to permit that transfer. Devices addressed

by the master are considered a slave. The address of the

LTC2461/LTC2463 is 0010100 (if A0 is tied to GND) or

SIGNALS

–8

BELOW

GND

–12

–16

–20

–0.001 –0.005

0

V

0.005 0.001 0.0015

+

/V

IN REF

24613 F03

Figure 3. Output Code vs V_IN⁺with V_IN^–= 0 (LTC2463)

2

I C INTERFACE

1010100 (if A0 is tied to V ).

2

CC

The LTC2461/LTC2463 communicate through an I C in-

terface. The I C interface is a 2-wire open-drain interface

supporting multiple devices and masters on a single bus.

The connected devices can only pull the data line (SDA)

LOW and can never drive it HIGH. SDA must be externally

connected to the supply through a pull-up resistor. When

2

The LTC2461/LTC2463 can only be addressed as a slave.

It can only transmit the last conversion result. The serial

clockline,SCL,isalwaysaninputtotheLTC2461/LTC2463

andtheserialdatalineSDAisbidirectional.Figure4shows

2

the deﬁnition of the I C timing.

SDA

t

SU(DAT)

t

r

t

f

t

BUF

t

f

HD(SDA)

SP

LOW

SCL

t

SU(STO)

HD(STA)

SU(STA)

t

HIGH

S

Sr

P

S

HD(DAT)

24613 F04

Figure 4. Deﬁnition of Timing for Fast/Standard Mode Devices on the I²C Bus

24613f

10

LTC2461/LTC2463

APPLICATIONS INFORMATION

The START and STOP Conditions

Output Data Format

After a START condition, the master sends a 7-bit address

followed by a read request (R) bit. The bit R is 1 for a

Read Request. If the 7-bit address matches the LTC2461/

LTC2463’saddress(0010100or1010100,dependingonthe

state of the pin A0) the ADC is selected. When the device is

addressed during the conversion state, it does not accept

therequestandissuesaNAKbyleavingtheSDAlineHIGH.

If the conversion is complete, the LTC2461/LTC2463 issue

an ACK by pulling the SDA line LOW.

A START (S) condition is generated by transitioning SDA

from HIGH to LOW while SCL is HIGH. The bus is consid-

ered to be busy after the START condition. When the data

transfer is ﬁnished, a STOP (P) condition is generated by

transitioning SDA from LOW to HIGH while SCL is HIGH.

ThebusisfreeafteraSTOPisgenerated.STARTandSTOP

conditions are always generated by the master.

When the bus is in use, it stays busy if a repeated START

(Sr)isgeneratedinsteadofaSTOPcondition.Therepeated

START timing is functionally identical to the START and

is used for reading from the device before the initiation

of a new conversion.

FollowingtheACK, theLTC2461/LTC2463canoutputdata.

The data output stream is 16 bits long and is shifted out

on the falling edges of SCL (see Figure 5a).

The DATA INPUT/OUTPUT state is concluded once all 16

data bits have been read or after a STOP condition.

Data Transferring

2

After the START condition, the I C bus is busy and data

The LTC2463 (differential input) output code is given by

transfer can begin between the master and the addressed

slave. Data is transferred over the bus in groups of nine

bits, one byte followed by one acknowledge (ACK) bit. The

master releases the SDA line during the ninth SCL clock

cycle. The slave device can issue an ACK by pulling SDA

LOW or issue a Not Acknowledge (NAK) by leaving the

SDA line HIGH impedance (the external pull-up resistor

will hold the line HIGH). Change of data only occurs while

the clock line (SCL) is LOW.

+

–

32768 • (V – V )/V

+ 32768. The ﬁrst bit output

IN

REF

+

by the LTC2463, D15, is the MSB, which is 1 for V

≥

IN

–

+

–

V

and 0 for V < V . This bit is followed by succes-

IN

IN IN

sively less signiﬁcant bits (D14, D13, …) until the LSB is

output by the LTC2463, see Table 1.

1

7

8

9

1

2

3

8

9

1

2

3

8

9

SCL

SDA

7-BIT

ADDRESS

R

D15

D14

D13

D8

D7

D6

D5

D0

MSB

LSB

START BY

MASTER

ACK BY

LTC2461/LTC2463

ACK BY

MASTER

NACK BY

MASTER

SLEEP

DATA OUTPUT

CONVERSION

24613 F05a

Figure 5a. Read Sequence Timing Diagram

24613f

11

LTC2461/LTC2463

APPLICATIONS INFORMATION

The LTC2461 (single-ended input) output code is a direct

binary encoded result, see Table 1.

The speed bit (SPD) is only used by the LTC2461. In the

default mode, SPD = 0, the output rate is 60Hz and con-

tinuousbackgroundoffsetcalibrationisnotperformed.By

changing the SPD bit to 1, background offset calibration

is performed and the output rate is reduced to 30Hz. The

LTC2463 data output rate is always 60Hz and background

offset calibration is performed (SPD = don’t care).

Data Input Format

After a START condition, the master sends a 7-bit ad-

dress followed by a read/write request (R/W) bit. The

R/W bit is 0 for a write. The data input word is 4 bits long

and consists of two enable bits (EN1 and EN2) and two

programming bits (SPD and SLP), see Figure 5b. EN1 is

applied to the ﬁrst rising edge of SCL after a valid write

address is acknowledged. Programming is enabled by

setting EN1 = 1 and EN2 = 0.

The sleep bit (SLP) is used to power down the on chip

reference. In the default mode, the reference remains

powered up even when the ADC is powered down. If the

SLP bit is set HIGH, the reference will power down after

Table 1. LTC2461/LTC2463 Output Data Format

SINGLE ENDED INPUT V

(LTC2461)

DIFFERENTIAL INPUT VOLTAGE

D15

(MSB)

D14

D13

D12...D2

D1

D0

(LSB)

CORRESPONDING

DECIMAL VALUE

IN

+

–

V

– V (LTC2463)

IN

≥V

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

65535

65534

49152

49151

32768

32767

16384

16383

0

REF

V

– 1LSB

V

– 1LSB

REF

0.75 • V

0.5 • V

REF

0.75 • V – 1LSB

0.5 • V – 1LSB

REF

0.5 • V

0

REF

0.5 • V – 1LSB

–1LSB

REF

0.25 • V

–0.5 • V

REF

0.25 • V – 1LSB

–0.5 • V – 1LSB

REF

0

≤ –V

REF

1

2

…

7

8

9

1

2

3

4

5

6

7

8

9

SCL

SDA

7-BIT ADDRESS

EN1

EN2

SPD

SLP

W

ACK BY

LTC2461/LTC2463

ACK BY

LTC2461/LTC2463

START BY

MASTER

SLEEP

DATA INPUT

24613 F03

Figure 5b. Timing Diagram for Writing to the LTC2461/LTC2463

24613f

12

LTC2461/LTC2463

APPLICATIONS INFORMATION

the next conversion is complete. It will remain powered

downuntilavalidaddressisacknowledged. Thereference

startup time is approximately 12ms. In order to ensure a

stable reference for the following conversions, either the

data input/output time should be delayed 12ms after an

address acknowledge or the ﬁrst conversion following a

reference start up should be discarded.

end of a read operation, a new conversion automatically

begins. At the conclusion of the conversion cycle, the next

result may be read using the method described above. If

the conversion cycle is not complete and a valid address

selects the device, the LTC2461/LTC2463 generate a NAK

signal indicating the conversion cycle is in progress. See

Figure 7a for an example state diagram.

Discarding a Conversion Result and Initiating a New

Conversion

OPERATION SEQUENCE

Continuous Read

It is possible to start a new conversion without reading

the old result, as shown in Figure 7b. Following a valid

7-bit address, a read request (R/W) bit, and a valid ACK,

a STOP command will start a new conversion.

Conversions from the LTC2461/LTC2463 can be continu-

ously read, see Figure 6. The R/W is 1 for a read. At the

7-BIT ADDRESS

(0010100 OR 1010100)

7-BIT ADDRESS

(0010100 OR 1010100)

S

R

ACK

READ

P

S

R

ACK

READ

P

SLEEP

DATA OUTPUT

CONVERSION

SLEEP

DATA OUTPUT

CONVERSION

24613 F06

Figure 6. Consecutive Reading

WRITE INPUT

CONFIGURATION

(FIGURE 5b)

ACK

7-BIT ADDRESS:

0010100 OR 1010100

R/W

BIT LOW

2

I C START

I C STOP

CONVERT

CONVERSION

FINISHED

WRITE INPUT

CONFIGURATION

(FIGURE 5b)

R/W

BIT LOW

7-BIT ADDRESS:

0010100 OR 1010100

2

I C (REPEAT) START

I C START

FOR CYCLE N

CONVERSION

FINISHED

ACK

NAK

7-BIT ADDRESS:

0010100 OR 1010100

R/W

BIT HIGH

READ DATA FROM

CYCLE N-1

2

I C STOP

CONVERT

24613 F07b

ACK

Figure 7a. I²C State Diagram

7-BIT ADDRESS

S

R

ACK READ (OPTIONAL)

DATA OUTPUT

P

(0010100 OR 1010100)

CONVERSION

SLEEP

CONVERSION

24613 F07a

Figure 7b. Start a New Conversion without Reading Old Conversion Result

24613f

13

LTC2461/LTC2463

APPLICATIONS INFORMATION

PRESERVING THE CONVERTER ACCURACY

Very low impedance ground and power planes, and star

connections at both V and GND pins, are preferable.

CC

TheLTC2461/LTC2463aredesignedtominimizetheconver-

sion result’s sensitivity to device decoupling, PCB layout,

antialiasingcircuits,lineandfrequencyperturbations.Nev-

ertheless, inordertopreservethehighaccuracycapability

of this part, some simple precautions are desirable.

The V pin should have two distinct connections: the

CC

ﬁrst to the decoupling capacitors described above, and

the second to the ground return for the power supply

voltage source.

REFOUT and COMP

Digital Signal Levels

The on-chip 1.25V precision reference is internally tied

to the LTC2461/LTC2463 converter’s reference input and

its output to the REFOUT pin. A 0.1ꢀF capacitor should

be placed on the REFOUT pin. It is possible to reduce

this capacitor, but the transition noise increases. A 0.1ꢀF

capacitor should also be placed on the COMP pin. This

pin is tied to an internal point in the reference and is used

for stability. In order for the reference to remain stable the

capacitor placed on the COMP pin must be greater than or

Due to the nature of CMOS logic, it is advisable to keep

inputdigitalsignalsnearGNDorV .Voltagesintherange

CC

of 0.5V to V – 0.5V may result in additional current

CC

leakage from the part. Undershoot and overshoot should

also be minimized, particularly while the chip is convert-

ing. Excessive noise on the digital lines could degrade the

ADC performance.

Driving V and GND

CC

InrelationtotheV andGNDpins, the LTC2461/LTC2463

CC

INTERNAL

V

CC

REFERENCE

R

SW

15k

combinesinternalhighfrequencydecouplingwithdamping

elements, which reduce the ADC performance sensitivity

to PCB layout and external components. Nevertheless,

the very high accuracy of this converter is best pre-

served by careful low and high frequency power supply

decoupling.

I

LEAK

(TYP)

REFOUT

R

SW

15k

I

LEAK

(TYP)

+

A 0.1μF, high quality, ceramic capacitor in parallel with

a 10μF low ESR ceramic capacitor should be connected

IN

LEAK

between the V and GND pins, as close as possible to

CC

C

EQ

the package. The 0.1μF capacitor should be placed closest

R

SW

0.35pF

(TYP)

15k

to the ADC package. It is also desirable to avoid any via

I

LEAK

(TYP)

–

in the circuit path, starting from the converter V pin,

IN

CC

passing through these two decoupling capacitors, and

returningtotheconverterGNDpin.Theareaencompassed

by this circuit path, as well as the path length, should be

minimized.

LEAK

R

SW

15k

I

LEAK

(TYP)

24613 F08

–

REF

–

As shown in Figure 8, REF is used as the negative refer-

LEAK

ence voltage input to the ADC. This pin can be tied directly

to ground or Kelvined to sensor ground. In the case where

–

Figure 8. LTC2461/LTC2463 Analog Input/Reference

Equivalent Circuit

REF is used as a sense input, it should be bypassed to

ground with a 0.1ꢀF ceramic capacitor in parallel with a

10ꢀF low ESR ceramic capacitor.

24613f

14

LTC2461/LTC2463

APPLICATIONS INFORMATION

V

CC

equaltothecapacitortiedtotheREFOUTpin. TheREFOUT

pin should not be overridden by an external voltage. If

a reference voltage greater than 1.25V is required, the

LTC2451/LTC2453 should be used.

IN

R

SW

(LTC2461)

15k

I

LEAK

R

(TYP)

S

+

IN

(LTC2463)

I

LEAK

+

C

+

–

IN

EQ

V

I

SIG

CONV

0.35pF

(TYP)

C

PAR

The internal reference has a corresponding start up

time depending on the size of the capacitors tied to the

REFOUT and COMP pins. This start up time is typically

12ms when 0.1ꢀF capacitors are used. At initial power up,

the ﬁrst conversion result can be aborted or ignored. At

the completion of this ﬁrst conversion, the reference has

settled and all subsequent conversions are valid.

V

CC

R

SW

15k

I

LEAK

(TYP)

–

S

IN

(LTC2463)

I

LEAK

–

C

+

–

IN

EQ

SIG

CONV

0.35pF

(TYP)

C

PAR

24613 F09

Figure 9. LTC2461/LTC2463 Input Drive Equivalent Circuit

If the reference is put to sleep (program SLP = 1) the refer-

ence is powered down after the next conversion. This last

conversionresultisvalid.Onavalidaddressacknowledge,

the reference is powered back up. In order to ensure the

reference output has settled before the next conversion,

the power up time can be extended by delaying the data

read 12ms. Once all 16 bits are read from the device, the

nextconversionautomaticallybegins.Inthedefaultopera-

tion, the reference remains powered up at the conclusion

of the conversion cycle.

Therearesomeimmediatetrade-offsinR andC without

S

IN

needing a full circuit analysis. Increasing R and C can

S

IN

give the following beneﬁts:

1) Due to the LTC2461/LTC2463’s input sampling algo-

+

–

rithm, the input current drawn by IN , IN or IN over

a conversion cycle is typically 50nA. A high R • C

S

IN

attenuates the high frequency components of the input

current, and R values up to 1k result in <1LSB error.

S

2) The bandwidth from V is reduced at the input pins

+

–

SIG

Driving V and V

IN

+

–

(IN , IN or IN). This bandwidth reduction isolates the

ADCfromhighfrequencysignals, andassuchprovides

simple antialiasing and input noise reduction.

The input drive requirements can best be analyzed using

the equivalent circuit of Figure 9. The input signal V is

SIG

+

–

connected to the ADC input pins (IN and IN ) through an

3) Switching transients generated by the ADC are attenu-

ated before they go back to the signal source.

equivalentsourceresistanceR .Thisresistorincludesboth

S

the actual generator source resistance and any additional

optional resistors connected to the input pins. Optional

4) A large C gives a better AC ground at the input pins,

IN

input capacitors C are also connected to the ADC input

helping reduce reﬂections back to the signal source.

IN

pins. This capacitor is placed in parallel with the input

5) Increasing R protects the ADC by limiting the current

S

parasitic capacitance C . This parasitic capacitance

PAR

during an outside-the-rails fault condition.

includes elements from the printed circuit board (PCB)

There is a limit to how large R • C should be for a given

and the associated input pin of the ADC. Depending on the

S

IN

application. Increasing R beyond a given point increases

PCBlayout, C hastypicalvaluesbetween2pFand15pF.

S

PAR

the voltage drop across R due to the input current,

In addition, the equivalent circuit of Figure 9 includes the

S

converter equivalent internal resistor R and sampling

SW

capacitor C .

EQ

24613f

15

LTC2461/LTC2463

APPLICATIONS INFORMATION

to the point that signiﬁcant measurement errors exist.

on. The resultant INL vs V is shown in Figure 11. The

IN

Additionally, forsomeapplications, increasingtheR •C

measurements of Figure 11 include a capacitor C

cor-

S

IN

PAR

product too much may unacceptably attenuate the signal

respondingtoaminimumsizedlayoutpadandaminimum

width input trace of about 1 inch length.

at frequencies of interest.

For most applications, it is desirable to implement C as

IN

Signal Bandwidth, Transition Noise and Noise

Equivalent Input Bandwidth

a high-quality 0.1μF ceramic capacitor and to set R ≤ 1k.

S

This capacitor should be located as close as possible to

1

+

–

The LTC2461/LTC2463 include a sinc type digital ﬁlter

the actual IN , IN or IN package pin. Furthermore, the

area encompassed by this circuit path, as well as the path

length, should be minimized.

with the ﬁrst notch located at f = 60Hz. As such, the

0

3dB input signal bandwidth is 26.54Hz. The calculated

LTC2461/LTC2463 input signal attenuation vs frequency

over a wide frequency range is shown in Figure 12. The

calculated LTC2461/LTC2463 input signal attenuation vs

frequency at low frequencies is shown in Figure 13. The

In the case of a 2-wire sensor that is not remotely

grounded, it is desirable to split R and place series

S

resistors in the ADC input line as well as in the sensor

ground return line, which should be tied to the ADC GND

pin using a star connection topology.

converter noise level is about 2.2μV

and can be mod-

RMS

eled by a white noise source connected at the input of a

noise-free converter.

Figure 10 shows the measured LTC2463 INL vs Input

Voltage as a function of R value with an input capacitor

S

On a related note, the LTC2463 uses two separate A/D

converters to digitize the positive and negative inputs.

C = 0.1μF.

IN

Insomecases,R canbeincreasedabovetheseguidelines.

Each of these A/D converters has 2.2μV

transition

S

RMS

The input current is zero when the ADC is either in sleep

noise. If one of the input voltages is within this small

transition noise band, then the output will ﬂuctuate one

bit, regardless of the value of the other input voltage. If

both of the input voltages are within their transition noise

bands, the output can ﬂuctuate 2 bits.

or I/O modes. Thus, if the time constant of the input RC

circuit τ = R • C , is of the same order of magnitude or

S

IN

longer than the time periods between actual conversions,

then one can consider the input current to be reduced

correspondingly.

Forasimplesystemnoiseanalysis,theV drivecircuitcan

IN

These considerations need to be balanced out by the input

be modeled as a single-pole equivalent circuit character-

signal bandwidth. The 3dB bandwidth ≈ 1/(2πR C ).

ized by a pole location f and a noise spectral density n .

S IN

i

If the converter has an unlimited bandwidth, or at least a

Finally, if the recommended choice for C is unacceptable

IN

bandwidth substantially larger than f , then the total noise

i

fortheuser’sspeciﬁcapplication,analternatestrategyisto

contribution of the external drive circuit would be:

eliminateC andminimizeC andR .Inpracticalterms,

IN

PAR

S

thisconﬁgurationcorrespondstoalowimpedancesensor

directly connected to the ADC through minimum length

traces. Actual applications include current measurements

through low value sense resistors, temperature measure-

ments, low impedance voltage source monitoring, and so

V_n= n_iπ /2• f_i

Then, the total system noise level can be estimated as

2

the square root of the sum of (V ) and the square of the

n

2

LTC2461/LTC2463 noise ﬂoor (~2.2μV ).

24613f

16

LTC2461/LTC2463

APPLICATIONS INFORMATION

3

2

C

V

T

= 0.1μF

= 5V

C

V

T

= 0

IN

CC

= 25°C

IN

CC

A

= 5V

= 25°C

2

1

A

R

= 10k

R = 10k

S

1

R

= 1k

S

R

S

= 0k

0

R

= 0k

R

= 1k

S

–1

–2

–3

–1

–2

–3

–1.25

–0.75

–0.25

0.25

0.75

1.25

–1.25

–0.75

–0.25

0.25

0.75

1.25

DIFFERENTIAL INPUT VOLTAGE (V)

24613 F10

24613 F11

Figure 10. Measured INL vs Input Voltage (C_IN= 0.1μF)

Figure 11. Measured INL vs Input Voltage (C_IN= 0)

0

V

T

= 5V

V

T

= 5V

CC

A

CC

A

= 25°C

–5

–10

–15

–20

–25

–30

–35

–40

–45

–50

–20

–40

–60

–80

–100

0

5.0

7.5

1.00 1.25 1.50

2.5

0

60 120 180 240 300 360 420 480 540 600

INPUT SIGNAL FREQUENCY (Hz)

INPUT SIGNAL FREQUENCY (MHz)

24613 F12

24613 F13

Figure 12. LTC2463 Input Signal Attentuation vs Frequency

Figure 13. LTC2463 Input Signal Attenuation

vs Frequency (Low Frequencies)

24613f

17

LTC2461/LTC2463

PACKAGE DESCRIPTION

DD Package

12-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1725 Rev A)

0.70 0.05

2.38 0.05

1.65 0.05

3.50 0.05

2.10 0.05

PACKAGE

OUTLINE

0.25 0.05

0.45 BSC

2.25 REF

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

R = 0.115

0.40 0.10

TYP

7

12

2.38 0.10

3.00 0.10

(4 SIDES)

1.65 0.10

PIN 1 NOTCH

PIN 1

TOP MARK

R = 0.20 OR

0.25 × 45°

CHAMFER

(SEE NOTE 6)

6

1

0.23 0.05

0.45 BSC

0.75 0.05

0.200 REF

2.25 REF

(DD12) DFN 0106 REV A

0.00 – 0.05

BOTTOM VIEW—EXPOSED PAD

NOTE:

1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

24613f

18

LTC2461/LTC2463

PACKAGE DESCRIPTION

MS Package

12-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1668 Rev Ø)

0.889 p 0.127

(.035 p .005)

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

4.039 p 0.102

(.159 p .004)

(NOTE 3)

0.65

(.0256)

BSC

0.42 p 0.038

(.0165 p .0015)

TYP

0.406 p 0.076

(.016 p .003)

REF

12 11 10 9 8 7

RECOMMENDED SOLDER PAD LAYOUT

DETAIL “A”

0o – 6o TYP

3.00 p 0.102

(.118 p .004)

(NOTE 4)

4.90 p 0.152

(.193 p .006)

0.254

(.010)

GAUGE PLANE

0.53 p 0.152

(.021 p .006)

1

2 3 4 5 6

0.86

(.034)

REF

1.10

(.043)

MAX

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.22 – 0.38

(.009 – .015)

TYP

0.1016 p 0.0508

(.004 p .002)

MSOP (MS12) 1107 REV Ø

0.650

(.0256)

BSC

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

24613f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

19

LTC2461/LTC2463

TYPICAL APPLICATION

10μF

V

CC

V

1μF

CC

0.1μF

CC

V

CC

μC

1

12

5k

REFOUT

V

1k

CC

5

4

7

5

9

+

–

SCK/SCL

MOSI/SDA

MISO/SDO

SCL

IN

LTC2463

–

0.1μF

1k

6

3

SDA

A0

–

IN

10

GND

8

COMP REF GND

0.1μF

2

8

7, 11, 4

0.1μF

24613 TA02

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LTC1860/LTC1861

12-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP

850μA at 250ksps, 2μA at 1ksps, SO-8 and MSOP Packages

450μA at 150ksps, 10μA at 1ksps, SO-8 and MSOP Packages

850μA at 250ksps, 2μA at 1ksps, SO-8 and MSOP Packages

450μA at 150ksps, 10μA at 1ksps, SO-8 and MSOP Packages

3V Supply, 1.5mW at 100ksps, TSOT 6-pin/8-pin Packages

LTC1860L/LTC1861L 12-Bit, 3V, 1-/2-Channel 150ksps SAR ADC

LTC1864/LTC1865 16-Bit, 5V, 1-/2-Channel 250ksps SAR ADC in MSOP

LTC1864L/LTC1865L 16-bit, 3V, 1-/2-Channel 150ksps SAR ADC

LTC2360

LTC2440

LTC2480

12-Bit, 100ksps SAR ADC

200nV

Noise, 4kHz Output Rate, 15ppm INL

24-Bit No Latency ΔΣ™ADC

RMS

Easy-Drive Input Current Cancellation, 600nV

Tiny 10-Lead DFN Package

Noise,

16-Bit, Differential Input, No Latency ΔΣ ADC, with PGA,

Temp. Sensor, SPI

RMS

LTC2481

LTC2482

LTC2483

LTC2484

LTC2485

Easy-Drive Input Current Cancellation, 600nV

Tiny 10-Lead DFN Package

16-Bit, Differential Input, No Latency ΔΣ ADC, with PGA,

2

Temp. Sensor, I C

Easy-Drive Input Current Cancellation, 600nV

Tiny 10-Lead DFN Package

16-Bit, Differential Input, No Latency ΔΣ ADC, SPI

2

Easy-Drive Input Current Cancellation, 600nV

Tiny 10-Lead DFN Package

16-Bit, Differential Input, No Latency ΔΣ ADC, I C

Easy-Drive Input Current Cancellation, 600nV

Tiny 10-Lead DFN Package

24-Bit, Differential Input, No Latency ΔΣ ADC, SPI with

Temp. Sensor

2

Easy-Drive Input Current Cancellation, 600nV

Tiny 10-Lead DFN Package

24-Bit, Differential Input, No Latency ΔΣ ADC, I C with

Temp. Sensor

LTC6241

LTC2450

Dual, 18MHz, Low Noise, Rail-to-Rail Op Amp

550nV Noise, 125μV Offset Max

P-P

Easy-to-Use, Ultra-Tiny 16-Bit ADC, SPI, 0V to 5.5V

Input Range

2 LSB INL, 50nA Sleep current, Tiny 2mm × 2mm DFN-6 Package,

30Hz Output Rate

LTC2450-1

LTC2451

LTC2452

LTC2453

Easy-to-Use, Ultra-Tiny 16-Bit ADC, SPI, 0V to 5.5V

Input Range

2 LSB INL, 50nA Sleep Current, Tiny 2mm × 2mm DFN-6 Package,

60Hz Output Rate

2

Easy-to-Use, Ultra-Tiny 16-Bit ADC, I C, 0V to 5.5V

2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT

Package, Programmable 30Hz/60Hz Output Rates

Input Range

Easy-to-Use, Ultra-Tiny 16-Bit Differential ADC, SPI,

5.5V Input Range

2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT

Package

2

Easy-to-Use, Ultra-Tiny 16-Bit Differential ADC, I C,

2 LSB INL, 50nA Sleep Current, Tiny 3mm × 2mm DFN-8 or TSOT

Package

5.5V Input Range

LTC2460

LTC2462

16-Bit, ΔΣ SPI ADC with 10ppm Max Reference

Single-Ended, Tiny 12-Lead 3mm × 3mm DFN and MSOP Packages

Differential Input, Tiny 12-Lead 3mm × 3mm DFN and MSOP Packages

No Latency ΔΣ is a trademark of Linear Technology Corporation.

24613f

LT 0609 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

20

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC2461CDDPBF
厂家：	Linear
描述：	Ultra-Tiny, 16-Bit IÂ²C ÎÎ£ ADCs with 10ppm/Â°C Max Precision Reference 超纤巧， 16位IÂ²C我？我英镑的ADC，以及为10ppm / A ° C（最大值）精密基准
文件：	总20页 (文件大小：223K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2461CDDPBF [Linear]

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