LTC2480IMS-PBF [Linear]
16-Bit ÎΣ ADC with Easy Drive Input Current Cancellation; 16位I ??我英镑ADC使用Easy Drive输入电流消除
| 型号： | LTC2480IMS-PBF |
| 厂家： | 
Linear |
| 描述： | 16-Bit ÎΣ ADC with Easy Drive Input Current Cancellation |
| 文件： | 总42页 (文件大小：494K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2480
16-BitΔΣADCwithEasyDrive
InputCurrentCancellation
FEATURES
DESCRIPTION
The LTC®2480 combines a 16-bit plus sign No Latency
n
Easy Drive Technology Enables Rail-to-Rail Inputs
with Zero Differential Input Current
™
™
ΔΣ analog-to-digitalconverterwithpatentedEasyDrive
n
Directly Digitizes High Impedance Sensors with
technology. The patented sampling scheme eliminates
dynamic input current errors and the shortcomings of on-
chipbufferingthroughautomaticcancellationofdifferential
inputcurrent.Thisallowslargeexternalsourceimpedances
andinputsignals, withrail-to-railinputrangetobedirectly
digitized while maintaining exceptional DC accuracy.
Full Accuracy
n
Programmable Gain from 1 to 256
n
Integrated Temperature Sensor
n
GND to V Input/Reference Common Mode Range
CC
n
Programmable 50Hz, 60Hz or Simultaneous
50Hz/60Hz Rejection Mode
The LTC2480 includes on-chip programmable gain, a
temperature sensor and an oscillator. The LTC2480 can
be configured to provide a programmable gain from 1
to 256 in 8 steps, measure an external signal or internal
temperaturesensorandrejectlinefrequencies.50Hz,60Hz
or simultaneous 50Hz/60Hz line frequency rejection can
be selected as well as a 2x speed-up mode.
n
2ppm (0.25LSB) INL, No Missing Codes
n
1ppm Offset and 15ppm Full-Scale Error
n
Selectable 2x Speed Mode (15Hz Using Internal
Oscillator)
n
No Latency: Digital Filter Settles in a Single Cycle
n
Single Supply 2.7V to 5.5V Operation
Internal Oscillator
n
n
The LTC2480 allows a wide common mode input range
Available in a Tiny (3mm × 3mm) 10-Lead
DFN Package and 10-Lead MSOP Package
(0V to V ) independent of the reference voltage. The
CC
reference can be as low as 100mV or can be tied directly
APPLICATIONS
to V . The LTC2480 includes an on-chip trimmed oscil-
CC
lator eliminating the need for external crystals or oscil-
lators. Absolute accuracy and low drift are automatically
maintained through continuous, transparent, offset and
full-scale calibration.
n
Direct Sensor Digitizer
n
Weight Scales
n
Direct Temperature Measurement
n
Strain Gauge Transducers
L, LT, LTC and LTM, Linear Technology and the Linear logo are registered trademarks and
No Latency ΔΣ and Easy Drive are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Patents pending.
n
Instrumentation
n
Industrial Process Control
n
DVMs and Meters
TYPICAL APPLICATION
+FS Error vs RSOURCE at IN+ and IN–
80
V
V
V
V
= 5V
= 5V
= 3.75V
= 1.25V
= GND
= 25°C
CC
V
CC
REF
60
40
20
+
IN
–
IN
1μF
SDI
f
O
T
A
C
IN
= 1μF
10k
10k
I
= 0
V
V
CC
DIFF
REF
+
0
V
IN
SDO
SCK
4-WIRE
SPI INTERFACE
1μF
SENSE
LTC2480
GND
–20
–
V
IN
CS
2480 TA01
–40
–60
–80
f
O
10
100
10k
1
100k
1k
(Ω)
2480 TA04
R
SOURCE
2480fc
1
LTC2480
ABSOLUTE MAXIMUM RATINGS (Notes 1, 2)
Operating Temperature Range
Supply Voltage (V ) to GND...................... –0.3V to 6V
CC
LTC2480C ............................................... 0°C to 70°C
LTC2480I ............................................ –40°C to 85°C
LTC2480H ........................................ –40°C to 125°C
Storage Temperature Range.................. –65°C to 125°C
Analog Input Voltage to GND ....... –0.3V to (V + 0.3V)
CC
Reference Input Voltage to GND .. –0.3V to (V + 0.3V)
CC
Digital Input Voltage to GND ........ –0.3V to (V + 0.3V)
CC
Digital Output Voltage to GND...... –0.3V to (V + 0.3V)
CC
PIN CONFIGURATION
TOP VIEW
TOP VIEW
SDI
1
2
3
4
5
10
9
f
O
SDI
1
2
3
4
5
10
9
f
O
V
CC
SCK
GND
SDO
CS
11
GND
V
SCK
GND
SDO
CS
CC
V
8
REF
V
8
REF
+
+
IN
7
IN
7
6
–
–
IN
IN
6
MS PACKAGE
10-LEAD PLASTIC MSOP
= 125°C, θ = 120°C/W
DD PACKAGE
10-LEAD (3mm s 3mm) PLASTIC DFN
T
JMAX
JA
T
= 125°C, θ = 43°C/W
JA
JMAX
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC2480CDD#PBF
LTC2480IDD#PBF
LTC2480CMS#PBF
LTC2480IMS#PBF
LTC2480HDD#PBF
LTC2480HMS#PBF
TAPE AND REEL
PART MARKING*
LBJY
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC2480CDD#TRPBF
LTC2480IDD#TRPBF
LTC2480CMS#TRPBF
LTC2480IMS#TRPBF
LTC2480HDD#TRPBF
LTC2480HMS#TRPBF
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
LBJY
–40°C to 85°C
0°C to 70°C
LTCWB
LTCWB
LBJY
10-Lead Plastic MSOP
–40°C to 85°C
–40°C to 125°C
–40°C to 125°C
10-Lead (3mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
LTCWB
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2480fc
2
LTC2480
ELECTRICAL CHARACTERISTICS (NORMAL SPEED) The l denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
0.1 ≤ V ≤ V , –FS ≤ V ≤ +FS (Note 5)
MIN
TYP
MAX
UNITS
l
l
Resolution (No Missing Codes)
Integral Nonlinearity
16
Bits
REF
CC
IN
5V ≤ V ≤ 5.5V, V = 5V, V
= 2.5V (Note 6)
2
1
10
ppm of V
ppm of V
CC
REF
IN(CM)
REF
REF
2.7V ≤ V ≤ 5.5V, V = 2.5V, V
= 1.25V (Note 6)
CC
REF
IN(CM)
–
+
l
Offset Error
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 14)
0.5
10
2.5
μV
REF
CC
CC
CC
+
–
Offset Error Drift
Positive Full-Scale Error
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V
nV/°C
REF
CC
+
+
–
–
l
l
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
25
40
ppm of V
ppm of V
REF
CC
REF
REF
REF
REF
REF
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V (H-Grade)
REF
CC
REF
+
–
Positive Full-Scale Error Drift
Negative Full-Scale Error
Negative Full-Scale Error Drift
Total Unadjusted Error
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
0.1
ppm of
REF
REF
CC
REF
REF
V
/°C
+
+
–
–
l
l
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
25
40
ppm of V
ppm of V
REF
CC
REF
REF
REF
REF
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V (H-Grade)
REF
CC
REF
REF
+
–
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
0.1
15
ppm of
REF
CC
REF
REF
V
/°C
REF
5V ≤ V ≤ 5.5V, V = 2.5V, V
= 1.25V
ppm of V
ppm of V
ppm of V
CC
REF
IN(CM)
REF
REF
REF
5V ≤ V ≤ 5.5V, V = 5V, V = 2.5V
CC
CC
REF
IN(CM)
2.7V ≤ V ≤ 5.5V, V = 2.5V, V
= 1.25V
REF
IN(CM)
–
+
Output Noise
5V ≤ V ≤ 5.5V, V = 5V, GND ≤ IN = IN ≤ V (Note 13)
0.6
420
1.4
μV
RMS
CC
REF
CC
Internal PTAT Signal
T = 27°C
A
mV
Internal PTAT Temperature Coefficient
Programmable Gain
mV/°C
l
1
256
ELECTRICAL CHARACTERISTICS (2X SPEED) The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
0.1 ≤ V ≤ V , –FS ≤ V ≤ +FS (Note 5)
MIN
TYP
MAX
UNITS
l
l
Resolution (No Missing Codes)
Integral Nonlinearity
16
Bits
REF
CC
IN
5V ≤ V ≤ 5.5V, V = 5V, V
= 2.5V (Note 6)
2
1
10
2
ppm of V
ppm of V
CC
REF
IN(CM)
REF
REF
2.7V ≤ V ≤ 5.5V, V = 2.5V, V
= 1.25V (Note 6)
CC
REF
IN(CM)
–
+
l
Offset Error
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 14)
0.5
mV
REF
CC
CC
CC
+
–
Offset Error Drift
Positive Full-Scale Error
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V
100
nV/°C
REF
CC
+
+
–
–
l
l
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
25
40
ppm of V
ppm of V
REF
CC
REF
REF
REF
REF
REF
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V (H-Grade)
REF
CC
REF
+
–
Positive Full-Scale Error Drift
Negative Full-Scale Error
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
0.1
ppm of
REF
REF
CC
REF
REF
V
/°C
+
+
–
–
l
l
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
25
40
ppm of V
ppm of V
REF
CC
REF
REF
REF
REF
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V (H-Grade)
REF
CC
REF
REF
+
–
Negative Full-Scale Error Drift
2.5V ≤ V ≤ V , IN = 0.75V , IN = 0.25V
0.1
ppm of
REF
REF
CC
REF
REF
V
/°C
–
+
Output Noise
5V ≤ V ≤ 5.5V, V = 5V, GND ≤ IN = IN ≤ V (Note 13)
0.84
μV
RMS
CC
REF
CC
l
Programmable Gain
(Note 15)
1
128
2480fc
3
LTC2480
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 5)
MIN
140
140
TYP
MAX
UNITS
dB
–
+
l
l
Input Common Mode Rejection DC
REF
CC
CC
–
+
Input Common Mode Rejection
50Hz 2ꢀ
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 5)
dB
REF
CC
CC
–
+
l
Input Common Mode Rejection
60Hz 2ꢀ
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 5)
140
dB
REF
CC
CC
–
–
+
+
l
l
Input Normal Mode Rejection
50Hz 2ꢀ
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Notes 5, 7)
110
104
120
120
dB
dB
REF
CC
CC
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Notes 5, 7) (H-Grade)
REF
CC
CC
–
–
+
+
l
l
Input Normal Mode Rejection
60Hz 2ꢀ
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Notes 5, 8)
110
104
dB
dB
REF
CC
CC
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Notes 5, 8) (H-Grade)
REF
CC
CC
–
+
l
Input Normal Mode Rejection
50Hz/60Hz 2ꢀ
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Notes 5, 9)
87
dB
REF
CC
CC
–
+
l
Reference Common Mode
Rejection DC
2.5V ≤ V ≤ V , GND ≤ IN = IN ≤ V (Note 5)
120
140
dB
REF
CC
CC
–
+
Power Supply Rejection DC
V
REF
V
REF
V
REF
= 2.5V, IN = IN = GND
120
120
120
dB
dB
dB
–
+
Power Supply Rejection, 50Hz 2ꢀ
Power Supply Rejection, 60Hz 2ꢀ
= 2.5V, IN = IN = GND (Notes 7, 9)
–
+
= 2.5V, IN = IN = GND (Notes 8, 9)
ANALOG INPUT AND REFERENCE The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
+
IN
Absolute/Common Mode IN Voltage
GND – 0.3V
GND – 0.3V
V
CC
V
CC
+ 0.3V
V
V
V
–
–
IN
Absolute/Common Mode IN Voltage
+ 0.3V
+
–
l
l
l
l
FS
Full-Scale of the Differential Input (IN – IN )
0.5V /GAIN
REF
16
LSB
Least Significant Bit of the Output Code
FS/2
+
–
V
V
Input Differential Voltage Range (IN – IN )
Reference Voltage Range
–FS
0.1
+FS
V
V
IN
V
REF
CC
+
+
C (IN )
IN Sampling Capacitance
11
11
11
1
pF
pF
pF
nA
nA
nA
S
–
–
C (IN )
IN Sampling Capacitance
S
C (V
S
)
V
Sampling Capacitance
REF
DC_LEAK
DC_LEAK
REF
+
+
+
l
l
l
I
I
I
(IN )
IN DC Leakage Current
Sleep Mode, IN = GND
–10
–10
10
–
–
–
(IN )
IN DC Leakage Current
Sleep Mode, IN = GND
1
10
(V
)
V
DC Leakage Current
Sleep Mode, V = V
CC
–100
1
100
DC_LEAK REF
REF
REF
ANALOG INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS
High Level Input Voltage CS, f , SDI 2.7V ≤ V ≤ 5.5V
MIN
TYP
MAX
UNITS
l
l
l
l
l
V
IH
V
IL
V
IH
V
IL
V
V
– 0.5
V
V
O
CC
CC
CC
Low Level Input Voltage CS, f , SDI
2.7V ≤ V ≤ 5.5V
0.5
O
CC
High Level Input Voltage SCK
Low Level Input Voltage SCK
2.7V ≤ V ≤ 5.5V (Note 10)
– 0.5
V
CC
2.7V ≤ V ≤ 5.5V (Note 10)
0.5
10
V
CC
I
IN
Digital Input Current CS, f , SDI
0V ≤ V ≤ V
CC
–10
μA
O
IN
2480fc
4
LTC2480
ANALOG INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
0V ≤ V ≤ V (Note 10)
MIN
TYP
MAX
UNITS
μA
pF
pF
V
l
I
Digital Input Current SCK
–10
10
IN
IN
CC
C
C
V
V
V
V
Digital Input Capacitance CS, f , SDI
10
10
IN
O
Digital Input Capacitance SCK
High Level Output Voltage SDO
Low Level Output Voltage SDO
High Level Output Voltage SCK
Low Level Output Voltage SCK
Hi-Z Output Leakage SDO
IN
l
l
l
l
l
I = –800μA
O
V
V
– 0.5
OH
OL
OH
OL
CC
CC
I = 1.6mA
O
0.4
V
I = –800μA
O
– 0.5
V
I = 1.6mA
O
0.4
10
V
I
OZ
–10
μA
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
V
Supply Voltage
Supply Current
2.7
5.5
V
CC
l
l
l
I
CC
Conversion Mode (Note 12)
Sleep Mode (Note 12)
H-Grade
160
1
250
2
20
μA
μA
μA
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
10
TYP
MAX
4000
100
UNITS
kHz
μs
l
l
l
f
t
t
t
External Oscillator Frequency Range
External Oscillator High Period
External Oscillator Low Period
Conversion Time for 1x Speed Mode
(Note 15)
EOSC
HEO
0.125
0.125
100
μs
LEO
l
l
l
l
l
l
l
50Hz Mode
50Hz Mode (H-Grade)
60Hz Mode
60Hz Mode (H-Grade)
Simultaneous 50Hz/60Hz Mode
Simultaneous 50Hz/60Hz Mode (H-Grade)
External Oscillator
157.2
157.2
131.0
131.0
144.1
144.1
160.3
160.3
133.6
133.6
146.9
146.9
163.5
165.1
136.3
137.6
149.9
151.0
ms
ms
ms
ms
ms
ms
ms
CONV_1
41036/f
(in kHz)
EOSC
l
l
l
l
l
l
l
t
Conversion Time for 2x Speed Mode
50Hz Mode
78.7
65.6
72.2
80.3
81.9
82.7
68.2
68.9
75.1
75.6
ms
ms
ms
ms
ms
ms
ms
CONV_2
50Hz Mode (H-Grade)
60Hz Mode
66.9
73.6
60Hz Mode (H-Grade)
Simultaneous 50Hz/60Hz Mode
Simultaneous 50Hz/60Hz Mode (H-Grade)
External Oscillator
20556/f
(in kHz)
EOSC
f
Internal SCK Frequency
Internal Oscillator (Note 10)
External Oscillator (Notes 10, 11)
38.4
/8
EOSC
kHz
kHz
ISCK
f
l
l
D
Internal SCK Duty Cycle
(Note 10)
(Note 10)
45
55
ꢀ
ISCK
f
External SCK Frequency Range
4000
kHz
ESCK
2480fc
5
LTC2480
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
(Note 10)
MIN
125
125
0.61
TYP
MAX
UNITS
ns
l
l
t
t
t
External SCK Low Period
External SCK High Period
LESCK
(Note 10)
ns
HESCK
l
l
Internal SCK 24-Bit Data Output Time Internal Oscillator (Notes 10, 12)
External Oscillator (Notes 10, 11)
0.625
0.64
ms
ms
DOUT_ISCK
192/f
(in kHz)
EOSC
l
l
l
l
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
t
t
t
External SCK 24-Bit Data Output Time (Note 10)
CS↓ to SDO Low
24/f
(in kHz)
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DOUT_ESCK
ESCK
0
0
200
200
200
1
CS↑ to SDO High Z
2
Internal SCK Mode
External SCK Mode
0
CS↓ to SCK↓
3
50
CS↓ to SCK↑
4
200
50
SCK↓ to SDO Valid
SDO Hold After SCK↓
SCK Set-Up Before CS↓
SCK Hold After CS↓
SDI Setup Before SCK↑
SDI Hold After SCK↑
KQMAX
(Note 5)
15
50
KQMIN
5
6
7
8
(Note 5)
(Note 5)
100
100
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 8: 60Hz mode (internal oscillator) or f
oscillator).
Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or f
280kHz 2ꢀ (external oscillator).
= 307.2kHz 2ꢀ (external
EOSC
=
EOSC
Note 2: All voltage values are with respect to GND.
Note 10: The SCK can be configured in external SCK mode or internal SCK
Note 3: V = 2.7V to 5.5V unless otherwise specified.
mode. In external SCK mode, the SCK pin is used as digital input and the
CC
driving clock is f
output and the output clock signal during the data output is f
. In internal SCK mode, the SCK pin is used as digital
ESCK
V
V
= V /2, FS = 0.5V /GAIN
REFCM
REF
REF
+
.
+
–
–
ISCK
= IN – IN , V
= (IN + IN )/2
IN
IN(CM)
Note 11: The external oscillator is connected to the f pin. The external
O
Note 4: Use internal conversion clock or external conversion clock source
with f = 307.2kHz unless otherwise specified.
oscillator frequency, f , is expressed in kHz.
EOSC
EOSC
Note 12: The converter uses the internal oscillator.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 15: Refer to Applications Information section for performance vs
data rate graphs.
Note 7: 50Hz mode (internal oscillator) or f
oscillator).
= 256kHz 2ꢀ (external
EOSC
2480fc
6
LTC2480
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity
(VCC = 5V, VREF = 5V)
Integral Nonlinearity
Integral Nonlinearity
(VCC = 2.7V, VREF = 2.5V)
(VCC = 5V, VREF = 2.5V)
3
2
3
2
3
2
V
V
V
= 5V
V
V
V
= 5V
V
V
V
= 2.7V
CC
CC
CC
= 5V
= 2.5V
= 2.5V
REF
REF
REF
= 2.5V
= 1.25V
= 1.25V
IN(CM)
IN(CM)
IN(CM)
f
= GND
f
= GND
f = GND
O
O
O
1
0
–45°C
1
0
1
0
25°C
–45°C, 25°C, 90°C
–45°C, 25°C, 90°C
85°C
–1
–2
–3
–1
–2
–3
–1
–2
–3
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–1.25 –0.75
–0.25
0.25
0.75
1.25
–1.25 –0.75
–0.25
0.25
0.75
1.25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2480 G06
2480 G04
2480 G05
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
Total Unadjusted Error
(VCC = 5V, VREF = 2.5V)
Total Unadjusted Error
(VCC = 2.7V, VREF = 2.5V)
12
8
12
8
12
8
V
V
V
= 5V
V
V
V
= 5V
V
V
V
= 2.7V
CC
CC
CC
= 5V
= 5V
= 2.5V
REF
REF
85°C
REF
= 2.5V
= 1.25V
= 1.25V
IN(CM)
IN(CM)
IN(CM)
85°C
f
= GND
f
= GND
f = GND
O
O
O
85°C
25°C
25°C
25°C
4
0
4
0
4
0
–45°C
–45°C
–45°C
–4
–8
–4
–8
–4
–8
–12
–12
–12
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–1.25 –0.75
–0.25
0.25
0.75
1.25
–1.25 –0.75
–0.25
0.25
0.75
1.25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2480 G01
2480 G02
2480 G03
Noise Histogram (6.8sps)
Noise Histogram (7.5sps)
Long-Term ADC Readings
14
12
14
12
5
4
V
= 5V, V
= 5V, V = 0V, V
= 2.5V
IN(CM)
10,000 CONSECUTIVE
READINGS
10,000 CONSECUTIVE
READINGS
CC
REF
IN
GAIN = 256, T = 25°C, RMS NOISE = 0.60μV
A
RMS = 0.59μV
AVERAGE = –0.19μV
RMS = 0.60μV
AVERAGE = –0.69μV
V
V
V
= 5V
V
V
V
= 2.7V
CC
REF
IN
CC
REF
= 0V
IN
3
= 5V
= 2.5V
= 0V
10
8
10
8
2
GAIN = 256
= 25°C
GAIN = 256
T = 25°C
A
1
T
A
0
6
6
–1
–2
–3
–4
–5
4
4
2
2
0
0
–1.8 –1.2 –0.6
0
1.8
–1.8 –1.2 –0.6
0
1.8
–3 –2.4
0.6 1.2
–3 –2.4
0.6 1.2
0
10
30
40
50
60
20
TIME (HOURS)
OUTPUT READING (μV)
OUTPUT READING (μV)
2480 G07
2480 G08
2480 G09
2480fc
7
LTC2480
TYPICAL PERFORMANCE CHARACTERISTICS
RMS Noise
vs Input Differential Voltage
RMS Noise vs VIN(CM)
RMS Noise vs Temperature (TA)
1.0
0.9
1.0
0.9
0.8
0.7
1.0
0.9
0.8
0.7
0.6
0.5
0.4
V
V
V
V
= 5V
= 5V
V
V
= 5V
= 5V
V
V
V
V
= 5V
= 5V
CC
REF
IN
CC
REF
GAIN = 256
CC
REF
IN
= 0V
= 0V
= GND
V
T
= 2.5V
= 25°C
= GND
IN(CM)
IN(CM)
IN(CM)
GAIN = 256
GAIN = 256
A
0.8
0.7
T
= 25°C
A
0.6
0.5
0.4
0.6
0.5
0.4
3
5
6
–1
0
1
2
4
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–45
0
30 45 60 75 90
–30 –15
15
INPUT DIFFERENTIAL VOLTAGE (V)
TEMPERATURE (°C)
V
(V)
IN(CM)
2480 G10
2480 G11
2480 G12
RMS Noise vs VCC
RMS Noise vs VREF
Offset Error vs VIN(CM)
1.0
0.9
0.3
0.2
0.1
0
1.0
0.9
0.8
0.7
V
V
V
= 5V
= 0V
IN(CM)
V
V
V
= 5V
= 5V
V
V
V
= 2.5V
CC
IN
CC
REF
IN
REF
= 0V
IN
IN(CM)
= GND
= 0V
= GND
GAIN = 256
= 25°C
GAIN = 256
= 25°C
GAIN = 256
= 25°C
T
T
T
A
A
A
0.8
0.7
0.6
0.5
0.4
–0.1
–0.2
–0.3
0.6
0.5
0.4
3
5
6
0
1
2
3
(V)
4
5
–1
0
1
2
4
4.3
(V)
5.1 5.5
2.7 3.1 3.5 3.9
V
4.7
V
V
(V)
REF
IN(CM)
CC
2480 G14
2480 G15
2480 G13
Offset Error vs Temperature
Offset Error vs VCC
Offset Error vs VREF
0.3
0.2
0.1
0
0.3
0.2
0.3
0.2
+
V
= 5V
REF = 2.5V
V
V
V
V
= 5V
CC
CC
–
–
REF = GND
REF = GND
= 5V
REF
V
V
= 0V
V
V
= 0V
= 0V
IN
IN(CM)
IN
IN(CM)
IN
IN(CM)
= GND
= GND
= GND
= GND
GAIN = 256
= 25°C
GAIN = 256
= 25°C
f
O
0.1
0.1
0
T
A
T
A
0
–0.1
–0.1
–0.2
–0.3
–0.1
–0.2
–0.3
–0.2
–0.3
4.3
(V)
5.1
5.5
2.7 3.1
3.5 3.9
V
4.7
0
1
2
3
4
5
–45 –30 –15
0
15 30 45 60 75 90
V
(V)
TEMPERATURE (°C)
REF
CC
2480 G17
2480 G18
2480 G16
2480fc
8
LTC2480
TYPICAL PERFORMANCE CHARACTERISTICS
Temperature Sensor
vs Temperature
Temperature Sensor Error
vs Temperature
On-Chip Oscillator Frequency
vs Temperature
310
308
306
304
302
300
5
4
0.40
0.35
0.30
0.25
0.20
V
f
= 5V
V
V
O
= 5V
REF
= GND
CC
O
CC
= GND
= 1.4V
f
3
2
V
= 1.4V
REF
1
0
–1
–2
–3
–4
–5
V
V
V
V
= 4.1V
CC
= 2.5V
REF
= 0V
IN
IN(CM)
= GND
= GND
f
O
–60
–30
0 30
TEMPERATURE (°C)
60
90
120
–60
–30
0
30
60
TEMPERATURE (°C)
90
120
–45 –30 –15
0
15 30 45 60 75 90
TEMPERATURE (°C)
2480 G25
2480 G26
2480 G24
On-Chip Oscillator Frequency
vs VCC
PSRR vs Frequency at VCC
PSRR vs Frequency at VCC
310
308
306
304
0
–20
0
V
V
V
f
= 2.5V
V
V
= 4.1V DC
= 2.5V
V
V
= 4.1V DC 1.4V
= 2.5V
REF
IN
CC
REF
CC
REF
= 0V
–20
+
+
= GND
IN = GND
IN = GND
IN(CM)
–
–
= GND
IN = GND
IN = GND
f
O
–40
–40
f
= GND
= 25°C
= GND
T = 25°C
A
O
O
T
A
–60
–60
–80
–80
–100
–120
–140
–100
–120
302
300
–140
2.5
3.5
4.0
(V)
4.5
5.0
5.5
3.0
1
1k
10k 100k 1M
10
100
20 40
80
100 120 140 160 180 200 220
0
60
V
FREQUENCY AT V (Hz)
FREQUENCY AT V (Hz)
CC
CC
CC
2480 G27
2480 G28
2480 G29
Conversion Current
vs Temperature
Sleep Mode Current
vs Temperature
PSRR vs Frequency at VCC
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
–20
–40
200
180
f
= GND
V
V
= 4.1V DC 0.7V
= 2.5V
f
= GND
O
CC
REF
O
CS = V
CS = GND
SCK = NC
SDO = NC
SDI = GND
CC
+
IN = GND
SCK = NC
SDO = NC
SDI = GND
–
IN = GND
f
= GND
= 25°C
V
= 5V
CC
O
A
T
160
V
= 5V
CC
–60
–80
V
= 2.7V
CC
140
120
100
V
= 2.7V
CC
–100
–120
–140
–45 –30 –15
0
15 30 45 60 75 90
30650
30700
30800
30600
30750
–45 –30 –15
0
15 30 45 60 75 90
TEMPERATURE (°C)
FREQUENCY AT V (Hz)
TEMPERATURE (°C)
CC
2480 G32
2480 G30
2480 G31
2480fc
9
LTC2480
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (2x Speed
Mode; VCC = 5V, VREF = 5V)
Integral Nonlinearity (2x Speed
Mode; VCC = 5V, VREF = 2.5V)
Conversion Current
vs Output Data Rate
500
450
400
350
300
250
200
150
100
3
2
3
2
V
= V
CC
V
V
V
= 5V
V
V
V
= 5V
REF
CC
CC
+
IN = GND
= 5V
= 2.5V
REF
REF
–
IN = GND
= 2.5V
= 1.25V
IN(CM)
IN(CM)
SCK = NC
SDO = NC
SDI = GND
CS GND
F
= GND
F = GND
O
O
V
= 5V
CC
1
0
1
0
90°C
25°C, 90°C
F
= EXT OSC
= 25°C
O
A
T
V
= 3V
CC
–45°C, 25°C
–1
–2
–3
–1
–2
–3
–45°C
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2480 G33
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
–1.25 –0.75
–0.25
0.25
0.75
1.25
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2480 G34
2480 G35
Noise Histogram
(2x Speed Mode)
RMS Noise vs VREF
(2x Speed Mode)
Integral Nonlinearity (2x Speed
Mode; VCC = 2.7V, VREF = 2.5V)
1.0
0.8
0.6
0.4
0.2
0
3
2
16
14
12
10
8
RMS = 0.86μV
10,000 CONSECUTIVE
READINGS
V
V
V
F
= 2.7V
CC
AVERAGE = 0.184mV
= 2.5V
REF
IN(CM)
= GND
V
V
V
= 5V
= 5V
= 1.25V
CC
REF
IN
O
= 0V
1
0
GAIN = 256
= 25°C
90°C
T
A
6
–45°C, 25°C
–1
–2
–3
V
V
V
= 5V
= 0V
CC
IN
4
= GND
IN(CM)
2
F
= GND
O
T
A
= 25°C
0
0
1
2
3
4
5
–1.25 –0.75
–0.25
0.25
0.75
1.25
181.4
183.8
188.6
179
186.2
INPUT VOLTAGE (V)
V
(V)
OUTPUT READING (μV)
REF
2480 G38
2480 G36
2480 G37
Offset Error vs Temperature
(2x Speed Mode)
Offset Error vs VIN(CM)
(2x Speed Mode)
200
198
196
194
192
190
188
186
184
182
180
240
230
220
210
200
190
180
170
160
V
V
V
= 5V
REF
= 0V
= GND
= 25°C
CC
V
V
V
V
= 5V
CC
= 5V
= 5V
REF
IN
= 0V
IN
IN(CM)
F
O
= GND
= GND
T
A
F
O
–1
1
2
3
4
5
6
0
15 30
TEMPERATURE (°C)
–45 –30 –15
0
45 60 75 90
V
(V)
IN(CM)
2480 G39
2480 G40
2480fc
10
LTC2480
TYPICAL PERFORMANCE CHARACTERISTICS
Offset Error vs VREF
(2x Speed Mode)
PSRR vs Frequency at VCC
(2x Speed Mode)
Offset Error vs VCC
(2x Speed Mode)
250
200
150
100
50
0
–20
240
230
220
210
V
= 4.1V DC
V
V
V
f
= 2.5V
V
V
V
f
= 5V
= 0V
IN(CM)
= GND
= 25°C
CC
REF
CC
IN
+
REF = 2.5V
= 0V
IN
IN(CM)
–
REF = GND
= GND
= GND
+
–
IN = GND
= GND
= 25°C
O
O
–40
IN = GND
T
T
A
A
f
= GND
= 25°C
O
A
T
–60
200
190
–80
–100
–120
–140
180
170
160
0
10k
FREQUENCY AT V (Hz)
1M
2
2.5
3
3.5
V
4
4.5
5
5.5
1
2
4
1
10
100
1k
100k
0
5
3
(V)
V
(V)
CC
CC
REF
2480 G43
2480 G41
2480 G42
PSRR vs Frequency at VCC
(2x Speed Mode)
PSRR vs Frequency at VCC
(2x Speed Mode)
0
0
V
= 4.1V DC 1.4V
V
= 4.1V DC 0.7V
CC
CC
+
+
REF = 2.5V
REF = 2.5V
–20
–
–20
–
REF = GND
REF = GND
+
–
+
–
IN = GND
IN = GND
–40
IN = GND
–40 IN = GND
f
= GND
= 25°C
f
= GND
T = 25°C
A
O
O
T
A
–60
–80
–60
–80
–100
–120
–100
–120
–140
–140
30650
30700
30800
30600
30750
0
60
100 120 140 160 180 200 220
20 40
80
FREQUENCY AT V (Hz)
FREQUENCY AT V (Hz)
CC
CC
2480 G45
2480 G44
PIN FUNCTIONS
+
–
IN (Pin 4), IN (Pin 5): Differential Analog Inputs. The
SDI (Pin 1): Serial Data Input. This pin is used to select
the GAIN, line frequency rejection, input, temperature
sensor and 2x speed mode. Data is shifted into the SDI
pin on the rising edge of serial clock (SCK).
voltage on these pins can have any value between GND
– 0.3V and V + 0.3V. Within these limits the converter
CC
+
–
bipolar input range (V = IN – IN ) extends from –0.5
IN
• V /GAIN to 0.5 • V /GAIN. Outside this input range
REF
REF
V (Pin2):PositiveSupplyVoltage.BypasstoGND(Pin 8)
CC
the converter produces unique overrange and underrange
witha1μFtantalumcapacitorinparallelwith0.1μFceramic
output codes.
capacitor as close to the part as possible.
CS (Pin 6): Active LOW Chip Select. A LOW on this pin
enables the digital input/output and wakes up the ADC.
Following each conversion the ADC automatically enters
the sleep mode and remains in this low power state as
2480fc
V
(Pin 3): Positive Reference Input. The voltage on
REF
this pin can have any value between 0.1V and V . The
CC
negative reference input is GND (Pin 8).
11
LTC2480
PIN FUNCTIONS
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the data output transfer aborts the data transfer
and starts a new conversion.
data input/output period. In external serial clock operation
mode, SCK is used as the digital input for the external se-
rial interface clock during the data output period. A weak
internal pull-up is automatically activated in internal serial
clock operation mode. The serial clock operation mode
is determined by the logic level applied to the SCK pin at
power up or during the most recent falling edge of CS.
SDO (Pin 7): Three-State Digital Output. During the data
output period, this pin is used as the serial data output.
When the chip select CS is HIGH (CS = V ), the SDO pin
CC
is in a high impedance state. During the conversion and
sleep periods, this pin is used as the conversion status
output. The conversion status can be observed by pulling
CS LOW.
f (Pin 10): Frequency Control Pin. Digital input that
O
controls the conversion clock. When f is connected to
O
GND the converter uses its internal oscillator running at
307.2kHz.Theconversionclockmayalsobeoverriddenby
GND(Pin8):Ground.Sharedpinforanalogground,digital
groundandreferenceground.Shouldbeconnecteddirectly
to a ground plane through a minimum impedance.
driving the f pin with an external clock in order to change
O
the output rate or the digital filter rejection null.
GND (Exposed Pad Pin 11): This pin is ground and should
be soldered to the PCB ground plane. For prototyping
purposes, this pin may remain floating.
SCK (Pin 9): Bidirectional Digital Clock Pin. In internal
serial clock operation mode, SCK is used as the digital
output for the internal serial interface clock during the
FUNCTIONAL BLOCK DIAGRAM
2
V
REF
V
CC
3
+
IN
IN
SDI
+
4
5
REF
1
9
7
6
+
–
IN
IN
–
SCK
SD0
CS
SERIAL
INTERFACE
3RD ORDER
$3 ADC
MUX
(1-256)
GAIN
–
REF
F
O
TEMP
SENSOR
AUTOCALIBRATION
AND CONTROL
10
INTERNAL
OSCILLATOR
GND
8
2480 FD
V
CC
TEST CIRCUITS
1.69k
SDO
SDO
1.69k
C
LOAD
= 20pF
C
LOAD
= 20pF
Hi-Z TO V
Hi-Z TO V
OH
OH
OL
OL
V
OL
V
OH
TO V
V
OH
V
OL
TO V
TO Hi-Z
2480 TA02
TO Hi-Z
2480 TA03
2480fc
12
LTC2480
TIMING DIAGRAMS
Timing Diagram Using Internal SCK
CS
t
t
2
1
3
SDO
SCK
SDI
t
KQMIN
t
t
KQMAX
t
8
t
7
2480 TD1
SLEEP
DATA IN/OUT
CONVERSION
Timing Diagram Using External SCK
CS
SDO
SCK
t
1
t
2
t
5
t
KQMIN
t
t
6
4
t
KQMAX
t
8
t
7
SDI
2480 TD2
SLEEP
DATA IN/OUT
CONVERSION
APPLICATIONS INFORMATION
CONVERTER OPERATION
CONVERT
SLEEP
Converter Operation Cycle
The LTC2480 is a low power, delta-sigma analog-to-digi-
tal converter with an easy to use 4-wire serial interface
and automatic differential input current cancellation.
Its operation is made up of three states. The converter
operating cycle begins with the conversion, followed by
the low power sleep state and ends with the data output
(see Figure 1). The 4-wire interface consists of serial data
output (SDO), serial clock (SCK), chip select (CS) and
serial data input (SDI).
FALSE
CS = LOW
AND
SCK
TRUE
DATA OUTPUT
CONFIGURATION INPUT
2480 F01
Initially, the LTC2480 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
Figure 1. LTC2480 State Transition Diagram
2480fc
13
LTC2480
APPLICATIONS INFORMATION
While in this sleep state, power consumption is reduced
by two orders of magnitude. The part remains in the sleep
state as long as CS is HIGH. The conversion result is held
indefinitely in a static shift register while the converter is
in the sleep state.
current. This enables external RC networks and high
impedance sensors to directly interface to the LTC2480
without external amplifiers. The remaining common
mode input current is eliminated by either balancing
the differential input impedances or setting the common
mode input equal to the common mode reference (see
the Automatic Input Current Cancellation section). This
unique architecture does not require on-chip buffers
enabling input signals to swing all the way to ground
Once CS is pulled LOW, the device exits the low power
modeandentersthedataoutputstate. IfCSispulledHIGH
before the first rising edge of SCK, the device returns to
the low power sleep mode and the conversion result is
still held in the internal static shift register. If CS remains
LOW after the first rising edge of SCK, the device begins
outputting the conversion result. Taking CS high at this
point will terminate the data input and output state and
start a new conversion. The conversion result is shifted
out of the device through the serial data output pin (SDO)
on the falling edge of the serial clock (SCK) (see Figure 2).
The LTC2480 includes a serial data input pin (SDI) in
which data is latched by the device on the rising edge of
SCK (Figure 2). The bit stream applied to this pin can be
used to select various features of the LTC2480, including
an on-chip temperature sensor, programmable GAIN, line
frequency rejection and output data rate. Alternatively,
this pin may be tied to ground and the part will perform
conversions in a default state. In the default state (SDI
grounded) the device simply performs conversions on
the user applied input with a GAIN of 1 and simultaneous
rejection of 50Hz and 60Hz line frequencies.
and up to V . Furthermore, the cancellation does
CC
not interfere with the transparent offset and full-scale
auto-calibration and the absolute accuracy (full-scale
+ offset + linearity) is maintained even with external
RC networks.
Accessing the Special Features of the LTC2480
The LTC2480 combines a high resolution, low noise ΔΣ
analog-to-digital converter with an on-chip selectable
temperature sensor, programmable gain, programmable
digitalfilterandoutputratecontrol. Thesespecialfeatures
areselectedthroughasingle8-bitserialinputwordduring
the data input/output cycle (see Figure 2).
The LTC2480 powers up in a default mode commonly
used for most measurements. The device will remain in
this mode as long as the serial data input (SDI) is low.
In this default mode, the measured input is external, the
GAIN is 1, the digital filter simultaneously rejects 50Hz
and 60Hz line frequency noise, and the speed mode is 1x
(offset automatically, continuously calibrated).
ThroughtimingcontroloftheCSandSCKpins,theLTC2480
offers several flexible modes of operation (internal or
external SCK and free-running conversion modes). These
variousmodesdonotrequireprogrammingconfiguration
registers;moreover,theydonotdisturbthecyclicoperation
described above. These modes of operation are described
in detail in the Serial Interface Timing Modes section.
A simple serial interface grants access to any or all special
functionscontainedwithintheLTC2480.Inordertochange
the mode of operation, an enable bit (EN) followed by up
to 7 bits of data are shifted into the device (see Table 1).
The first 3 bits (GS2, GS1, GS0) control the GAIN of the
converter from 1 to 256. The 4th bit (IM) is used to select
the internal temperature sensor as the conversion input,
while the 5th and 6th bits (FA, FB) combine to determine
the line frequency rejection mode. The 7th bit (SPD) is
used to double the output rate by disabling the offset auto
calibration.
Easy Drive Input Current Cancellation
TheLTC2480combinesahighprecisiondelta-sigmaADC
with an automatic differential input current cancellation
front end. A proprietary front-end passive sampling
network transparently removes the differential input
2480fc
14
LTC2480
APPLICATIONS INFORMATION
CS
BIT 23
EOC
BIT 22
DMY
BIT 21 BIT 20 BIT 19 BIT 18
BIT 4
LSB
BIT 3
GS2
BIT 2
GS1
BIT 1 BIT 0
GS0 IM
SDO
SIG
MSB
B16
Hi-Z
CONVERSION RESULT
PREVIOUS
CONFIGURATION BITS
SCK
SDI
EN
GS2
GS1
GS0
IM
FA
FB
SPD
DON’T CARE
CONVERSION
SLEEP
DATA INPUT/OUTPUT
2480 F02
Figure 2. Input/Output Data Timing
Table 1. Selecting Special Modes
Rejection
Mode
Gain
EN GS2 GS1 GS0 IM FA FB SPD
Comments
Keep Previous Mode
External Input, Gain = 1, Autocalibration
External Input, Gain = 4, Autocalibration
External Input, Gain = 8, Autocalibration
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
External Input, Gain = 16, Autocalibration
External Input, Gain = 32, Autocalibration
External Input, Gain = 64, Autocalibration
External Input, Gain = 128, Autocalibration
External Input, Gain = 256, Autocalibration
External Input, Gain = 1, 2x Speed
External Input, Gain = 2, 2x Speed
External Input, Gain = 4, 2x Speed
External Input, Gain = 8, 2x Speed
External Input, Gain = 16, 2x Speed
External Input, Gain = 32, 2x Speed
External Input, Gain = 64, 2x Speed
External Input, Gain = 128, 2x Speed
External Input, Simultaneous 50Hz/60Hz Rejection
External Input, 50Hz Rejection
External Input, 60Hz Rejection
Reserved, Do Not Use
Temperature Input, 50Hz/60Hz Rejection, Gain = 1, Autocalibration
Temperature Input, 50Hz Rejection, Gain = 1, Autocalibration
Temperature Input, 60Hz Rejection, Gain = 1, Autocalibration
Reserved, Do Not Use
Any
Rejection
Mode
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Any
Speed
Any Gain
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2480 TBL1
2480fc
15
LTC2480
APPLICATIONS INFORMATION
Table 2a. The LTC2480 Performance vs GAIN in Normal Speed Mode (VCC = 5V, VREF = 5V)
GAIN
1
2.5
4
0.625
9.54
65536
5
8
0.312
4.77
65536
5
16
0.156
2.38
65536
5
32
78m
1.19
65536
5
64
39m
0.596
65536
5
128
19.5m
0.298
32768
5
256
9.76m
0.149
16384
8
UNIT
V
Input Span
LSB
38.1
65536
5
μV
Noise Free Resolution*
Gain Error
Offset Error
Counts
ppm of FS
μV
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Table 2b. The LTC2480 Performance vs GAIN in 2x Speed Mode (VCC = 5V, VREF = 5V)
GAIN
1
2.5
2
1.25
19.1
65536
5
4
8
16
0.156
2.38
65536
5
32
78m
1.19
65536
5
64
39m
0.596
45875
5
128
19.5m
0.298
22937
5
UNIT
V
Input Span
LSB
0.625
9.54
65536
5
0.312
4.77
65536
5
38.1
65536
5
μV
Noise Free Resolution*
Gain Error
Offset Error
Counts
ppm of FS
μV
200
200
200
200
200
200
200
200
*The resolution in counts is calculated as the FS divided by LSB or the RMS noise value, whichever is larger.
GAIN (GS2, GS1, GS0)
Rejection Mode (FA, FB)
The input referred gain of the LTC2480 is adjustable from
1 to 256. With a gain of 1, the differential input range is
The LTC2480 includes a high accuracy on-chip oscilla-
tor with no required external components. Coupled with
a 4th order digital lowpass filter, the LTC2480 rejects
line frequency noise. In the default mode, the LTC2480
simultaneously rejects 50Hz and 60Hz by at least 87dB.
The LTC2480 can also be configured to selectively reject
50Hz or 60Hz to better than 110dB.
V
/2 and the common mode input range is rail-to-rail.
REF
As the GAIN is increased, the differential input range is re-
ducedto V /2•GAINbutthecommonmodeinputrange
REF
remains rail-to-rail. As the differential gain is increased,
low level voltages are digitized with greater resolution. At
a gain of 256, the LTC2480 digitizes an input signal range
of 9.76mV with over 16,000 counts.
Speed Mode (SPD)
The LTC2480 continuously performs offset calibrations.
Everyconversioncycle,twoconversionsareautomatically
performed (default) and the results combined. This result
isfreefromoffsetanddrift.Inapplicationswheretheoffset
is not critical, the autocalibration feature can be disabled
with the benefit of twice the output rate.
Temperature Sensor (IM)
The LTC2480 includes an on-chip temperature sensor.
The temperature sensor is selected by setting IM = 1 in
the serial input data stream. Conversions are performed
directly on the temperature sensor by the converter. While
operating in this mode, the device behaves as a tempera-
ture to bits converter. The digital reading is proportional
to the absolute temperature of the device. This feature
allows the converter to linearize temperature sensors or
continuously remove temperature effects from external
sensors. Several applications leveraging this feature are
presented in more detail in the applications section. While
operating in this mode, the gain is set to 1 and the speed
is set to normal independent of the control bits (GS2,
GS1, GS0 and SPD).
Linearity, full-scale accuracy and full-scale drift are identi-
cal for both 2x and 1x speed modes. In both the 1x and
2x speed there is no latency. This enables input steps or
multiplexer channel changes to settle in a single conver-
sion cycle easing system overhead and increasing the
effective conversion rate.
2480fc
16
LTC2480
APPLICATIONS INFORMATION
Output Data Format
Bit 21 (third output bit) is the conversion result sign
indicator (SIG). If V is >0, this bit is HIGH. If V is <0,
IN
IN
The LTC2480 serial output data stream is 24 bits long.
The first 3 bits represent status information indicating
the sign and conversion state. The next 17 bits are the
conversion result, MSB first. The remaining 4 bits indicate
the configuration state associated with the current con-
version result. The third and fourth bit together are also
used to indicate an underrange condition (the differential
input voltage is below –FS) or an overrange condition (the
differential input voltage is above +FS).
this bit is LOW.
Bit20(fourthoutputbit)isthemostsignificantbit(MSB)of
the result. This bit in conjunction with bit 21 also provides
the underrange or overrange indication. If both bit 21 and
bit 20 are HIGH, the differential input voltage is above +FS.
If both bit 21 and bit 20 are LOW, the differential input
voltage is below –FS.
The function of these bits is summarized in Table 3.
In applications where the processor generates 32 clock
cycles, or to remain compatible with higher resolution
converters, the LTC2480’s digital interface will ignore
extra clock edges seen during the next conversion period
after the 24th and output “1” for the extra clock cycles.
Furthermore, CS may be pulled high prior to outputting
all 24 bits, aborting the data out transfer and initiating a
new conversion.
Table 3. LTC2480 Status Bits
BIT 23
EOC
BIT 22
DMY
BIT 21
SIG
BIT 20
MSB
INPUT RANGE
≥ 0.5 • V
V
0
0
0
0
0
0
0
0
1
1/0
0
1
0
1
0
IN
REF
0V ≤ V < 0.5 • V
IN
REF
–0.5 • V ≤ V < 0V
REF
IN
V
< –0.5 • V
0
IN
REF
Bits 20-4 are the 16-bit plus sign conversion result MSB
first.
Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bits 3-0 are the corresponding configuration bits for the
present conversion result. Bits 3-1 are the gain set bits
and bit 0 is IM (see Figure 2).
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
Data is shifted out of the SDO pin under control of the
serial clock (SCK) (see Figure 2). Whenever CS is HIGH,
Table 4. LTC2480 Output Data Format
DIFFERENTIAL INPUT VOLTAGE
V *
BIT 23
EOC
BIT 22
DMY
BIT 21
SIG
BIT 20
MSB
BIT 19
BIT 18
BIT 17
…
BIT 4
IN
V * ≥ FS**
FS** – 1LSB
0
0
0
0
1
1
1
0
0
1
0
1
0
1
…
…
0
1
IN
0.5 • FS**
0.5 • FS** – 1LSB
0
0
0
0
1
1
0
0
1
0
0
1
0
1
…
…
0
1
0
0
0
0
0
1/0***
0
0
1
0
1
0
1
0
1
…
…
0
1
–1LSB
–0.5 • FS**
–0.5 • FS** – 1LSB
0
0
0
0
0
0
1
1
1
0
0
1
0
1
…
…
0
1
–FS**
0
0
0
0
0
0
1
0
0
1
0
1
0
1
…
…
0
1
V * < –FS**
IN
+
–
* The differential input voltage V = IN – IN .
** The full-scale voltage FS = 0.5 • V
*** The sign bit changes state during the 0 output code when the device is operating in the 2× speed mode.
IN
.
REF
2480fc
17
LTC2480
APPLICATIONS INFORMATION
SDO remains high impedance and any externally gener-
ated SCK clock pulses are ignored by the internal data
out shift register.
or better than 87dB normal mode rejection from 48Hz to
62.4Hz. The rejection mode is selected by writing to the
on-chip configuration register and the default mode at
POR is simultaneous 50Hz/60Hz rejection.
In order to shift the conversion result out of the device,
CS must first be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes in real
time from HIGH to LOW at the completion of a conversion.
This signal may be used as an interrupt for an external
microcontroller. Bit 23 (EOC) can be captured on the first
rising edge of SCK. Bit 22 is shifted out of the device on
the first falling edge of SCK. The final data bit (bit 0) is
shifted out on the falling edge of the 23rd SCK and may
be latched on the rising edge of the 24th SCK pulse. On
the falling edge of the 24th SCK pulse, SDO goes HIGH
indicating the initiation of a new conversion cycle. This
bit serves as EOC (bit 23) for the next conversion cycle.
Table 4 summarizes the output data format.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2480 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the f pin and turns off the internal oscillator.
O
The frequency f
of the external signal must be at least
EOSC
10kHz to be detected. The external clock signal duty cycle
is not significant as long as the minimum and maximum
specifications for the high and low periods t
are observed.
and t
HEO
LEO
While operating with an external conversion clock of a
frequency f , the LTC2480 provides better than 110dB
EOSC
+
–
As long as the voltage on the IN and IN pins is main-
normal mode rejection in a frequency range of f
4ꢀ and its harmonics. The normal mode rejection as a
function of the input frequency deviation from f
is shown in Figure 3.
/5120
EOSC
tainedwithinthe–0.3Vto(V +0.3V)absolutemaximum
CC
operating range, a conversion result is generated for any
/5120
EOSC
differential input voltage V from –FS = –0.5 • V /GAIN
IN
REF
to +FS = 0.5 • V /GAIN. For differential input voltages
REF
–80
–85
greater than +FS, the conversion result is clamped to the
value corresponding to the +FS + 1LSB. For differential
inputvoltagesbelow–FS,theconversionresultisclamped
to the value corresponding to –FS – 1LSB.
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a SINC or Comb filter). For
high resolution, low frequency applications, this filter is
typicallydesignedtorejectlinefrequenciesof50Hzor60Hz
plus their harmonics. The filter rejection performance is
directly related to the accuracy of the converter system
clock.TheLTC2480incorporatesahighlyaccurateon-chip
oscillator. This eliminates the need for external frequency
setting components such as crystals or oscillators.
–12
–8
–4
0
4
8
12
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY f
/5120(ꢀ)
EOSC
2480 F03
Figure 3. LTC2480 Normal Mode Rejection When Using
an External Oscillator
Whenever an external clock is not present at the f pin,
O
the converter automatically activates its internal oscilla-
tor and enters the internal conversion clock mode. The
LTC2480 operation will not be disturbed if the change of
conversion clock source occurs during the sleep state
or during the data output state while the converter uses
2480fc
Frequency Rejection Selection (f )
O
TheLTC2480internaloscillatorprovidesbetterthan110dB
normal mode rejection at the line frequency and all its
harmonics (up to the 255th) for 50Hz 2ꢀ or 60Hz 2ꢀ,
18
LTC2480
APPLICATIONS INFORMATION
Table 5. LTC2480 State Duration
STATE
OPERATING MODE
DURATION
CONVERT
Internal Oscillator
60Hz Rejection
133ms, Output Data Rate ≤ 7.5 Readings/s for 1x Speed Mode
67ms, Output Data Rate ≤ 15 Readings/s for 2x Speed Mode
50Hz Rejection
160ms, Output Data Rate ≤ 6.2 Readings/s for 1x Speed Mode
80ms, Output Data Rate ≤ 12.5 Readings/s for 2x Speed Mode
50Hz/60Hz Rejection
147ms, Output Data Rate ≤ 6.8 Readings/s for 1x Speed Mode
73.6ms, Output Data Rate ≤ 13.6 Readings/s for 2x Speed Mode
External Oscillator
f = External Oscillator
41036/f
s, Output Data Rate ≤ f
/41036 Readings/s for
O
EOSC
EOSC
with Frequency f
kHz
1x Speed Mode
20556/f s, Output Data Rate ≤ f
EOSC
(f
/5120 Rejection)
EOSC
/20556 Readings/s for
EOSC
EOSC
2x Speed Mode
SLEEP
As Long As CS = HIGH, After a Conversion is Complete
DATA OUTPUT
Internal Serial Clock
f = LOW/HIGH
As Long As CS = LOW But Not Longer Than 0.62ms
(24 SCK Cycles)
O
(Internal Oscillator)
f = External Oscillator with
As Long As CS = LOW But Not Longer Than 192/f
ms
EOSC
O
Frequency f
kHz
(24 SCK Cycles)
EOSC
External Serial Clock with
As Long As CS = LOW But Not Longer Than 24/f ms
SCK
Frequency f
kHz
(24 SCK Cycles)
SCK
an external serial clock. If the change occurs during the
conversion state, the result of the conversion in progress
may be outside specifications but the following conver-
sions will not be affected. If the change occurs during the
data output state and the converter is in the Internal SCK
mode, the serial clock duty cycle may be affected but the
serial data stream will remain valid.
Power-Up Sequence
The LTC2480 automatically enters an internal reset state
when the power supply voltage V drops below ap-
proximately 2V. This feature guarantees the integrity of
the conversion result and of the serial interface mode
selection.
CC
When the V voltage rises above this critical threshold,
CC
Table 5 summarizes the duration of each state and the
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 4ms. The POR
signalclearsallinternalregisters.FollowingthePORsignal,
the LTC2480 starts a normal conversion cycle and follows
the succession of states described in Figure 1. The first
conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
achievable output data rate as a function of f .
O
Ease of Use
The LTC2480 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
The LTC2480 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
theuserandhasnoeffectonthecyclicoperationdescribed
above. Theadvantageofcontinuouscalibrationisextreme
stability of offset and full-scale readings with respect to
time, supply voltage change and temperature drift.
On-Chip Temperature Sensor
The LTC2480 contains an on-chip PTAT (proportional to
absolutetemperature)signalthatcanbeusedasatempera-
turesensor. TheinternalPTAThasatypicalvalueof420mV
at 27°C and is proportional to the absolute temperature
2480fc
19
LTC2480
APPLICATIONS INFORMATION
value with a temperature coefficient of 420/(27 + 273) =
1.40mV/°C (SLOPE), as shown in Figure 4. The internal
PTAT signal is used in a single-ended mode referenced
to device ground internally. The GAIN is automatically
set to one (independent of the values of GS0, GS1, GS2)
in order to preserve the PTAT property at the ADC output
code and avoid an out of range error. The 1x speed mode
with automatic offset calibration is automatically selected
for the internal PTAT signal measurement as well.
If the same V
source is used during calibration and
REF
temperature measurement, the actual value of the V
REF
is not needed to measure the temperature as shown in
the calculation below:
RSDO • VREF
TC =
– 273
SLOPE
RSDO
R0SDO
=
• T0 + 273 – 273
(
)
600
V
= 5V
CC
Reference Voltage Range
IM = 1
= GND
F
O
The LTC2480 external reference voltage range is 0.1V
SLOPE = 1.40mV/°C
500
400
300
200
to V . The converter output noise is determined by
CC
the thermal noise of the front-end circuits, and as such,
its value in nanovolts is nearly constant with reference
voltage. Since the transition noise (600nV) is much less
than the quantization noise (V /217), a decrease in the
REF
reference voltage will increase the converter resolution. A
reduced reference voltage will also improve the converter
performance when operated with an external conversion
–60
–30
0
30
60
90
120
2480 F04
TEMPERATURE (°C)
clock (external f signal) at substantially higher output
O
data rates (see the Output Data Rate section). V must
Figure 4. Internal PTAT Signal vs Temperature
REF
be ≥1.1V to use the internal temperature sensor.
When using the internal temperature sensor, if the output
code is normalized to R
is calculated using the following formula:
The negative reference input to the converter is internally
tied to GND. GND (Pin 8) should be connected to a ground
plane through as short a trace as possible to minimize
voltage drop. The LTC2480 has an average operational
current of 160μA and for 0.1Ω parasitic resistance, the
voltage drop of 16μV causes a gain error of 3.2ppm for
= V
/V , the temperature
SDO
PTAT REF
RSDO • VREF
TK =
and
TC =
in Kelvin
SLOPE
V
REF
= 5V.
RSDO • VREF
SLOPE
– 273 in °C
Input Voltage Range
where SLOPE is nominally 1.4mV/°C.
Theanaloginputistrulydifferentialwithanabsolute/com-
+
–
mon mode range for the IN and IN input pins extending
Since the PTAT signal can have an initial value variation
which results in errors in SLOPE, to achieve better tem-
perature measurements, a one-time calibration is needed
to adjust the SLOPE value. The converter output of the
from GND – 0.3V to V + 0.3V. Outside these limits, the
CC
ESD protection devices begin to turn on and the errors
due to input leakage current increase rapidly. Within these
limits, the LTC2480 converts the bipolar differential input
PTAT signal, R0 , is measured at a known temperature
SDO
+
–
signal, V = IN – IN , from –FS to +FS where FS = 0.5 •
REF
T0 (in °C) and the SLOPE is calculated as:
IN
V
/GAIN. Outside this range, the converter indicates the
R0SDO • VREF
SLOPE =
overrangeortheunderrangeconditionusingdistinctoutput
codes.Sincethedifferentialinputcurrentcancellationdoes
not rely on an on-chip buffer, current cancellation as well
T0 + 273
This calibrated SLOPE can be used to calculate the tem-
perature.
as DC performance is maintained rail-to-rail.
2480fc
20
LTC2480
APPLICATIONS INFORMATION
+
–
Input signals applied to IN and IN pins may extend by
3-or4-wireI/O,singlecycleorcontinuousconversion.The
following sections describe each of these serial interface
timing modes in detail. In all these cases, the converter
300mV below ground and above V . In order to limit any
CC
fault current, resistors of up to 5k may be added in series
+
–
withtheIN andIN pinswithoutaffectingtheperformance
of the devices. The effect of the series resistance on the
converter accuracy can be evaluated from the curves
presentedintheInputCurrent/ReferenceCurrentsections.
In addition, series resistors will introduce a temperature
dependent offset error due to the input leakage current.
A 1nA input leakage current will develop a 1ppm offset
can use the internal oscillator (f = LOW or f = HIGH)
O
O
or an external oscillator connected to the f pin. Refer to
O
Table 6 for a summary.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift
out the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 5.
error on a 5k resistor if V
= 5V. This error has a very
REF
strong temperature dependency.
Serial Interface Timing Modes
The serial clock mode is selected on the falling edge
of CS. To select the external serial clock mode, the
serial clock pin (SCK) must be LOW during each CS
falling edge.
The LTC2480’s 4-wire interface is SPI and MICROWIRE
compatible. This interface offers several flexible modes of
operation. These include internal/external serial clock,
Table 6. LTC2480 Interface Timing Modes
CONVERSION
DATA OUTPUT
CONTROL
CONNECTION
CONFIGURATION
SCK SOURCE
External
CYCLE CONTROL
AND WAVEFORMS
External SCK, Single Cycle Conversion
External SCK, 3-Wire I/O
CS and SCK
SCK
CS and SCK
SCK
Figures 5, 6
Figure 7
External
Internal SCK, Single Cycle Conversion
Internal SCK, 3-Wire I/O, Continuous Conversion
Internal
Figures 8, 9
Figure 10
CS↓
CS↓
Internal
Continuous
Internal
2.7V TO 5.5V
1μF
2
10
INT/EXT CLOCK
V
V
F
O
CC
LTC2480
3
1
REFERENCE
SDI
REF
VOLTAGE
9
SCK
0.1V TO V
CC
4-WIRE
SPI INTERFACE
7
8
SDO
CS
4
5
6
+
IN
IN
ANALOG
INPUT
–
TEST EOC
(OPTIONAL)
GND
CS
TEST EOC
TEST EOC
BIT 23
BIT 22
BIT 21
SIG
BIT 20
MSB
BIT 19
BIT 18
BIT 17
BIT 16
BIT 4
LSB
BIT 0
IM
SDO
EOC
Hi-Z
Hi-Z
Hi-Z
SCK
(EXTERNAL)
SDI*
DON’T CARE
DON’T CARE
EN
GS2
GS1
GS0
IM
FA
FB
DATA OUTPUT
SPD
CONVERSION
CONVERSION
2480 F05
SLEEP
SLEEP
Figure 5. External Serial Clock, Single Cycle Operation
2480fc
21
LTC2480
APPLICATIONS INFORMATION
2.7V TO 5.5V
1μF
2
10
INT/EXT CLOCK
V
V
F
O
CC
LTC2480
3
1
9
REFERENCE
VOLTAGE
0.1V TO V
SDI
REF
SCK
CC
4-WIRE
SPI INTERFACE
7
8
SDO
CS
4
5
6
+
IN
IN
ANALOG
INPUT
–
GND
TEST EOC
(OPTIONAL)
CS
TEST EOC
TEST EOC
BIT 0
BIT 23
BIT 22
BIT 21
BIT 20
MSB
BIT 19
BIT 18
BIT 17
BIT 16
BIT 9
BIT 8
SDO
EOC
EOC
SIG
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCK
(EXTERNAL)
SDI*
DON’T CARE
CONVERSION
DON’T CARE
EN
GS2
GS1
GS0
IM
FA
FB
SPD
SLEEP
DATA OUTPUT
CONVERSION
2480 F06
DATA
OUTPUT
SLEEP
SLEEP
Figure 6. External Serial Clock, Reduced Data Output Length
2.7V TO 5.5V
1μF
2
10
INT/EXT CLOCK
V
V
F
O
CC
LTC2480
3
1
9
REFERENCE
VOLTAGE
SDI
REF
SCK
0.1V TO V
3-WIRE
SPI INTERFACE
CC
7
SDO
CS
4
5
6
8
+
IN
IN
ANALOG
INPUT
–
GND
CS
BIT 23
BIT 22
BIT 21
SIG
BIT 20
MSB
BIT 19
BIT 18
BIT 17
BIT 16
BIT 4
LSB
BIT 0
IM
SDO
EOC
SCK
(EXTERNAL)
SDI*
DON’T CARE
DON’T CARE
EN
GS2
GS1
GS0
IM
FA
FB
DATA OUTPUT
SPD
CONVERSION
CONVERSION
2480 F07
Figure 7. External Serial Clock, CS = 0 Operation
2480fc
22
LTC2480
APPLICATIONS INFORMATION
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0
if the device is in the sleep state. Independent of CS, the
deviceautomaticallyentersthelowpowersleepstateonce
the conversion is complete.
time CS is pulled HIGH, the SDI information is discarded
and the previous configuration is kept. This is useful for
systems not requiring all 24 bits of output data, aborting
an invalid conversion cycle or synchronizing the start of
a conversion.
External Serial Clock, 3-Wire I/O
This timing mode utilizes a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 7. CS
may be permanently tied to ground, simplifying the user
interface or transmission over an isolation barrier.
When the device is in the sleep state, its conversion result
isheldinaninternalstaticshiftregister.Thedeviceremains
in the sleep state until the first rising edge of SCK is seen
while CS is LOW. The input data is then shifted in via the
SDI pin on the rising edge of SCK (including the first rising
edge) and the output data is shifted out of the SDO pin on
each falling edge of SCK. This enables external circuitry
to latch the output on the rising edge of SCK. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result can be latched on the 24th rising
edge of SCK. On the 24th falling edge of SCK, the device
begins a new conversion. SDO goes HIGH (EOC = 1)
indicating a conversion is in progress. In applications
where the processor generates 32 clock cycles, or to
remain compatible with higher resolution converters, the
LTC2480’s digital interface will ignore extra clock edges
seen during the next conversion period after the 24th and
outputs “1” for the extra clock cycles.
The external serial clock mode is selected at the end of
the power-on reset (POR) cycle. The POR cycle is con-
cluded typically 4ms after V exceeds approximately 2V.
CC
The level applied to SCK at this time determines if SCK
is internal or external. SCK must be driven LOW prior to
the end of POR in order to enter the external serial clock
timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can
be continuously monitored at the SDO pin during the
convertandsleepstates. EOCmaybeusedasaninterrupt
to an external controller indicating the conversion result
is ready. EOC = 1 while the conversion is in progress and
EOC = 0 once the conversion ends. On the falling edge
of EOC, the conversion result is loaded into an internal
static shift register. The input data is then shifted in via
the SDI pin on the rising edge of SCK (including the first
rising edge) and the output data is shifted out of the SDO
pin on each falling edge of SCK. EOC can be latched on
the first rising edge of SCK. On the 24th falling edge of
SCK, SDO goes HIGH (EOC = 1) indicating a new con-
version has begun. In applications where the processor
generates 32 clock cycles, or to remain compatible
with higher resolution converters, the LTC2480’s digital
interface will ignore extra clock edges seen during the
next conversion period after the 24th and outputs “1”
for the extra clock cycles.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time
in order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pull-
ing CS HIGH anytime between the first rising edge and
the 24th falling edge of SCK (see Figure 6). On the rising
edge of CS, the device aborts the data output state and
immediately initiates a new conversion. If the device has
not finished loading the last input bit SPD of SDI by the
2480fc
23
LTC2480
APPLICATIONS INFORMATION
Internal Serial Clock, Single Cycle Operation
rising edge of SCK. In the internal SCK timing mode, SCK
goes HIGH and the device begins outputting data at time
This timing mode uses an internal serial clock to shift out
theconversionresultandaCSsignaltomonitorandcontrol
the state of the conversion cycle, see Figure 8.
t
after the falling edge of CS (if EOC = 0) or t
EOCtest
EOCtest
after EOC goes LOW (if CS is LOW during the falling edge
of EOC). The value of t is 12μs if the device is using
EOCtest
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resis-
tor is active on the SCK pin during the falling edge of CS;
therefore,theinternalserialclocktimingmodeisautomati-
cally selected if SCK is not externally driven.
itsinternaloscillator. Iff isdrivenbyanexternaloscillator
O
of frequency f
, then t
is 3.6/f
EOCtest
in seconds. If
EOSC
EOCtest
EOSC
CS is pulled HIGH before time t
, the device returns
to the sleep state and the conversion result is held in the
internal static shift register.
If CS remains LOW longer than t
, the first rising
EOCtest
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data I/O cycle concludes
after the 24th rising edge. The input data is shifted in via
the SDI pin on the rising edge of SCK (including the first
rising edge) and the output data is shifted out of the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
EOC can be latched on the first rising edge of SCK and the
last bit of the conversion result on the 24th rising edge of
SCK.Afterthe24thrisingedge,SDOgoesHIGH(EOC = 1),
SCK stays HIGH and a new conversion starts.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC
= 0), the device will exit the low power mode during the
EOC test. In order to allow the device to return to the low
power sleep state, CS must be pulled HIGH before the first
2.7V TO 5.5V
1μF
2
3
10
INT/EXT CLOCK
V
V
F
O
CC
V
CC
LTC2480
1
9
REFERENCE
VOLTAGE
10k
SDI
REF
SCK
0.1V TO V
CC
4-WIRE
SPI INTERFACE
7
8
SDO
CS
4
5
6
+
IN
IN
ANALOG
INPUT
TEST EOC
–
GND
<t
EOCtest
CS
TEST EOC
BIT 23
EOC
BIT 22
BIT 21
SIG
BIT 20
MSB
BIT 19
BIT 18
BIT 17
BIT 16
BIT 4
LSB
BIT 0
IM
SDO
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCK
(INTERNAL)
SDI*
DON’T CARE
CONVERSION
DON’T CARE
EN
GS2
GS1
GS0
IM
FA
FB
SPD
DATA OUTPUT
CONVERSION
2480 F08
SLEEP
SLEEP
Figure 8. Internal Serial Clock, Single Cycle Operation
2480fc
24
LTC2480
APPLICATIONS INFORMATION
CS remains LOW during the data output state. However,
the data output state may be aborted by pulling CS HIGH
anytime between thefirstand 24th rising edge ofSCK(see
Figure 9). On the rising edge of CS, the device aborts the
data output state and immediately initiates a new conver-
sion. If the device has not finished loading the last input
bit SPD of SDI by the time CS is pulled HIGH, the SDI
information is discarded and the previous configuration
is still kept. This is useful for systems not requiring all 24
bits of output data, aborting an invalid conversion cycle,
or synchronizing the start of a conversion. If CS is pulled
HIGH while the converter is driving SCK LOW, the internal
pull-upisnotavailabletorestoreSCKtoalogicHIGHstate.
This will cause the device to exit the internal serial clock
mode on the next falling edge of CS. This can be avoided
by adding an external 10k pull-up resistor to the SCK pin
or by never pulling CS HIGH when SCK is LOW.
certainapplicationsmayrequireanexternaldriveronSCK.
If this driver goes Hi-Z after outputting a LOW signal, the
LTC2480’s internal pull-up remains disabled. Hence, SCK
remains LOW. On the next falling edge of CS, the device is
switched to the external SCK timing mode. By adding an
external 10k pull-up resistor to SCK, this pin goes HIGH
once the external driver goes Hi-Z. On the next CS falling
edge, the device will remain in the internal SCK timing
mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. Once CS goes HIGH (within the time
period defined above as t ), the internal pull-up is
EOCtest
activated. For a heavy capacitive load on the SCK pin, the
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
Whenever SCK is LOW, the LTC2480’s internal pull-up at
pinSCKisdisabled. Normally, SCKisnotexternallydriven
if the device is in the internal SCK timing mode. However,
2.7V TO 5.5V
1μF
2
3
10
INT/EXT CLOCK
V
V
F
O
CC
V
CC
10k
LTC2480
1
9
REFERENCE
VOLTAGE
SDI
REF
SCK
0.1V TO V
CC
4-WIRE
SPI INTERFACE
7
8
SDO
CS
4
5
6
+
IN
IN
TEST EOC
(OPTIONAL)
ANALOG
INPUT
–
GND
>t
<t
EOCtest
EOCtest
CS
TEST EOC
TEST EOC
BIT 0
EOC
BIT 23
EOC
BIT 22
BIT 21
SIG
BIT 20
MSB
BIT 19
BIT 18
BIT 17
BIT 16
BIT 8
SDO
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCK
(INTERNAL)
SDI*
DON’T CARE
CONVERSION
DON’T CARE
CONVERSION
EN
GS2
GS1
GS0
IM
FA
FB
SPD
SLEEP
DATA OUTPUT
DATA
OUTPUT
2480 F09
SLEEP
SLEEP
Figure 9. Internal Serial Clock, Reduce Data Output Length
2480fc
25
LTC2480
APPLICATIONS INFORMATION
Internal Serial Clock, 3-Wire I/O,
Continuous Conversion
period) then immediately begins outputting data. The
data input/output cycle begins on the first rising edge of
SCK and ends after the 24th rising edge. The input data
is then shifted in via the SDI pin on the rising edge of
SCK (including the first rising edge) and the output data
is shifted out of the SDO pin on each falling edge of SCK.
The internally generated serial clock is output to the SCK
pin. This signal may be used to shift the conversion result
into external circuitry. EOC can be latched on the first ris-
ing edge of SCK and the last bit of the conversion result
can be latched on the 24th rising edge of SCK. After the
24th rising edge, SDO goes HIGH (EOC = 1) indicating a
new conversion is in progress. SCK remains HIGH during
the conversion.
This timing mode uses a 3-wire interface. The conversion
result is shifted out of the device by an internally gener-
ated serial clock (SCK) signal, see Figure 10. CS may be
permanently tied to ground, simplifying the user interface
or transmission over an isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after V exceeds 2V. An internal weak
CC
pull-upisactiveduringthePORcycle;therefore,theinternal
serial clock timing mode is automatically selected if SCK
is not externally driven LOW (if SCK is loaded such that
the internal pull-up cannot pull the pin HIGH, the external
SCK mode will be selected).
Preserving the Converter Accuracy
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating
the conversion has finished and the device has entered
the low power sleep state. The part remains in the sleep
state a minimum amount of time (1/2 the internal SCK
The LTC2480 is designed to reduce as much as possible
theconversionresultsensitivitytodevicedecoupling,PCB
layout, anti-aliasing circuits, line frequency perturbations
and so on. Nevertheless, in order to preserve the 24-bit
accuracy capability of this part, some simple precautions
are required.
2.7V TO 5.5V
1μF
2
10
INT/EXT CLOCK
V
V
F
O
CC
V
CC
10k
LTC2480
3
1
9
REFERENCE
SDI
REF
VOLTAGE
SCK
0.1V TO V
CC
3-WIRE
SPI INTERFACE
7
SDO
CS
4
5
6
8
+
IN
IN
ANALOG
INPUT
–
GND
CS
BIT 23
BIT 22
BIT 21
SIG
BIT 20
MSB
BIT 19
BIT 18
BIT 17
BIT 16
BIT 4
LSB
BIT 0
IM
SDO
EOC
SCK
(INTERNAL)
SDI*
DON’T CARE
CONVERSION
DON’T CARE
EN
GS2
GS1
GS0
IM
FA
FB
DATA OUTPUT
SPD
CONVERSION
2480 F10
Figure 10. Internal Serial Clock, CS = 0 Continuous Operation
2480fc
26
LTC2480
APPLICATIONS INFORMATION
Digital Signal Levels
Parallel termination near the LTC2480 pin will eliminate
this problem but will increase the driver power dissipa-
tion. A series resistor between 27Ω and 56Ω placed near
the driver output pin will also eliminate this problem
without additional power dissipation. The actual resistor
value depends upon the trace impedance and connection
topology.
The LTC2480’s digital interface is easy to use. Its digital
inputs (SDI, f , CS and SCK in External SCK mode of
O
operation) accept standard CMOS logic levels and the
internal hysteresis receivers can tolerate edge transition
times as slow as 100μs. However, some considerations
are required to take advantage of the exceptional accuracy
and low supply current of this converter.
Analternatesolutionistoreducetheedgerateofthecontrol
signals. It should be noted that using very slow edges will
increase the converter power supply current during the
transition time. The differential input architecture reduces
the converter’s sensitivity to ground currents.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
Particular attention must be given to the connection of
(V – 0.5V), the CMOS input receiver draws additional
CC
the f signal when the LTC2480 is used with an external
O
current from the power supply. It should be noted that,
conversion clock. This clock is active during the conver-
sion time and the normal mode rejection provided by the
internal digital filter is not very high at this frequency. A
normal mode signal of this frequency at the converter
reference terminals can result in DC gain and INL errors.
A normal mode signal of this frequency at the converter
input terminals can result in a DC offset error. Such pertur-
bations can occur due to asymmetric capacitive coupling
when any one of the digital input signals (SDI, f , CS and
O
SCKinExternalSCKmodeofoperation)iswithinthisrange,
thepowersupplycurrentmayincreaseevenifthesignalin
questionisatavalidlogiclevel.Formicropoweroperation,
it is recommended to drive all digital input signals to full
CMOS levels [V < 0.4V and V > (V – 0.4V)].
IL
OH
CC
During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the pins can
severely disturb the analog to digital conversion process.
Undershoot and overshoot occur because of the imped-
ance mismatch of the circuit board trace at the converter
pin when the transition time of an external control signal
is less than twice the propagation delay from the driver
to the LTC2480. For reference, on a regular FR-4 board,
signal propagation velocity is approximately 183ps/inch
for internal traces and 170ps/inch for surface traces.
Thus, a driver generating a control signal with a minimum
transition time of 1ns must be connected to the converter
pin through a trace shorter than 2.5 inches. This problem
becomesparticularlydifficultwhensharedcontrollinesare
used and multiple reflections may occur. The solution is
to carefully terminate all transmission lines close to their
characteristic impedance.
between the f signal trace and the converter input and/or
O
reference connection traces. An immediate solution is to
maintain maximum possible separation between the f
signal trace and the input/reference signals. When the f
O
O
signalisparallelterminatedneartheconverter, substantial
AC current is flowing in the loop formed by the f con-
O
nection trace, the termination and the ground return path.
Thus,perturbationsignalsmaybeinductivelycoupledinto
the converter input and/or reference. In this situation, the
user must reduce to a minimum the loop area for the f
O
signal as well as the loop area for the differential input
and reference connections. Even when f is not driven,
O
other nearby signals pose similar EMI threats which will
be minimized by following good layout practices.
2480fc
27
LTC2480
APPLICATIONS INFORMATION
Driving the Input and Reference
period is 2.5/f
and, for a settling error of less than
EOSC
1ppm, τ ≤ 0.178/f
.
EOSC
The input and reference pins of the LTC2480 converter
are directly connected to a network of sampling capaci-
tors. Depending upon the relation between the differential
input voltage and the differential reference voltage, these
capacitors are switching between these four pins transfer-
ring small amounts of charge in the process. A simplified
equivalent circuit is shown in Figure 11.
Automatic Differential Input Current Cancellation
In applications where the sensor output impedance is
low (up to 10kΩ with no external bypass capacitor or up
to 500Ω with 0.001μF bypass), complete settling of the
input occurs. In this case, no errors are introduced and
direct digitization of the sensor is possible.
For a simple approximation, the source impedance R
S
+
–
+
driving an analog input pin (IN , IN , V
or GND) can
For many applications, the sensor output impedance
combined with external bypass capacitors produces RC
time constants much greater than the 580ns required for
1ppmaccuracy.Forexample,a10kΩbridgedrivinga0.1μF
bypasscapacitorhasatimeconstantanorderofmagnitude
greater than the required maximum. Historically, settling
issues were solved using buffers. These buffers led to
increased noise, reduced DC performance (Offset/Drift),
limited input/output swing (cannot digitize signals near
REF
be considered to form, together with R and C (see
SW
EQ
Figure 11), a first order passive network with a time
constant τ = (R + R ) • C . The converter is able to
S
SW
EQ
sample the input signal with better than 1ppm accuracy
if the sampling period is at least 14 times greater than the
input circuit time constant τ. The sampling process on
the four input analog pins is quasi-independent so each
time constant should be considered by itself and, under
worst-case circumstances, the errors may add.
ground or V ), added system cost and increased power.
CC
The LTC2480 uses a proprietary switching algorithm that
forcestheaveragedifferentialinputcurrenttozeroindepen-
dent of external settling errors. This allows accurate direct
digitization of high impedance sensors without the need
of buffers. Additional errors resulting from mismatched
leakage currents must also be taken into account.
Whenusingtheinternaloscillator,theLTC2480’sfront-end
switched-capacitor network is clocked at 123kHz corre-
sponding to an 8.1μs sampling period. Thus, for settling
errors of less than 1ppm, the driving source impedance
shouldbechosensuchthatτ≤8.1μs/14=580ns.Whenan
externaloscillatoroffrequencyf
isused,thesampling
EOSC
V
CC
+
I
REF
R
(TYP)
SW
I
I
LEAK
10k
+
V
IN(CM) ꢄ VREF(CM)
V
I INꢀ
ꢃ I IN–
ꢃ
REF
ꢁ
ꢂ
ꢁ
ꢂ
AVG
AVG
0.5vREQ
LEAK
2
2
1.5VREF ꢀ VREF(CM) – V
V
ꢁ
IN(CM)
ꢂ
1.5v VREF ꢄ VINCM ꢀ VREFCM
0.5vREQ
0.5• VREF • DT
REQ
V
IN
V
CC
IN
I REFꢀ
ꢃ
ꢄ
ꢄ
–
+
ꢁ
ꢂ
I
IN
AVG
VREF vREQ
0.5•REQ
VREF •REQ
R
(TYP)
10k
SW
I
I
LEAK
LEAK
where:
+
V
IN
ꢀ
´
C
¥
EQ
VREF
2
VREFCM
ꢃ
¦
12pF
µ
§
¶
(TYP)
V
ꢃ INꢀ ꢄINꢄ
CC
V
IN
–
I
IN
R
R
(TYP)
ꢀ
IN ꢀINꢄ
SW
¥
´
I
LEAK
LEAK
V
INCM
ꢃ
10k
¦
µ
–
2
§
¶
V
IN
REQ ꢃ 2.71M7 INTERNAL OSCILLATOR 60Hz MODE
REQ ꢃ 2.98M7 INTERNAL OSCILLATOR 50Hz AND 60Hz MODE
REQ ꢃ 0.833v1012 / fEOSC EXTERNAL OSCILLATOR
I
V
CC
–
I
REF
ꢁ
ꢂ
(TYP)
SW
10k
I
I
LEAK
LEAK
DT IS THE DENSITY OF A DIGITAL TRANSITION AT THE MODULATOR OUTPUT
WHERE REF IS INTERNALLY TIED TO GND
2480 F11
GND
–
SWITCHING FREQUENCY
f
f
= 123kHz INTERNAL OSCILLATOR
SW
SW
= 0.4 • f
EXTERNAL OSCILLATOR
EOSC
Figure 11. LTC2480 Equivalent Analog Input Circuit
2480fc
28
LTC2480
APPLICATIONS INFORMATION
R
The switching algorithm forces the average input current
SOURCE
+
IN
+
on the positive input (I ) to be equal to the average input
IN
C
PAR
–
V
+ 0.5V
C
INCM
IN
EXT
current on the negative input (I ). Over the complete
20pF
IN
LTC2480
conversion cycle, the average differential input current
+
–
(I – I ) is zero. While the differential input current
IN
IN
R
SOURCE
–
+
–
IN
is zero, the common mode input current (I + I )/2 is
IN
IN
2480 F12
C
PAR
proportional to the difference between the common mode
V
– 0.5V
C
INCM
IN
EXT
20pF
input voltage (V
voltage (V
) and the common mode reference
INCM
).
REFCM
Figure 12. An RC Network at IN+ and IN–
In applications where the input common mode voltage
is equal to the reference common mode voltage, as in
the case of a balance bridge type application, both the
differential and common mode input current are zero.
The accuracy of the converter is unaffected by settling
80
V
V
V
V
= 5V
CC
= 5V
REF
60
40
20
+
= 3.75V
= 1.25V
IN
–
+
errors. Mismatches in source impedances between IN
IN
–
F
= GND
O
C
= 0pF
EXT
and IN also do not affect the accuracy.
T
= 25°C
A
C
= 100pF
EXT
In applications where the input common mode voltage is
constant but different from the reference common mode
voltage, the differential input current remains zero while
the common mode input current is proportional to the
0
C
= 1nF, 0.1μF, 1μF
EXT
–20
–40
–60
–80
difference between V
and V
. For a reference
INCM
REFCM
common mode of 2.5V and an input common mode of
1.5V, the common mode input current is approximately
0.74μA(insimultaneous50Hz/60Hzrejectionmode). This
commonmodeinputcurrenthasnoeffectontheaccuracy
10
100
10k
1
100k
1k
R
(Ω)
SOURCE
2480 F13
Figure 13. +FS Error vs RSOURCE at IN+ or IN–
+
–
if the external source impedances tied to IN and IN are
matched. Mismatches in these source impedances lead
to a fixed offset error but do not affect the linearity or full-
scale reading. A 1ꢀ mismatch in 1k source resistances
leads to a 15ppm shift (74μV) in offset voltage.
80
V
V
V
V
F
= 5V
= 5V
= 1.25V
= 3.75V
= GND
= 25°C
CC
REF
60
40
20
+
IN
–
IN
In applications where the common mode input voltage
varies as a function of input signal level (single-ended
input, RTDs, half bridges, current sensors, etc.), the
common mode input current varies proportionally with
input voltage. For the case of balanced input impedances,
thecommonmodeinputcurrenteffectsarerejectedbythe
large CMRR of the LTC2480 leading to little degradation in
accuracy. Mismatches in source impedances lead to gain
errorsproportionaltothedifferencebetweenthecommon
mode input voltage and the common mode reference
voltage. 1ꢀ mismatches in 1k source resistances lead to
worst-case gain errors on the order of 15ppm or 1LSB
(for 1V differences in reference and input common mode
O
C
= 1nF, 0.1μF, 1μF
EXT
T
A
0
C
EXT
= 100pF
–20
C
= 0pF
EXT
–40
–60
–80
10
100
R
10k
1
100k
1k
(Ω)
SOURCE
2480 F14
Figure 14. –FS Error vs RSOURCE at IN+ or IN–
2480fc
29
LTC2480
APPLICATIONS INFORMATION
voltage). Table 7 summarizes the effects of mismatched
source impedance and differences in reference/input
common mode voltages.
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for C
will deteriorate the converter offset and
REF
gainperformancewithoutsignificantbenefitsofreference
filtering and the user is advised to avoid them.
Table 7. Suggested Input Configuration for LTC2480
BALANCED INPUT
RESISTANCES
UNBALANCED INPUT
RESISTANCES
Larger values of reference capacitors (C > 1nF) may be
REF
+
Constant
IN(CM)
C
> 1nF at Both
C
> 1nF at Both IN
requiredasreferencefiltersincertainconfigurations.Such
capacitors will average the reference sampling charge and
the external source resistance will see a quasi constant
reference differential impedance.
EXT
EXT
+
–
–
V
– V
IN and IN . Can Take
and IN . Can Take Large
REF(CM)
REF(CM)
Large Source Resistance Source Resistance.
with Negligible Error
Unbalanced Resistance
Results in an Offset
EXT
+
+
–
Varying
IN(CM)
C
> 1nF at Both IN
Minimize IN and IN
–
In the following discussion, it is assumed the input and
reference common mode are the same. Using internal
oscillator for 60Hz mode, the typical differential reference
V
– V
and IN . Can Take Large Capacitors and Avoid
Source Resistance with
Negligible Error
Large Source Impedance
(<5kΩ Recommended)
resistance is 1MΩ which generates a full-scale (V /2)
Themagnitudeofthedynamicinputcurrentdependsupon
thesizeoftheverystableinternalsamplingcapacitorsand
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
andpowersupplyrangeistypicallybetterthan0.5ꢀ.Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
REF
gain error of 0.51ppm for each ohm of source resistance
driving the V
pin. For 50Hz/60Hz mode, the related
REF
difference resistance is 1.1MΩ and the resulting full-scale
error is 0.46ppm for each ohm of source resistance driv-
ing the V
pin. For 50Hz mode, the related difference
REF
resistance is 1.2MΩ and the resulting full-scale error is
0.42ppm for each ohm of source resistance driving the
+
used for the external source impedance seen by IN and
–
V
pin. When f is driven by an external oscillator with a
IN , the expected drift of the dynamic current and offset
REF
frequencyf
O
(externalconversionclockoperation),the
will be insignificant (about 1ꢀ of their respective values
over the entire temperature and voltage range). Even for
the most stringent applications, a one-time calibration
operation may be sufficient.
EOSC
typicaldifferentialreferenceresistanceis0.30•1012/f
EOSC
REF
Ω and each ohm of source resistance driving the V pin
will result in 1.67 • 10–6 • f
ppm gain error. The typical
EOSC
+FS and –FS errors for various combinations of source
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA ( 10nA max), results
in a small offset shift. A 1k source resistance will create a
1μV typical and 10μV maximum offset voltage.
resistance seen by the V pin and external capacitance
REF
connected to that pin are shown in Figures 15-18.
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
The INL is caused by the input dependent terms
2
–V /(V • R ) – (0.5 • V • D )/R in the reference
Reference Current
IN
REF
EQ
REF
T
EQ
pin current as expressed in Figure 11. When using internal
oscillatorand60Hzmode,every100Ωofreferencesource
resistance translates into about 0.67ppm additional INL
error.Whenusinginternaloscillatorand50Hz/60Hzmode,
every 100Ω of reference source resistance translates into
about 0.61ppm additional INL error. When using internal
oscillatorand50Hzmode,every100Ωofreferencesource
resistance translates into about 0.56ppm additional INL
In a similar fashion, the LTC2480 samples the differential
+
reference pins V
and GND transferring small amount
REF
of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can
be analyzed in two distinct situations.
Forrelativelysmallvaluesoftheexternalreferencecapaci-
error. When f is driven by an external oscillator with a
O
tors (C
< 1nF), the voltage on the sampling capacitor
frequency f
, every 100Ω of source resistance driving
REF
EOSC
2480fc
30
LTC2480
APPLICATIONS INFORMATION
10
0
90
V
V
V
V
F
= 5V
CC
80
70
60
50
40
30
20
10
0
= 5V
REF
+
= 3.75V
= 1.25V
IN
–
–10
–20
–30
–40
–50
–60
–70
–80
–90
C
REF
C
= 0.01μF
REF
IN
C
= 0.001μF
= GND
= 25°C
O
= 100pF
REF
C
T
A
= 0pF
REF
C
= 0.01μF
REF
C
= 0.001μF
REF
C
= 100pF
= 0pF
REF
C
V
V
V
V
= 5V
REF
CC
= 5V
REF
+
= 1.25V
= 3.75V
IN
–
IN
F
= GND
O
T
A
= 25°C
–10
10
100
R
1k
10k
100k
0
10
100
R
1k
10k
100k
0
(Ω)
(Ω)
SOURCE
SOURCE
2480 F16
2480 F15
Figure 15. +FS Error vs RSOURCE at VREF (Small CREF
)
Figure 16. –FS Error vs RSOURCE at VREF (Small CREF
)
500
0
V
V
V
V
F
= 5V
CC
C
= 1μF, 10μF
REF
= 5V
REF
+
= 3.75V
= 1.25V
IN
–
400
300
200
100
0
–100
IN
C
= 0.01μF
= 0.1μF
= GND
= 25°C
REF
O
T
C
= 0.1μF
A
REF
–200
–300
–400
–500
C
= 1μF, 10μF
REF
V
V
V
V
= 5V
C
CC
REF
= 5V
C
= 0.01μF
REF
REF
+
= 1.25V
= 3.75V
IN
–
IN
F
= GND
O
T
A
= 25°C
0
200
400
R
600
(Ω)
800
1000
0
200
400
R
600
(Ω)
800
1000
SOURCE
SOURCE
2480 F17
2480 F18
Figure 18. –FS Error vs RSOURCE at VREF (Large CREF
)
Figure 17. +FS Error vs RSOURCE at VREF (Large CREF
)
10
–6
V
V
V
= 5V
V
translates into about 2.18 • 10 • f
ppm addi-
EOSC
CC
REF
8
6
= 5V
REF
IN(CM)
= 25°C
tional INL error. Figure 19 shows the typical INL error due
to the source resistance driving the V pin when large
R = 1k
= 2.5V
T
A
REF
C
= 10μF
REF
4
C
REF
values are used. The user is advised to minimize the
source impedance driving the V pin.
2
R = 500Ω
R = 100Ω
REF
0
–2
–4
–6
–8
–10
In applications where the reference and input common
mode voltages are different, extra errors are introduced.
For every 1V of the reference and input common mode
voltage difference (V
– V
) and a 5V reference,
REFCM
INCM
–0.5
–0.3
–0.1
/V
0.1
(V)
0.3
0.5
each Ohm of reference source resistance introduces an
extra (V – V )/(V • R ) full-scale gain error,
V
IN REF
REFCM
INCM
REF
EQ
2480 F19
whichis0.074ppmwhenusinginternaloscillatorand60Hz
Figure 19. INL vs Differential Input Voltage and
Reference Source Resistance for CREF > 1μF
mode.Whenusinginternaloscillatorand50Hz/60Hzmode,
the extra full-scale gain error is 0.067ppm. When using
2480fc
31
LTC2480
APPLICATIONS INFORMATION
internal oscillator and 50Hz mode, the extra gain error is
Output Data Rate
0.061ppm. If an external clock is used, the corresponding
When using its internal oscillator, the LTC2480 produces
upto7.5samplespersecond(sps)withanotchfrequency
of 60Hz, 6.25sps with a notch frequency of 50Hz and
6.82sps with the 50Hz/60Hz rejection mode. The actual
output data rate will depend upon the length of the sleep
and data output phases which are controlled by the user
and which can be made insignificantly short. When oper-
extra gain error is 0.24 • 10–6 • f ppm.
EOSC
The magnitude of the dynamic reference current depends
uponthesizeoftheverystableinternalsamplingcapacitors
andupontheaccuracyoftheconvertersamplingclock.The
accuracy of the internal clock over the entire temperature
andpowersupplyrangeistypicallybetterthan0.5ꢀ.Such
a specification can also be easily achieved by an external
ated with an external conversion clock (f connected to
O
an external oscillator), the LTC2480 output data rate can
clock. When relatively stable resistors (50ppm/°C) are
+
be increased as desired. The duration of the conversion
used for the external source impedance seen by V
REF
phase is 41036/f
. If f
= 307.2kHz, the converter
EOSC
EOSC
and GND, the expected drift of the dynamic current gain
error will be insignificant (about 1ꢀ of its value over the
entire temperature and voltage range). Even for the most
stringent applications a one-time calibration operation
may be sufficient.
behaves as if the internal oscillator is used and the notch
is set at 60Hz.
An increase in f
over the nominal 307.2kHz will
EOSC
translate into a proportional increase in the maximum
output data rate. The increase in output rate is neverthe-
less accompanied by three potential effects, which must
be carefully considered.
In addition to the reference sampling charge, the refer-
ence pins ESD protection diodes have a temperature
dependentleakagecurrent.Thisleakagecurrent,nominally
1nA ( 10nA max), results in a small gain error. A 100Ω
source resistance will create a 0.05μV typical and 0.5μV
maximum full-scale error.
First, a change in f
will result in a proportional change
EOSC
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line fre-
50
40
3500
3000
0
V
V
F
= V
REF
V
V
V
= V
REF
IN(CM)
CC
REF(CM)
= 5V
IN(CM)
REF(CM)
= 5V
= V
= V
CC
–500
= EXT CLOCK
= 0V
O
IN
F
= EXT CLOCK
O
2500
–1000
30
20
T
= 85°C
T = 25°C
A
A
T
= 85°C
A
2000
1500
1000
500
–1500
–2000
–2500
–3000
T
= 85°C
A
T
A
= 25°C
10
0
V
V
O
= V
REF
IN(CM)
CC
= EXT CLOCK
REF(CM)
= 5V
= V
T
= 25°C
A
F
0
–10
–3500
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
10 20
40
50 60 70 80 90 100
0
30
40
50 60 70 80 90 100
0
30
10 20
OUTPUT DATA RATE (READINGS/SEC)
OUTPUT DATA RATE (READINGS/SEC)
2480 F21
2480 F20
2480 F22
Figure 20. Offset Error vs Output Data
Rate and Temperature
Figure 21. +FS Error vs Output Data
Rate and Temperature
Figure 22. –FS Error vs Output Data
Rate and Temperature
2480fc
32
LTC2480
APPLICATIONS INFORMATION
quency.Inmanyapplications,thesubsequentperformance
degradation can be substantially reduced by relying upon
theLTC2480’sexceptionalcommonmoderejectionandby
carefully eliminating common mode to differential mode
conversion sources in the input circuit. The user should
avoid single-ended input filters and should maintain a
very high degree of matching and symmetry in the circuits
any value of
. If small external input and/or reference
IN REF
fEOSC
capacitors (C , C ) are used, the effect of the external
source resistance upon the LTC2480 typical performance
can be inferred from Figures 13, 14, 15 and 16 in which
the horizontal axis is scaled by 307200/f
.
EOSC
Third,anincreaseinthefrequencyoftheexternaloscillator
above 1MHz (a more than 3× increase in the output data
rate) will start to decrease the effectiveness of the internal
autocalibration circuits. This will result in a progressive
degradationintheconverteraccuracyandlinearity.Typical
measured performance curves for output data rates up to
100 readings per second are shown in Figures 20 to 27. In
order to obtain the highest possible level of accuracy from
this converter at output data rates above 20 readings per
+
–
driving the IN and IN pins.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (C , C ) are used, the
IN REF
previoussectionprovidesformulaeforevaluatingtheeffect
ofthesourceresistanceupontheconverterperformancefor
22
20
18
16
24
22
20
V
V
F
= V
REF(CM)
IN(CM)
IN
O
T
= 25°C
A
= 0V
= EXT CLOCK
= 25°C
15
10
5
T
= 85°C
A
T
A
20
T
= 25°C
T
= 85°C
A
18
16
14
12
V
= V
= 5V
REF
A
CC
14
12
10
0
–5
V
V
V
= V
REF
IN(CM)
REF(CM)
= 5V
= V
V
V
O
= V
REF
CC
IN
IN(CM)
= V
= EXT CLOCK
RES = LOG 2 (V /INL
REF(CM)
= 5V
= 0V
CC
F
= EXT CLOCK
F
O
V
= 5V, V
= 2.5V
REF
CC
RES = LOG 2 (V /NOISE
)
)
REF
RMS
REF
MAX
10
–10
40
50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
0
30
40
50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
0
30
10 20
10 20
40
50 60 70 80 90 100
0
30
10 20
OUTPUT DATA RATE (READINGS/SEC)
2480 F23
2480 F24
2480 F25
Figure 23. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 25. Offset Error vs Output
Data Rate and Reference Voltage
Figure 24. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Temperature
24
22
20
18
16
V
= V
= 5V
REF
CC
22
20
V
= 5V, V
= 2.5V
REF
CC
V
= V
= 5V
REF
CC
18
16
14
12
V
= 5V, V
= 2.5V
REF
CC
V
V
= V
REF(CM)
IN(CM)
IN
14
12
10
V
= V
= 0V
IN(CM)
IN
REF(CM)
–
V
F
= 0V
REF = GND
= EXT CLOCK
= EXT CLOCK
= 25°C
F
O
O
A
T
T
= 25°C
A
RES = LOG 2 (V /NOISE
)
RMS
RES = LOG 2 (V /INL
)
REF
REF
MAX
10
70
100
80 90
0
30
50 60 70 80 90 100
0
30
60
10 20
40
10 20
40
50
OUTPUT DATA RATE (READINGS/SEC)
OUTPUT DATA RATE (READINGS/SEC)
2480 F26
2480 F27
Figure 26. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Reference Voltage
Figure 27. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Reference Voltage
2480fc
33
LTC2480
APPLICATIONS INFORMATION
0
–1
–2
–3
–4
–5
–6
second, the user is advised to maximize the power supply
voltage used and to limit the maximum ambient operating
temperature. In certain circumstances, a reduction of the
differential reference voltage may be beneficial.
50Hz AND
60Hz MODE
50Hz MODE
60Hz MODE
Input Bandwidth
4
The combined effect of the internal SINC digital filter and
oftheanaloganddigitalautocalibrationcircuitsdetermines
theLTC2480inputbandwidth. Whentheinternaloscillator
isusedwiththenotchsetat60Hz,the3dBinputbandwidth
is 3.63Hz. When the internal oscillator is used with the
notch set at 50Hz, the 3dB input bandwidth is 3.02Hz.
If an external conversion clock generator of frequency
0
1
2
3
4
5
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2480 F28
Figure 28. Input Signal Bandwidth Using the Internal Oscillator
f
is connected to the f pin, the 3dB input bandwidth
EOSC
is 11.8 • 10 • f
O
–6
.
EOSC
100
Due to the complex filtering and calibration algorithms
utilized, the converter input bandwidth is not modeled
very accurately by a first order filter with the pole located
at the 3dB frequency. When the internal oscillator is used,
the shape of the LTC2480 input bandwidth is shown in
60Hz MODE
50Hz MODE
10
1
Figure 28. When an external oscillator of frequency f
EOSC
is used, the shape of the LTC2480 input bandwidth can
be derived from Figure 28, 60Hz mode curve in which the
horizontal axis is scaled by f
/307200.
EOSC
0.1
0.1
The conversion noise (600nV
typical for V
= 5V)
1
10 100 1k 10k 100k 1M
INPUT NOISE SOURCE SINGLE POLE
EQUIVALENT BANDWIDTH (Hz)
RMS
REF
can be modeled by a white noise source connected to a
noisefreeconverter.Thenoisespectraldensityis47nV√Hz
for an infinite bandwidth source and 64nV√Hz for a single
0.5MHz pole source. From these numbers, it is clear that
particular attention must be given to the design of external
amplification circuits. Such circuits face the simultaneous
requirements of very low bandwidth (just a few Hz) in
order to reduce the output referred noise and relatively
high bandwidth (at least 500kHz) necessary to drive the
input switched-capacitor network. A possible solution is
a high gain, low bandwidth amplifier stage followed by a
high bandwidth unity-gain buffer.
2480 F29
Figure 29. Input Referred Noise Equivalent Bandwidth
of an Input Connected White Noise Source
corner frequency f . The amplifier noise spectral density
i
is n . From Figure 29, using f as the x-axis selector, we
i
i
can find on the y-axis the noise equivalent bandwidth freq
i
of the input driving amplifier. This bandwidth includes
the band limiting effects of the ADC internal calibration
and filtering. The noise of the driving amplifier referred
to the converter input and including all these effects can
When external amplifiers are driving the LTC2480, the
ADC input referred system noise calculation can be
simplified by Figure 29. The noise of an amplifier driving
the LTC2480 input pin can be modeled as a band limited
white noise source. Its bandwidth can be approximated
by the bandwidth of a single pole lowpass filter with a
be calculated as N = n • √freq . The total system noise
i i
(referred to the LTC2480 input) can now be obtained by
summing as square root of sum of squares the three ADC
input referred noise sources: the LTC2480 internal noise,
+
the noise of the IN driving amplifier and the noise of the
–
IN driving amplifier.
2480fc
34
LTC2480
APPLICATIONS INFORMATION
If the f pin is driven by an external oscillator of frequency
lows external lowpass filtering without degrading the DC
performance of the device.
O
f
, Figure 29 can still be used for noise calculation if
EOSC
the x-axis is scaled by f
/307200. For large values of
4
EOSC
TheSINC digitalfilterprovidesgreaterthan120dBnormal
the ratio f
/307200, the Figure 29 plot accuracy begins
EOSC
mode rejection at all frequencies except DC and integer
to decrease, but at the same time the LTC2480 noise floor
rises and the noise contribution of the driving amplifiers
lose significance.
multiples of the modulator sampling frequency (f ). The
S
LTC2480’s autocalibration circuits further simplify the
anti-aliasing requirements by additional normal mode
signal filtering both in the analog and digital domain.
Normal Mode Rejection and Anti-aliasing
Independent of the operating mode, f = 256 • f = 2048
S
N
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital filtering. Combined
with a large oversampling ratio, the LTC2480 significantly
simplifies anti-aliasing filter requirements. Additionally,
the input current cancellation feature of the LTC2480 al-
• f
where f is the notch frequency and f
OUT(MAX)
N OUT(MAX)
is the maximum output data rate. In the internal oscilla-
tor mode with a 50Hz notch setting, f = 12800Hz, with
S
50Hz/60Hz rejection, f = 13960Hz and with a 60Hz notch
S
setting f = 15360Hz. In the external oscillator mode, f =
S
S
0
–10
0
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–100
–110
–120
0
f
2f 3f 4f 5f 6f 7f 8f 9f 10f 11f 12f
0
f
2f 3f 4f 5f 6f 7f 8f 9f 10f
S S S S S S S S S S
S
S
S
S
S
S
S
S
S
S
S
S
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2480 F30
2480 F31
Figure 30. Input Normal Mode Rejection,
Internal Oscillator and 50Hz Notch Mode
Figure 31. Input Normal Mode Rejection, Internal
Oscillator and 60Hz Notch Mode or External Oscillator
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
f
= f
EOSC/5120
N
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–120
0
f
2f
3f
4f
5f
6f
7f
8f
N
250f 252f 254f 256f 258f 260f 262f
N
N
N
N
N
N
N
N
N
N
N
N
N
N
INPUT SIGNAL FREQUENCY (Hz)
INPUT SIGNAL FREQUENCY (Hz)
2480 F32
2480 F33
Figure 32. Input Normal Mode Rejection at DC
Figure 33. Input Normal Mode Rejection at fS = 256fN
2480fc
35
LTC2480
APPLICATIONS INFORMATION
f
/20. The performance of the normal mode rejection
the LTC2480 for the 50Hz rejection mode and 50Hz/60Hz
rejection mode are shown in Figures 35 and 36.
EOSC
is shown in Figures 30 and 31.
In 1x speed mode, the regions of low rejection occurring
As a result of these remarkable normal mode specifica-
tions,minimal(ifany)anti-aliasfilteringisrequiredinfront
of the LTC2480. If passive RC components are placed in
front of the LTC2480, the input dynamic current should
be considered (see Input Current section). In this case,
the differential input current cancellation feature of the
LTC2480 allows external RC networks without significant
degradation in DC performance.
at integer multiples of f have a very narrow bandwidth.
S
Magnified details of the normal mode rejection curves
are shown in Figure 32 (rejection near DC) and Figure 33
(rejection at f = 256f ) where f represents the notch
S
N
N
frequency. These curves have been derived for the exter-
nal oscillator mode but they can be used in all operating
modes by appropriately selecting the f value.
N
The user can expect to achieve this level of performance
using the internal oscillator as it is demonstrated by
Figures 34, 35 and 36. Typical measured values of the
normal mode rejection of the LTC2480 operating with an
internal oscillator and a 60Hz notch setting are shown in
Figure 34 superimposed over the theoretical calculated
curve. Similarly, the measured normal mode rejection of
Traditional high order delta-sigma modulators, while pro-
vidingverygoodlinearityandresolution,sufferfrompoten-
tial instabilities at large input signal levels. The proprietary
architecture used for the LTC2480 third order modulator
resolves this problem and guarantees a predictable stable
behavior at input signal levels of up to 150ꢀ of full-scale.
Inmanyindustrialapplications,itisnotuncommontohave
0
0
V
V
V
V
= 5V
V
V
V
V
T
= 5V
CC
CC
MEASURED DATA
CALCULATED DATA
MEASURED DATA
CALCULATED DATA
= 5V
= 5V
REF
REF
–20
–40
–20
–40
= 2.5V
= 5V
= 2.5V
= 5V
IN(CM)
IN(P-P)
IN(CM)
IN(P-P)
T
A
= 25°C
= 25°C
A
–60
–60
–80
–80
–100
–120
–100
–120
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
0
15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2480 F35
2480 F34
Figure 35. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full-Scale (50Hz Notch)
Figure 34. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full-Scale (60Hz Notch)
0
0
V
V
V
V
= 5V
= 5V
V
V
V
T
= 5V
= 5V
CC
CC
MEASURED DATA
CALCULATED DATA
V
V
= 5V
= 7.5V
IN(P-P)
IN(P-P)
REF
REF
–20
–40
–20
–40
= 2.5V
= 5V
= 2.5V
IN(CM)
IN(P-P)
IN(CM)
(150ꢀ OF FULL SCALE)
= 25°C
A
T
A
= 25°C
–60
–60
–80
–80
–100
–120
–100
–120
0
20
40
60
80
100
120
140
160
180
200
220
0
15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
2480 F36
2480 F37
Figure 37. Measured Input Normal Mode Rejection
vs Input Frequency with Input Perturbation of 150%
Full-Scale (60Hz Notch)
Figure 36. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full-Scale (50Hz/60Hz Mode)
2480fc
36
LTC2480
APPLICATIONS INFORMATION
0
–20
0
V
V
V
= 5V
CC
V
V
= 5V
= 7.5V
IN(P-P)
IN(P-P)
= 5V
= 2.5V
REF
IN(CM)
= 25°C
–20
–40
(150ꢀ OF FULL SCALE)
T
A
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
f
N
2f
3f
4f 5f
6f
7f
N
8f
N
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
N
N
N
N
N
INPUT SIGNAL FREQUENCY (f
)
N
2480 F39
2480 F38
Figure 39. Input Normal Mode
Rejection 2x Speed Mode
Figure 38. Measured Input Normal Mode Rejection
vs Input Frequency with Input Perturbation of 150%
Full-Scale (50Hz Notch)
0
–70
–80
0
MEASURED DATA
CALCULATED DATA
V
V
V
V
F
= 5V
CC
= 5V
REF
–20
–40
–20
–40
= 2.5V
INCM
NO AVERAGE
= 5V
IN(P-P)
–90
–100
–110
–120
–130
–140
= GND
= 25oC
O
T
A
WITH
RUNNING
AVERAGE
–60
–60
–80
–80
–100
–100
–120
–120
248 250 252 254 256 258 260 262 264
INPUT SIGNAL FREQUENCY (f
48 50
52
54 56
58
60
62
0
25 50 75 100 125 150 175 200 225
INPUT FREQUENCY (Hz)
)
N
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2480 F48
2480 F42
2480 F41
Figure 40. Input Normal Mode
Rejection 2x Speed Mode
Figure 41. Input Normal Mode
Rejection vs Input Frequency,
2x Speed Mode and 50Hz/60Hz Mode
Figure 42. Input Normal Mode
Rejection 2x Speed Mode
tomeasuremicrovoltlevelsignalssuperimposedovervolt
level perturbations and the LTC2480 is eminently suited
for such tasks. When the perturbation is differential, the
specification of interest is the normal mode rejection for
user must observe that such signals do not violate the
device absolute maximum ratings.
Using the 2x speed mode of the LTC2480, the device
bypasses the digital offset calibration operation to double
the output data rate. The superior normal mode rejection
is maintained as shown in Figures 30 and 31. However,
largeinputsignallevels.WithareferencevoltageV = 5V,
REF
the LTC2480 has a full-scale differential input range of
5V peak-to-peak. Figures 37 and 38 show measurement
results for the LTC2480 normal mode rejection ratio with a
7.5V peak-to-peak (150ꢀ offull-scale)inputsignalsuper-
imposed over the more traditional normal mode rejection
ratio results obtained with a 5V peak-to-peak (full-scale)
input signal. In Figure 37, the LTC2480 uses the internal
the magnified details near DC and f = 256f are different,
S
N
see Figures 39 and 40. In 2x speed mode, the bandwidth is
11.4Hz for the 50Hz rejection mode, 13.6Hz for the 60Hz
rejection mode and 12.4Hz for the 50Hz/60Hz rejection
mode. Typical measured values of the normal mode rejec-
tion of the LTC2480 operating with the internal oscillator
and 2x speed mode is shown in Figure 41.
oscillator with the notch set at 60Hz (f = LOW) and in
O
Figure 38 it uses the internal oscillator with the notch set
at 50Hz. It is clear that the LTC2480 rejection performance
is maintained with no compromises in this extreme situ-
ation. When operating with large input signal levels, the
When the LTC2480 is configured in 2x speed mode, by
performingarunningaverage, aSINC1notchiscombined
with the SINC4 digital filter, yielding the normal mode
2480fc
37
LTC2480
APPLICATIONS INFORMATION
rejection identical as that for the 1x speed mode. The
averaging operation still keeps the output rate with the
following algorithm:
meter, the cold junction temperature sensor must be at
the same temperature as the junction between the ther-
mocouple materials and the copper printed circuit board
traces. The tiny LTC2480 can be tucked neatly underneath
an Omega MPJ-K-F thermocouple socket ensuring close
thermal coupling.
Result 1 = average (sample 0, sample 1)
Result 2 = average (sample 1, sample 2)
……
The LTC2480’s 1.4mV/°C PTAT circuit measures the
cold junction temperature. Once the thermocouple volt-
age and cold junction temperature are known, there are
many ways of calculating the thermocouple temperature
including a straight-line approximation, lookup tables or
a polynomial curve fit. Calibration is performed by apply-
ing an accurate 500mV to the ADC input derived from an
LT®1236 reference and measuring the local temperature
with an accurate thermometer as shown in Figure 43. In
calibration mode, the up and down buttons are used to
adjust the local temperature reading until it matches an
accurate thermometer. Both the voltage and temperature
calibration are easily automated.
Result n = average (sample n – 1, sample n)
The main advantage of the running average is that it
achieves simultaneous 50Hz/60Hz rejection at twice the
effectiveoutputrate,asshowninFigure42.Therawoutput
data provides a better than 70dB rejection over 48Hz to
62.4Hz,whichcoversboth50Hz 2ꢀand60Hz 2ꢀ.With
running average on, the rejection is better than 87dB for
both 50Hz 2ꢀ and 60Hz 2ꢀ.
Complete Thermocouple Measurement System with
Cold Junction Compensation
The LTC2480 is ideal for direct digitization of thermo-
couples and other low voltage output sensors. The input
has a typical offset error of 500nV (2.5μV max) offset
The complete microcontroller code for this application is
available on the LTC2480 product Web page at:
drift of 10nV/°C and a noise level of 600nV
. The input
RMS
http://www.linear.com
span may be optimized for various sensors by setting the
gain of the PGA. Using an external 5V reference with a
PGA gain of 64 gives a 78mV input rangeꢁperfect for
thermocouples.
It can be used as a template for may different instruments
and it illustrates how to generate calibration coefficients
for the onboard temperature sensor. Extensive comments
detail the operation of the program. The read_LTC2480()
function controls the operation of the LTC2480 and is
listed below for reference.
Figure 44 (last page of this data sheet) is a complete type
K thermocouple meter. The only signal conditioning is a
simple surge protection network. In any thermocouple
5V
ISOTHERMAL
LT1236
C8
1μF
C7
0.1μF
2
6
3
2
IN OUT
TRIM
GND
4
R2
2k
6
9
7
1
5
REF
V
CC
R7
8k
CS
SCK
SDO
SDI
4
5
+
+
–
IN
G1
NC1M4V0
LTC2480
R8
1k
IN
10
F
O
GND GND
8
11
2480 F43
TYPE K
THERMOCOUPLE
JACK
(OMEGA MPJ-K-F)
26.3C
Figure 43. Calibration Setup
2480fc
38
LTC2480
APPLICATIONS INFORMATION
/*** read_LTC2480() ************************************************************
This is the function that actually does all the work of talking to the LTC2480.
The spi_read() function performs an 8 bit bidirectional transfer on the SPI bus.
Data changes state on falling clock edges and is valid on rising edges, as
determined by the setup_spi() line in the initialize() function.
A good starting point when porting to other processors is to write your own
spi_write function. Note that each processor has its own way of configuring
the SPI port, and different compilers may or may not have built-in functions
for the SPI port. Also, since the state of the LTC2480ʼs SDO line indicates
when a conversion is complete you need to be able to read the state of this line
through the processorʼs serial data input. Most processors will let you read
this pin as if it were a general purpose I/O line, but there may be some that
donʼt.
When in doubt, you can always write a “bit bang” function for troubleshooting
purposes.
The “fourbytes” structure allows byte access to the 32 bit return value:
struct fourbytes // Define structure of four consecutive bytes
{
// To allow byte access to a 32 bit int or float.
//
// The make32() function in this compiler will
// also work, but a union of 4 bytes and a 32 bit int
// is probably more portable.
int8 te0;
int8 te1;
int8 te2;
int8 te3;
};
Also note that the lower 4 bits are the configuration word from the previous
conversion. The 4 LSBs are cleared so that
they donʼt affect any subsequent mathematical operations. While you can do a
right shift by 4, there is no point if you are going to convert to floating point
numbers - just adjust your scaling constants appropriately.
*******************************************************************************/
signed int32 read_LTC2480(char config)
{
union
{
// adc_code.bits32
// adc_code.by.te0
// adc_code.by.te1
// adc_code.by.te2
// adc_code.by.te3
all 32 bits
byte 0
byte 1
byte 2
byte 3
signed int32 bits32;
struct fourbytes by;
} adc_code;
output_low(CS);
// Enable LTC2480 SPI interface
while(input(PIN_C4)) {}
// Wait for end of conversion. The longest
// you will ever wait is one whole conversion period
// Now is the time to switch any multiplexers because the conversion is finished
// and you have the whole data output time for things to settle.
adc_code.by.te3 = 0;
// Set upper byte to zero.
adc_code.by.te2 = spi_read(config);
adc_code.by.te1 = spi_read(0);
adc_code.by.te0 = spi_read(0);
// Read first byte, send config byte
// Read 2nd byte, send speed bit
// Read 3rd byte. ʻ0ʼ argument is necessary
// to act as SPI master!! (compiler
// and processor specific.)
output_high(CS);
// Disable LTC2480 SPI interface
// Clear configuration bits and subtract offset. This results in
// a 2ʼs complement 32 bit integer with the LTC2480ʼs MSB in the 2^20 position
adc_code.by.te0 = adc_code.by.te0 & 0xF0;
adc_code.bits32 = adc_code.bits32 - 0x00200000;
return adc_code.bits32;
} // End of read_LTC2480()
2480fc
39
LTC2480
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev B)
R = 0.125
TYP
6
0.40 p 0.10
10
0.70 p0.05
3.55 p0.05
2.15 p0.05 (2 SIDES)
1.65 p0.05
3.00 p0.10
(4 SIDES)
1.65 p 0.10
(2 SIDES)
PACKAGE
OUTLINE
PIN 1
TOP MARK
(DD) DFN REV B 0309
(SEE NOTE 6)
5
1
0.25 p 0.05
0.50 BSC
0.75 p0.05
0.200 REF
0.25 p 0.05
0.50
BSC
2.38 p0.10
(2 SIDES)
2.38 p0.05
(2 SIDES)
0.00 – 0.05
BOTTOM VIEWꢁEXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION
OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT
STATUS OF VARIATION ASSIGNMENT
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661 Rev E)
3.00 0.102
(.118 .004)
(NOTE 3)
0.889 0.127
(.035 .005)
0.497 0.076
(.0196 .003)
REF
10 9
8
7 6
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
3.00 0.102
(.118 .004)
(NOTE 4)
4.90 0.152
(.193 .006)
DETAIL “A”
0° – 6° TYP
0.254
(.010)
GAUGE PLANE
0.50
(.0197)
BSC
0.305 0.038
(.0120 .0015)
TYP
1
2
3
4 5
0.53 0.152
(.021 .006)
RECOMMENDED SOLDER PAD LAYOUT
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 0.0508
(.004 .002)
0.50
(.0197)
BSC
MSOP (MS) 0307 REV E
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
2480fc
40
LTC2480
REVISION HISTORY (Revision history begins at Rev B)
REV
DATE
DESCRIPTION
PAGE NUMBER
B
11/09 Revised Tables 3 and 4.
17
C
04/10 Added H-Grade to Absolute Maximum Ratings, Order Information, Electrical Characteristics (Normal Speed),
Electrical Characteristics (2x Speed), Converter Characteristics, Power Requirements, and Timing Characteristics.
2-5
2480fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
41
LTC2480
TYPICAL APPLICATION
5V
PIC16F73
RC7
C8
C7
0.1μF
20
18
17
16
15
14
13
12
11
28
27
26
25
24
23
22
21
7
5V
V
1μF
DD
C6
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
RA5
RA4
RA3
RA2
RA1
RA0
0.1μF
ISOTHERMAL
Y1
3
2
R2
2k
9
6MHz
6
9
7
1
REF
V
CC
CS
SCK
SDO
SDI
OSC1
OSC2
4
5
+
–
IN
10
LTC2480
D1
BAT54
R1
10k
IN
10
TYPE K
THERMOCOUPLE
JACK
f
O
GND GND
1
5V
MCLR
8
11
(OMEGA MPJ-K-F)
5V
D7
D6
D5
D4
EN
RW
RS
V
CC
2 s 16 CHARACTER
LCD DISPLAY
(OPTREX DMC162488
OR SIMILAR)
6
5
4
3
5V
1
3
R6
5k
9
CONTRAST
V
V
SS
19
GND D0 D1 D2 D3
2
2
SS
5V
2480 F44
R3
R4
R5
CALIBRATE
10k 10k 10k
2
1
DOWN
UP
Figure 44. Complete Type K Thermocouple Meter
RELATED PARTS
PART NUMBER
LTC1050
DESCRIPTION
COMMENTS
Precision Chopper Stabilized Op Amp
Precision Bandgap Reference, 5V
No External Components 5μV Offset, 1.6μV Noise
P-P
LT1236A-5
0.05ꢀ Max Initial Accuracy, 5ppm/°C Drift
LT1460
Micropower Series Reference
0.075ꢀ Max Initial Accuracy, 10ppm/°C Max Drift
LTC2400
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA
0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA
24-Bit, No Latency ΔΣ ADC in SO-8
1-/2-Channel, 24-Bit, No Latency ΔΣ ADCs in MSOP
LTC2401/LTC2402
LTC2404/LTC2408
4-/8-Channel, 24-Bit, No Latency ΔΣ ADCs
with Differential Inputs
LTC2410
0.8μV
Noise, 2ppm INL
Noise, 4ppm INL,
24-Bit, No Latency ΔΣ ADC with Differential Inputs
RMS
LTC2411/LTC2411-1
1.45μV
RMS
24-Bit, No Latency ΔΣ ADCs with Differential Inputs in MSOP
Simultaneous 50Hz/60Hz Rejection (LTC2411-1)
LTC2413
Simultaneous 50Hz/60Hz Rejection, 800nV
Noise
RMS
24-Bit, No Latency ΔΣ ADC with Differential Inputs
24-Bit, No Latency ΔΣ ADCs with 15Hz Output Rate
8-/16-Channel 24-Bit, No Latency ΔΣ ADCs
20-Bit, No Latency ΔΣ ADC in SO-8
LTC2415/LTC2415-1
LTC2414/LTC2418
LTC2420
Pin-Compatible with the LTC2410
0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200μA
1.2ppm Noise, 8ppm INL, Pin-Compatible with LTC2400
2.8μV Noise, SSOP-16/MSOP Package
LTC2430/LTC2431
LTC2435/LTC2435-1
LTC2440
20-Bit, No Latency ΔΣ ADCs with Differential Inputs
20-Bit, No Latency ΔΣ ADCs with 15Hz Output Rate
High Speed, Low Noise 24-Bit ΔΣ ADC
3ppm INL, Simultaneous 50Hz/60Hz Rejection
3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs
Pin-Compatible with LTC2480/LTC2484
LTC2482
16-Bit ΔΣ ADC with Easy Drive Inputs
LTC2484
Pin-Compatible with LTC2480/LTC2482
24-Bit ΔΣ ADC with Easy Drive Inputs
2480fc
LT 0410 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
42
●
●
© LINEAR TECHNOLOGY CORPORATION 2005
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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