LTC2512IDKD-24#PBF [Linear]
LTC2512-24 - 24-Bit Over-Sampling ADC with Configurable Flat Passband Digital Filter; Package: DFN; Pins: 24; Temperature Range: -40°C to 85°C;
| 型号： | LTC2512IDKD-24#PBF |
| 厂家： | 
Linear |
| 描述： | LTC2512-24 - 24-Bit Over-Sampling ADC with Configurable Flat Passband Digital Filter; Package: DFN; Pins: 24; Temperature Range: -40°C to 85°C 光电二极管 转换器 |
| 文件： | 总38页 (文件大小：692K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2512-24
24-Bit Over-Sampling ADC
with Configurable Flat Passband Digital Filter
FEATURES
DESCRIPTION
The LTC®2512-24 is a low noise, low power, high-perfor-
n
±±11pm INmꢀ(y1)
n
±±7dBmDynapicmRangemꢀ(y1)matm50ks1s
±08dBmDynapicmRangemꢀ(y1)matm400ks1s
Guaranteedm24-BitsmIomMissingmCodes
ConfigurablemDigitalmFiltermwithmSynchronization
mance 24-bit ADC with an integrated configurable digital
filter. Operating from a single 2.5V supply, the LTC2512-
n
n
n
24 features a fully differential input range up to VREF
with V
,
ranging from 2.5V to 5.1V. The LTC2512-24
REF
n
RelaxedmAnti-AliasingmFiltermRequirepents
supports a wide common mode range from 0V to V
REF
n
DualmOut1utm24-BitmSARmADC
simplifying analog signal conditioning requirements.
n
24-BitmDigitallymFilteredmNowmIoisemOut1utm
The LTC2512-24 simultaneously provides two output
codes: (1) a 24-bit digitally filtered high precision low
noise code, and (2) a 22-bit no latency composite code.
The configurable digital filter reduces measurement noise
by lowpass filtering and down-sampling the stream of
data from the SAR ADC core, giving the 24-bit filtered
output code. The 22-bit composite code consists of a
14-bit code representing the differential voltage and an
8-bit code representing the common mode voltage. The
22-bit composite code is available each conversion cycle,
with no cycle of latency.
n
±4-BitmDifferentialm+m8-BitmCopponmModemm
IomNatencymOut1ut
n
n
n
n
n
Widem n1utmCoppon-ModemRange
Guaranteed Operation to 85°C
1.8V to 5V SPI-Compatible Serial I/O
Low Power: 30mW at 1.6Msps
24-Lead 7mm × 4mm DFN Package
APPLICATIONS
n
Seismology
n
Energy Exploration
The digital filter can be easily configured for 4 different
down-sampling factors by pin strapping. The configura-
tions provide a dynamic range of 108dB at 400ksps and
117dB at 50ksps. The digital lowpass filter relaxes the
requirements for analog anti-aliasing. Multiple LTC2512-
24 devices can be easily synchronized using the SYNC pin.
n
Automated Test Equipment (ATE)
High-Accuracy Instrumentation
n
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents, including 7705765, 7961132, 8319673, 8576104, 8810443, 9054727,
9231611, 9331709 and Patents pending.
TYPICAL APPLICATION
ntegralmIonlinearitymm
vsm n1utmVoltage
2.5V
1.8V TO 5V
3
10µF
0.1µF
+
–
IN , IN
2
V
OV
DD
LTC2512-24
SAMPLE
CLOCK
MCLK
BUSY
DRL
SDOA
SCKA
RDLA
RDLB
SDOB
SCKB
251224 TA01
DD
ARBITRARY
DIFFERENTIAL
V
V
REF
REF
+
1
0
PIN SELECTABLE
LOW-PASS
IN
24-BIT
SAR ADC
CORE
0V
0V
FLAT PASSBAND
DIGITAL FILTER
24-BIT
14-BIT
BIPOLAR
UNIPOLAR
V
REF
V
REF
–
IN
–1
–2
–3
0V
0V
REF
GND
+
–
DIFFERENTIAL INPUTS IN /IN WITH
WIDE INPUT COMMON MODE RANGE
2.5V TO 5.1V
47µF
(X7R, 1210 SIZE)
–5
–2.5
0
2.5
5
INPUT VOTLAGE (V)
251224f TA01a
251224fa
1
For more information www.linear.com/LTC2512-24
LTC2512-24
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
ꢀIotesm±,m2)
TOP VIEW
Supply Voltage (V )...............................................2.8V
DD
Supply Voltage (OV )................................................6V
DD
RDLA 1
RDLB 2
24 GND
23 GND
Reference Input (REF).................................................6V
V
DD
3
22 OV
DD
Analog Input Voltage (Note 3)
GND 4
21 BUSY
20 SDOB
19 SCKB
18 SCKA
17 SDOA
16 GND
15 DRL
14 SYNC
13 MCLK
+
+
–
IN
IN
5
6
IN , IN .........................(GND – 0.3V) to (REF + 0.3V)
Digital Input Voltage
–
25
GND
GND 7
REF 8
REF 9
REF 10
SEL0 11
SEL1 12
(Note 3).......................... (GND – 0.3V) to (OV + 0.3V)
DD
Digital Output Voltage
(Note 3).......................... (GND – 0.3V) to (OV + 0.3V)
DD
Power Dissipation.............................................. 500mW
Operating Temperature Range
DKD PACKAGE
24-LEAD (7mm ꢀ 4mm) PLASTIC DFN
LTC2512C-24 ........................................... 0°C to 70°C
LTC2512I-24.........................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
T
= 125°C, θ = 40°C/W
JA
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
JMAX
htt1://www.linear.cop/1roduct/N(C25±2-24#orderinfo
ORDER INFORMATION
NEADmFREEmF I SH
(APEmAIDmREEN
LTC2512CDKD-24#TRPBF 251224
LTC2512IDKD-24#TRPBF 251224
PAR(mMARK IG*
PACKAGEmDESCR P( OI
24-Lead (7mm × 4mm) Plastic DFN
24-Lead (7mm × 4mm) Plastic DFN
(EMPERA(UREmRAIGE
0°C to 70°C
–40°C to 85°C
LTC2512CDKD-24#PBF
LTC2512IDKD-24#PBF
Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
ELECTRICAL CHARACTERISTICS (hemlmdenotesmthems1ecificationsmwhichma11lymovermthemfullmo1eratingm
tep1eraturemrange,motherwisems1ecificationsmarematm(Am=m25°C.mꢀIotem4)
SYMBON
PARAME(ER
COID ( OIS
M I
0
(YP
MAX
UI (S
+
+
l
l
l
l
V
V
V
V
Absolute Input Range (IN )
(Note 5)
V
V
V
V
V
V
IN
IN
IN
REF
REF
REF
REF
–
+
–
Absolute Input Range (IN )
(Note 5)
0
–
+
–
– V
Input Differential Voltage Range
Common-Mode Input Range
Analog Input Leakage Current
Analog Input Capacitance
V
IN
= V – V
–V
REF
V
IN
IN
IN
0
V
CM
I
10
nA
IN
C
IN
Sample Mode
Hold Mode
45
5
pF
pF
CMRR
Input Common Mode Rejection Ratio
Filtered Output
IN
128
dB
+
–
V
= V = 4.5V , 2kHz Sine
IN P-P
251224fa
2
For more information www.linear.com/LTC2512-24
LTC2512-24
CONVERTER CHARACTERISTICS FOR FILTERED OUTPUT (SDOA) (hemlmdenotesm
thems1ecificationsmwhichma11lymovermthemfullmo1eratingmtep1eraturemrange,motherwisems1ecificationsmarematm(Am=m25°C.mꢀIotem4)
SYMBON
PARAME(ER
COID ( OIS
M I
24
24
4
(YP
MAX
UI (S
Bits
l
l
l
Resolution
No Missing Codes
Down-sampling Factor
Transition Noise
Bits
DF
32
DF = 4 (Note 6)
DF = 8 (Note 6)
DF = 16 (Note 6)
DF = 32 (Note 6)
21
LSB
RMS
RMS
RMS
RMS
14.9
10.5
7.5
LSB
LSB
LSB
l
l
INL
Integral Linearity Error
Zero-Scale Error
(Note 7)
(Note 9)
–3.5
–14
1
0
3.5
14
ppm
ppm
ZSE
Zero-Scale Error Drift
Full-Scale Error
7
ppb/°C
ppm
l
FSE
(Note 9)
–100
10
0.05
100
Full-Scale Error Drift
ppm/°C
DYNAMIC ACCURACY FOR FILTERED OUTPUT (SDOA) (hemlmdenotesmthems1ecificationsm
whichma11lymovermthemfullmo1eratingmtep1eraturemrange,motherwisems1ecificationsmarematm(Am=m25°CmandmA m=m–±dBFS.mꢀIotesmm4,m±0)
I
SYMBON
PARAME(ER
COID ( OIS
M I
(YP
MAX
UI (S
DR
Dynamic Range
f
IN
f
IN
f
IN
f
IN
= 2kHz, V = 5V, DF = 4
108
111
114
117
dB
dB
dB
dB
REF
= 2kHz, V = 5V, DF = 8
REF
= 2kHz, V = 5V, DF = 16
REF
= 2kHz, V = 5V, DF = 32
REF
l
l
l
SINAD
SNR
Signal-to-(Noise + Distortion) Ratio
Signal-to-Noise Ratio
f
f
= 2kHz, V = 5V, DF = 4
103
103
107
107
dB
dB
IN
IN
REF
= 2kHz, V = 5V, DF = 4
REF
THD
Total Harmonic Distortion
f
f
= 2kHz, V = 5V, DF = 4
–120
–120
–110
dB
dB
IN
IN
REF
= 2kHz, V = 2.5V, DF = 4
REF
l
SFDR
Spurious Free Dynamic Range
f
IN
f
IN
= 2kHz, V = 5V, DF = 4
110
120
120
dB
dB
REF
= 2kHz, V = 2.5V, DF = 4
REF
Aperture Delay
500
4
ps
Aperture Jitter
ps
RMS
Transient Response
Full-Scale Step
152
ns
251224fa
3
For more information www.linear.com/LTC2512-24
LTC2512-24
m
denotesmthems1ecificationsmwhichma11lymovermthemfullmo1eratingmtep1eraturemrange,motherwisems1ecificationsmarematm(Am=m25°C.mꢀIotem4)
SYMBON
PARAME(ER
COID ( OIS
M I
(YP
MAX
UI (S
Resolution:
l
l
Differential
14
8
Bits
Bits
Common Mode
No Missing Codes:
Differential
Common Mode
l
l
14
8
Bits
Bits
Transition Noise
Differential
(Note 6)
(Note 7)
1
1
LSB
RMS
RMS
Common Mode
LSB
INL
Integral Linearity Error
Differential
Common Mode
0.2
0.2
LSB
LSB
DNL
Differential Linearity Error
Differential
Common Mode
0.2
0.2
LSB
LSB
–3dB Input Linear Bandwidth
34
MHz
ZSE
FSE
Zero Scale Error
Differential
1
1
LSB
LSB
Common Mode
Full Scale Error
Differential
Common Mode
1
1
LSB
LSB
R
EFERENCE INPUT (hemlmdenotesmthems1ecificationsmwhichma11lymovermthemfullmo1eratingmtep1eraturemrange,motherwisem
s1ecificationsmarematm(Am=m25°C.mꢀIotesm4,m9)
SYMBON
PARAME(ER
COID ( OIS
(Note 5)
M I
(YP
MAX
5.1
UI (S
V
l
l
V
Reference Voltage
Reference Input Current
2.5
REF
REF
I
(Note 11)
1.5
1.8
mA
m
fullmo1eratingmtep1eraturemrange,motherwisems1ecificationsmarematm(Am=m25°C.mꢀIotem4)
SYMBON
PARAME(ER
COID ( OIS
M I
(YP
MAX
UI (S
V
l
l
l
V
IH
V
IL
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
0.8•OV
DD
0.2•OV
10
V
DD
I
V
IN
= 0V to OV
DD
–10
μA
pF
IN
C
V
V
Digital Input Capacitance
High Level Output Voltage
Low Level Output Voltage
Hi-Z Output Leakage Current
Output Source Current
Output Sink Current
5
IN
l
l
l
I = –500µA
O
OV –0.2
DD
V
OH
OL
I = 500µA
O
0.2
10
V
I
I
I
V
OUT
V
OUT
V
OUT
= 0V to OV
DD
–10
µA
mA
mA
OZ
= 0V
= OV
–10
10
SOURCE
SINK
DD
251224fa
4
For more information www.linear.com/LTC2512-24
LTC2512-24
m
range,motherwisems1ecificationsmarematm(Am=m25°C.mꢀIotem4)
SYMBON
PARAME(ER
Supply Voltage
Supply Voltage
COID ( OIS
M I
2.375
1.71
(YP
MAX
2.625
5.25
16
UI (S
l
l
l
V
2.5
V
V
DD
OV
DD
I
I
I
Supply Current
Supply Current
Power Down Mode
1.6Msps Sample Rate
12
0.4
1
mA
mA
µA
VDD
OVDD
PD
1.6Msps Sample Rate (C = 20pF)
L
l
Conversion Done (I
+ I
+ I
)
)
350
VDD
OVDD
REF
P
Power Dissipation
Power Down Mode
1.6Msps Sample Rate (I
Conversion Done (I
)
30
2.5
40
875
mW
µW
D
VDD
+ I
+ I
VDD
OVDD
REF
m
tep1eraturemrange,motherwisems1ecificationsmarematm(Am=m25°C.mꢀIotem4)
SYMBON
PARAME(ER
COID ( OIS
M I
(YP
MAX
1.6
UI (S
Msps
ksps
Msps
ns
l
l
l
l
l
l
l
l
l
l
l
l
l
l
f
f
f
t
t
t
t
t
t
t
t
t
t
t
t
Maximum Sampling Frequency
Output Data Rate at SDOA
Output Data Rate at SDOB
Conversion Time
(Note 12)
SMPL
DRA
400
1.6
(Note 12)
DRB
405
152
625
20
460
CONV
ACQ
Acquisition Time
t
= t
– t
– t (Note 8)
BUSYLH
ns
ACQ
CYC
CONV
Time Between Conversions
MCLK High Time
ns
CYC
ns
MCLKH
MCLKL
BUSYLH
DRLLH
QUIET
SCKA
Minimum Low Time for MCLK
MCLK↑ to BUSY↑ Delay
MCLK↑ to DRL↑ Delay
SCKA, SCKB Quiet Time from MCLK↑
SCKA Period
(Note 13)
C = 20pF
20
ns
13
18
ns
L
C = 20pF
L
ns
(Note 8)
10
10
4
ns
(Notes 13, 14)
ns
SCKA High Time
ns
SCKAH
SCKAL
DSDOA
SCKA Low Time
4
ns
l
l
l
SDOA Data Valid Delay from SCKA↑
C = 20pF, OV = 5.25V
8.5
8.5
9.5
ns
ns
ns
L
DD
DD
DD
C = 20pF, OV = 2.5V
L
C = 20pF, OV = 1.71V
L
l
l
l
l
l
l
l
t
t
t
t
t
t
t
t
SDOA Data Remains Valid Delay from SCKA↑
SDOA Data Valid Delay from DRL↓
Bus Enable Time After RDLA↓
Bus Relinquish Time After RDLA↑
SCKB Period
C = 20pF (Note 8)
1
ns
ns
ns
ns
ns
ns
ns
HSDOA
DSDOADRLL
ENAA
L
C = 20pF (Note 8)
L
5
(Note 13)
16
13
(Note 13)
DISA
(Notes 13, 14)
10
4
SCKB
SCKB High Time
SCKBH
SCKBL
DSDOB
SCKB Low Time
4
l
l
l
SDOB Data Valid Delay from SCKB↑
C = 20pF, OV = 5.25V
8.5
8.5
9.5
ns
ns
ns
L
DD
C = 20pF, OV = 2.5V
L
DD
C = 20pF, OV = 1.71V
L
DD
l
t
SDOB Data Remains Valid Delay from SCKB↑
C = 20pF (Note 8)
L
1
ns
HSDOB
251224fa
5
For more information www.linear.com/LTC2512-24
LTC2512-24
m
tep1eraturemrange,motherwisems1ecificationsmarematm(Am=m25°C.mꢀIotem4)
SYMBON
PARAME(ER
COID ( OIS
M I
(YP
MAX
5
UI (S
ns
l
l
t
t
t
SDOB Data Valid Delay from BUSY↓
Bus Enable Time After RDLB↓
Bus Relinquish Time After RDLB↑
C = 20pF (Note 8)
L
DSDOBBUSYL
ENB
(Note 13)
(Note 13)
16
13
ns
ns
DISB
Iotem±: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Iotem2: All voltage values are with respect to ground.
Iotem3: When these pin voltages are taken below ground or above REF or
Iotem8: Guaranteed by design, not subject to test.
Iotem9: Bipolar zero-scale error is the offset voltage measured from
–0.5LSB when the output code flickers between 0000 0000 0000 0000
0000 0000 and 1111 1111 1111 1111 1111 1111. Full-scale bipolar error
is the worst-case of –FS or +FS untrimmed deviation from ideal first and
last code transitions and includes the effect of offset error.
OV , they will be clamped by internal diodes. This product can handle
Iotem±0: All specifications in dB are referred to a full-scale 5V input with
a 5V reference voltage.
DD
input currents up to 100mA below ground or above REF or OV without
DD
latch-up.
Iotem±±: f
= 1.6MHz, I varies proportionally with sample rate.
REF
SMPL
Iotem4: V = 2.5V, OV = 2.5V, REF = 5V, V = 2.5V, f = 1.6MHz,
DF = 4.
DD
DD
CM
SMPL
Iotem±2: f
and f
are specified with only shifting out the 14-bit
SMPL
DRB
differential result. Shifting out the 8-bit common-mode result requires
additional I/O time resulting in maximum sampling and output data rates
of 1.42Msps.
Iotem5: Recommended operating conditions.
+
Iotem6: Transition noise is defined as the noise level of the ADC with IN
–
and IN shorted.
Iotem±3: Parameter tested and guaranteed at OV = 1.71V, OV = 2.5V
DD DD
and OV = 5.25V.
DD
Iotem7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Iotem±4: t
, t
of 10ns maximum allows a shift clock frequency up
SCKA SCKB
to 100MHz for rising edge capture.
0.8•OV
t
DD
t
WIDTH
0.2•OV
DD
50%
50%
t
DELAY
DELAY
251224 F01
0.8•OV
0.2•OV
0.8•OV
0.2•OV
DD
DD
DD
DD
Figurem±.mVoltagemNevelsmformS1ecifications
251224fa
6
For more information www.linear.com/LTC2512-24
LTC2512-24
m
(Am=m25°C,mVDDm=m2.5V,mOVDDm=m2.5V,mVCMm=m2.5V,m
TYPICAL PERFORMANCE CHARACTERISTICS
REFm=m5V,mfSMPNm=m±.6Ms1s,mDFm=m4,mFilteredmOut1ut,munlessmotherwisemnoted.
ntegralmIonlinearitymm
vsm n1utmVoltage
DifferentialmIonlinearitymm
vsm n1utmVoltage
ntegralmIonlinearitymm
vsmOut1utmCode
3.50
3
2
1.0
0.8
0.6
1.75
0
0.4
1
0.2
0
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
–1
–2
–3
–1.75
ARBITRARY DRIVE
+
–
IN /IN SWEPT 0V to 5V
–3.50
–5
–2.5
0
2.5
5
–5
–2.5
0
2.5
5
–5
–2.5
0
2.5
5
INPUT VOLTAGE (V)
INPUT VOTLAGE (V)
INPUT VOLTAGE (V)
251224 G03
251224 G02
251224 G01
DCmHistograp,mDFm=m4
DCmHistograp,mDFm=m8
DCmHistograp,mDFm=m±6
20000
16000
12000
8000
4000
0
20000
16000
12000
8000
4000
0
20000
16000
12000
8000
4000
0
σ = 23.9
σ = 16.9
σ = 12.02
–200
–100
0
100
200
–200
–100
0
100
200
–50
–25
0
25
50
CODE
CODE
CODE
251224 G05
251224 G04
251224 G06
±28kmPointmFF(mfSMPNm=m±.6Ms1s,mm
f m=m2kHz,mDFm=m4
±28kmPointmFF(mfSMPNm=m±.6Ms1s,mm
f m=m2kHz,mDFm=m8
DCmHistograp,mDFm=m32
I
I
20000
16000
12000
8000
4000
0
0
–20
0
–20
SNR = 111dB
SNR = 108dB
σ = 8.47
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
–50
–25
0
25
50
0
50
100
FREQUENCY (kHz)
150
200
0
25
50
FREQUENCY (kHz)
75
100
CODE
251224 G09
251224 G07
251224 G08
251224fa
7
For more information www.linear.com/LTC2512-24
LTC2512-24
(Am=m25°C,mVDDm=m2.5V,mOVDDm=m2.5V,mVCMm=m2.5V,m
TYPICAL PERFORMANCE CHARACTERISTICS
REFm=m5V,mfSMPNm=m±.6Ms1s,mDFm=m4,mFilteredmOut1ut,munlessmotherwisemnoted.
±28kmPointmFF(mfSMPNm=m±.6Ms1s,mm
f m=m2kHz,mDFm=m±6
±28kmPointmFF(mfSMPNm=m±.6Ms1s,mm
f m=m2kHz,mDFm=m32
DynapicmRange,m(ransitionmIoisem
vsmDF
I
I
0
–20
0
–20
125
120
115
110
105
25
SNR = 114dB
SNR = 117dB
–40
–40
18.75
12.5
6.25
0
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
–180
0
12.5
25
FREQUENCY (kHz)
37.5
50
0
5
10
15
20
25
4
8
16
32
FREQUENCY (kHz)
DOWN SAMPLING FACTOR (DF)
251224 G10
251224 G11
251224 G12
FrequencymRes1onse,mm
DFm=m4,m8,m±6,m32
SIR,mS IADmvsm n1utmNevel,mm
f m=m2kHz
SIR,mS IADmvsm n1utmFrequency
I
110
109
108
107
106
105
10
0
110
109
108
107
106
105
DF = 4
DF = 8
DF = 16
DF = 32
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
SNR
SNR
SINAD
SINAD
0
F
/16
F
/8
F
/4 3F
SMPL
/16
SMPL
0
25
50
75
100
–40
–30
–20
–10
0
SMPL
SMPL
INPUT FREQUENCY (kHz)
INPUT LEVEL (dB)
FREQUENCY (Hz)
251224 G14
251224 G13
251224 G15
SIR,mS IADmvsmReferencem
Voltage,mf m=m2kHz
(HD,mHarponicsmvsmReferencem
ReferencemCurrentmm
vsmReferencemVoltage
Voltage,mf m=m2kHz
I
I
108
107
106
105
104
103
102
–115
–120
–125
–130
–135
–140
–145
2.0
1.5
1.0
0.5
SNR
SINAD
THD
2ND
3RD
2.5
3
3.5
4
4.5
5
2.5
3
3.5
4
4.5
5
2.5
3
3.5
4
4.5
5
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
251224 G16
251224 G17
251224 G18
251224fa
8
For more information www.linear.com/LTC2512-24
LTC2512-24
m
(Am=m25°C,mVDDm=m2.5V,mOVDDm=m2.5V,mVCMm=m2.5V,m
TYPICAL PERFORMANCE CHARACTERISTICS
REFm=m5V,mfSMPNm=m±.6Ms1s,mDFm=m4,mFilteredmOut1ut,munlessmotherwisemnoted.
SIR,mS IADmvsm(ep1erature,mm
f m=m2kHz
(HD,mHarponicsmm
vsm(ep1erature,mf m=m2kHz
INmvsm(ep1erature
I
I
110
109
108
107
106
105
–120
–122
–124
–126
–128
–130
4
3
2
THD
MAX INL
SNR
1
SINAD
0
2ND
3RD
–1
–2
–3
–4
MIN INL
–40
–15
10
35
60
85
–40
–15
10
35
60
85
–40
–15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
251224 G19
251224 G20
251224 G21
Full-ScalemErrormvsm(ep1erature
OffsetmErrormvsm(ep1erature
Su11lymCurrentmvsm(ep1erature
10
5
5
4
15
12
9
3
I
I
I
2
VDD
OVDD
REF
–FS
+FS
1
0
0
–1
–2
–3
–4
–5
6
–5
3
–10
0
–40
–15
10
35
60
85
–40
–15
10
35
60
85
–40
–15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
251224 G22
251224 G23
251224 G24
CopponmModemRejectionmm
vsm n1utmFrequency
ShutdownmCurrentmvsm(ep1erature
40
30
20
10
0
200
175
150
125
100
75
–40
–15
10
35
60
85
0.0001
0.001
0.01
0.1
1
4
FREQUENCY (MHz)
TEMPERATURE (°C)
251224 G25
251224 G26
251224fa
9
For more information www.linear.com/LTC2512-24
LTC2512-24
m
(Am=m25°C,mVDDm=m2.5V,mOVDDm=m2.5V,mVCMm=m2.5V,m
TYPICAL PERFORMANCE CHARACTERISTICS
REFm=m5V,mfSMPNm=m±.6Ms1s,mIomNatencym±4-BitmOut1ut,munlessmotherwisemnoted.
IomNatencymDifferentialmOut1utm
±28kmPointmFF(,mf m=m2kHz
IomNatencymDifferentialmOut1utm INm
vsm n1utmVoltage
IomNatencymDifferentialmOut1utmDINm
vsm n1utmVoltage
I
0
–20
0.5
0.4
0.5
0.4
SNR = 86dB
–40
0.3
0.3
–60
0.1
0.1
–80
0
0
–100
–120
–140
–160
–0.1
–0.3
–0.4
–0.5
–0.1
–0.3
–0.4
–0.5
0
200
400
600
800
–5
–2.5
0
2.5
5
FREQUENCY (kHz)
INPUT VOTLAGE (V)
–5
–2.5
0
2.5
5
251224 G27
251224 G28
INPUT VOTLAGE (V)
251224 G29
IomNatencymCopponmModemOut1ut
±28kmPointmFF(,mf I = 2kHz
0
–20
SNR = 48dB
–40
–60
–80
–100
–120
0
200
400
600
800
FREQUENCY (kHz)
251224 G30
251224fa
10
For more information www.linear.com/LTC2512-24
LTC2512-24
PIN FUNCTIONS
RDNAmꢀPinm±): Read Low Input A (Filtered Output).
When RDLA is low, the serial data output A (SDOA) pin
is enabled. When RDLA is high, SDOA pin is in a high-
DRNmꢀPinm±5): Data Ready Low Output. A falling edge
on this pin indicates that a new filtered output code is
available in the output register of SDOA. Logic levels are
impedance state. Logic levels are determined by OV .
determined by OV .
DD
DD
RDNBmꢀPinm2): Read Low Input B (No Latency Output).
When RDLB is low, the serial data output B (SDOB) pin
is enabled. When RDLB is high, SDOB pin is in a high-
SDOAmꢀPinm±7) : Serial Data Output A (Filtered Output).
The filtered output code appears on this pin (MSB first)
on each rising edge of SCKA. The output data is in 2’s
complement format. Logic levels are determined by OVDD.
impedance state. Logic levels are determined by OV .
DD
VDDmꢀPinm3): 2.5V Power Supply. The range of VDD is
2.375V to 2.625V. Bypass VDD to GND with a 10µF
ceramic capacitor.
SCKAmꢀPinm±8):Serial Data Clock Input A (Filtered Output).
When SDOA is enabled, the filtered output code is shifted
out (MSB first) on the rising edges of this clock. Logic
levels are determined by OV .
DD
GIDmꢀPinsm4,m7,m±6,m23,m24): Ground.
SCKBmꢀPinm±9): Serial Data Clock Input B (No Latency
Output). When SDOB is enabled, the no latency output
code is shifted out (MSB first) on the rising edges of this
+
I mꢀPinm5): Positive Analog Input.
–
I mꢀPinm6): Negative Analog Input.
clock. Logic levels are determined by OV .
DD
REFmꢀPinsm8,m9,m±0): Reference Input. The range of REF
is 2.5V to 5.1V. This pin is referred to the GND pin and
should be decoupled closely to the pin with a 47µF ceramic
capacitor (X7R, 1210 size, 10V rating).
SDOBmꢀPinm20): Serial Data Output B (No Latency Output).
The 22-bit no latency composite output code appears on
this pin (MSB first) on each rising edge of SCKB. The
output data is in 2’s complement format. Logic levels are
SEN0,mSEN±mꢀPinsm±±,m±2): Down-Sampling Factor Select
Input 0, Down-Sampling Factor Select Input 1. Selects the
down-sampling factor for the digital filter. Down-sampling
factors of 4, 8, 16 and 32 are selected for [SEL1 SEL0]
combinations of 00, 01, 10 and 11 respectively. Logic
determined by OV .
DD
BUSYmꢀPinm2±): BUSY Indicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished. Logic levels are determined by OV .
DD
levels are determined by OV .
DD
OV mꢀPinm22): I/O Interface Digital Power. The range of
DD
MCNKmꢀPinm±3): Master Clock Input. A rising edge on this
OV is 1.71V to 5.25V. This supply is nominally set to
DD
input powers up the part and initiates a new conversion.
the same supply as the host interface (1.8V, 2.5V, 3.3V,
or 5V). Bypass OVDD to GND (Pin 23) close to the pin with
a 0.1µF capacitor.
Logic levels are determined by OV .
DD
SYICmꢀPinm±4) : Synchronization Input. A pulse on this
input is used to synchronize the phase of the digital filter.
GIDmꢀEx1osedmPadmPinm25): Ground. Exposed pad must
be soldered directly to the ground plane.
Logic levels are determined by OV .
DD
251224fa
11
For more information www.linear.com/LTC2512-24
LTC2512-24
FUNCTIONAL BLOCK DIAGRAM
V
DD
= 2.5V
OV = 1.8V TO 5V
DD
REF = 5V
LTC2512-24
+
IN
IN
+
–
SCKA
SDOA
RDLA
24
24-BIT
SAR ADC
DIGITAL
FILTER
SPI
PORT
–
SCKB
SDOB
RDLB
14
MCLK
BUSY
DRL
CONTROL LOGIC
SYNC
SEL0
SEL1
GND
251224f FBD
TIMING DIAGRAM
Conversionm(ipingmUsingmthemSerialm nterface
RDLA = RDLB = 0
MCLK
CONVERT
DRL
SCKA
DA22 DA20 DA18 DA16 DA14 DA12 DA10
DA8
DA6
DA4
CB2
DA2
CB0
DA0
WA6
WA4
WA2
WA0
SDOA
BUSY
SCKB
SDOB
DA23 DA21 DA19 DA17 DA15 DA13 DA11
DA9
DA7
DA5
DA3
CB1
DA1
WA7
WA5
WA3
WA1
CONVERT
POWER DOWN AND ACQUIRE
DB12 DB10
DB8
DB6
DB4
DB2
DB0
CB6
CB4
251224 TD
DB13 DB11
DB9
DB7
DB5
DB3
DB1
CB7
CB5
CB3
251224fa
12
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
OVERV EW
voltage are combined to form a 22-bit composite code.
The 22-bit composite code is available each conversion
cycle, without any cycle of latency.
The LTC2512-24 is a low noise, low power, high-perfor-
mance 24-bit ADC with an integrated configurable digital
filter. Operating from a single 2.5V supply, the LTC2512-
(RAISFERmFUIC( OI
24 features a fully differential input range up to VREF
with V
,
ranging from 2.5V to 5.1V. The LTC2512-24
REF
The LTC2512-24 digitizes the full-scale differential voltage
24
supports a wide common mode range from 0V to V
REF
of 2× V into 2 levels, resulting in an LSB size of 596nV
REF
simplifying analog signal conditioning requirements.
with a 5V reference. The ideal transfer function is shown
in Figure 2. The output data is in 2’s complement format.
The LTC2512-24 simultaneously provides two output
codes: (1) a 24-bit digitally filtered high precision low
noise code, and (2) a 22-bit no latency composite code.
The configurable digital filter reduces measurement noise
by lowpass filtering and down-sampling the stream of
data from the SAR ADC core, giving the 24-bit filtered
output code. The 22-bit composite code consists of a
14-bit code representing the differential voltage and an
8-bit code representing the common mode voltage. The
22-bit composite code is available each conversion cycle,
with no cycle of latency.
011...111
BIPOLAR
ZERO
011...110
000...001
000...000
111...111
111...110
100...001
100...000
FSR = +FS – –FS
1LSB = FSR/16777216
–1 0V
The digital filter can be easily configured for 4 different
down-sampling factors by pin strapping. The configura-
tions provide a dynamic range of 108dB at 400ksps and
117dB at 50ksps. The digital lowpass filter relaxes the
requirements for analog anti-aliasing. Multiple LTC2512-
24 devices can be easily synchronized using the SYNC pin.
1
LSB
–FSR/2
FSR/2 – 1LSB
LSB
INPUT VOLTAGE (V)
251224 F02
Figurem2.mN(C25±2-24m(ransfermFunction
AIANOGm IPU(
The LTC2512-24 samples the voltage difference (IN+
– IN–) between its analog input pins over a wide com-
mon mode input range while attenuating unwanted sig-
nals common to both input pins by the common-mode
rejection ratio (CMRR) of the ADC. Wide common mode
COIVER(ERmOPERA( OI
The LTC2512-24 operates in two phases. During the
acquisition phase, a 24-bit charge redistribution capacitor
D/A converter (CDAC) is connected to the IN+ and IN– pins
to sample the analog input voltages. A rising edge on the
MCLK pin initiates a conversion. During the conversion
phase, the 24-bit CDAC is sequenced through a succes-
sive approximation algorithm, effectively comparing the
sampled inputs with binary-weighted fractions of the ref-
+
–
input range coupled with high CMRR allows the IN /IN
analog inputs to swing with an arbitrary relationship to
each other, provided each pin remains between GND and
V . This unique feature of the LTC2512-24 enables it
REF
to accept a wide variety of signal swings, including tra-
ditional classes of analog input signals such as pseudo-
differential unipolar, pseudo-differential true bipolar, and
fully differential, thereby simplifying signal chain design.
erence voltage (e.g. V /2, V /4 … V /16777216). At
the end of conversionR,EthFe CDAC outputRaEpFproximates the
sampled analog input. The ADC control logic then passes
the 24-bit digital output code to the digital filter for further
processing. A 14-bit code representing the differential
voltage and an 8-bit code representing the common mode
REF
In the acquisition phase, each input sees approximately
45pF (C ) from the sampling circuit in series with 40Ω
IN
(RON) from the on-resistance of the sampling switch.
The inputs draw a current spike while charging the C
IN
251224fa
13
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
REF
requires wider bandwidth than LPF1. This filter also helps
minimize the noise contribution from the buffer. A buffer
amplifier with a low noise density must be selected to
minimize degradation of SNR.
C
45pF
IN
R
40Ω
ON
+
IN
BIAS
VOLTAGE
REF
LPF2
C
45pF
IN
R
40Ω
ON
6800pF
SINGLE-ENDED-
10Ω
–
IN
LPF1
INPUT SIGNAL
+
–
IN
500Ω
3300pF
LTC2512-24
251224 F03
6600pF
IN
10Ω
Figurem3.m(hemEquivalentmCircuitmformthemDifferentialm
Analogm n1utmofmthemN(C25±2-24
251224 F04
SINGLE-ENDED- 6800pF
TO-DIFFERENTIAL
DRIVER
BW = 48kHz
BW = 1.2MHz
capacitors during acquisition. During conversion, the ana-
log inputs draw only a small leakage current.
Figurem4.mFilteringm n1utmSignal
High quality capacitors and resistors should be used in
the RC filters since these components can add distor-
tion. NPO and silver mica type dielectric capacitors have
excellent linearity. Carbon surface mount resistors can
generate distortion from self-heating and from damage
that may occur during soldering. Metal film surface mount
resistors are much less susceptible to both problems.
IPU(mDR VEmC RCU (S
A low impedance source can directly drive the high imped-
ance inputs of the LTC2512-24 without gain error. A high
impedance source should be buffered to minimize settling
time during acquisition and to optimize ADC linearity. For
best performance, a buffer amplifier should be used to
drive the analog inputs of the LTC2512-24. The ampli-
fier provides low output impedance, which produces fast
settling of the analog signal during the acquisition phase.
It also provides isolation between the signal source and
the ADC inputs.
n1utmCurrents
An important consideration when coupling an amplifier to
the LTC2512-24 is in dealing with current spikes drawn by
the ADC inputs at the start of each acquisition phase. The
ADC inputs may be modeled as a switched capacitor load
of the drive circuit. A drive circuit may rely partially on
attenuating switched-capacitor current spikes with small
IoisemandmDistortion
The noise and distortion of an input buffer amplifier and
other supporting circuitry must be considered since they
add to the ADC noise and distortion. Noisy input signals
should be filtered prior to the buffer amplifier with a low
bandwidth filter to minimize noise. The simple one-pole
RC lowpass filter (LPF1) shown in Figure 4 is sufficient
for many applications.
filter capacitors C
placed directly at the ADC inputs,
FILT
and partially on the driver amplifier having sufficient band-
width to recover from the residual disturbance. Amplifiers
optimized for DC performance may not have sufficient
bandwidth to fully recover at the ADC’s maximum con-
version rate, which can produce nonlinearity and other
errors. Coupling filter circuits may be classified in three
broad categories:
A coupling filter network (LPF2) should be used between
the buffer and ADC input to minimize disturbances
reflected into the buffer from sampling transients. Long
RC time constants at the analog inputs will slow down
the settling of the analog inputs. Therefore, LPF2 typically
251224fa
14
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
Fully Settled – This case is characterized by filter time
constants and an overall settling time that is consider-ably
shorter than the sample period. When acquisition begins,
the coupling filter is disturbed. For a typical first order RC
filter, the disturbance will look like an initial step with an
exponential decay. The amplifier will have its own response
to the disturbance, which may include ringing. If the input
settles completely (to within the accuracy of the LTC2512-
24), the disturbance will not contribute any error.
LTC2512-24
+
–
IN
14k
C
C
>>45pF
>>45pF
FILT
FILT
(R
)
)
EQ
BIAS
VOLTAGE
14k
(R
EQ
IN
1
R
=
EQ
f
• 45pF
SMPL
251224 F05
Partially Settled – In this case, the beginning of acquisi-
tion causes a disturbance of the coupling filter, which then
begins to settle out towards the nominal input voltage.
However, acquisition ends (and the conversion begins)
before the input settles to its final value. This generally
produces a gain error, but as long as the settling is linear,
no distortion is produced. The coupling filter’s response
is affected by the amplifier’s output impedance and other
parameters. A linear settling response to fast switched-
capacitor current spikes can NOT always be assumed for
precision, low bandwidth amplifiers. The coupling filter
serves to attenuate the current spikes’ high-frequency
energy before it reaches the amplifier.
Figurem5.mEquivalentmCircuitmformthemDifferentialm
Analogm n1utmofmthemN(C25±2-24matm±.6Ms1s
10
V
= V
REF
IN
7
4
DIFFERENTIAL
COMMON
1
–2
–5
–40
–15
10
35
60
85
TEMPERATURE (°C)
Fully Averaged – If the coupling filter capacitors (C ) at
251224 F06
FILT
the ADC inputs are much larger than the ADC’s sample
capacitors (45pF), then the sampling glitch is greatly
attenuated. The driving amplifier effectively only sees
the average sampling current, which is quite small. At
1.6Msps, the equivalent input resistance is approximately
14k (as shown in Figure 5), a benign resistive load for
most precision amplifiers. However, resistive voltage divi-
sion will occur between the coupling filter’s DC resistance
and the ADC’s equivalent (switched-capacitor) input resis-
tance, thus producing a gain error.
Figurem6.mCopponmModemandmDifferentialm n1utm
NeakagemCurrentmOverm(ep1erature
Let RS1 and RS2 be the source impedances of the dif-
ferential input drive circuit shown in Figure 7, and let I
L1
and I be the leakage currents flowing out of the ADC’s
L2
analog inputs. The differential voltage error, VE, due to the
leakage currents can be expressed as:
RS1+R
IL1+IL2
VE =
S2 • I –I + R –R
•
)
S2
(
)
(
L1 L2
S1
2
2
The input leakage currents of the LTC2512-24 should
also be considered when designing the input drive circuit,
because source impedances will convert input leakage
currents to an added input voltage error. The input leak-
age currents, both common mode and differential, are
typically extremely small over the entire operating tem-
perature range. Figure 6 shows the input leakage currents
over temperature for a typical part.
The common mode input leakage current, (I + I )/2, is
L1
L2
typically extremely small (Figure 6) over the entire operat-
ing temperature range and common mode input voltage
range. Thus, any reasonable mismatch (below 5%) of the
source impedances R and R will cause only a negligible
error. The differentialSle1akage Sc2urrent is also typically very
small, and its nonlinear component is even smaller. Only
the nonlinear component will impact the ADC’s linearity.
251224fa
15
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
settling and good DC linearity with 1.9nV/RT(Hz) input-
referred noise density, enabling it to achieve the full ADC
data sheet SNR and THD specifications as shown in the
FFT plot in Figure 8b.
I
L1
R
S1
+
IN
+
LTC2512-24
V
E
–
–
IN
R
S2
I
L2
0
251224 F07
SNR = 107dB
–20
Figurem7.mSourcem p1edancesmofmamDrivermandm
n1utmNeakagemCurrentsmofmthemN(C25±2-24
–40
–60
–80
For optimal performance, it is recommended that the
source impedances, RS1 and RS2, be between 5Ω and
50Ω and with 1% tolerance. For source impedances in
this range, the voltage and temperature coefficients of
–100
–120
–140
–160
–180
–200
R
and R are usually not critical. The guaranteed AC
S1
S2
and DC specifications are tested with 5Ω source imped-
ances, and the specifications will gradually degrade with
increased source impedances due to incomplete settling.
0
50
100
150
200
FREQUENCY (kHz)
251224 F08b
Figurem8b.m±28kmPointmFF(mwithmf m=m2kHz,m
I
BufferingmArbitrarymAnalogm n1utmSignals
DFm=m4mformCircuitmShownminmFigurem8a
The wide common mode input range and high CMRR
BufferingmSingle-EndedmAnalogm n1utmSignals
+
of the LTC2512-24 allow the analog input pins, IN and
–
While the circuit shown in Figure 8a is capable of buffering
single-ended input signals, the circuit shown in Figure 9
is preferable when the single-ended signal reference level
is inherently low impedance and doesn’t require buffer-
ing. This circuit eliminates one driver and one lowpass
filter, reducing the part count, power dissipation, and SNR
degradation due to driver noise.
IN , to swing with an arbitrary relationship to each other,
provided that each pin remains between V
and GND.
REF
This unique feature of the LTC2512-24 enables it to accept
a wide variety of signal swings, simplifying signal chain
design.
It is recommended that the LTC2512-24 be driven using
the LT6203 ADC driver configured as two unity gain buf-
fers, as shown in Figure 8a. The LT6203 combines fast
2.5V
1.8V TO 5.1V
10µF
0.1µF
+
+
V
IN
10Ω
1/2 LT6203
V
DD
OV
DD
1.2nF
1.2nF
–
+
IN
LTC2512-24
–
IN
–
10Ω
REF
GND
1/2 LT6203
2.5V TO 5.1V
–
47µF
+
V
IN
(X7R, 1210 SIZE)
251224 F08a
Figurem8a.mBufferingm(womSingle-EndedmAnalogm n1utmSignals
251224fa
16
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
2.5V 1.8V TO 5V
10µF
0.1µF
V
OV
DD
DD
+
V
+
IN
10Ω
+
–
IN
IN
LT6202
LTC2512-24
–
1.2nF
REF
GND
2.5V TO 5.1V
47µF
(X7R, 1210 SIZE)
251224 F09
Figurem9.mBufferingmSingle-EndedmSignals
8V
LT5400-4
1k
6800pF
0.1µF
30.1Ω
30.1Ω
1k
+
+
IN
VOCM
V
/2
REF
6800pF
LTC6363
1k
1k
5V
0V
–
IN
–
+
V
IN
6800pF
–5V
0.1µF
–3V
0.1µF
251224 F10a
Figurem±0a.mBufferingmandmConvertingmam±5Vm(ruemBi1olarm n1utmSignalmtomamFullymDifferentialm n1ut
MaxipizingmthemSIRmUsingmFullymDifferentialm n1utm
Though not shown here, the LTC6363 may also be con-
figured to amplify or attenuate a signal to match the full
scale input range of the LTC2512-24.
Drive
In order to maximize the SNR, the input signal swing must
be maximized. A fully differential signal with a common-
mode of VREF/2 maximizes the input signal swing. The
circuit in Figure 8a is capable of buffering such a signal.
DrivingmDCmSignals
While the DC specifications of the LTC2512-24 are excel
-
lent, the digital filter, having a wide passband and low
passband ripple, is optimized for AC applications. The
digital filter of the LTC2512-24 improves the dynamic
range to 117dB with DF = 32. The LTC2508-32 has
digital filters with much lower bandwidths, leading to
greater noise suppression. Using the digital filter on the
LTC2508-32 with DF = 16384 leads to a dynamic range
of 146dB. This makes the LTC2508-32 a better choice
for digitizing DC inputs.
If the input signal does not have a common-mode of
VREF/2 or is single-ended, the LTC6363 differential ampli-
fier may be used in conjunction with the LT5400-4 preci-
sion resistors to produce a fully differential signal with a
common-mode of V /2. Figure 10a shows the LTC6363
buffering, level-shiftRinEgF and performing a single-ended to
differential conversion on a 5V single-ended true bipolar
input signal. The FFT in Figure 10b shows that near data
sheet performance is obtained with this driver solution.
251224fa
17
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
0
SNR = 107dB
cycle. The reference replenishes this charge with an
–20
average current, I
= Q
/t . The current drawn
REF
CONV CYC
–40
–60
from the REF pin, I , depends on the sampling rate and
REF
output code. If the LTC2512-24 continuously samples
a signal at a constant rate, the LTC6655-5 will keep the
deviation of the reference voltage over the entire code
span to less than 0.5ppm.
–80
–100
–120
–140
–160
–180
–200
When idling, the REF pin on the LTC2512-24 draws only
a small leakage current (< 1μA). In applications where
a burst of samples is taken after idling for long periods
0
50
100
150
200
FREQUENCY (kHz)
as shown in Figure 11, I
quickly goes from approxi-
REF
251224 F10b
mately 0μA to a maximum of 1mA at 1.6Msps. This step in
average current drawn causes a transient response in the
reference that must be considered, since any deviation in
the reference output voltage will affect the accuracy of the
output code. In applications where the transient response
of the reference is important, the fast settling LTC6655-5
reference is also recommended.
Figurem±0b.m±28kmPointmFF(mwithmf m=m2kHz,m
I
DFm=m4mformCircuitmShownminmFigurem±0a
ADCmREFEREICE
An external reference defines the input range of the
LTC2512-24. A low noise, low temperature drift reference
is critical to achieving the full data sheet performance
of the ADC. Analog Devices offers a portfolio of high
performance references designed to meet the needs of
many applications. With its small size, low power and high
accuracy, the LTC6655-5 is particularly well suited for
use with the LTC2512-24. The LTC6655-5 offers 0.025%
(max) initial accuracy and 2ppm/°C (max) temperature
coefficient for high precision applications.
ReferencemIoisem
The dynamic range of the ADC will increase approximately
3dB for every 2× increase in the down-sampling factor
(DF). The SNR should also improve as a function of DF in
the same manner. For large input signals near full-scale,
however, any reference noise will limit the improvement
of the SNR as DF increases, because any noise on the REF
pin will modulate around the fundamental frequency of the
input signal. Therefore, it is critical to use a low-noise ref-
erence, especially if the input signal amplitude approaches
full-scale. For small input signals, the dynamic range will
improve as described earlier in this section.
When choosing a bypass capacitor for the LTC6655-5, the
capacitor’s voltage rating, temperature rating, and pack-
age size should be carefully considered. Physically larger
capacitors with higher voltage and temperature ratings
tend to provide a larger effective capacitance, better filter-
ing the noise of the LTC6655-5, and consequently facili-
tating a higher SNR. Therefore, we recommend bypassing
the LTC6655-5 with a 47μF ceramic capacitor (X7R, 1210
size, 10V rating) close to the REF pin.
DYIAM CmPERFORMAICE
Fast Fourier Transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
The REF pin of the LTC2512-24 draws charge (Q
from the 47μF bypass capacitor during each conversion
)
CONV
MCLK
IDLE
PERIOD
IDLE
PERIOD
251224 F11
Figurem±±.mMCNKmWaveforpmShowingmBurstmSap1ling
251224fa
18
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
the ADC’s spectral content can be examined for frequen-
cies outside the fundamental. The LTC2512-24 provides
guaranteed tested limits for both AC distortion and noise
measurements.
(otalmHarponicmDistortionmꢀ(HD)
Total Harmonic Distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the funda-
mental itself. The out-of-band harmonics alias into the
frequency band between DC and half the sampling fre-
DynapicmRange
quency (f
/2). THD is expressed as:
SMPL
The dynamic range is the ratio of the RMS value of a
full scale input to the total RMS noise measured with
V22 +V32 +V42 +!+VN2
THD=20LOG
the inputs shorted to V /2. The dynamic range of the
REF
V1
LTC2512-24 with DF = 4 is 108dB which improves by 3dB
for every 2× increase in the down-sampling factor.
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the sec-
ond through Nth harmonics.
Signal-to-IoisemandmDistortionmRatiomꢀS IAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band-limited
to frequencies from above DC and below half the sampling
frequency. Figure 12 shows that the LTC2512-24 achieves
a typical SINAD of 108dB at a 1.6MHz sampling rate with
a 2kHz input, and DF = 4.
POWERmCOIS DERA( OIS
The LTC2512-24 has two power supply pins: the 2.5V
power supply (V ), and the digital input/output interface
DD
power supply (OV ). The flexible OV supply allows the
DD
DD
LTC2512-24 to communicate with any digital logic operat-
ing between 1.8V and 5V, including 2.5V and 3.3V systems.
0
PowermSu11lymSequencing
SNR = 108dB
–20
–40
The LTC2512-24 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2512-24 has
a power-on-reset (POR) circuit that will reset the LTC2512-
24 at initial power-up or whenever the power supply volt-
age drops below 1V. Once the supply voltage re-enters
the nominal supply voltage range, the POR will re initialize
the ADC. No conversions should be initiated until 200μs
after a POR event to ensure the re-initialization period has
ended. Any conversions initiated before this time will pro-
duce invalid results.
–60
–80
–100
–120
–140
–160
–180
0
50
100
150
200
FREQUENCY (kHz)
251224 F12
Figurem±2.m±28kmPointmFF(mPlotmofmN(C25±2-24m
withmDFm=m4,mf m=m2kHzmandmfSMPNm=m±.6MHz
I
( M IGmAIDmCOI(RON
MCNKm(iping
Signal-to-IoisemRatiomꢀSIR)
The signal-to-noise ratio (SNR) is the ratio between the RMS
amplitude of the fundamental input frequency and the RMS
amplitude of all other frequency components except the first
five harmonics and DC. Figure 12 shows that the LTC2512-24
achieves an SNR of 108dB when sampling a 2kHz input at a
1.6MHz sampling rate with DF = 4.
A rising edge on MCLK will power up the LTC2512-24 and
start a conversion. Once a conversion has been started,
further transitions on MCLK are ignored until the con-
version is complete. For best results, the falling edge
251224fa
19
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
of MCLK should occur within 40ns from the start of the
conversion, or after the conversion has been completed.
For optimum performance, MCLK should be driven by a
clean low jitter signal. Converter status is indicated by the
BUSY output which remains high while the conversion
is in progress. Once the conversion has completed, the
LTC2512-24 powers down and begins acquiring the input
signal for the next conversion.
DigitalmFiltering
The input to the LTC2512-24 is sampled at a rate f
and digital words D (n) are transmitted to the digital
,
SMPL
ADC
filter at that rate. Noise from the 24-bit SAR ADC core is
distributed uniformly in frequency from DC to fSMPL/2.
Figure 15 shows the frequency spectrum of D (n) at
ADC
the output of the SAR ADC core. In this example, the
bandwidth of interest f is a small fraction of f
/2.
SMPL
B
16
nternalmConversionmClockm
I
I
I
VDD
OVDD
REF
The LTC2512-24 has internal timing circuity that is
trimmed to achieve a maximum conversion time of 460ns.
With a maximum sample rate of 1.6Msps, a minimum
acquisition time of 152ns is guaranteed without any exter-
nal adjustments.
12
8
4
AutomPowermDownm
The LTC2512-24 automatically powers down after a
conversion has been completed and powers up once a
new conversion is initiated on the rising edge of MCLK.
During power-down, data from the last conversion can be
clocked out. To minimize power dissipation during power-
down, disable SDOA, SDOB and turn off SCKA, SCKB. The
auto power-down feature will reduce the power dissipa-
tion of the LTC2512-24 as the sampling rate is reduced.
Since power is consumed only during a conversion, the
LTC2512-24 remains powered down for a larger frac-
0
0
0.4
0.8
1.2
1.6
SAMPLING RATE (Msps)
251224 F13
Figurem±3.mPowermSu11lymCurrentmofm
themN(C25±2-24mvsmSap1lingmRate
INTEGRATED DECIMATION FILTER
24-BIT
SAR ADC
CORE
D
ADC
(n)
D (n)
1
DIGITAL
FILTER
DOWN
SAMPLER
V
IN
D
OUT
(k)
tion of the conversion cycle (t ) at lower sample rates,
CYC
thereby reducing the average power dissipation which
scales with the sampling rate as shown in Figure 13.
251224 F14
Figurem±4.mN(C25±2-24mDigitallymFilteredmOut1utmSignalmPath
DEC MA( OImF N(ERS
D
ADC
Many ADC applications use digital filtering techniques
to reduce noise. An FPGA or DSP is typically needed to
implement a digital filter. The LTC2512-24 features an
integrated decimation filter that provides 4 selectable digi-
tal filtering functions without any external hardware, thus
simplifying the application solution. Figure 14 shows the
LTC2512-24 digitally filtered output signal path, wherein
f
/2
f
B
SMPL
251224 F15
the output D (n) of the 24-bit SAR ADC core is passed
ADC
Figurem±5.mFrequencymS1ectrupmofmSARmADCmCoremOut1ut
on to the integrated decimation filter.
251224fa
20
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
D
DC to half the sampling frequency (a.k.a. the Nyquist fre-
quency). An input signal whose bandwidth exceeds the
Nyquist frequency, when sampled, will experience distor-
tion due to an effect called “Aliasing”.
1
DIGITAL FILTER CUTOFF FREQUENCY
When aliasing, frequency components greater than the
Nyquist frequency undergo a frequency shift and appear
within the Nyquist bandwidth. Figure 17 illustrates alias-
ing in the time domain. The solid line shows a sinusoi-
dal input signal of a frequency greater than the Nyquist
f
/2
f
B
SMPL
251224 F16
Figurem±6.mFrequencymS1ectrupmofmDigitalmFiltermCoremOut1ut
frequency (f /2). The circles show the signal sampled
O
The digital filter integrated in the LTC2512-24 suppresses
out-of-band noise power, thereby lowering overall noise
and increasing the dynamic range (DR). The lower the fil-
ter bandwidth, the lower the noise, and the higher the DR.
Figure 16 shows the corresponding frequency spectrum of
D (n) at the output of the digital filter, where noise beyond
the cutoff frequency is suppressed by the digital filter.
at f . Note that the sampled signal is identical to that of
O
sampling another sinusoidal input signal of a lower fre-
quency shown with the dashed line. To avoid aliasing, it
is necessary to band limit an input signal to the Nyquist
bandwidth before sampling. A filter that suppresses
spectral components outside the Nyquist bandwidth is
called an “Anti-Aliasing Filter”(AAF).
1
SAMPLED SIGNAL
Down-Sap1ling
INPUT SIGNAL
(ALIASED)
The output data rate of the digital filter is reduced by a
down-sampler without causing spectral interference in
the bandwidth of interest.
The down-sampler reduces the data rate by passing every
DFth sample to the output, while discarding all other sam-
ples. The sampling frequency fO at the output of the down
251224 F17
sampler is the ratio of f
and DF, i.e., f = f
/DF.
SMPL
O
SMPL
Figurem±7.m(ipemDopainmViewmofmAliasing
The LTC2512-24 enables the user to select DF accord-
ing to a desired bandwidth of interest. The four available
configurations can be selected by pin strapping pins SEL0
and SEL1. Table 1 summarizes the different decimation
filter configurations and properties.
Anti-AliasingmFilters
Figure 18 shows a typical signal chain including a low-
pass AAF and an ADC sampling at a rate of f . The AAF
rejects input signal components exceedingOfO/2, thus
avoiding aliasing. If the bandwidth of interest is close
Aliasing
to f /2, then the AAF must have a very steep roll-off. The
O
The maximum bandwidth that a signal being sampled can
have and be accurately represented by its samples is the
Nyquist bandwidth. The Nyquist bandwidth ranges from
complexity of the analog AAF increases with the steep-
ness of the roll-off, and it may be prohibitive if a very
steep filter is required.
(ablem±.mPro1ertiesmofmFiltersminmN(C25±2-24
SEN±:SEN0
DOWImSAMPN IGmFAC(ORm
ꢀDF)
–3dBmBAIDW D(HmWHEIm
m=m±.6MHz
OU(PU(mDA(AmRA(EmꢀODR)m
WHEImf m=m±.6MHz
DYIAM CmRAIGE
f
SMPN
SMPN
00
01
10
11
4
8
16
32
133kHz
66.7kHz
33.3kHz
16.7kHz
400ksps
200ksps
100ksps
50ksps
108dB
111dB
114dB
117dB
251224fa
21
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
Alternatively, a simple low-order analog filter in combi-
nation with a digital filter can be used to create a mixed-
mode equivalent AAF with a very steep roll-off. A mixed-
mode filter implementation is shown in Figure 19 where
an analog filter with a gradual roll-off is followed by the
digital filter H (f), as shown in Figure 20. The digital filter
2
provides a steep roll-off, allowing the analog filter to have
a relatively gradual roll-off.
The digital filter in the LTC2512-24 operates at the ADC
sampling rate f
and suppresses signals at frequen-
SMPL
LTC2512-24 sampling at a rate of f
= DF • f . The
SMPL
O
cies exceeding f /2. The frequency response of the digi-
O
LTC2512-24 has an integrated digital filter at the output
tal filter H (f) repeats at multiples of f
, resulting in
. The ana-
2
SMPL
of the ADC core. The equivalent AAF, HEQ(f), is the product
of the frequency responses of the analog filter H (f) and
unwanted passbands at each multiple of f
log filter should be designed to provide SaMdePqLuate sup-
1
pression of the unwanted passbands, such that H (f)
f
0
EQ
ANTI-ALIASING FILTER
has only one passband corresponding to the frequency
range of interest. Larger DF settings correspond to less
bandwidth of the digital filter, allowing for the analog filter
to have a more gradual roll-off. A simple first- or second-
order analog filter will provide adequate suppression for
most systems.
V
IN
ADC
D
(k)
OUT
AT f (sps)
O
f /2
0
f
0
251224 F18
Figurem±8.mADCmSignalmChainmwithmAAF
f =mDFm•mf
SMPNm O
LTC2512-24
ANALOG FILTER
DIGITAL FILTER
IMAGE
DOWN-SAMPLER
H
1
H
2
D
1
(n)
f
– f /2
0
SMPL
ADC
CORE
D
(k)
OUT
0
DF
f
– f /2
V
IN
SMPL
0
AT f (sps)
f /2
0
f
SMPL
f /2
0
f
SMPL
251224 F19
Figurem±9.mMixed-ModemFiltermSignalmChain
H
1
H
2
ANALOG FILTER
DIGITAL FILTER
f
– f /2
0
SMPL
f
– f /2
0
SMPL
f /2
0
f
f /2
0
f
SMPL
SMPL
H
EQ
EQUIVALENT AAF
V
IN
TO ADC
f /2
0
f
SMPL
251224 F20
Figurem20.mMixed-ModemAnti-AliasingmFiltermꢀAAF)
251224fa
22
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
FrequencymRes1onsemofmDigitalmFilters
response undergoes a sharp decrease. At f /2, the stop-
O
band begins. There is a minimum of 65dB attenuation
Figure 21a shows the magnitude of the frequency response
of the digital filter when the LTC2512-24 is configured to
over the entire stopband region for frequencies in the
range of f /2 to f
– f /2. The minimum attenuation in
O
O
SMPL
operate with DF = 4 at a sampling rate of f
. In this
SMPL
the stopband improves to 80dB over the frequency range
case, f is f
/4. Note that a replica of the passband
O
SMPL
of 2f /3 to f – 2f /3.
O
SMPL
O
occurs at f
and multiples thereof. In each configura-
SMPL
The FIR filter coefficients of the 4 digital filter configura-
tions are available at http://www.linear.com/docs/55376.
Table 2 lists the length and group delay of each digital
filter’s response.
tion, the digital filter provides a finite impulse response
(FIR) filter with a lowpass amplitude response and linear
phase response.
Figure 21b shows the amplitude response in the fre-
quency range from DC to f . Labels are shown for four
O
(ablem2.mNengthmofmDigitalmFilter
distinct regions: a low ripple passband, a 3dB passband,
a transition band and a stopband. The low ripple passband
ranges from DC to fO/4 and provides a constant amplitude
( 0.001dB) as shown in Figure 21c. The 3dB passband
DOWI-SAMPN IGm NEIG(HmOFmD G (ANmF N(ERm
GROUPmDENAYmm
ꢀ±7.5mOU(PU(m
SAMPNES)
FAC(ORmꢀDF)
MPUNSEmRESPOISEmm
ꢀIUMBERmOFmMCNKmPER ODS)
4
8
140
280
43.75µs
87.5µs
175µs
ranges from DC to f /3 where the amplitude response
O
16
32
560
1120
has dropped by 3dB. The transition band is defined from
350µs
f /3 to f /2 and is where the magnitude of the amplitude
O
O
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
HIGHLIGHTED AREA
SHOWN IN FIGURE 21B
0
f
f
/2
SMPL
f
O
SMPL
FREQUENCY (Hz)
251224 F21a
Figurem2±a.mMagnitudemofmFrequencymRes1onsemofmDigitalmFiltermwithmDFm=m4
251224fa
23
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
20
TRANSITION BAND
3dB PASSBAND
STOPBAND
10
0
LOW RIPPLE
PASSBAND
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
HIGHLIGHTED AREA
SHOWN IN FIGURE 21C
65dB
80dB
0
f
/4
f
/3
f
/2
2f /3
f
O
O
O
O
O
FREQUENCY (Hz)
251224 F21b
Figurem2±b.mHighlightedmPortionmofmFrequencymRes1onsemfropmFigurem2±a
0.002
0.001
0
0.001dB
–0.001
–0.002
–0.001dB
0
f /4
O
FREQUENCY (Hz)
251224 F21c
Figurem2±c.mNowmRi11lemPassbandmPortionmofmFrequencymRes1onsemfropmFigurem2±b
251224fa
24
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
Settlingm(ipemandmGrou1mDelay
D G (ANm I(ERFACE
The length of each digital filter’s impulse response deter-
mines its settling time. Linear phase filters exhibit con-
stant delay time versus input frequency (that is, constant
group delay). Group delay of the digital filter is defined to
be the delay to the center of the impulse response.
The LTC2512-24 features two digital serial interfaces.
Serial interface A is used to read the filtered output data.
Serial interface B is used to read the no latency output
data. Both interfaces support a flexible OVDD supply,
allowing the LTC2512-24 to communicate with any digi-
tal logic operating between 1.8V and 5V, including 2.5V
and 3.3V systems.
LTC2512-24 is optimized for low latency, and it pro-
vides fast settling. Figure 22 shows the output settling
behavior after a step change on the analog inputs of the
LTC2512-24. The X axis is given in units of output sample
number. The step response is representative for all values
of DF. Full settling is achieved in 35 output samples.
1
Analog Step Input Signal
Digital Filter Output D1(n)
0
LTC2512−24 Output Samples Dout(k)
−2−1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Output Sample Number
251224 F22
Figurem22.mSte1mRes1onsemofmN(C25±2-24
251224fa
25
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
FilteredmOut1utmData
DistributedmRead
Figure 23 shows a typical operation for reading the fil-
tered output data. The I/O register contains filtered output
LTC2512-24 enables the user to read out the contents
of the I/O register over multiple conversions. Figure 24
codes D (k) provided by the decimation filter. D (k)
shows a case where one bit of D (k) is read for each
OUT
OUT
OUT
is updated once in every DF number of conversion cycles.
A timing signal DRL indicates when D (k) is updated.
DRL goes high at the beginning of eOveUrTy DFth conver-
sion, and it goes low when the conversion completes. The
of 24 consecutive A/D conversions, enabling the use of
a much slower serial clock (SCKA). Transitions on the
digital interface should be avoided during A/D conversion
operations (when BUSY is high).
24-bits of D (k) can be read out before the beginning
OUT
of the next A/D conversion.
1
2
DF
DF+1
DF+2
2DF
2DF+1
2DF+2
3DF
CONVERSION
NUMBER
MCLK
DRL
DF NUMBER OF
CONVERSIONS
DF NUMBER OF
CONVERSIONS
DF NUMBER OF
CONVERSIONS
FILTERED OUTPUT
REGISTER
(REGISTER UPDATED ONCE
EVERY DF CONVERSIONS)
D
(0)
OUT
D (1)
OUT
D (2)
OUT
D
(3)
OUT
1
24
1
24
1
24
SCKA
251224 F23
Figurem23.m(y1icalmFilteredmOut1utmDatamO1erationm(iping
DF NUMBER OF CONVERSIONS
CONVERSION
0
1
2
3
23
24
25
DF
DF+1
NUMBER
MCLK
DRL
(REGISTER UPDATED ONCE FOR
EVERY DF CONVERSIONS)
FILTERED OUTPUT
REGISTER
D (0)
OUT
D
(1)
OUT
1
2
3
24
1
SCKA
1 SCKA
1 SCKA
1 SCKA
24 SCKA
1 SCKA/CNV
1 SCKA
0 SCKA
251224 F24
Figurem24.mReadingmOutmFilteredmOut1utmDatamwithmDistributedmRead
251224fa
26
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
Synchronization
SYNC signal, to be synchronized with each other. This
allows each LTC2512-24 device to update its output reg-
ister at the same time. Note that all devices being syn-
chronized must operate with the same DF.
The output of the digital filter D1(n) is updated every
conversion, whereas the down-sampler output D (k)
OUT
is updated only once every DF number of conversions.
Synchronization is the process of selecting when the out-
PeriodicmSynchronization
put D (k) is updated.
OUT
SYNCpulsesthatreinforceanexistingsynchronizationdo
not interfere with normal operation. Figure 26 shows a
case where a SYNC pulse is applied for each DF num-
ber of conversions to continually reinforce a synchro-
nization. Figure 26 indicates synchronization windows
when a SYNC pulse may be applied to reinforce the
synchronized operation.
This is done by applying a pulse on the SYNC pin of the
LTC2512-24. The I/O register for D (k) is updated at
OUT
each multiple of DF number of conversions after a SYNC
pulse is provided, as shown in Figure 25. A timing signal
DRL indicates when D (k) is updated.
OUT
The SYNC function allows multiple LTC2512-24 devices,
operated from the same master clock using a common
1
2
DF
DF+1
DF+2
2DF
2DF+1
2DF+2
3DF
CONVERSION
NUMBER
MCLK
DRL
DF NUMBER
OF CONVERSIONS
DF NUMBER
OF CONVERSIONS
DF NUMBER
OF CONVERSIONS
SYNC
FILTERED OUTPUT
REGISTER
D (0)
OUT
D (1)
OUT
D (2)
OUT
D (3)
OUT
251224 F25
Figurem25.mSynchronizationmUsingmamSinglemSYICmPulse
1
2
DF
DF+1
DF+2
2DF
2DF+1
2DF+2
3DF
3DF+1
CONVERSION
NUMBER
MCLK
SYNCHRONIZATION
WINDOW
SYNCHRONIZATION
WINDOW
SYNCHRONIZATION
WINDOW
DRL
SYNC
FILTERED OUTPUT
REGISTER
D (0)
OUT
D (1)
OUT
D (2)
OUT
D (3)
OUT
251224 F26
Figurem26.mSynchronizationmUsingmamPeriodicmSYICmPulse
251224fa
27
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
Self-CorrectingmSynchronization
IomNatencymOut1utmData
Figure 27 shows a case where an unexpected glitch on
MCLK causes an extra A/D conversion to occur. This extra
conversion alters the update instants for D (k). The
applied periodic SYNC pulse reestablishes OthUeT desired
synchronization and self corrects within one conversion
cycle. Note that the digital filter is reset when the synchro-
nization is changed (reestablished).
Figure 28 shows a typical operation for reading the no
latency output data. The no latency I/O register holds a
22-bit composite code R(n) from the most recent sample
+
–
taken of inputs IN and IN at the rising edge of MCLK.
The first 14 bits of R(n) represent the input voltage dif-
+
–
ference (IN – IN ), MSB first. The last 8 bits represent
+
–
the common-mode input voltage (IN + IN )/2, MSB first.
1
2
DF–1
DF
DF+1
2DF–1
2DF
2DF+1
2DF+2
USER CONVERSION
NUMBER
USER PROVIDED
MCLK
SYNCHRONIZATION
WINDOW
UNWANTED
GLITCH
CORRUPTED
MCLK
EXPECTED DRL
DRL W/O
PERIODIC SYNC
DF NUMBER
OF CONVERSIONS
DF NUMBER
OF CONVERSIONS
PERIODIC SYNC
EXPECTED DRL
CORRECTED DRL
DRL WITH
PERIODIC SYNC
251224 F27
Figurem27.mRecoveringmSynchronizationmfropmUnex1ectedmGlitch
0
1
2
3
4
5
6
CONVERSION
NUMBER
MCLK
BUSY
NO-LATENCY
OUTPUT REGISTER
R(0)
22
R(1)
22
R(2)
22
R(3)
22
R(4)
22
R(5)
22
R(6)
1
1
1
1
1
1
1
22
SCKB
251224 F28
Figurem28.m(y1icalmIyquistmOut1utmDatamO1erationm(iping
251224fa
28
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
ConfigurationmWord
(ablem3.mConfigurationmWORDmformDifferentmDFmValues
DF
4
8
16
32
WA[7:0]
00100110
00110110
01000110
01010110
An 8-bit configuration word, WA[7:0], is appended to the
24-bit output code on SDOA to produce a total output
word of 32 bits as shown in Figure 29. The configura-
tion word designates which downsampling factor (DF)
the digital filter is configured to operate with. Clocking
out the configuration word is optional. Table 3 lists the
configuration words for each DF value.
MCLK
CONVERT
DRL
SCKA
DA22 DA20 DA18 DA16 DA14 DA12 DA10
DA23 DA21 DA19 DA17 DA15 DA13 DA11 DA9
DA8
DA6
DA4
DA2
DA0
WA6
WA4
WA2
WA0
SDOA
DA7
DA5
DA3
DA1
WA7
WA5
WA3
WA1
251224 F29
Figurem29.mUsingmamSinglemN(C25±2-24mwithmDFm=m4mtomReadmFilteredmOut1ut
251224fa
29
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
FilteredmOut1utmData,mSinglemDevice,mDFm=m4
Figure 30 shows an LTC2512-24 configured to operate
with DF = 4. With RDLA grounded, SDOA is enabled and
MSB (DA23) of the output result is available t
after the falling edge of DRL.
DSDOBUSYL
MASTER CLK
DIGITAL HOST
IRQ
MCLK
LTC2512-24
SCKA
DRL
RDLA
SEL0
SEL1
DATA IN
CLK
SDOA
RDLA = GND
CONVERT
POWER-DOWN AND ACQUIRE
CONVERT
t
MCLKH
t
MCLKL
MCLK
DRL
t
DRLLH
BUSY
t
CONV
t
BUSYLH
t
t
t
QUIET
SCKA
SCKAH
SCKA
SDOA
1
2
3
30
31
32
t
SCKAL
t
HSDOA
t
DSDOADRLL
t
DSDOA
DA31
DA30
DA29
DA1
DA0
251224 F30
Figurem30.mUsingmamSinglemN(C25±2-24mwithmDFm=m4mtomReadmFilteredmOut1ut
251224fa
30
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
FilteredmOut1utmData,mMulti1lemDevices,mDFm=m4
of each ADC must be used to allow only one LTC2512-24
to drive SDOA at a time in order to avoid bus conflicts.
As shown in Figure 31, the RDLA inputs idle high and are
individually brought low to read data out of each device
between conversions. When RDLA is brought low, the
MSB of the selected device is output on SDOA.
Figure 31 shows two LTC2512-24 devices configured to
operate with DF = 4, while sharing MCLK, SYNC, SCKA
and SDOA. By sharing MCLK, SYNC, SCKA and SDOA, the
number of required signals to operate multiple ADCs in
parallel is reduced. Since SDOA is shared, the RDLA input
SYNC
RDLA
RDLA
X
Y
MASTER CLK
DIGITAL HOST
IRQ
MCLK
MCLK
RDLA
SYNC
RDLA
SYNC
DRL
LTC2512-24
X
LTC2512-24
Y
SEL0
SEL1
SEL0
SEL1
DATA IN
SDOA
SDOA
SCKA
SCKA
CLK
CONVERT
POWER-DOWN AND ACQUIRE
CONVERT
t
MCLKL
MCLK
DRL
t
DRLLH
BUSY
t
CONV
t
BUSYLH
RDLA
RDLA
X
Y
SYNC
SCKA
t
SCKA
t
QUIET
t
SCKAH
1
2
3
30
31
32
33
34
35
62
63
64
t
t
HSDOA
SCKAL
t
t
DISA
t
ENA
DSDOA
Hi-Z
Hi-Z
Hi-Z
SDOA
251224 F31
DA31X DA30X DA29X
DA1X DA0X
DA31Y DA30Y DA29Y
DA1Y DA0Y
Figurem3±.mReadingmFilteredmOut1utmwithmMulti1lemDevicesmSharingmMCNK,mSCKAmandmSDOA
251224fa
31
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
IomNatencymOut1utmData,mSinglemDevice
Figure 32 shows a single LTC2512-24 configured to read
the no latency data out. With RDLB grounded, SDOB is
enabled and MSB (DB13) of the output result is available
t
after the falling edge of BUSY.
DSDOBBUSYL
MASTER CLK
DIGITAL HOST
IRQ
MCLK
LTC2512-24
SCKB
BUSY
SDOB
RDLB
DATA IN
CLK
CONVERT
POWER-DOWN AND ACQUIRE
CONVERT
RDLB = GND
MCLK
t
CYC
t
MCLKH
t
MCLKL
t
= t
– t
– t
ACQ CYC CONV BUSYLH
BUSY
t
t
ACQ
CONV
t
BUSYLH
t
t
t
QUIET
SCKB
SCKBH
SCKB
SDOB
1
2
3
12
13
14
t
SCKBL
t
HSDOB
t
t
DSDOBBUSYL
DSDOB
DB13
DB12
DB11
DB1
DB0
CB7
251224 F32
Figurem32.mUsingmamSinglemN(C25±2-24mtomReadmIomNatencymOut1ut
251224fa
32
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
IomNatencymOut1utmData,mMulti1lemDevices
ADC must be used to allow only one LTC2512-24 to drive
SDOB at a time in order to avoid bus conflicts. As shown
in Figure 33, the RDLB inputs idle high and are individu-
ally brought low to read data out of each device between
conversions. When RDLB is brought low, the MSB of the
selected device is output on SDOB.
Figure 33 shows multiple LTC2512-24 devices configured
to read no latency data out, while sharing MCLK, SCKB
and SDOB. By sharing MCLK, SCKB and SDOB, the num-
ber of required signals to operate multiple ADCs in parallel
is reduced. Since SDOB is shared, the RDLB input of each
RDLB
RDLB
X
Y
MASTER CLK
DIGITAL HOST
IRQ
MCLK
MCLK
BUSY
SDOB
RDLB
RDLB
LTC2512-24
LTC2512-24
Y
X
DATA IN
SDOB
SCKB
SCKB
CLK
CONVERT
POWER-DOWN AND ACQUIRE
CONVERT
t
MCLKL
MCLK
BUSY
t
CONV
t
BUSYLH
RDLB
RDLB
X
Y
t
SCKB
t
QUIET
t
SCKBH
SCKB
SDOB
1
2
3
20
21
22
23
24
25
42
43
44
t
t
HSDOB
SCKBL
t
t
DISB
t
ENB
DSDOB
Hi-Z
Hi-Z
Hi-Z
251224 F33
DB13X DB12X DB11X
CB1X CB0X
DB13Y DB12Y DB11Y
CB1Y CB0Y
Figurem33.mReadingmIomNatencymOut1utmwithmMulti1lemDevicesmSharingmMCNK,mSCKBmandmSDOB
251224fa
33
For more information www.linear.com/LTC2512-24
LTC2512-24
APPLICATIONS INFORMATION
FilteredmOut1utmData,mIomNatencymData,mSinglemDevice
shared SDO bus at a time in order to avoid bus conflicts.
As shown in Figure 34, the RDLA and RDLB inputs idle
high and are individually brought low to read data from
each serial output when data is available. When RDLA
is brought low, the MSB of the filtered output data from
SDOA is output on the shared SDO bus. When RDLB is
brought low, the MSB of the no latency data output from
SDOB is output on the shared SDO bus.
Figure 34 shows a single LTC2512-24 configured to read
both filtered and no latency output data, while sharing
SDOA with SDOB and SCKA with SCKB. Sharing signals
reduces the total number of required signals to read both
the filtered and no latency data from the ADC. Since SDOA
and SDOB are shared, the RDLA and RDLB inputs of the
ADC must be used to allow only one output to drive the
RDLA
RDLB
MASTER CLK
DIGITAL HOST
MCLK
RDLA
DRL
IRQ
RDLB
LTC2512-24
DATA IN
SDOA
SEL0
SDOB
SEL1
SCKA
SCKB
CLK
CONVERT
POWER-DOWN AND ACQUIRE
CONVERT
t
MCLKL
MCLK
DRL
t
DRLLH
BUSY
RDLA
t
CONV
t
BUSYLH
RDLB
t
t
SCKB
SCKA
t
QUIET
t
t
SCKAH
SCKBH
44
SCKA/
SCKB
1
2
3
22
23
24
25
26
27
45
46
t
t
t
SCKAL
SCKBL
HSDOA
t
t
ENB
HSDOB
t
t
DISA
t
ENA
t
DSDOA
DSDOB
SDOA/
SDOB
Hi-Z
Hi-Z
Hi-Z
DA23 DA22 DA21
DA1 DA0 CB7
DB13 DB12 DB11
CB1 CB0
251224 F34
Figurem34.mReadingmFilteredmOut1utmandmIomNatencymOut1utmbymSharingmSCK,mandmSDO
251224fa
34
For more information www.linear.com/LTC2512-24
LTC2512-24
BOARD LAYOUT
To obtain the best performance from the LTC2512-24, a
four-layer printed circuit board (PCB) is recommended.
Layout for the PCB should ensure the digital and analog
signal lines are separated as much as possible. In particu-
lar, care should be taken not to run any digital clocks or
signals alongside analog signals or underneath the ADC.
low noise operation of the ADC. A single solid ground
plane is recommended for this purpose. When possible,
screen the analog input traces using ground.
ReferencemDesign
For a detailed look at the reference design for this con-
verter, including schematics and PCB layout, please refer to
http://www.linear.com/docs/55376, the evaluation kit for
the LTC2512-24. DC2222A is designed to achieve the full
data sheet performance of the LTC2512-24. Customer
board layout should copy DC2222A grounding, and place-
ment of bypass capacitor as closely as possible.
Supply bypass capacitors should be placed as close as
possible to the supply pins. Low impedance common
returns for these bypass capacitors are essential to the
251224fa
35
For more information www.linear.com/LTC2512-24
LTC2512-24
PACKAGE DESCRIPTION
Pleasemrefermtomhtt1://www.linear.cop/1roduct/N(C25±2-24#1ackagingmformthempostmrecentm1ackagemdrawings.
DKDmPackage
24-NeadmPlasticmDFImꢀ7pp × 4pp)
(Reference LTC DWG # 05-08-1864 Rev Ø)
0.70 ±0.05
4.50 ±0.05
6.43 ±0.05
2.64 ±0.05
3.10 ±0.05
PACKAGE
OUTLINE
0.50 BSC
0.25 ±0.05
5.50 REF
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.115
TYP
7.00 ±0.10
13
24
R = 0.05
TYP
0.40 ±0.10
6.43 ±0.10
2.64 ±0.10
4.00 ±0.10
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
12
1
0.25 ±0.05
0.50 BSC
0.75 ±0.05
5.50 REF
BOTTOM VIEW—EXPOSED PAD
(DKD24) DFN 0210 REV Ø
0.200 REF
NOTE:
0.00 – 0.05
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WXXX)
IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
251224fa
36
For more information www.linear.com/LTC2512-24
LTC2512-24
REVISION HISTORY
REV
DA(E
DESCR P( OI
PAGEmIUMBER
A
02/18 Corrected order of [SEL1 SEL0] bits
11
29
Corrected configuration WORD bits WA[7:0] in Table 3
251224fa
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
37
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
LTC2512-24
TYPICAL APPLICATION
BufferingmandmConvertingmam±±0Vm(ruemBi1olarm n1utmSignalmtomamFullymDifferentialmADCm n1utm
1k
8V
5V
2.5V
6800pF
0.1µF
REF
V
2k
2k
30.1Ω
30.1Ω
DD
+
–
+
IN
IN
VOCM
V
/2
REF
6800pF
LTC6363
LTC2512-24
GND
10V
0V
–
+
V
IN
6800pF
–10V
0.1µF
0.1µF
–3V
1k
251224 TA02
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Amplifier/Driver
Single 2.8V to 11V Supply, 1.9mA Supply Current, MSOP-8 and 2mm × 3mm
DFN-8 Packages
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Output Amplifier/Driver
Single 2.8V to 5.25V Supply, 1mA Supply Current, MSOP-8 and 3mm × 3mm
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251224fa
LT 0218 REV A • PRINTED IN USA
www.linear.com/LTC2512-24
ANALOG DEVICES, INC. 2016
38
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