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LTC3126EUFD#PBF [Linear]

LTC3126 - 42V, 2.5A Synchronous Step-Down Regulator with No-Loss Input PowerPath; Package: QFN; Pins: 28; Temperature Range: -40°C to 85°C;
LTC3126EUFD#PBF
型号： LTC3126EUFD#PBF
厂家： Linear    Linear
描述：

LTC3126 - 42V, 2.5A Synchronous Step-Down Regulator with No-Loss Input PowerPath; Package: QFN; Pins: 28; Temperature Range: -40°C to 85°C

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LTC3126  
42V, 2.5A Synchronous  
Step-Down Regulator with  
No-Loss Input PowerPath  
DescripTion  
FeaTures  
The LTC®3126 is a high efficiency synchronous buck  
converterwithaninternalno-lossPowerPath™supporting  
seamlessoperationfromtwoseparateinputpowersources.  
Pin-selectable ideal diode-OR and priority input modes  
withuserprogrammableundervoltagelockoutthresholds  
provide full control over the transition between the input  
power sources. The fast, automatic switchover provided  
by the internal PowerPath eliminates the need for hold-up  
capacitors and minimizes disturbances on the output rail.  
An active input channel indicator and independent input  
andoutputpowergoodsignalsprovidecompletefeedback  
of the power system status.  
n
Seamless, Automatic Transition Between Two Input  
Power Sources  
n
Wide Input Voltage Range: 2.4V to 42V  
n
Wide Output Voltage Range: 0.818V to V  
Up to 2.5A Continuous Output Current  
IN  
n
n
n
n
n
n
n
n
n
n
n
n
Pin-Selectable Priority and Ideal Diode-OR Modes  
Burst Mode® Operation, I = 2µA  
Q
95% Efficiency at 1A, V = 12V, V  
1µA Current in Shutdown  
= 5V  
IN  
OUT  
Programmable Input UVLO Thresholds  
Input Valid, Priority Channel and PGOOD Indicators  
200kHz to 2.2MHz Fixed Frequency PWM  
Synchronizable to an External Clock  
Current Mode Control with 60ns Minimum On-Time  
Minimal External Components  
A wide 2.4V to 42V input voltage range, 2.5A output cur-  
rent capability and 2µA Burst Mode operation quiescent  
current facilitate use of the LTC3126 with a wide variety  
of power sources including supercapacitors, automo-  
tive batteries, unregulated wall adapters and single to  
multicell stacks of most battery chemistries. Additional  
features include 1µA current in shutdown, internal soft-  
start and thermal protection. The LTC3126 is available  
in thermally enhanced 28-lead 4mm × 5mm QFN and  
28-lead TSSOP packages.  
Thermally Enhanced 28-Lead 4mm × 5mm QFN and  
28-Lead TSSOP Packages  
applicaTions  
n
Portable Industrial/Communications Test Equipment  
n
Battery and Supercapacitor Backup Power  
n
Automotive Power with Battery Backup  
Uninterruptible Power Supplies  
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks  
and PowerPath is a trademark of Linear Technology Corporation. All other trademarks are the  
property of their respective owners.  
n
Typical applicaTion  
2MHz, 3.3V/2.5A Supply from Automotive and Battery Inputs  
0.1µF  
0.1µF  
AUTOMOTIVE  
10V TO 24V  
42V TRANSIENT  
Switchover to Battery Power, 2.5A Load  
BST2 COM2 BST1 COM1  
V
PV  
2.2µH  
IN1  
V
OUT  
15µF  
3.3V  
SW  
EXTV  
IN1  
V
5V/DIV  
IN1  
47µF 2.5A  
CC  
V
PV  
V
5V/DIV  
+
+
IN2  
1.13M  
374k  
10pF  
IN2  
4.7µF  
BATTERY  
4.2V TO 24V  
IN2  
AUTOMOTIVE  
INPUT UNPLUGGED  
FB  
PV  
CC  
LTC3126  
V
CC  
ENA  
V
OUT  
200mV/DIV  
4.7µF  
V
V
V
REF  
INDUCTOR CURRENT 2A/DIV  
PRIORITY  
VALID1  
VALID2  
PGOOD  
499k  
SET1  
PRIORITY 5V/DIV  
249k  
249k  
3126 TA01b  
SET2  
50µs/DIV  
PWM/SYNC  
DIODE  
16.5k  
RT  
GND  
PGND  
3126 TA01a  
3126f  
1
For more information www.linear.com/LTC3126  
LTC3126  
absoluTe MaxiMuM raTings (Note 1)  
PV , PV , V , V .............................................42V  
BST2 Pin Above COM2 ...............................................6V  
IN1  
IN2 IN1 IN2  
EXTV .....................................................................42V  
Operating Junction Temperature Range  
CC  
V , PV ....................................................................6V  
(Notes 2, 4)............................................ –40°C to 150°C  
Storage Temperature.............................. –65°C to 150°C  
Lead Temperature (Soldering, 10 sec)  
CC  
V
CC  
, V  
, V  
, FB, RT ..........................................6V  
REF SET1 SET2  
PWM/SYNC, DIODE, ENA ...........................................6V  
VALID1, VALID2, PGOOD, PRIORITY............................6V  
BST1 Pin Above COM1 ...............................................6V  
TSSOP ..............................................................300°C  
pin conFiguraTion  
TOP VIEW  
TOP VIEW  
1
2
V
IN1  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
IN2  
PV  
PWM/SYNC  
VALID1  
IN1  
3
DIODE  
BST1  
COM1  
SW  
28 27 26 25 24 23  
4
VALID2  
VALID2  
1
2
3
4
5
6
7
8
22  
21  
20  
19  
18  
17  
16  
15  
BST1  
COM1  
SW  
5
V
PV  
CC  
CC  
CC  
V
CC  
6
PV  
CC  
7
PGND  
PGND  
SW  
EXTV  
V
EXTV  
CC  
PGND  
PGND  
SW  
29  
PGND  
29  
PGND  
8
V
SET1  
SET1  
SET2  
V
9
V
SET2  
V
COM2  
BST2  
10  
11  
12  
13  
14  
COM2  
BST2  
ENA  
REF  
V
REF  
GND  
GND  
FB  
9
10 11 12 13 14  
UFD PACKAGE  
PV  
IN2  
RT  
PRIORITY  
PGOOD  
FE PACKAGE  
28-LEAD (4mm × 5mm) PLASTIC QFN  
28-LEAD PLASTIC TSSOP  
T
JMAX  
= 150°C, θ = 34°C/W  
JA  
T
= 150°C, θ = 30°C/W  
JA  
EXPOSED PAD (PIN 29) IS PGND, MUST BE SOLDERED TO PCB  
JMAX  
EXPOSED PAD (PIN 29) IS PGND, MUST BE SOLDERED TO PCB  
http://www.linear.com/product/LTC3126#orderinfo  
orDer inForMaTion  
LEAD FREE FINISH  
LTC3126EUFD#PBF  
LTC3126IUFD#PBF  
LTC3126EFE#PBF  
LTC3126IFE#PBF  
LTC3126HFE#PBF  
LTC3126MPFE#PBF  
TAPE AND REEL  
PART MARKING*  
3126  
PACKAGE DESCRIPTION  
28-Lead (4mm × 5mm) Plastic QFN  
TEMPERATURE RANGE  
–40°C to 125°C  
LTC3126EUFD#TRPBF  
LTC3126IUFD#TRPBF  
LTC3126EFE#TRPBF  
LTC3126IFE#TRPBF  
LTC3126HFE#TRPBF  
LTC3126MPFE#TRPBF  
3126  
28-Lead (4mm × 5mm) Plastic QFN  
28-Lead Plastic TSSOP (4.4mm)  
28-Lead Plastic TSSOP (4.4mm)  
28-Lead Plastic TSSOP (4.4mm)  
28-Lead Plastic TSSOP (4.4mm)  
–40°C to 125°C  
–40°C to 125°C  
–40°C to 125°C  
–40°C to 150°C  
–55°C to 150°C  
LTC3126FE  
LTC3126FE  
LTC3126FE  
LTC3126FE  
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.  
For more information on lead free part marking, go to: http://www.linear.com/leadfree/  
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through  
designated sales channels with #TRMPBF suffix.  
3126f  
2
For more information www.linear.com/LTC3126  
LTC3126  
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating  
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). PVIN1 = VIN1 = 24V, PVIN2 = VIN2 = 12V,  
VSET1 = VSET2 = GND, unless otherwise noted.  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
l
Input Operating Voltage  
After Start-Up  
2.4  
42  
V
l
l
V
V
V
V
V
V
, V UVLO Threshold  
V
/V Rising  
IN1 IN2  
2.50  
2.34  
2.6  
2.4  
V
V
IN1 IN2  
V
/V Falling  
IN1 IN2  
l
UVLO Threshold  
Current in Disable  
Current in Disable  
Current in Standby  
Current in Standby  
V
V
Rising  
Falling  
2.3  
2.2  
2.4  
2.3  
V
V
CC  
CC  
CC  
ENA Low, V = 24V, V = 12V  
ENA Low, V = 12V, V = 24V  
1.35  
0.55  
µA  
µA  
IN1  
IN2  
IN1  
IN2  
IN1  
IN1  
IN2  
IN2  
ENA Low, V = 24V, V = 12V  
ENA Low, V = 12V, V = 24V  
1.35  
0.55  
µA  
µA  
IN2  
IN2  
IN1  
IN1  
ENA High, Buck in UVLO, V = 24V, V = 12V  
ENA High, Buck in UVLO, V = 12V, V = 24V  
1.65  
0.55  
µA  
µA  
IN1  
IN1  
IN2  
IN2  
ENA High, Buck in UVLO, V = 24V, V = 12V  
ENA High, Buck in UVLO, V = 12V, V = 24V  
1.65  
0.55  
µA  
µA  
IN2  
IN2  
IN1  
IN1  
V
V
Current, Operating from V  
Current, Operating from V  
ENA High, Buck Operating, V = 24V, V = 27V  
1.2  
1.2  
5.5  
µA  
µA  
µA  
IN1  
IN2  
IN1  
IN2  
ENA High, Buck Operating, V = 24V, V = 27V  
IN2  
IN1  
IN2  
IN1  
Burst Mode Operation Quiescent Current from V Not Switching, V = 0.850V  
IN  
FB  
l
l
Oscillator Frequency  
Programmable Frequency  
T
200  
900  
2200  
1100  
kHz  
kHz  
R Resistor = 33.2k  
1000  
l
PWM/SYNC Applied Clock Frequency  
PWM/SYNC High Pulse Width  
PWM/SYNC Low Pulse Width  
200  
100  
150  
0.3  
2200  
kHz  
ns  
ns  
V
l
l
Logic Input Threshold (ENA, DIODE, PWM/SYNC)  
Feedback Voltage  
0.8  
1.1  
812  
804  
818  
818  
824  
832  
mV  
mV  
Feedback Voltage Line Regulation  
Feedback Pin Current  
V
, V = 2.4V to 42V  
0.2  
1
%
nA  
%
IN1 IN2  
–20  
7.4  
20  
12  
Feedback Pin Overvoltage Comparator Threshold FB Rising, as a Percentage of the Feedback Voltage  
Feedback Pin Overvoltage Comparator Hysteresis  
9.8  
1.1  
7.5  
–8.7  
1
%
Soft-Start Duration  
ms  
%
l
PGOOD Threshold  
FB Falling, as a Percentage of the Feedback Voltage  
FB Falling  
–10.7  
–6.6  
PGOOD Threshold Hysteresis  
PGOOD Delay  
%
200  
µs  
V
Voltage  
0.995  
0.982  
1.000  
1.000  
1.005  
1.018  
V
V
REF  
l
V
V
V
Output Current  
Current Limit  
1
mA  
mA  
REF  
13  
REF  
Comparator Threshold  
V
IN1  
V
IN1  
Rising, V = 24V  
24.18  
23.83  
V
V
BEST  
IN2  
Falling, V = 24V  
IN2  
V
V
Comparator Hysteresis  
Comparator Delay  
280  
365  
450  
mV  
BEST  
V
IN1  
V
IN2  
Falling, V = 24V  
11  
40  
µs  
µs  
BEST  
IN2  
Falling, V = 24V  
IN1  
l
l
l
l
V , V Input Valid Threshold, Rising  
IN1 IN2  
V
SET1  
V
SET1  
V
SET1  
V
SET1  
= V  
= V  
= V  
= V  
= 1000mV  
= 500mV  
= 250mV  
= 150mV  
19.8  
9.9  
20.0  
10.0  
5.0  
20.2  
10.1  
5.1  
V
V
V
V
SET2  
SET2  
SET2  
SET2  
4.9  
2.91  
3.0  
3.09  
3126f  
3
For more information www.linear.com/LTC3126  
LTC3126  
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating  
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). PVIN1, = VIN1 = 24V, PVIN2 = VIN2 = 12V,  
VSET1 = VSET2 = GND, unless otherwise noted.  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
V
, V Input Valid Threshold, Falling  
IN1 IN2  
V
SET1  
V
SET1  
V
SET1  
V
SET1  
= V  
= V  
= V  
= V  
= 1000mV  
= 500mV  
= 250mV  
= 150mV  
17.57  
8.77  
4.34  
2.57  
17.75  
8.86  
4.43  
2.65  
17.93  
8.95  
4.52  
2.73  
V
V
V
V
SET2  
SET2  
SET2  
SET2  
V
V
, V Input Valid Threshold Hysteresis  
As a Percentage of the Rising Threshold  
11  
%
IN1 IN2  
, V Input Valid Comparator Delay  
IN1 IN2  
V
V
/V Falling, 2V/µs, V /V  
SET1 SET2  
= 1V  
= 1V  
60  
120  
µs  
µs  
IN1 IN2  
/V Rising, 2V/µs, V  
/V  
IN1 IN2  
SET1 SET2  
Open-Drain Output Voltage  
Open-Drain Pull-Down Resistance  
Open-Drain Leakage  
PGOOD, PRIORITY, VALID1, VALID2  
PGOOD, PRIORITY, VALID1, VALID2  
PGOOD, PRIORITY, VALID1, VALID2  
5.5  
1
V
Ω
70  
µA  
mΩ  
mΩ  
mV  
A
Low Side Switch Resistance  
High Side Switch Resistance  
Dropout Voltage  
70  
200  
310  
3.9  
5.2  
1A Load, V  
(Note 3)  
= 3.3V  
OUT  
High Side Switch Current Limit  
Low Side Switch Current Limit  
Zero Cross Threshold  
3.0  
3.8  
4.8  
6.8  
(Note 3)  
A
PWM/SYNC = Low (Note 3)  
PWM/SYNC = High or Clocked (Note 3)  
220  
0
mA  
mA  
SW Leakage Current  
V
= V = PV = PV = 42V, V = 0V, 42V  
–3  
4.12  
35  
3
µA  
V
IN1  
IN2  
IN1  
IN2  
SW  
V
V
V
Voltage  
I
= 1mA  
4.22  
67  
4.32  
CC  
CC  
CC  
VCC  
Current Limit  
Drop-Out Voltage  
V
= 3.5V  
mA  
CC  
Powered from V or V , V = 2.4V, I  
Powered from EXTV , V  
= 5mA  
= 5mA  
LOAD  
70  
100  
mV  
mV  
IN1  
IN2 IN  
CC EXTVCC  
LOAD  
= 3.3V, I  
V
Load Regulation  
I
= 1mA to 15mA  
LOAD  
1.1  
%
V
CC  
EXTV Applied Voltage  
3.15  
2.95  
42  
CC  
l
EXTV Valid, Rising Threshold  
3.05  
167  
0.2  
8.8  
200  
46  
3.15  
V
CC  
EXTV Valid, Hysteresis  
mV  
µA  
mA  
mV  
ns  
CC  
EXTV Current in Shutdown  
EXTV = 3.3V, ENA = Low  
CC  
CC  
EXTV Current  
Switching, f = 1MHz  
SW  
CC  
Frequency Foldback Threshold on FB  
SW Minimum On-Time  
V
V
= 24V, 1A Load, EXTV = OPEN  
IN  
CC  
SW Minimum Low-Time  
100  
16  
ns  
SW Frequency Foldback Factor  
SW Frequency Divider in Drop-Out  
< 0.2V  
FB  
8
Note 1: Stresses beyond those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. Exposure to any Absolute  
Maximum Rating condition for extended periods may affect device  
reliability and lifetime.  
150°C operating junction temperature range. High temperatures degrade  
operating lifetimes; operating lifetime is derated for junction temperatures  
greater than 125°C.  
Note 3: Current measurements are performed when the LTC3126 is  
not switching. The current limit values measured in operation will be  
somewhat higher due to the propagation delay of the comparators.  
Note 2: The LTC3126 is tested under pulsed load conditions such that  
T ≈ T . The LTC3126E is guaranteed to meet specifications from  
J
A
0°C to 85°C junction temperature. Specification over the –40°C to  
125°C operating junction temperature range are assured by design,  
characterization and correlation with statistical process controls. The  
LTC3126I specifications are guaranteed over the –40°C to 125°C operating  
junction temperature range. The LTC3126H specifications are guaranteed  
over the –40°C to 150°C operating junction temperature range. The  
LTC3126MP specifications are guaranteed and tested over the –55°C to  
Note 4: This IC includes overtemperature protection that is intended to  
protect the device during momentary overload conditions. The maximum  
rated junction temperature will be exceeded when this protection is active.  
Continuous operation above the specified absolute maximum operating  
junction temperature may impair device reliability or permanently damage  
the device.  
3126f  
4
For more information www.linear.com/LTC3126  
LTC3126  
TA = 25°C, unless otherwise noted.  
Typical perForMance characTerisTics  
Efficiency, VOUT = 5V,  
fSW = 700KHz  
Efficiency, VOUT = 3.3V,  
fSW = 700KHz  
Efficiency, VOUT = 1.8V,  
fSW = 700KHz  
100  
95  
90  
85  
80  
75  
70  
100  
95  
90  
85  
80  
75  
70  
100  
90  
80  
70  
60  
50  
V
IN  
= 12V  
V
IN  
= 12V  
V
IN  
= 12V  
IN  
IN  
IN  
V
= 24V  
V
= 24V  
V
= 24V  
L = 10µH  
PWM/SYNC = LOW  
L = 10µH  
PWM/SYNC = LOW  
L = 4.7µH  
PWM/SYNC = LOW  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
LOAD CURRENT (A)  
LOAD CURRENT (A)  
LOAD CURRENT (A)  
3126 G01  
3126 G02  
3126 G03  
Efficiency, VOUT = 5V,  
fSW = 700KHz  
Efficiency, VOUT = 3.3V,  
fSW = 700KHz  
Efficiency, VOUT = 1.8V,  
fSW = 700KHz  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
Burst Mode  
OPERATION  
Burst Mode  
OPERATION  
Burst Mode  
OPERATION  
PWM  
MODE  
PWM  
PWM  
MODE  
MODE  
L = 10µH  
L = 4.7µH  
L = 10µH  
V
IN  
= 12V  
= 24V  
V
IN  
= 12V  
= 24V  
V
V
= 12V  
IN  
IN  
IN  
IN  
V
V
= 24V  
0.0001 0.001 0.01  
0.1  
1
4
0.0001  
0.001  
0.01  
0.1  
1
4
0.0001  
0.001  
0.01  
0.1  
1
4
LOAD CURRENT (A)  
LOAD CURRENT (A)  
LOAD CURRENT (A)  
3126 G04  
3126 G05  
3126 G06  
Efficiency, VOUT = 5V,  
fSW = 2MHz  
Efficiency, VOUT = 3.3V,  
fSW = 2MHz  
Efficiency, VOUT = 1.8V,  
fSW = 2MHz  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
L = 2.2µH  
V
= 12V  
IN  
Burst Mode  
OPERATION  
Burst Mode  
OPERATION  
Burst Mode  
OPERATION  
PWM  
MODE  
PWM  
MODE  
PWM  
MODE  
L = 2.2µH  
L = 2.2µH  
V
IN  
= 12V  
V
IN  
= 12V  
= 24V  
IN  
IN  
V
= 24V  
V
0.0001  
0.001  
0.01  
0.1  
1
4
0.0001  
0.001  
0.01  
0.1  
1
4
0.0001  
0.001  
0.01  
0.1  
1
4
LOAD CURRENT (A)  
LOAD CURRENT (A)  
LOAD CURRENT (A)  
3126 G07  
3126 G08  
3126 G09  
3126f  
5
For more information www.linear.com/LTC3126  
LTC3126  
TA = 25°C, unless otherwise noted.  
Typical perForMance characTerisTics  
Efficiency vs Switching Frequency  
No-Load Input Current  
Shutdown Current vs VIN  
96  
94  
92  
90  
88  
86  
84  
8
7
6
5
4
3
2
1
0
2.0  
V
IN  
= 12V  
= 24V  
IN  
V
OUT  
= 3.3V  
ENA = LOW  
V
PWM/SYNC = LOW  
EXTV = V  
CC  
OUT  
1.6  
1.2  
0.8  
0.4  
0
V
= 5V  
OUT  
LOAD = 1A  
L = 10µH  
200  
600  
1000  
1400  
1800  
2200  
0
5
10 15 20 25 30 35 40 45  
0
5
10 15 20 25 30 35 40 45  
SWITCHING FREQUENCY (kHz)  
INPUT VOLTAGE (V)  
INPUT VOLTAGE (V)  
3126 G10  
3126 G11  
3126 G12  
EXTVCC Current vs Switching  
Frequency  
EXTVCC Current vs Input Voltage  
Load Regulation  
18  
16  
14  
12  
10  
8
20  
16  
12  
8
1.0  
0.8  
V
IN  
= 12V  
= 24V  
IN  
f
f
= 700kHz  
= 2MHz  
SW  
SW  
V
0.6  
0.4  
0.2  
0.0  
–0.2  
–0.4  
–0.6  
–0.8  
–1.0  
6
LOAD = 1A  
4
4
V
= 5V  
CC  
OUT  
LOAD = 1A  
= 5V  
2
EXTV = V  
OUT  
V
OUT  
L = 10µH  
0
0
200  
600  
1000  
1400  
1800  
2200  
5
15  
25  
INPUT VOLTAGE (V)  
35  
45  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
SWITCHING FREQUENCY (kHz)  
LOAD CURRENT (A)  
3126 G13  
3126 G14  
3126 G15  
VCC LDO Voltage Drop vs  
Switching Frequency  
Line Regulation  
FB Voltage vs Temperature  
0.5  
0.4  
0.5  
0.4  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
V
= 2.4V  
IN  
PWM/SYNC = HIGH  
0.3  
0.3  
0.2  
0.2  
0.1  
0.1  
BUCK OPERATING  
IN REGULATION  
–0.0  
–0.1  
–0.2  
–0.3  
–0.4  
–0.5  
–0.0  
–0.1  
–0.2  
–0.3  
–0.4  
–0.5  
BUCK OPERATING  
IN DROPOUT  
V
= 3.3V  
OUT  
LOAD = 0.5A  
PWM/SYNC = HIGH  
0
5
10 15 20 25 30 35 40 45  
–50 –25  
0
25 50 75 100 125 150  
200  
600  
1000  
1400  
1800  
2200  
INPUT VOLTAGE (V)  
TEMPERATURE (°C)  
SWITCHING FREQUENCY (kHz)  
3126 G16  
3126 G17  
3126 G18  
3126f  
6
For more information www.linear.com/LTC3126  
LTC3126  
TA = 25°C, unless otherwise noted.  
Typical perForMance characTerisTics  
V
CC Dropout Voltage  
vs Temperature  
VCC Load Regulation  
Switching Frequency vs RT  
120  
110  
100  
90  
4
3
3000  
2
1
1000  
80  
0
70  
–1  
–2  
–3  
–4  
60  
V
CC  
= 2.5V  
IN  
50  
I
= 5mA  
40  
100  
–50 –25  
0
25 50 75 100 125 150  
0
4
8
I
12  
(mA)  
16  
20  
10  
20  
100  
200 300  
TEMPERATURE (°C)  
R (kΩ)  
T
CC  
3126 G19  
3126 G20  
3126 G21  
Power Switch Resistance vs  
Temperature  
Reverse Current Out of the  
Unused Input (VIN1 or VIN2  
Switching Frequency  
vs Temperature  
)
350  
300  
250  
200  
150  
100  
50  
5.0  
4.0  
1.5  
1.0  
0.5  
0
TOP  
SWITCH  
f
f
= 700kHz  
= 2MHz  
SW  
SW  
3.0  
2.0  
1.0  
0
BOTTOM  
SWITCH  
–1.0  
–2.0  
–3.0  
–4.0  
–5.0  
V
= 3.3V  
OUT  
IN  
V
= 24V  
I
= 2A  
LOAD  
0
–50 –25  
0
25 50 75 100 125 150  
–50 –25  
0
25 50 75 100 125 150  
0
0.4  
0.8  
1.2  
1.6  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
VOLTAGE ON THE UNUSED INPUT (V)  
3126 G24  
3126 G23  
3126 G22  
Temperature Rise  
vs Load Current  
Minimum On-Time  
vs Temperature  
High Side Current Limit  
Threshold vs Temperature  
60  
56  
52  
48  
44  
40  
4.5  
4.2  
3.9  
3.6  
3.3  
3.0  
60  
50  
40  
30  
20  
10  
0
V
IN  
V
IN  
V
IN  
= 12V  
= 24V  
= 36V  
EXTV = OPEN  
OUT  
LOAD = 1A  
f
= 1MHz  
OUT  
CC  
SW  
V
= 3.3V  
V
= 3.3V  
ON DEMO PCB  
–50 –25  
0
25 50 75 100 125 150  
–50  
0
50  
100  
150  
0.5  
1
1.5  
LOAD CURRENT (A)  
2
2.5  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
3126 G25  
3126 G26  
3126 G27  
3126f  
7
For more information www.linear.com/LTC3126  
LTC3126  
TA = 25°C, unless otherwise noted.  
Typical perForMance characTerisTics  
Temperature Rise  
vs Load Current  
Minimum Load for Full Frequency  
Switching (No Pulse Skipping)  
Dropout Voltage vs Load Current  
60  
50  
40  
30  
20  
10  
0
800  
700  
600  
500  
400  
300  
200  
100  
0
40  
30  
20  
10  
0
f
= 700kHz  
SW  
V
IN  
= 12V  
IN  
L = 4.7µH  
= 5V  
V
= 24V  
V
OUT  
PWM/SYNC = HIGH  
f
= 1MHz  
= 3.3V  
= 3.3V  
SW  
IN  
OUT  
V
f
= 2MHz  
OUT  
SW  
V
V
= 3.3V  
ON DEMO PCB  
0.5  
1
1.5  
LOAD CURRENT (A)  
2
2.5  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
5
10 15 20 25 30 35 40 45  
LOAD CURRENT (A)  
INPUT VOLTAGE (V)  
3126 G28  
3126 G29  
3126 G30  
Maximum Input Voltage without  
Pulse Skipping  
Burst Mode Operation Threshold  
vs Input Voltage  
VREF vs Temperature  
45  
40  
35  
30  
25  
20  
15  
10  
5
1000  
800  
600  
400  
200  
0
1.2  
0.8  
f
f
f
= 700kHz, L = 4.7µH  
= 1MHz, L = 3.3µH  
= 2MHz, L = 2.2µH  
SW  
SW  
SW  
V
OUT  
= 3.3V  
0.4  
0.0  
250mA TO  
2.5A LOAD  
–0.4  
–0.8  
–1.2  
V
V
V
V
= 5V  
OUT  
OUT  
OUT  
OUT  
= 1.8V  
= 3.3V, EXTV = V  
= 3.3V, EXTV = OPEN  
CC  
CC  
OUT  
600 800 1000 1200 1400 1600 1800 2000 2200  
5
10 15 20 25 30 35 40 45  
–50 –25  
0
25 50 75 100 125 150  
SWITCHING FREQUENCY (kHz)  
INPUT VOLTAGE (V)  
TEMPERATURE (°C)  
3126 G31  
3126 G32  
3126 G33  
Switching Waveforms,  
PWM Mode  
Switching Waveforms,  
Burst Mode Operation  
Load Step, 0.5A to 1.5A  
LOAD  
CURRENT  
1A/DIV  
INDUCTOR  
CURRENT  
INDUCTOR  
CURRENT  
200mA/DIV  
500mA/DIV  
INDUCTOR  
CURRENT  
1A/DIV  
SW  
10V/DIV  
V
OUT  
50mV/DIV  
V
OUT  
100mV/DIV  
3126 G34  
3126 G35  
3126 G36  
200ns/DIV  
10µs/DIV  
24V TO 5V AT 25mA  
L = 2.2µH  
f = 2MHz  
SW  
100µs/DIV  
FRONT PAGE APPLICATION  
24V TO 5V AT 1A  
L = 2.2µH  
f
= 2MHz  
SW  
C
= 47µF  
OUT  
3126f  
8
For more information www.linear.com/LTC3126  
LTC3126  
TA = 25°C, unless otherwise noted.  
Typical perForMance characTerisTics  
Load Step, 0.5A to 2.5A  
Start-Up Waveforms  
ENA  
LOAD  
CURRENT  
2A/DIV  
5V/DIV  
VALID1  
5V/DIV  
INDUCTOR  
CURRENT  
2A/DIV  
V
OUT  
2V/DIV  
V
PGOOD  
5V/DIV  
OUT  
200mV/DIV  
3126 G37  
3126 G38  
100µs/DIV  
2ms/DIV  
FRONT PAGE APPLICATION  
FRONT PAGE APPLICATION  
Start-Up Dropout Performance  
Ideal Diode Mode Transition  
V
IN  
V
IN1  
V
, V  
IN1 IN2  
5V/DIV  
V
V
, V  
IN2  
IN OUT  
V
OUT  
2V/DIV  
PRIORITY  
5V/DIV  
I
500mA/DIV  
IN2  
INDUCTOR  
CURRENT  
500mA/DIV  
I
500mA/DIV  
100mV/DIV  
IN1  
V
OUT  
3126 G39  
3126 G40  
50ms/DIV  
50ms/DIV  
10Ω LOAD  
= 5V  
10Ω LOAD  
V = 5V  
OUT  
V
OUT  
Hot Plug of Automotive  
Input, VIN1  
Priority Mode Transition  
V
IN1  
V
IN2  
V
, V  
IN1 IN2  
V
V
, V  
SET1  
IN1 IN2  
10V/DIV  
THRESHOLD  
10V/DIV  
V
IN1  
V
IN2  
PRIORITY  
5V/DIV  
V
OUT  
100mV/DIV  
I
200mA/DIV  
200mA/DIV  
100mV/DIV  
IN2  
SW  
10V/DIV  
I
IN1  
V
OUT  
3126 G41  
3126 G42  
50ms/DIV  
20µs/DIV  
10Ω LOAD  
FRONT PAGE APPLICATION  
1A LOAD  
V
V
= 10V  
IN2  
OUT  
= 3.3V  
V
V
= 13.8V  
= 6V  
IN1  
IN2  
3126f  
9
For more information www.linear.com/LTC3126  
LTC3126  
pin FuncTions (QFN/TSSOP)  
V , PV (Pins 2, 3/Pins 5, 6): Internal Linear Regula-  
application(i.e.,ifthereisnoresistorfromV toground)  
REF  
CC  
CC  
tor Output and Power Supply for the Low Voltage Control  
then the V pin must be connected to V .  
REF CC  
Circuitry in the IC. Internal linear regulators generate a  
GND(Pin8/Pin11):SignalGround. Thispinistheground  
connection for the control circuitry of the IC and must be  
tied to ground.  
regulated voltage on these pins from either V , V or  
IN1 IN2  
EXTV . V and PV must be connected together in the  
CC CC  
CC  
application. A 4.7μF or larger bypass capacitor must be  
FB (Pin 9/Pin 12): Feedback Voltage Input. A resistor di-  
vider connected to this pin establishes the output voltage  
of the buck converter. Care should be taken in the rout-  
ing of connections to this pin in order to minimize stray  
coupling to the SW, BST1, BST2, COM1 and COM2 pins.  
connected between these pins and ground. The V rail  
CC  
remains powered in shutdown and can be used to supply  
up to 1mA to external loads.  
EXTV (Pin 4/Pin 7): V Regulator Bootstrapping Pin. If  
CC  
CC  
this pin is forced to 3.15V or greater then EXTV will be  
CC  
RT (Pin 10/Pin 13): Switching Frequency Programming  
Pin. A resistor placed from this pin to ground sets the  
switching frequency of the buck converter.  
used to power the internal V rail. Typically, the EXTV  
CC  
CC  
input is connected to the buck converter output voltage.  
Bootstrapping the internal V rail in this fashion provides  
CC  
a significant efficiency advantage and reduced quiescent  
PGOOD(Pin11/Pin14):Open-DrainPowerGoodIndicator  
fortheBuckConverterOutputVoltage.Thisoutputisdriven  
lowifthebuckconverteroutputvoltageismorethan8.7%  
below the regulation voltage or more than 9.8% above  
the regulation voltage. The PGOOD pin is also driven low  
whenever the buck converter is disabled. The maximum  
voltage that can be applied to the PGOOD pin is 5.5V.  
current especially in applications with high input voltage  
and low output voltage. If the EXTV pin is left open then  
CC  
the V rail will be powered from the V and V pins.  
CC  
IN1  
IN2  
V
, V  
(Pins 5, 6/Pins 8, 9): Programming Pins for  
SET1 SET2  
the UVLO Thresholds on V and V . The voltage on  
IN1  
IN2  
the V  
and V  
pins programs the UVLO threshold  
SET1  
SET2  
for the power source inputs V and V , respectively. A  
IN1  
IN2  
PRIORITY (Pin 12/Pin 15): Open-Drain Output Indicat-  
voltage between zero and 1V programs a corresponding  
UVLO threshold between zero and 20V. However, there  
is also a fixed internal UVLO threshold (typically 2.34V)  
on each input which is always in effect. The voltage on  
ing That the Priority Input (V ) Is Being Utilized. The  
IN1  
PRIORITY pin is driven low if the part is enabled and the  
buck converter is operating from the priority input, V  
.
IN1  
In disable (ENA low) the PRIORITY pull-down is disabled,  
allowing the pin to float. The maximum voltage that can  
be applied to the PRIORITY pin is 5.5V.  
V
can be set using a resistor divider from the accu-  
SET1,2  
rate reference output, V . Grounding V  
will allow  
REF  
SET1,2  
the respective input V  
internal UVLO threshold.  
to be used down to the fixed,  
IN1,2  
PV (Pin 13/Pin 16): Secondary Power Source Input  
IN2  
for the Buck Converter. In priority mode (DIODE pin low)  
the buck converter will only operate from this input if the  
priorityinputpowersourceisundervoltage. Thispinmust  
be bypassed with a 4.7µF or larger ceramic capacitor to  
V
(Pin 7/Pin 10): Voltage Reference Output for Pow-  
REF  
ering Resistor Dividers to Set the V  
and V  
Inputs.  
SET1  
SET2  
The voltage at this pin is regulated by the IC to maintain a  
high precision, temperature stable 1.0V output. Resistive  
ground. If the PV input will be subjected to inductive  
IN2  
dividers from the V pin can be used to set the voltage at  
REF  
shorts to ground, then a power Schottky diode must be  
the V  
and V  
pins and thereby program the UVLO  
SET1  
SET2  
added from ground to PV to prevent this pin from being  
IN2  
thresholdforeachinput.TheV outputmayalsobeused  
REF  
driven below ground.  
as a general purpose voltage reference in the application,  
providingatemperaturestablereferenceforcomparators,  
DACs or other functions. The total current drawn from this  
pin must be limited to 1mA and the total capacitive load  
should be limited to 470pF. If this pin is not used in the  
ENA (Pin 14/Pin 17): Enable Input. Forcing the ENA pin  
low disables the input voltage comparators, the V pin  
REF  
driverandthebuckconverter.TheV railremainspowered  
CC  
in disable and therefore ENA can be connected to V to  
CC  
3126f  
10  
For more information www.linear.com/LTC3126  
LTC3126  
pin FuncTions (QFN/TSSOP)  
continuously enable the part. The maximum voltage that  
can be applied to the ENA pin is 5.5V.  
4.7µF or larger ceramic capacitor to ground. If the PV  
IN1  
input will be subjected to inductive shorts to ground, then  
a power Schottky diode must be added from ground to  
PGND (Pins 18, 19, Exposed Pad Pin 29/Pins 21, 22,  
Exposed Pad Pin 29): Power Ground Connections. These  
pins must be connected to ground in the application.  
PV to prevent this pin from being driven below ground.  
IN1  
V
(Pin 25/Pin 28): Priority Power Source Kelvin Con-  
IN1  
nection. This pin must be bypassed with a 0.1µF ceramic  
For optimal thermal performance, the backpad should  
be soldered to the PC board and the PC board should  
be designed with the maximum possible number of vias  
connecting the backpad to the ground plane.  
capacitor to ground. The V pin must be connected to  
PV in the application.  
IN1  
IN1  
V
(Pin26/Pin1):SecondaryPowerSourceKelvinCon-  
IN2  
nection. This pin must be bypassed with a 0.1µF ceramic  
SW (Pins 17, 20/Pins 20, 23): Power Switch Inductor  
Connections. This pin should be connected to one side  
of the buck converter inductor.  
capacitor to ground. The V pin must be connected to  
PV in the application.  
IN2  
IN2  
PWM/SYNC (Pin 27/Pin 2): PWM/Burst Mode Operation  
Control and External Synchronization Clock Input. Forc-  
ing this pin high causes the buck converter to operate  
in PWM mode. In PWM mode, the converter maintains  
fixed frequency operation over the widest range of load  
currents possible, leaving fixed frequency operation only  
at extremely light loads where the converter skips pulses  
to maintain regulation. Forcing the PWM/SYNC pin low  
causes the IC to utilize Burst Mode operation at light loads  
and automatically transition to PWM mode at higher load  
current.BurstModeoperationimproveslightloadefficiency  
and significantly reduces no-load input quiescent current  
attheexpenseofmodestlyincreasedoutputvoltageripple.  
In addition, an external clock can be applied to the PWM/  
SYNC pin for synchronization purposes. When synchro-  
nized to an external clock the buck converter operates in  
PWM mode (Burst Mode operation is disabled).  
COM1, COM2 (Pins 16, 21/Pins 19, 24): Negative Ter-  
mination for Charge Pump Capacitors. External 0.1µF  
capacitors (with 5V rating or greater) must be connected  
between BST1 and COM1 and between BST2 and COM2.  
BST1, BST2 (Pins 15, 22/Pins 18, 25): High Side Gate  
Driver Supply Rails. External 0.1µF capacitors (with 5V  
rating or greater) must be connected between BST1 and  
COM1 and between BST2 and COM2. These pins are used  
togenerateagatedriverailforthehighsidepowerdevices.  
DIODE (Pin 23/Pin 26): Logic Input Used to Select Be-  
tween Ideal Diode-OR and Priority Modes. The integrated  
power path allows operation from either of two input  
power sources, V or V . An input is considered valid  
IN1  
IN2  
for use only if its voltage is above the UVLO threshold  
for that input as programmed by the respective voltage  
at the V  
or V  
pin. If DIODE is high then the part  
SET2  
SET1  
operates in ideal-diode mode and the buck converter will  
operate from the highest voltage valid input (V or V ).  
VALID1, VALID2 (Pins 1, 28/Pins 3, 4): Open-Drain  
Outputs Indicating Whether the V and V Inputs Are  
IN1  
IN2  
IN1  
IN2  
If DIODE is low then the part operates in priority mode and  
Valid. When the part is enabled (ENA is high) VALID1 and  
the buck converter will operate from V whenever it is  
VALID2 are driven low if the voltage at the V or V  
IN1  
IN1  
IN2  
valid and will switch to V only if V becomes invalid.  
input is above the UVLO threshold set by the respective  
IN2  
IN1  
In either mode, if both inputs are under voltage then the  
V
or V pin. When the part is disabled (ENA is low)  
SET1  
SET2  
buck converter will be disabled.  
the VALID1 and VALID2 pull-downs are disabled allowing  
the pins to float. The maximum voltage that can be applied  
to the VALID1 and VALID2 pins is 5.5V.  
PV (Pin 24/Pin 27): Priority Power Source Input for  
IN1  
the Buck Converter. In priority mode (DIODE pin low) the  
buck converter will preferentially operate from this input  
if both input power sources are valid (above their respec-  
tive UVLO thresholds). This pin must be bypassed with a  
3126f  
11  
For more information www.linear.com/LTC3126  
LTC3126  
block DiagraM Pin numbers shown for QFN package  
24  
21  
13  
PV  
16  
COM2  
–
+
PV  
COM1  
PRIORITY  
VALID1  
IN1  
IN2  
0.05V  
IN1  
12  
28  
1
V
SET1  
ENA  
5
RUN ON V  
IN1  
–
+
UVLO1  
HIGHER  
UVLO2  
V
IN1  
2.34V  
+
–
V
IN1  
–
+
ENA  
VALID  
V
POWER  
PATH  
IN2  
V
V
IN1  
IN2  
2.34V  
–
+
0.05V  
IN2  
VALID2  
V
SET2  
6
ENA  
VALID  
DIODE  
23  
V
V
IN2  
26  
25  
4
IN1  
TRIPLE INPUT  
LDO  
CURRENT  
EXTV  
CC  
SW  
SW  
LIMIT  
+
17  
20  
3.9A  
–
–
+
V
CC  
ZERO  
CURRENT  
2
3
PV  
CC  
GATE  
DRIVERS  
898mV  
+
–
PV  
CC  
0A  
FB  
FB  
+
–
CURRENT  
LIMIT  
PGOOD  
+
–
11  
747mV  
BST1  
BST2  
5.2A  
22  
15  
BUCK ENABLE  
SLOPE  
COMPENSATION  
+
PGND  
–
+
FB  
9
RT  
+
–
CLK  
10  
27  
OSCILLATOR  
818mV  
CONTROL  
LOGIC  
PWM/BURST  
MODE OPER.  
MODE SELECTION  
(PWM MODE IF  
PWM/SYNC IS HIGH  
OR SWITCHING  
+
–
FB  
898mV  
PWM/SYNC  
OV  
V
REF  
+
–
1.000V  
7
ENA  
ENA  
GND  
8
PGND PGND PGND  
18 19 29  
14  
3126 BD  
NOTE:  
IN1  
PV AND V MUST BE CONNECTED TOGETHER IN THE APPLICATION  
IN1  
PV AND V MUST BE CONNECTED TOGETHER IN THE APPLICATION  
IN2 IN2  
V
CC  
AND PV MUST BE CONNECTED TOGETHER IN THE APPLICATION  
CC  
Quick reFerence  
This section of the data sheet contains all of the equations  
necessary for external component selection as well as  
key part usage notes all compiled into one location for  
ease of use.  
Table 1. RT Value for Common Switching Frequencies  
f
R
T
SW  
300kHz  
500kHz  
750kHz  
1.0MHz  
1.2MHz  
1.5MHz  
2.0MHz  
110kΩ  
66.5kΩ  
44.2kΩ  
33.2kΩ  
27.4kΩ  
22.1kΩ  
16.5kΩ  
Switching Frequency  
The buck converter switching frequency, f , is set by the  
SW  
value of R resistor connected between the RT pin and  
T
ground according to the following equation:  
33.2MHz  
RT =  
kΩ  
fSW  
3126f  
12  
For more information www.linear.com/LTC3126  
LTC3126  
Quick reFerence  
Output Voltage  
Table 2. Recommended Minimum Inductor Values  
= 750kHz  
f
SW  
The buck converter output voltage is set via a resistor  
divider connected to the FB pin as shown in Figure 1.  
V
MINIMUM INDUCTOR VALUE  
OUT  
12V  
5V  
8.0µH  
3.3µH  
2.2µH  
1.2µH  
In most applications, choosing R  
resents a good trade-off between quiescent current and  
robustness against PCB leakage. R can be determined  
bythefollowingequationwhereV  
voltage:  
equal to 1MΩ rep-  
TOP  
3.3V  
1.8V  
BOT  
isthedesiredoutput  
OUT  
f
SW  
= 1MHz  
RTOP  
VOUT  
0.818V  
V
MINIMUM INDUCTOR VALUE  
OUT  
RBOT  
=
12V  
5V  
6.0µH  
2.5µH  
1.8µH  
1.0µH  
–1  
3.3V  
1.8V  
V
OUT  
R
FF  
R
R
TOP  
LTC3126  
FB  
C
FF  
f
SW  
= 2MHz  
V
MINIMUM INDUCTOR VALUE  
OUT  
GND  
BOT  
12V  
5V  
3.3µH  
1.5µH  
1.0µH  
1.0µH  
3126 F01  
3.3V  
1.8V  
Figure 1. FB Resistor Divider  
The peak-to-peak inductor ripple, ΔI , is given by the fol-  
Inductor Value  
L
lowing equation.  
Ifthebuckconverterwillbeoperatedatdutycyclesgreater  
than 50% (i.e., V < 2V ) then the inductor value must  
be equal or greater than L  
equation:  
VOUT  
VOUT  
IN  
OUT  
∆IL =  
1–  
as defined by the following  
MIN  
fSW •L  
V
IN  
MHz VOUT  
fSW 2V  
Output Capacitor  
LMIN  
=
•
µH  
The recommended minimum output capacitor, C , is  
given below as a function of output voltage:  
MIN  
1V  
VOUT  
CMIN  
=
150µF  
Table 3. Minimum Output Capacitor vs VOUT  
V
MINIMUM C  
10µF  
OUT  
OUT  
24V  
12V  
5V  
22µF  
33µF  
3.3V  
1.8V  
1.2V  
47µF  
100µF  
150µF  
3126f  
13  
For more information www.linear.com/LTC3126  
LTC3126  
Quick reFerence  
V
, V UVLO Thresholds  
IN1 IN2  
capacitor can be utilized to reduce the zero frequency and  
improve the transient response and phase margin. As  
The V and V UVLO thresholds are set by the volt-  
IN1  
IN2  
shown in Figure 1, a 10k feedforward resistor, R , can  
FF  
age on the V  
and V  
pins respectively. Each UVLO  
SET1  
SET2  
be added to improve noise immunity in applications with  
threshold can be set from a maximum of 20V down to the  
internal fixed UVLO threshold of 2.34V using a resistor  
high output voltage ripple or a long distance between the  
resistor divider and V  
.
OUT  
divider from the V  
output as shown in Figure 2. The  
REF  
rising UVLO threshold is given by the following equation:  
Open-Drain Outputs  
R2  
VUVLO1,2 = 20VSET1,2 = 20V  
R1+R2  
The open-drain outputs (PGOOD, PRIORITY, VALID1 and  
VALID2) are low voltage pins and cannot be pulled up to a  
voltage higher than 5.5V. PGOOD is forced low in disable.  
GroundingtheV  
pinwilldefinetherespectiveinputas  
SET1,2  
valid down to the fixed internal UVLO threshold of 2.34V.  
Logic Inputs  
V
The logic input pins (DIODE, ENA, PWM/SYNC) are low  
voltage pins and cannot be forced above 5.5V. To force  
any of these pins continuously high, the pin can be con-  
REF  
R1  
R2  
LTC3126  
V
SET1,2  
GND  
nected to V .  
CC  
3126 F02  
Important Usage Notes  
Figure 2. Input UVLO Threshold Divider  
1. PV  
and V  
must be connected together in the  
IN1  
IN1  
application.PV andV mustbeconnectedtogether  
IN2  
IN2  
External Synchronization Clock Frequency  
in the application. PV and PV must each have a  
IN1  
IN2  
Thebuckconvertercanbesynchronizedtoanexternalclock  
appliedto thePWM/SYNCpin. Thefrequencyoftheexternal  
clock must be higher than the internal oscillator frequency  
as set by the RT pin. In order to accommodate the 10%  
4.7µF or larger bypass capacitor installed and placed  
as close to the pin as possible. In addition, V and  
IN2  
IN1  
V
should have a separate 0.1µF bypass capacitor  
installed as close to the pin as possible.  
possible variation in the oscillator frequency, the R resistor  
T
2. The two SW pins must be connected together in the  
application.  
should be chosen to set the internal oscillator frequency at  
least 10% below the lowest synchronization frequency. For  
3. V and PV must be connected together in the  
example,tosynchronizetoanexternal1MHzclock,R should  
CC  
CC  
T
application and should be bypassed with a 4.7µF or  
be picked to set the internal oscillator at 900kHz or lower.  
larger capacitor.  
Feedforward Capacitor  
4. If the V pin is not used in the application (i.e., there  
REF  
The feedforward capacitor, C , as shown in Figure 1  
is no resistor from V to GND) then the V pin must  
FF  
REF  
REF  
improves the noise robustness of the FB pin and adds a  
be connected to V .  
CC  
zero to the loop at the frequency f  
given below:  
ZERO  
5. If PV or PV can be driven below ground in the  
IN1  
IN2  
1
application, for example due to large inductive ringing  
fZERO  
=
at the input, then Schottky diodes must be installed  
2π•RTOP •CFF  
from ground to PV /PV to protect the LTC3126.  
IN1  
IN2  
In most applications performance will be optimized if the  
zero frequency is set at approximately 16kHz. In applica-  
tions with large output capacitance, a larger feedforward  
3126f  
14  
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LTC3126  
operaTion  
TheLTC3126isadual-inputsynchronousmonolithicbuck  
converter featuring the ability to operate from two differ-  
ent input power sources with voltage ranges from 2.4V  
to 40V. An integrated lossless power path eliminates the  
need for an external diode-OR circuit or another type of  
externalpowerpathenablingacompletemulti-inputpower  
supplysolutionwithhigherefficiency, fewercomponents,  
lowerquiescentcurrentandreduceddrop-outvoltage.The  
LTC3126 integrates all of the control circuitry required to  
automatically transition between two input power sources  
based on user programmable UVLO thresholds and se-  
lectable ideal-diode and priority modes. These features  
allow the LTC3126 to serve as a complete single chip  
power supply solution from a variety of different power  
sources including automotive, wall adapter, USB/Firewire  
and a wide range of battery chemistries. In addition, the  
LTC3126 is ideally suited for capacitor backup supplies  
with its ability to automatically transition to a capacitive  
backup rail when primary power is interrupted. A low 1µA  
quiescent current in disable and 2µA operating current  
make the LTC3126 ideally suited for battery powered and  
automotive applications.  
LTC3126  
1.00V  
+
–
V
V
REF  
–
+
IN1,2  
V
IN1,2  
V
2.34V  
IN  
20  
–
R1  
UVLO1,2  
V
SET1,2  
+
R2  
3126 F03  
Figure 3. Programming the UVLO Thresholds on VIN1 and VIN2  
range of zero to 1V on the V  
corresponds to a UVLO  
. In addition, there is a  
SET1,2  
threshold of zero to 20V on V  
IN1,2  
fixed internal minimum UVLO threshold of 2.34V which is  
always enforced independent of the programmed voltage  
on the V  
and V  
pins. To enable a channel down  
SET1  
SET2  
to this minimum UVLO threshold, the respective V  
pin can be simply connected to ground.  
SET1,2  
The LTC3126 power path has two operational modes as  
determined by the state of the DIODE logic input. With  
DIODEhigh,thepartutilizesidealdiode-ORmodeandoper-  
ates from the input that has the higher voltage (assuming  
both inputs are above their respective UVLO thresholds).  
If one input is in UVLO then the other input will be utilized.  
If both inputs are in UVLO then the buck converter will  
be disabled. With the DIODE input low, the part operates  
PowerPath Operation  
The power path controls whether the buck converter  
operates from the V or V input based on program-  
IN1  
IN2  
mableundervoltagelockoutthresholdsforeachinput.The  
UVLO architecture used by the LTC3126 eliminates the  
need to connect external resistor dividers directly to the  
input voltages thereby providing a substantial reduction  
in quiescent current.  
in priority mode whereby V is always given priority  
IN1  
and is utilized as long as it is above its UVLO threshold.  
If V is in UVLO then V is utilized as long as it is not  
IN1  
IN2  
in UVLO. If both V and V are in UVLO then the buck  
IN1  
IN2  
The V  
and V  
pins are used to set the undervolt-  
SET2  
converter is disabled.  
SET1  
age lockout thresholds for the two power source inputs  
and V respectively. The UVLO threshold for each  
AllcurrentdrawnfromtheV pinissuppliedbyoneofthe  
inputs, V or V . If neither input is above its respective  
UVLO threshold, then this current will be drawn from the  
input with the higher voltage. Otherwise, this current will  
bedrawnbytheactivechannelasdeterminedbythepower  
path. The V pin current will be supplied by the EXTV  
pin if that pin is utilized and has a valid voltage present.  
REF  
V
IN1  
IN2  
IN1  
IN2  
input can be independently set to any voltage from 20V  
down to the internal fixed UVLO threshold of 2.34V us-  
ing an external resistor divider as shown in Figure 3. The  
V
pin is regulated to a fixed, temperature stable 1.0V.  
REF  
REF  
CC  
An external resistor divider from the V  
pin is used to  
SET2  
pin is compared to  
REF  
and V  
establish the voltage at the V  
programmed voltage at the V  
pins. The  
SET1  
SET1,2  
IN1  
The PRIORITY, VALID1 and VALID2 open-drain outputs  
provide feedback on the state of the power path. The  
VALID1 and VALID2 outputs indicate that the respective  
the respective input voltage (V or V ) scaled down  
IN2  
through an internal resistor divider with a ratio of 20:1 to  
determineifthatinputisundervoltage.Asaresult,avoltage  
inputispresentandaboveitsUVLOthreshold.Specifically,  
3126f  
15  
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LTC3126  
operaTion  
the VALID1 pin is driven low if the part is enabled (ENA is  
If PWM/SYNC is forced high or has an external clock ap-  
plied, then the buck converter will operate in PWM mode.  
In PWM mode operation, the buck converter will maintain  
fixed frequency switching at all possible load currents,  
switching topulse skipping only at very light load currents  
when the minimum on-time of the SW is reached. PWM  
mode provides low noise, fixed frequency operation and  
low output voltage ripple over the widest possible range  
of load currents and should be used when it is necessary  
to maintain the lowest possible noise levels. With PWM/  
SYNC forced low, the converter will automatically transi-  
tion to Burst Mode operation at light loads to increase  
efficiency and reduce no-load quiescent current.  
high) and V is above its UVLO threshold. The VALID2  
IN1  
pin is driven low if the part is enabled and V is above  
IN2  
its UVLO threshold. The PRIORITY pin is driven low if the  
part is enabled and the buck converter is operating from  
the priority channel, V . The PRIORITY pin provides the  
IN1  
ability to determine which input is being utilized in ideal-  
diode mode when both inputs are valid.  
The V rail stays powered even when the LTC3126 is  
CC  
disabled (ENA is low) as long as either V or V is  
IN1  
IN2  
powered. In this disabled state, the V output is powered  
CC  
from whichever input (V or V ) is higher in voltage  
IN1  
IN2  
independent of the state of the DIODE pin. Given that the  
V
output remains powered in shutdown, the ENA pin  
The LTC3126 buck converter is current limit protected  
to prevent damage to the IC during output overload and  
short-circuit conditions. If the inductor current exceeds  
the high side switch current limit threshold then the high  
side switch is turned off for the remainder of the cycle.  
If the inductor current exceeds the low side current limit  
threshold, then the high side switch will remain off during  
the next cycle to prevent increasing the inductor current  
further during the high side switch minimum on-time. In  
addition, the switching frequency is reduced by a factor  
of 16 if the FB voltage is below 200mV to ensure control  
of the inductor current is maintained during output over-  
current conditions.  
CC  
can be connected to V to continuously enable the part.  
CC  
Buck Converter Operation  
The LTC3126 buck converter utilizes constant frequency  
switching with peak current mode control to provide low  
noise operation. The switching frequency can be set from  
200kHz to 2.2MHz by appropriate choice of the RT pin  
resistor. In addition, the buck converter can be synchro-  
nized to an external clock applied to the PWM/SYNC pin.  
The buck converter always operates from a single input  
power source (V or V ) at any time. The input that is  
IN1  
IN2  
used is determined by the state of the DIODE input, the  
programmed UVLO thresholds and the voltage of each  
input as described in the PowerPath Operation section.  
Each switching cycle begins with the high side switch of  
the active input turning on. The high side switch remains  
on until the inductor current reaches the current level set  
bytheoutputoftheinternallycompensatederroramplifier.  
At that point, the low side synchronous rectifier turns on  
and remains on for the remainder of the cycle or until the  
inductor current falls to zero. The error amplifier continu-  
ously adjusts the commanded current level to maintain  
regulation of the FB pin voltage.  
The internal circuitry of the buck converter including the  
gate drivers is powered from V . Internal LDOs gener-  
CC  
ate the V rail from the active input, V or V . In  
CC  
IN1  
IN2  
applications where the buck converter output is 3.3V or  
greater, the V rail can be bootstrapped by connecting  
CC  
the EXTV pin to the buck converter output. This allows  
CC  
a third LDO to generate the V rail directly from EXTV .  
CC  
CC  
Given that the buck converter has much greater efficiency  
thantheLDOs,bootstrappingviatheEXTV pinincreases  
CC  
the efficiency of the converter and reduces its quiescent  
current. This is particularly the case for applications with  
high input voltage, low output voltage and high switching  
frequencies.  
3126f  
16  
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LTC3126  
applicaTions inForMaTion  
Input UVLO Thresholds on V , V  
IN1 IN2  
V
V
V
REF  
R1  
LTC3126  
The undervoltage lockout threshold for each input, V  
IN1  
SET2  
SET1,2  
SET1,2  
and V , is set by the voltage on the V  
and V  
IN2  
SET1  
R2  
R3  
pins respectively. A voltage between 0V and 1V on V  
SET2,1  
linearly programs a corresponding UVLO threshold of  
zero to 20V. There is also an additional internal minimum  
undervoltage lockout threshold of 2.34V on each input  
which is always in effect independent of the voltage at  
3126 F05  
Figure 5. Setting Both Input UVLO Thresholds Using  
a Single Resistor String  
the V  
pins. To allow an input to operate fully down  
SET1,2  
to the internal minimum UVLO threshold, the respective  
pin can be connected to ground.  
Resistor R3 can be chosen independently and selecting  
R3 equal to 200k is a reasonable starting choice for most  
applications. The value of R2 and R1 can then be deter-  
V
SET1,2  
In most applications, the voltage at the V  
and V  
SET2  
SET1  
pin is established using a resistor divider from the V  
REF  
mined from the following equations where V  
is the  
UVLOH  
pin as shown in Figure 4. The corresponding rising UVLO  
threshold is given by the following equation:  
undervoltage lockout threshold on the higher voltage  
channel and V  
is the UVLO threshold on the lower  
ULVOL  
voltage channel:  
R2  
VUVLO1,2 = 20VSET1,2 = 20V  
R1+R2  
VUVLOH  
R2=R3  
–1  
V
When neither input is valid (above its respective UVLO  
UVLOL  
threshold), the current drawn from the V  
pin will add  
REF  
directlytothequiescentcurrentofthehighervoltageinput  
20  
R1= R2+R3  
–1  
(
)
(V or V ). Therefore, use of large value resistors in  
IN1  
the V  
IN2  
V
UVLOH  
divider string will reduce the quiescent cur-  
SET1,2  
rent. However, larger value resistors also result in lower  
immunity to noise and leakage currents. A reasonable  
compromise in most applications is to utilize a total resis-  
tor string impedance of 1MΩ.  
If the resulting total resistance through the resistor chain  
(R1 + R2 + R3)is larger or smaller then desired, the choice  
of R3 can be adjusted in the appropriate direction and the  
calculation for R2 and R1 can be repeated.  
V
Input Hold-Up Capacitance  
REF  
R1  
R2  
LTC3126  
The LTC3126 features internal micropower UVLO com-  
parators which minimize the quiescent current required  
by the application. However, due to their low operating  
current, the UVLO comparators exhibit a significant delay  
when responding to an undervoltage condition. Sufficient  
input hold-up capacitance must be provided to ensure the  
voltage on the utilized channel remains sufficient to power  
the buck converter until the transition to the secondary  
channel is completed.  
V
SET1,2  
GND  
3126 F04  
Figure 4. Setting the Input UVLO Thresholds  
To minimize quiescent current and eliminate an external  
resistor it is also possible to set both UVLO thresholds via  
a single resistor string as shown in Figure 5. The upper  
Consider the example illustrated in Figure 6 where the  
resistor divider tap is connected to whichever pin, V  
SET1  
LTC3126 is being powered by the priority input (V  
)
IN1  
or V  
, requires the higher UVLO threshold.  
SET2  
at 12.8V and the UVLO threshold on the V channel is  
IN1  
3126f  
17  
For more information www.linear.com/LTC3126  
LTC3126  
applicaTions inForMaTion  
programmed to 10V. At time t , the priority input is un-  
+ 700mV = 4V. Finally, assuming an efficiency of 80%,  
the minimum required input hold-up capacitance on the  
priority channel can be calculated as:  
1
plugged and the buck converter begins discharging the  
input capacitor. At time t , the UVLO threshold is reached  
2
but the buck converter remains operating from the prior-  
2 3.3V 2.5A 60µs  
(
)(  
)(  
)
ity channel due to the comparator delay. At time t , after  
CIN =  
3
2
2
0.80[ 10V – 4V ]  
(
)
(
)
comparatordelayt  
,thebuckconverterswitchesover  
DELAY  
to the secondary input (V ) and the input capacitor on  
IN2  
µs•A  
V
=14.7  
=14.7µF  
V
IN1  
maintains its voltage since there is no longer any  
current being drawn on that channel. In this example, the  
input capacitor on V must be large enough that V  
Therefore, in this example a minimum capacitor value of  
IN1  
IN1  
remainsatsufficientvoltagetomaintaintheoutputvoltage  
15µF or greater must be utilized on V to maintain regu-  
IN1  
in regulation until time t . If V is allowed to drop lower  
lation of the buck converter output throughout the transi-  
tion to the secondary channel. In practice, an additional  
guardband should be included to account for variations  
in component tolerances and delays.  
3
IN1  
than the regulated output voltage then the buck converter  
outputwilltemporarilyloseregulationduringthetransition.  
t
DELAY  
V
IN1  
Soft-Start  
10V  
TheLTC3126incorporatesaninternalsoft-startcircuitwith  
a nominal duration of 7.5ms. The soft-start is implemented  
by a linearly increasing ramp of the error amplifier refer-  
ence voltage during the soft-start duration. As a result, the  
duration of the soft-start period is largely unaffected by the  
sizeoftheoutputcapacitorortheoutputregulationvoltage.  
Given the closed-loop nature of the soft-start implementa-  
tion, the converter is able to respond to load transients that  
occur during the soft-start interval. The soft-start period  
is reset by thermal shutdown, when the buck converter is  
disabled via the ENA pin and when both inputs are in UVLO.  
I
IN2  
t
t
t
3
3126 F06  
1
2
Figure 6. Waveforms During Transition from VIN1 to VIN2  
The required value of hold-up capacitance, C , can be  
IN  
OUT  
is the buck  
estimated from the following equation where V  
buck converter regulated output voltage, I  
is the  
LOAD  
converter load current, η is the buck converter efficiency,  
V
REF  
Output  
V
is the falling UVLO threshold of the active channel  
is the minimum required input voltage needed  
UVLO  
and V  
The V output is a regulated, temperature stable 1.00V  
MIN  
REF  
for the buck converter to maintain regulation.  
voltage reference. It is intended primarily to be used to  
establish the V  
and V  
pin voltages. However, it  
SET1  
SET2  
2VOUT •ILOAD •tDELAY  
CIN =  
can also be used for other functions as long as the total  
current drawn from the pin is limited to 1mA or less.  
In addition to that restriction, there is also a maximum  
2
η V  
2 – VMIN  
(
)
UVLO  
In the example from Figure 6, the UVLO threshold, V  
is 10V. The typical comparator delay of t  
,
amount of capacitance that can be placed on the V pin  
UVLO  
REF  
= 60µs is  
in order to maintain suitable phase margin in the internal  
DELAY  
specified in the Electrical Characteristics section of this  
data sheet. For the sake of this example, consider a buck  
converter output voltage of 3.3V with a 2.5A load. The  
buck converter dropout voltage at 2.5A is approximately  
700mV. Therefore, the minimum buck converter input  
pin driver. The maximum recommended capacitance on  
the V pin is 470pF or less. If the V pin is not being  
REF  
REF  
used in the application (i.e., there is no resistor from V  
REF  
to GND) then the V  
pin should be connected to V .  
REF  
CC  
The V pin cannot be left floating. The V pin is only  
REF  
REF  
voltage, V , required to maintain regulation is 3.3V  
powered when the part is enabled (ENA is high).  
MIN  
3126f  
18  
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LTC3126  
applicaTions inForMaTion  
Buck Converter Switching Frequency  
When powered through an inductive connection such as  
a long cable, the inductance of the power source and the  
input bypass capacitor form a High-Q resonant LC filter.  
In such applications, hot-plugging into a powered source  
can lead to a significant voltage overshoot, even up to  
twice the nominal input source voltage. Care must be  
taken in such situations to ensure that the absolute maxi-  
mum input voltage rating of the LTC3126 is not violated.  
See Linear Technology Application Note 88 for solutions  
to increase damping in the input filter and minimize this  
voltage overshoot.  
TheLTC3126buckconverterutilizesfixed-frequencyPWM  
to achieve low output ripple and low noise operation. The  
switching frequency can be set from 200kHz to 2.2MHz  
by appropriate selection of the R resistor placed between  
T
the RT pin and ground. See the Quick Reference section  
for details on selecting the value for R .  
T
Higher switching frequencies facilitate the use of smaller  
inductors as well as smaller input and output capacitors  
which results in a smaller solution size and reduced com-  
ponentheight.However,higherswitchingfrequenciesalso  
generally reduce conversion efficiency due to increased  
switching losses.  
The V and V pins provide power to the V regulator  
IN1  
IN2  
CC  
and other internal circuitry. Each of these pins should be  
connected to a 0.1µF bypass capacitor located as close  
to the pin as possible.  
The on-time of the buck converter SW pin decreases as  
the step-down ratio from V to V  
increases and as the  
IN  
OUT  
switching frequency is increased. The minimum switch  
Buck Output Capacitor  
on-time, t , is the smallest duration on-time that the  
ON(MIN)  
A low ESR capacitor should be utilized at the output of  
the buck converter in order to minimize output voltage  
ripple. For most applications, a ceramic capacitor with  
X5R or X7R dielectric is the optimal choice. There is also  
a minimum required output capacitor value as specified  
in the Quick Reference section. The crossover frequency  
of the voltage control loop increases with lower output  
capacitance and therefore a minimum capacitance value  
is required to limit the bandwidth and ensure stability  
of the voltage feedback loop. Given that the loop gain is  
dependent on the voltage divider ratio, the minimum re-  
quired output capacitor is a function of the output voltage  
as well. At lower output voltages, the loop gain is higher  
and a larger output capacitor is required to maintain a  
fixed loop crossover frequency. The larger recommended  
output capacitance at low output voltages also helps to  
reduce the magnitude of voltage steps on load transients  
in proportion to the reduced output voltage rail in order  
to maintain a constant percentage deviation.  
SW pin can generate. If the required on-time is shorter  
than the minimum on-time then the part will pulse skip to  
maintain regulation. Although regulation of the output will  
be maintained, pulse skipping results in lower frequency  
switching and increased output voltage ripple. In order to  
avoid pulse-skipping operation, the switching frequency  
should be selected to be less than f  
as given by  
SW(MAX)  
the following equation where t  
is the minimum SW  
ON(MIN)  
pin on time with a typical value of 60ns:  
VOUT  
fSW(MAX)  
=
V •t  
IN  
ON(MIN)  
The SW minimum on-time is a function of load current  
and temperature as shown in the Typical Performance  
Characteristics section.  
Input Capacitors  
To ensure proper functioning of the buck converter, mini-  
Increasingthevalueofthebuckconverteroutputcapacitor  
will decrease the bandwidth of the feedback loop. If the  
output capacitor gets too large, the crossover frequency  
may decrease too far below the compensation zero lead-  
ingtodegradedphasemarginandunderdampedtransient  
response. In such cases, the phase margin and transient  
performance can be improved by increasing the size  
mizeEMIandreduceinputripple, thePV andPV pins  
IN1  
IN2  
must each be connected to a low ESR bypass capacitor  
with a value of at least 4.7µF. Ceramic capacitors with  
X5R or X7R dielectric are recommended. Each bypass  
capacitor must be located as close as possible to the re-  
spective pin and should connect to the ground plane via  
the shortest route possible.  
3126f  
19  
For more information www.linear.com/LTC3126  
LTC3126  
applicaTions inForMaTion  
of the feedforward capacitor in parallel with the upper  
resistor divider resistor to restore the full bandwidth of  
the feedback loop.  
A reasonable choice for ripple current is ∆I = 1A which  
L
represents 33% of the minimum current limit. The DC cur-  
rent rating of the inductor should be at least equal to the  
maximum load current plus half the ripple current in order  
to prevent core saturation and loss of efficiency during  
operation. To optimize efficiency the inductor should have  
a low DC resistance. As a general guideline, the inductor  
resistance (ESR) should be approximately equal to the  
low side switch resistance (70mΩ) or less.  
Feedforward Resistor  
In applications where there is a long connection between  
the feedback resistor divider and the point at which the  
output voltage is sensed, it is recommended that a 10k  
feedforward resistor (R ) be added in series with the  
FF  
feedforward capacitor as shown in Figure 7 below. The  
High values of inductor ripple current will reduce the out-  
put current capability of the converter since higher ripple  
increases the peak switch current and will therefore trip  
the current limit at a lighter load current. The maximum  
output current is equal to the current limit minus half the  
peak-to-peak ripple current as shown in the following  
feedforward resistor prevents high frequency noise on  
the V  
trace from coupling into the sensitive FB node.  
OUT  
The addition of a 10k feedforward resistor will have little  
impact on the frequency response of the control loop  
since the divider pole location is dominated by the values  
of resistors R  
and R  
.
equation where I  
is the threshold of the high side  
TOP  
BOT  
LIMIT  
switch current limit:  
V
OUT  
R
∆IL  
2
FF  
R
R
10k  
IOUT(MAX) =ILIMIT  
–
TOP  
LTC3126  
FB  
C
FF  
In addition, there is a minimum inductor value required  
to maintain stability of the current loop as determined by  
the fixed internal slope compensation. Specifically, if the  
buck converter is going to be utilized at duty cycles over  
50%, the inductance value must be at least equal to L  
as given by the following equation:  
GND  
BOT  
3126 F07  
Figure 7. Feedforward Resistor (RFF) for Improved  
Noise Robustness  
MIN  
Inductor Selection  
MHz VOUT  
fSW 2V  
LMIN  
=
•
µH  
The choice of inductor value influences both the efficiency  
and the magnitude of the output voltage ripple. Larger  
inductance values will reduce inductor current ripple and  
will therefore lead to lower output voltage ripple. For a  
fixedDCresistance,alargervalueinductorwillyieldhigher  
efficiency via reduced RMS and core losses. However, a  
largerinductorwithinagiveninductorfamilywillgenerally  
have a greater series resistance, thereby counteracting  
thisefficiencyadvantage. Thepeak-to-peakcurrentripple,  
To ensure sufficient slope compensation if the external  
synchronization feature is being used, the inductor must  
be sized for the lowest possible switching frequency the  
part will experience which is determined by the internal  
oscillator frequency.  
PGOOD Output  
∆I , given by the following equation will be largest at the  
highest input voltage experienced in the application.  
L
The open-drain PGOOD output is driven low whenever FB  
is more than +9.8%/–8.7% (typical) from the FB reference  
voltage. The PGOOD output is also driven low whenever  
the buck converter is disabled. The maximum voltage that  
can be applied to the PGOOD output is 5.5V. The PGOOD  
comparatorhasadeglitchingdelayofapproximately200µs.  
VOUT  
fSW •L  
VOUT  
∆IL =  
1–  
V
IN  
3126f  
20  
For more information www.linear.com/LTC3126  
LTC3126  
applicaTions inForMaTion  
V
Regulators and Bootstrapping with EXTV  
consideration must be given to the thermal environment  
of the IC. This is even more important in applications that  
function over an extended ambient temperature range.  
CC  
CC  
The V rail powers the internal control circuitry and  
CC  
power device gate drivers of the LTC3126. Two internal  
lowdropoutlinearregulatorsprovidetheabilitytogenerate  
Specifically, the exposed die attach pad of both the QFN  
and TSSOP packages must be soldered to the PC board  
and the PC board should be designed to maximize the  
conduction of heat out of the IC package. This can be  
accomplished by utilizing multiple vias from the die attach  
padconnectiontootherPCBlayerscontainingalargearea  
of exposed copper.  
this rail from either V or V . When the IC is disabled  
IN1  
IN2  
(ENA low) the V rail is powered by the higher voltage  
CC  
input, V or V , regardless of the state of the V ,  
IN1  
IN2  
SET1  
V
and DIODE pins. When the IC is enabled, the input  
SET2  
voltage comparators on the V  
and V  
pins become  
SET1  
SET2  
active and the V rail will be powered by the active chan-  
CC  
nel. In ideal diode mode (DIODE high) the active channel  
If the die temperature exceeds approximately 170°C, the  
IC will enter overtemperature shutdown and all switching  
will be inhibited. The part will remain disabled until the  
die cools by approximately 10°C. The soft-start circuit is  
re-initialized in overtemperature shutdown to provide a  
smooth recovery when the fault condition is removed.  
is the valid input with the higher voltage. In priority mode  
(DIODE low) the active channel is V if V is valid or  
IN1  
IN1  
V
IN2  
otherwise (assuming it is valid). If both V and V  
IN1 IN2  
are in UVLO then the higher voltage input will be utilized  
to power the V rail.  
CC  
A third linear regulator allows the V rail to be powered  
CC  
PCB Layout Guidelines  
via the EXTV pin which can be connected to the buck  
CC  
converter output or an auxiliary rail with a voltage above  
The LTC3126 buck converter switches large currents at  
high frequencies. Special attention must be paid to the PC  
board layout to ensure a stable, noise-free and efficient  
application circuit. Figures 6 and 7 show representative  
PC board layouts for each package option to outline some  
of the primary considerations. A few key guidelines are  
listed below.  
3.15V. When operating at high input voltages, the losses  
in the V regulator powered from the input voltage can  
CC  
become a significant factor in conversion efficiency and  
canevenbecomeasubstantialsourceofpowerdissipation.  
A significant performance improvement can be obtained  
by connecting the EXTV input to the buck converter  
CC  
output so that the gate drive current is provided through  
the high efficiency buck converter rather than the less  
efficient linear regulator. This is of particular benefit at  
higher input voltages, lower output voltages and higher  
1. Theparasiticinductanceandresistanceofallcirculating  
high current paths should be minimized. This can be  
accomplished by keeping the routes to the inductor,  
output capacitor and PV  
bypass capacitors as  
IN1/2  
switching frequencies. The EXTV pin is only utilized to  
CC  
short and as wide as possible. Capacitor ground con-  
nections should via down to the ground plane by way  
of the shortest route possible. The bypass capacitors  
power the V rail when the buck converter is operating.  
CC  
Thermal Considerations  
on PV , PV and V should be placed as close to  
IN1  
IN2  
CC  
The LTC3126 is designed to operate continuously up to  
its full rated 2.5A output current. However, when operat-  
ing at high current levels there will be significant heat  
generated within the IC. In addition, in many applications  
theICaspossibleandshouldhavetheshortestpossible  
return paths to ground.  
2. The exposed pad in both packages provides one of the  
primary paths for heat generated within the package.  
The IC must be soldered down to the backpad and the  
backpad area should be filled with vias connecting it  
to the ground plane.  
the V regulator is operated with large input-to-output  
CC  
voltage differential resulting in significant levels of power  
dissipation in its pass element which can add significantly  
to the total power dissipated within the IC. To ensure full  
output current capability and optimal efficiency, careful  
3126f  
21  
For more information www.linear.com/LTC3126  
LTC3126  
applicaTions inForMaTion  
3. There should be an uninterrupted ground plane under  
the entire converter in order to minimize the cross-  
sectional area of the high frequency current loops.  
This minimizes EMI and reduces the inductive drops  
in these loops thereby minimizing SW pin overshoot  
and ringing.  
6. Keep the routes connecting to the high impedance  
noise sensitive inputs (FB, RT, V , V ) as short  
SET1 SET2  
as possible to minimize noise pickup.  
7. The BST1/BST2 pins transition at the switching fre-  
quency to the full input voltage. To minimize radiated  
noise and coupling, keep the routes connecting to the  
boost capacitors as short as possible and keep these  
routes away from all sensitive circuitry and pins (FB,  
4. Connections to the PV , PV and SW pins should  
IN1  
IN2  
be made as wide as possible to reduce the series im-  
pedance. This will improve efficiency and reduce the  
thermal resistance.  
RT, V  
, V  
).  
SET1 SET2  
8. The connection to the V  
pin (Pin 25) should be  
IN1  
5. To preventlargecirculatingcurrentsinthegroundplane  
from disrupting operation of the part, all small-signal  
groundsshouldeitherreturndirectlytothesmall-signal  
ground pin (GND) or via down to the ground plane  
close to the GND pin and not near the power stage  
components. This includes the ground connections for  
separate from the connection to the PV (Pin 24) and  
IN1  
shouldhaveaseparate0.1µFbypasscapacitor.Thiswill  
prevent noise from the PV trace from being coupled  
IN1  
into the sensitive V pin.  
IN1  
the R resistor, the FB resistor divider and the V  
T
SET1  
and V  
resistor dividers.  
SET2  
V
IN1  
V
IN2  
V
IN1  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
V
IN2  
2
3
28 27 26 25 24 23  
1
2
3
4
5
6
7
8
22  
21  
20  
19  
18  
17  
16  
15  
4
5
6
7
8
CONNECT  
TO  
OUT  
9
V
10  
11  
12  
13  
14  
V
OUT  
9
10 11 12 13 14  
V
OUT  
CONNECT  
TO  
V
OUT  
V
IN2  
V
IN2  
3126 F08  
3126 F09  
ALL COMPONENTS DISPLAYED  
ABOVE SHOULD BE PLACED AS  
CLOSE TO THE IC AS POSSIBLE  
VIA TO GROUND PLANE  
ALL COMPONENTS DISPLAYED  
ABOVE SHOULD BE PLACED AS  
CLOSE TO THE IC AS POSSIBLE  
VIA TO GROUND PLANE  
OUTLINE OF UNINTERRUPTED  
GROUND PLANE  
OUTLINE OF UNINTERRUPTED  
GROUND PLANE  
Figure 8. Recommended PC Board Layout for QFN Package  
Figure 9. Recommended PC Board Layout for TSSOP Package  
3126f  
22  
For more information www.linear.com/LTC3126  
LTC3126  
Typical applicaTions  
12V, 1MHz Step-Down Converter with Dual Inputs  
12V, 2MHz Step-Down Converter with Dual Inputs  
0.1µF  
0.1µF  
0.1µF  
0.1µF  
BST2 COM2 BST1 COM1  
BST2 COM2 BST1 COM1  
L1  
L1  
13.1V TO 42V  
13.1V TO 42V  
V
6.8µH  
13.1V TO 42V  
13.1V TO 42V  
V
4.7µH  
IN1  
V
IN1  
V
OUT  
OUT  
12V  
4.7µF  
4.7µF  
4.7µF  
4.7µF  
PV  
IN1  
SW  
CC  
PV  
IN1  
SW  
CC  
12V  
C
22µF  
×2  
2.5A  
C
2.5A  
EXTV  
EXTV  
OUT  
OUT  
33µF  
V
V
IN2  
IN2  
1M  
1M  
22pF  
12pF  
PV  
PV  
IN2  
IN2  
FB  
RT  
FB  
RT  
PV  
V
PV  
V
CC  
CC  
ENA  
CC  
CC  
ENA  
73.2k  
73.2k  
LTC3126  
LTC3126  
33.2k  
16.5k  
4.7µF  
4.7µF  
V
V
REF  
REF  
PRIORITY  
VALID1  
VALID2  
PGOOD  
L1: COILCRAFT XAL4030  
C
PRIORITY  
VALID1  
VALID2  
PGOOD  
L1: COILCRAFT XAL4030  
V
V
: TDK C4532X7R1E226M250KC  
V
V
C
: CHEMI-CON KTS250B366M55N0B00  
OUT  
SET1  
SET2  
OUT  
SET1  
SET2  
94% EFFICIENCY, V = 24V, 1A LOAD  
92% EFFICIENCY, V = 24V, 1.5A LOAD  
IN  
IN  
IN  
PWM/SYNC  
DIODE  
PWM/SYNC  
DIODE  
92% EFFICIENCY, V = 36V, 2A LOAD  
89% EFFICIENCY, V = 36V, 1.5A LOAD  
IN  
10µA NO LOAD I AT V = 24V  
GND PGND  
GND PGND  
11µA NO LOAD I AT V = 24V  
Q
IN  
Q
IN  
3126 TA03  
3126 TA04  
450mV DROPOUT AT 1A LOAD  
1.05V DROPOUT AT 2.5A LOAD  
0.6V DROPOUT AT 1A LOAD  
1.1V DROPOUT AT 2.5A LOAD  
5V, 750kHz Step-Down Converter with Dual Inputs  
5V, 2MHz Step-Down Converter with Dual Inputs  
0.1µF  
0.1µF  
0.1µF  
0.1µF  
BST2 COM2 BST1 COM1  
BST2 COM2 BST1 COM1  
L1  
L1  
6V TO 42V  
6V TO 42V  
V
4.7µH  
6V TO 42V  
6V TO 42V  
V
3.3µH  
IN1  
V
IN1  
V
OUT  
5V  
OUT  
4.7µF  
4.7µF  
4.7µF  
4.7µF  
PV  
IN1  
SW  
CC  
PV  
IN1  
SW  
CC  
5V  
C
47µF  
×2  
2.5A  
C
22µF  
×2  
2.5A  
EXTV  
EXTV  
OUT  
OUT  
V
V
IN2  
IN2  
1M  
1M  
33pF  
10pF  
PV  
PV  
IN2  
IN2  
FB  
RT  
FB  
RT  
PV  
V
PV  
V
CC  
CC  
ENA  
CC  
CC  
ENA  
196k  
196k  
LTC3126  
LTC3126  
44.2k  
16.5k  
4.7µF  
4.7µF  
V
V
REF  
REF  
PRIORITY  
VALID1  
VALID2  
PGOOD  
L1: COILCRAFT XAL4030  
C
PRIORITY  
VALID1  
VALID2  
PGOOD  
L1: TOKO FDSD0518  
C
V
V
: MURATA GRM43ER61A476KE19L  
V
V
: MURATA GRM43ER71A226KE01L  
OUT  
SET1  
SET2  
OUT  
SET1  
SET2  
93% EFFICIENCY, V = 12V, 1A LOAD  
91% EFFICIENCY, V = 12V, 1A LOAD  
IN  
IN  
IN  
PWM/SYNC  
DIODE  
PWM/SYNC  
DIODE  
90% EFFICIENCY, V = 24V, 1.5A LOAD  
87% EFFICIENCY, V = 24V, 1.5A LOAD  
IN  
3µA NO LOAD I AT V = 24V  
GND PGND  
GND PGND  
3µA NO LOAD I AT V = 24V  
Q
IN  
Q
IN  
3126 TA05  
3126 TA06  
330mV DROPOUT AT 1A LOAD  
850mV DROPOUT AT 2.5A LOAD  
390mV DROPOUT AT 1A LOAD  
680mV DROPOUT AT 2A LOAD  
3126f  
23  
For more information www.linear.com/LTC3126  
LTC3126  
Typical applicaTions  
3.3V, 750kHz Step-Down Converter with Dual Inputs  
3.3V, 2MHz Step-Down Converter with Dual Inputs  
0.1µF  
0.1µF  
0.1µF  
0.1µF  
BST2 COM2 BST1 COM1  
BST2 COM2 BST1 COM1  
L1  
L1  
4.3V TO 25V  
4.2V TO 42V  
4.2V TO 42V  
V
4.7µH  
V
3.3µH  
IN1  
V
3.3V  
2.5A  
IN1  
V
3.3V  
2.5A  
OUT  
OUT  
42V TRANSIENT*  
4.7µF  
4.7µF  
4.7µF  
4.7µF  
PV  
IN1  
SW  
CC  
PV  
IN1  
SW  
CC  
C
OUT  
47µF  
C
22µF  
×2  
EXTV  
EXTV  
OUT  
4.3V TO 25V  
42V TRANSIENT*  
V
V
IN2  
IN2  
909k  
301k  
909k  
301k  
10pF  
15pF  
PV  
PV  
IN2  
IN2  
FB  
RT  
FB  
RT  
PV  
V
PV  
V
CC  
CC  
ENA  
CC  
CC  
ENA  
LTC3126  
LTC3126  
44.2k  
L1: COILCRAFT XAL4030  
16.5k  
4.7µF  
4.7µF  
V
V
REF  
REF  
PRIORITY  
VALID1  
VALID2  
PGOOD  
PRIORITY  
VALID1  
VALID2  
PGOOD  
L1: TOKO FDSD0518  
V
V
V
V
C
: MURATA GRM43ER71A226KE01L  
SET1  
SET2  
SET1  
SET2  
OUT  
91% EFFICIENCY, V = 12V, 1A LOAD  
88% EFFICIENCY, V = 12V, 1A LOAD  
IN  
IN  
IN  
PWM/SYNC  
DIODE  
PWM/SYNC  
DIODE  
87% EFFICIENCY, V = 24V, 1A LOAD  
80% EFFICIENCY, V = 24V, 1A LOAD  
IN  
4µA NO LOAD I AT V = 24V  
GND PGND  
GND PGND  
2µA NO LOAD I AT V = 24V  
Q
IN  
Q
IN  
3126 TA07  
3126 TA08  
330mV DROPOUT AT 1A LOAD  
660mV DROPOUT AT 2A LOAD  
400mV DROPOUT AT 1A LOAD  
750mV DROPOUT AT 2A LOAD  
1.8V, 750kHz Step-Down Converter with Dual Inputs  
1.8V, 2MHz Step-Down Converter with Dual Inputs  
0.1µF  
0.1µF  
0.1µF  
0.1µF  
BST2 COM2 BST1 COM1  
BST2 COM2 BST1 COM1  
L1  
L1  
2.4V TO 36V  
2.4V TO 14V  
V
3.3µH  
V
2.2µH  
IN1  
V
1.8V  
2.5A  
IN1  
V
1.8V  
2.5A  
OUT  
OUT  
42V TRANSIENT*  
42V TRANSIENT*  
4.7µF  
4.7µF  
4.7µF  
4.7µF  
PV  
IN1  
SW  
CC  
PV  
IN1  
SW  
CC  
C
C
OUT  
100µF  
×2  
EXTV  
EXTV  
OUT  
2.4V TO 36V  
42V TRANSIENT*  
2.4V TO 14V  
42V TRANSIENT*  
100µF  
×2  
V
V
IN2  
IN2  
280k  
232k  
280k  
232k  
68pF  
82pF  
PV  
PV  
IN2  
IN2  
FB  
RT  
FB  
RT  
PV  
V
PV  
V
CC  
CC  
ENA  
CC  
CC  
ENA  
LTC3126  
LTC3126  
44.2k  
16.5k  
4.7µF  
4.7µF  
V
V
REF  
REF  
PRIORITY  
VALID1  
VALID2  
PGOOD  
L1: COILCRAFT XAL4030  
PRIORITY  
VALID1  
VALID2  
PGOOD  
L1: TOKO FDSD0518  
V
V
C
: AVX 12106D107KAT2A  
V
V
C
: AVX 12106D107KAT2A  
OUT  
SET1  
SET2  
OUT  
SET1  
SET2  
86% EFFICIENCY, V = 12V, 1A LOAD  
87% EFFICIENCY, V = 5V, 1A LOAD  
IN  
79% EFFICIENCY, V = 24V, 1.5A LOAD  
IN  
80% EFFICIENCY, V = 12V, 1A LOAD  
PWM/SYNC  
DIODE  
PWM/SYNC  
DIODE  
IN  
5µA NO LOAD I AT V = 24V  
IN  
5µA NO LOAD I AT V = 12V  
GND PGND  
GND PGND  
Q
IN  
Q
IN  
3126 TA09  
3126 TA10  
*The step-down converter can operate over the specified input voltage range without any pulse skipping for loads from 250mA to 2.5A. However, in all  
applications, the converter can operate from an input voltage as high as 42V, but pulse skipping may occur if operated above the specified voltage range.  
Pulse skipping is not detrimental to the IC, but can result in significant output voltage ripple and is therefore generally avoided while in nominal operating  
conditions.  
3126f  
24  
For more information www.linear.com/LTC3126  
LTC3126  
Typical applicaTions  
Automotive and Photovoltaic Powered 5V USB Supply  
0.1µF  
0.1µF  
BST2 COM2 BST1 COM1  
L1  
AUTOMOTIVE  
12V NOMINAL  
8V TO 40V  
4.7µH  
V
IN2  
V
OUT  
4.7µF  
22µF  
PV  
IN2  
5V  
SW  
CC  
C
2.5A  
EXTV  
OUT  
47µF  
V
IN1  
976k  
191k  
10pF  
PV  
IN1  
+
FB  
PV  
CC  
ENA  
CC  
LTC3126  
4.7µF  
309k  
18V  
V
+
PHOTOVOLTAIC  
PANEL  
V
PRIORITY  
VALID1  
VALID2  
PGOOD  
RT  
REF  
SET1  
SET2  
V
V
+
432k  
PWM/SYNC  
DIODE  
33.2k  
GND  
PGND  
499k  
3126 TA11a  
f
V
V
= 1MHz  
L1: COILCRAFT XAL4030  
SW  
UVLO THRESHOLD = 15V  
UVLO THRESHOLD = 8V  
IN1  
IN2  
Efficiency, VIN = 12V  
100  
Burst Mode OPERATION  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
PWM Mode  
0.001  
0.01  
0.1  
1
4
LOAD CURRENT (A)  
3126 TA11b  
Photovoltaic Panel Disconnect  
(Switch to Automotive Input)  
Load Step, 250mA to 2.5A  
V
V
V
IN1  
IN1, IN2  
5V/DIV  
V
OUT  
V
IN2  
200mV/DIV  
V
OUT  
200mV/DIV  
INDUCTOR  
CURRENT  
1A/DIV  
INDUCTOR CURRENT  
2A/DIV  
I
IN2  
2A/DIV  
3126 TA11c  
3126 TA11d  
50µs/DIV  
50µs/DIV  
V
= 18V  
V
V
= 18V  
= 12.8V  
IN  
IN1  
IN2  
2.5A LOAD  
3126f  
25  
For more information www.linear.com/LTC3126  
LTC3126  
Typical applicaTions  
5V, 2A Supply from Wall Adapter and Lead-Acid Backup Battery  
0.1µF  
0.1µF  
BST2 COM2 BST1 COM1  
L1  
12V WALL  
ADAPTER INPUT  
V
4.7µH  
IN1  
V
OUT  
+
4.7µF  
4.7µF  
PV  
IN1  
5V  
SW  
CC  
47µF  
47µF 2A  
EXTV  
ELECT  
V
IN2  
+
976k  
191k  
10pF  
12V  
SEALED  
PV  
IN2  
FB  
LEAD-ACID  
PV  
CC  
ENA  
CC  
LTC3126  
V
4.7µF  
V
REF  
499k  
V
V
SET1  
SET2  
PRIORITY  
VALID1  
VALID2  
PGOOD  
RT  
499k  
PWM/SYNC  
DIODE  
33.2k  
GND  
PGND  
3126 TA12a  
f
= 1MHz  
L1: COILCRAFT XAL5030  
SW  
Efficiency, VIN = 12V  
Load Step, 200mA to 2A  
100  
Burst Mode OPERATION  
90  
V
OUT  
200mV/DIV  
80  
70  
60  
50  
INDUCTOR CURRENT  
1A/DIV  
40  
PWM Mode  
3126 TA12c  
50µs/DIV  
30  
20  
10  
0
V
= 12V  
IN1  
0.0001  
0.001  
0.01  
0.1  
1
4
LOAD CURRENT (A)  
3126 TA12b  
Wall Adapter Plug-In Transient  
Wall Adapter Disconnect Transient  
V
IN2  
V
V
V
V
IN1, IN2  
IN1, IN2  
V
5V/DIV  
5V/DIV  
IN1  
V
IN2  
V
IN1  
V
V
OUT  
OUT  
200mV/DIV  
200mV/DIV  
I
I
IN1  
IN1  
1A/DIV  
1A/DIV  
INDUCTOR CURRENT  
2A/DIV  
INDUCTOR CURRENT  
2A/DIV  
3126 TA12d  
3126 TA12e  
20µs/DIV  
50µs/DIV  
2A LOAD  
2A LOAD  
3126f  
26  
For more information www.linear.com/LTC3126  
LTC3126  
Typical applicaTions  
3.3V/2.5A Supply from 24V Wall Adapter and Lead-Acid Battery  
0.1µF  
0.1µF  
BST2 COM2 BST1 COM1  
L1  
4.7µH  
24V  
V
IN1  
V
3.3V  
2.5A  
OUT  
WALL ADAPTER  
4.7µF  
PV  
IN1  
SW  
CC  
C
47µF  
×2  
EXTV  
OUT  
V
PV  
IN2  
+
12V  
LEAD-ACID  
1.13M  
374k  
12pF  
4.7µF  
4.7µF  
IN2  
FB  
PV  
CC  
CC  
LTC3126  
V
ENA  
PWM/SYNC  
PRIORITY  
VALID1  
VALID2  
PGOOD  
RT  
V
REF  
SET1  
SET2  
V
V
33.2k  
499k  
DIODE  
GND  
PGND  
3126 TA13a  
499k  
f
= 1MHz  
UVLO THRESHOLD = 20V  
UVLO THRESHOLD = 10V  
L1: WURTH 744 778 9004  
SW  
V
V
IN1  
IN2  
Load Step, 250mA to 2.5A  
Soft-Start  
ENA  
V
OUT  
2V/DIV  
200mV/DIV  
V
OUT  
2V/DIV  
PGOOD  
5V/DIV  
INDUCTOR CURRENT  
1A/DIV  
INDUCTOR CURRENT  
1A/DIV  
3126 TA13b  
3126 TA13c  
100µs/DIV  
2ms/DIV  
V
= 24V  
IN  
Wall Adapter Plug-In Transient  
Wall Adapter Disconnect Transient  
V
IN1  
V
IN1  
V
V
V
V
IN1, IN2  
IN1, IN2  
10V/DIV  
10V/DIV  
V
IN2  
V
IN2  
V
V
OUT  
OUT  
200mV/DIV  
200mV/DIV  
I
I
IN1  
IN1  
1A/DIV  
1A/DIV  
INDUCTOR CURRENT  
2A/DIV  
INDUCTOR CURRENT  
2A/DIV  
3126 TA13d  
3126 TA13e  
50µs/DIV  
50µs/DIV  
3126f  
27  
For more information www.linear.com/LTC3126  
LTC3126  
package DescripTion  
Please refer to http://www.linear.com/product/LTC3126#packaging for the most recent package drawings.  
UFD Package  
28-Lead Plastic QFN (4mm × 5mm)  
(Reference LTC DWG # 05-08-1712 Rev C)  
0.70 ±0.05  
4.50 ±0.05  
3.10 ±0.05  
2.50 REF  
2.65 ±0.05  
3.65 ±0.05  
PACKAGE OUTLINE  
0.25 ±0.05  
0.50 BSC  
3.50 REF  
4.10 ±0.05  
5.50 ±0.05  
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS  
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED  
PIN 1 NOTCH  
R = 0.20 OR 0.35  
× 45° CHAMFER  
2.50 REF  
R = 0.115  
TYP  
R = 0.05  
TYP  
0.75 ±0.05  
4.00 ±0.10  
(2 SIDES)  
27  
28  
0.40 ±0.10  
PIN 1  
TOP MARK  
(NOTE 6)  
1
2
5.00 ±0.10  
(2 SIDES)  
3.50 REF  
3.65 ±0.10  
2.65 ±0.10  
(UFD28) QFN 0816 REV C  
0.25 ±0.05  
0.200 REF  
0.50 BSC  
0.00 – 0.05  
BOTTOM VIEW—EXPOSED PAD  
NOTE:  
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3).  
2. DRAWING NOT TO SCALE  
3. ALL DIMENSIONS ARE IN MILLIMETERS  
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE  
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE  
5. EXPOSED PAD SHALL BE SOLDER PLATED  
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION  
ON THE TOP AND BOTTOM OF PACKAGE  
3126f  
28  
For more information www.linear.com/LTC3126  
LTC3126  
package DescripTion  
Please refer to http://www.linear.com/product/LTC3126#packaging for the most recent package drawings.  
FE Package  
28-Lead Plastic TSSOP (4.4mm)  
(Reference LTC DWG # 05-08-1663 Rev K)  
Exposed Pad Variation EB  
9.60 – 9.80*  
(.378 – .386)  
4.75  
(.187)  
4.75  
(.187)  
28 27 26 2524 23 22 21 20 1918 17 16 15  
2.74  
(.108)  
EXPOSED  
PAD HEAT SINK  
ON BOTTOM OF  
PACKAGE  
6.60 0.10  
4.50 0.10  
SEE NOTE 4  
6.40  
2.74  
(.252)  
(.108)  
BSC  
0.45 0.05  
1.05 0.10  
0.65 BSC  
RECOMMENDED SOLDER PAD LAYOUT  
5
7
1
2
3
4
6
8
9 10 12 13 14  
11  
1.20  
(.047)  
MAX  
4.30 – 4.50*  
(.169 – .177)  
0.25  
REF  
0° – 8°  
0.65  
(.0256)  
BSC  
0.09 – 0.20  
(.0035 – .0079)  
0.50 – 0.75  
(.020 – .030)  
0.05 – 0.15  
(.002 – .006)  
0.195 – 0.30  
FE28 (EB) TSSOP REV K 0913  
(.0077 – .0118)  
TYP  
NOTE:  
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE  
2. DIMENSIONS ARE IN  
FOR EXPOSED PAD ATTACHMENT  
MILLIMETERS  
(INCHES)  
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH  
SHALL NOT EXCEED 0.150mm (.006") PER SIDE  
3. DRAWING NOT TO SCALE  
3126f  
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.  
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-  
29  
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.  
LTC3126  
Typical applicaTion  
3.3V Supply with 200ms Transient Ride-Through Capability  
0.1µF  
0.1µF  
BST2 COM2 BST1 COM1  
L2  
12V  
INPUT RAIL  
4.7µH  
V
IN1  
V
3.3V  
2A  
OUT  
4.7µF  
4.7µF  
L1  
PV  
IN1  
SW  
CC  
D1  
10µH  
0.1Ω  
EXTV  
47µF  
35V  
V
IN2  
1.13M  
374k  
10pF  
1000µF  
50V  
+
4.7µF  
PV  
IN2  
FB  
ISN  
ISP  
SW  
FB  
PV  
CC  
V
887k  
ELECT  
LTC3126  
×3  
CC  
ENA  
LT1618  
V
CC  
33.2k  
4.7µF  
V
SHDN  
CC  
V
IN  
100k 100k 100k  
V
REF  
499k  
4.7µF  
PRIORITY  
VALID1  
VALID2  
PGOOD  
RT  
I
V
C
GND  
10nF  
ADJ  
V
V
SET1  
SET2  
249k  
249k  
33.2k  
PWM/SYNC  
DIODE  
2k  
D1: MBR0530  
GND  
PGND  
L1: SUMIDA CR43-100  
f
= 1MHz  
SW  
L2: BOURNS SRN5020-4R7M  
3126 TA02a  
VOUT Hold-Up with Loss of  
Input Supply  
Transient Ride-Through  
Power-Up Waveforms  
V
IN1  
V
V
IN1  
IN2  
10V/DIV  
10V/DIV  
10V/DIV  
V
IN2  
V
V
IN2  
IN1  
20V/DIV  
10V/DIV  
10V/DIV  
V
V
OUT  
OUT  
2V/DIV  
V
2V/DIV  
OUT  
2V/DIV  
I
I
IN2  
IN1  
2A/DIV  
500mA/DIV  
3126 TA02b  
3126 TA02c  
3126 TA02d  
100ms/DIV  
50ms/DIV  
100ms/DIV  
relaTeD parTs  
PART NUMBER  
DESCRIPTION  
COMMENTS  
V : 3V to 42V, I = 2.5μA, I = 1μA, MSOP-10E Package  
LT®8609  
42V, 2A (3A Peak) 2MHz Synchronous Step-Down  
Regulator with I = 2.5µA  
IN  
Q
SD  
Q
LTC3118  
18V, 2A Buck-Boost DC/DC Converter with Low Loss  
Dual Input PowerPath  
V : 2.2V to 18V, I = 50μA, I = 2μA, TSSOP-28, QFN-24 Packages  
IN Q SD  
LT8610  
42V, 2.5A Synchronous Step-Down Regulator  
Prioritized PowerPath Controller  
V : 3.4V to 42V, I = 2.5μA, I = 1μA, MSOP-16 Package  
IN Q SD  
LTC4417  
Controller for External P-Channel MOSFETs, Three Channels,  
V : 2.5V to 36V, I = 28μA, SSOP-24, QFN-24 Packages  
IN  
Q
LTC3114-1  
LTC3115-1  
40V, 1A Synchronous 4-Switch Monolithic Buck-Boost  
DC/DC Converter  
V : 2.2V to 40V, V : 2.7V to 40V, I = 30μA, I = 3μA,  
IN OUT Q SD  
TSSOP-16, DFN-16 Packages  
40V, 2A Synchronous 4-Switch Monolithic Buck-Boost  
DC/DC Converter  
V : 2.7V to 40V, V : 2.7V to 40V, I = 30μA, I = 3μA,  
IN  
OUT  
Q
SD  
TSSOP-20, DFN-16 Packages  
3126f  
LT 0916 • PRINTED IN USA  
LinearTechnology Corporation  
1630 McCarthy Blvd., Milpitas, CA 95035-7417  
30  
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3126  
●
●
© LINEAR TECHNOLOGY CORPORATION 2016  

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