LTC3411AIMS-PBF [Linear]
1.25A, 4MHz, Synchronous Step-Down DC/DC Converter; 1.25A ，为4MHz ，同步降压型DC / DC转换器
| 型号： | LTC3411AIMS-PBF |
| 厂家： | 
Linear |
| 描述： | 1.25A, 4MHz, Synchronous Step-Down DC/DC Converter |
| 文件： | 总20页 (文件大小：620K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3411A
1.25A, 4MHz, Synchronous
Step-Down DC/DC Converter
FEATURES
DESCRIPTION
The LTC®3411A is a constant frequency, synchronous
step-down DC/DC converter. Intended for medium power
applications, it operates from a 2.5V to 5.5V input voltage
range and has a user configurable operating frequency
up to 4MHz, allowing the use of tiny, low cost capacitors
and inductors 1mm or less in height. The output voltage is
adjustablefrom0.8Vto5.5V. Internalsynchronouspower
switches provide high efficiency. The LTC3411A’s current
mode architecture and external compensation allow the
transient response to be optimized over a wide range of
loads and output capacitors.
■
Uses Tiny Capacitors and Inductor
■
High Frequency Operation: Up to 4MHz
■
Low R
Internal Switches: 0.15Ω
DS(ON)
■
■
High Efficiency: Up to 96%
Selectable Low Ripple (25mV ) Burst Mode®
Operation: I = 40μA
P-P
Q
■
■
Stable with Ceramic Capacitors
Current Mode Operation for Excellent Line
and Load Transient Response
■
■
■
■
■
■
■
Short-Circuit Protected
Low Dropout Operation: 100% Duty Cycle
Low Shutdown Current: I ≤ 1μA
Q
The LTC3411A can be configured for automatic power
saving Burst Mode operation (I = 40μA) to reduce gate
charge losses when the load current drops below the level
required for continuous operation. For reduced noise and
RF interference, the SYNC/MODE pin can be configured to
skip pulses or provide forced continuous operation.
Output Voltages from 0.8V to 5V
Q
Synchronizable to External Clock
Supports Pre-Biased Outputs
Small 10-Lead 3mm × 3mm DFN or MSOP Package
APPLICATIONS
To further maximize battery life, the P-channel MOSFET
is turned on continuously in dropout (100% duty cycle).
In shutdown, the device draws <1μA.
L, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners. Protected by
U.S. Patents including 5481178, 6580258, 6498466, 6611131.
■
Notebook Computers
■
Digital Cameras
■
Cellular Phones
Handheld Instruments
Board Mounted Power Supplies
■
■
TYPICAL APPLICATION
Efficiency and Power Loss vs Output Current
Step-Down 2.5V/1.25A Regulator
100
90
80
70
60
50
40
30
20
10
0
1
V
IN
2.5V TO 5.5V
10μF
0.1
SYNC
SYNC/MODE
PGOOD
PV
SV
IN
IN
2.2μH
22pF
V
OUT
0.01
0.001
SW
2.5V
LTC3411A
1.25A
I
22μF
TH
SHDN/R
V
V
V
= 2.7V
= 3.6V
= 4.2V
887k
IN
IN
IN
V
FB
T
12.1k
680pF
SGND
PGND
0.0001
10000
549k
412k
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
3411a TA01a
f
= 1MHz
O
3411A TA01b
Burst Mode OPERATION
3411afa
1
LTC3411A
ABSOLUTE MAXIMUM RATINGS (Note 1)
PV , SV Voltages ..................................... –0.3V to 6V
Operating Junction Temperature Range
IN
IN
V , I , SHDN/R Voltages ..........–0.3V to (V + 0.3V)
(Notes 2, 5, 8)........................................ –40°C to 125°C
Storage Temperature Range................... –65°C to 125°C
Lead Temperatu re (Soldering, 10 sec) ............... 300°C
FB TH
T
IN
SYNC/MODE Voltage .....................–0.3V to (V + 0.3V)
IN
SW Voltage ..................................–0.3V to (V + 0.3V)
IN
PGOOD Voltage ........................................... –0.3V to 6V
PIN CONFIGURATION
TOP VIEW
TOP VIEW
SHDN/R
1
2
3
4
5
10
9
I
TH
T
SHDN/R
SYNC/MODE
SGND
1
2
3
4
5
10
9
I
TH
SYNC/MODE
SGND
V
FB
T
V
FB
11
8
PGOOD
8
PGOOD
SW
7
SV
IN
SW
PGND
7
6
SV
IN
PV
IN
PGND
6
PV
IN
MS PACKAGE
10-LEAD PLASTIC MSOP
= 125°C, θ = 120°C/W, θ = 10°C/W
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
T
JMAX
JA
JC
T
= 125°C, θ = 43°C/W, θ = 3°C/W
JMAX
JA JC
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
LTC3411AEDD#PBF
LTC3411AIDD#PBF
LTC3411AEMS#PBF
LTC3411AIMS#PBF
TAPE AND REEL
PART MARKING*
LAJM
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
LTC3411AEDD#TRPBF
LTC3411AIDD#TRPBF
LTC3411AEMS#TRPBF
LTC3411AIMS#TRPBF
10-Lead (3mm × 3mm) Plastic DFN
10-Lead (3mm × 3mm) Plastic DFN
10-Lead Plastic MSOP
LAJM
–40°C to 125°C
LTAJK
–40°C to 125°C
LTAJK
10-Lead Plastic MSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *Temperature grades are identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 3.6V, RT = 125k unless otherwise specified. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
●
●
●
V
Operating Voltage Range
2.5
5.5
V
IN
I
Feedback Pin Input Current
Feedback Voltage
(Note 3)
(Note 3)
0.1
0.816
0.2
μA
V
FB
V
0.784
0.8
0.04
0.02
300
FB
ΔV
ΔV
Reference Voltage Line Regulation
Output Voltage Load Regulation
Error Amplifier Transconductance
V
= 2.5V to 5.5V
%/V
%
LINEREG
IN
TH
TH
I
I
= 0.55V to 0.9V
0.2
LOADREG
g
Pin Load = 5μA (Note 3)
μS
m(EA)
3411afa
2
LTC3411A
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 3.6V, RT = 125k unless otherwise specified. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Input DC Supply Current (Note 4)
Active Mode
S
V
V
V
= 3.6V, V = 0.75V
330
40
0.1
450
60
1
μA
μA
μA
SYNC/MODE
SYNC/MODE
SHDN/RT
FB
Sleep Mode
= 3.6V, V = 0.84V
FB
Shutdown
= 3.6V
V
Shutdown Threshold High Active
Oscillator Resistor
Oscillator Frequency
V
– 0.6
125k
2.5
V
– 0.4
V
SHDN/RT
IN
IN
1M
Ω
f
R = 125k
(Note 7)
(Note 7)
2.25
2.8
4
4
MHz
MHz
MHz
OSC
T
f
I
Synchronization Frequency
Peak Switch Current Limit
Top Switch On-Resistance
0.4
1.6
SYNC
LIM
V
= 0.5V
2.1
2.6
0.18
A
FB
R
MS Package
DD Package (Note 6)
0.15
0.15
Ω
Ω
DS(ON)
Bottom Switch On-Resistance
Switch Leakage Current
MS Package
0.13
0.13
0.01
0.16
1
Ω
Ω
μA
DD Package (Note 6)
I
V
= 5.5V, V
= 5.5V, V = 0V
SW(LKG)
IN
SHDN/RT
SW
or 5.5V
V
Undervoltage Lockout Threshold
Power Good Threshold
V
Ramping Down
1.8
2.1
2.4
V
UVLO
IN
PGOOD
V
V
Ramping Up from 0.68V to 0.8V
Ramping Down from 0.92V to 0.8V
–5
5
–7
7
%
%
FB
FB
Power Bad Threshold
V
V
Ramping Down from 0.8V to 0.68V
Ramping Up from 0.8V to 0.9V
–10
10
–12
12
%
%
FB
FB
R
Power Good Pull-Down On-Resistance
15
30
Ω
PGOOD
PGOOD Blanking
V
V
Step from 0V to 0.8V
Step from 0.8V to 0V
40
105
μs
μs
FB
FB
V
Pulse Skip
Force Continous
Burst
0.63
IN
V
V
V
SYNC-MODE
0.93
V
– 1.05
V
– 0.75
0.5
IN
t
10% to 90% of Regulation
0.8
1.0
ms
SOFT-START
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 5: T is calculated from the ambient T and power dissipation P
according to the following formulas:
J
A
D
LTC3411AEDD: T = T + (P • 43°C/W)
J
A
D
LTC3411AEMS: T = T + (P • 120°C/W)
J
A
D
Note 2: The LTC3411AE is guaranteed to meet performance specifications
from 0°C to 85°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3411AI is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 6: For the DD package, switch on-resistance is sampled at wafer
level measurements and assured by design, characterization and
correlation with statistical process controls.
Note 7: 4MHz operation is guaranteed by design but not production
tested and is subject to duty cycle limitations (see Applications
Information).
Note 8: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is
active. Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 3: The LTC3411A is tested in a feedback loop which servos V to
FB
the midpoint for the error amplifier (V = 0.7V).
ITH
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
3411afa
3
LTC3411A
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 3.6V, fO = 1MHz, unless
otherwise noted.
Efficiency vs Input Voltage
Efficiency vs Output Current
Efficiency vs Output Current
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
I
= 100mA
I
= 10mA
OUT
OUT
I
= 1.25A
OUT
I
= 1mA
OUT
I
= 0.1mA
5.0
OUT
V
V
V
= 2.7V
= 3.6V
= 4.2V
V
V
V
= 2.7V
= 3.6V
= 4.2V
IN
IN
IN
20
10
0
IN
IN
IN
V
= 1.8V
OUT
V
= 1.8V
1
V
= 1.5V
1
OUT
OUT
4.5
INPUT VOLTAGE(V)
5.5
2.5
3.0
3.5
4.0
0.1
10
100
1000
10000
0.1
10
100
1000
10000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
3411A G02
3411A G03
3411A G01
Efficiency vs Output Current
Efficiency vs Frequency
Load Regulation
95
94
93
92
91
90
89
88
1.00
100
90
80
70
60
50
40
30
20
10
0
Burst Mode
OPERATION
4.7μH
0.75
0.50
PULSE
SKIP
2.2μH
Burst Mode OPERATION
0.25
FORCED CONTINUOUS
PULSE SKIP
0.00
1μH
FORCED CONTINUOUS
= 1.8V
–0.25
–0.50
V
LOAD
= 1.8V
OUT
V
OUT
I
= 400mA
V
= 1.8V
1000
OUT
4
800
1000 1200 1400
0
1
2
3
5
0
200 400 600
0.1
1
10
100
10000
OUTPUT CURRENT (mA)
FREQUENCY (MHz)
OUTPUT CURRENT(mA)
3411A G04
3411A G05
3411A G06
Reference Voltage vs
Temperature
Frequency Variation vs
Temperature
Line Regulation
815
0.6
6
V
= 3.6V
IN
810
805
800
795
790
785
0.4
0.2
4
2
0.0
0
–0.2
–0.4
–0.6
–2
–4
–6
V
= 1.8V
= 400mA
OUT
I
LOAD
50
TEMPERATURE(°C)
–50 –25
0
25
75 100 125
4.5
–50
25
50
75 100 125
2.5
3.0
3.5
4.0
5.0
5.5
–25
0
INPUT VOLTAGE(V)
TEMPERATURE(°C)
3411A G08
3411A G07
3411A G09
3411afa
4
LTC3411A
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 3.6V, fO = 1MHz, unless
otherwise noted.
Frequency Variation vs VIN
RDS(ON) vs Input Voltage
RDS(ON) vs Temperature
0.25
0.20
0.30
0.25
6
4
2
0.20
0.15
0.10
0.15
0.10
0
–2
–4
–6
–8
0.05
0.0
0.05
0.0
MAIN SWITCH
MAIN SWITCH
SYNCHRONOUS SWITCH
SYNCHRONOUS SWITCH
4.5
INPUT VOLTAGE (V)
2.5
3.0
3.5
4.0
5.0
5.5
50
TEMPERATURE (°C)
–50 –25
0
25
75 100 125
4.5
2.5
3.0
3.5
4.0
(V)
5.0
5.5
V
IN
3411A G11
3411A G12
3411A G10
Dynamic Supply Current vs Input
Voltage
Dynamic Supply Current vs
Temperature
Switch Leakage vs Input Voltage
100
10
2500
100
10
FORCED CONTINUOUS
FORCED CONTINUOUS
2000
1500
1000
MAIN SWITCH
1
1
PULSE SKIP
PULSE SKIP
Burst Mode
OPERATION
Burst Mode
OPERATION
0.1
0.1
SYNCHRONOUS SWITCH
0.01
0.001
0.01
0.001
500
0
V
I
= 1.8V
= 0A
V
LOAD
= 1.8V
OUT
LOAD
OUT
I
= 0A
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
4
0
1
2
3
5
6
–50 –25
0
25
50
75
100 125
V
TEMPERATURE (°C)
IN
INPUT VOLTAGE(V)
3411A G13
3411A G14
3411A G15
Burst Mode Operation
Pulse Skippng Mode
Switch Leakage vs Temperature
600
500
SW
2V/DIV
SW
2V/DIV
400
300
200
100
0
V
V
OUT
OUT
50mV/DIV
50mV/DIV
AC COUPLED
AC COUPLED
I
I
L
L
200mA/DIV
200mA/DIV
MAIN SWITCH
SYNCHRONOUS SWITCH
3411A G17
3411A G18
4μs/DIV
4μs/DIV
V
V
I
= 3.6V
V
V
I
= 3.6V
IN
OUT
IN
OUT
= 1.8V
= 1.8V
= 5mA
= 50mA
50
–50 –25
0
25
75 100 125
LOAD
LOAD
TEMPERATURE (°C)
3411A G16
3411afa
5
LTC3411A
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 3.6V fO = 1MHz, unless
Start-Up from Shutdown
otherwise noted.
Forced Continuous Mode
Start-Up from Shutdown
SW
2V/DIV
SHDN/R
T
2V/DIV
SHDN/R
T
2V/DIV
V
OUT
50mV/DIV
AC COUPLED
V
V
OUT
OUT
1V/DIV
1V/DIV
I
L
I
200mA/DIV
I
L
L
1A/DIV
1A/DIV
3411A G19
3411A G21
3411A G20
2μs/DIV
200μs/DIV
200μs/DIV
V
V
I
= 3.6V
V
V
I
= 3.6V
V
V
I
= 3.6V
IN
OUT
IN
OUT
IN
OUT
= 1.8V
= 1.8V
= 1.8V
= 0A
= 80mA
= 1.25A
LOAD
LOAD
LOAD
Start-Up from Shutdown with
a Prebiased Output (Forced
Continuous Mode)
Load Step
Load Step
V
V
OUT
V
OUT
OUT
100mV/DIV
100mV/DIV
1V/DIV
AC COUPLED
AC COUPLED
I
I
I
L
L
L
1A/DIV
1A/DIV
500mA/DIV
I
I
LOAD
1A/DIV
LOAD
1A/DIV
3411A G23
3411A G24
3411A G22
40μs/DIV
40μs/DIV
200μs/DIV
V
V
I
= 3.6V
V
V
I
= 3.6V
V
= 3.6V
IN
OUT
IN
OUT
IN
= 1.8V
= 0A to 1.25A
= 1.8V
= 50mA to 1.25A
PREBIASED V
= 3V, V
= 1.8V
OUT
OUT
I
= 0A
LOAD
LOAD
LOAD
Burst Mode OPERATION
Burst Mode OPERATION
VOUT Short to VIN (Forced
Continuous Mode)
VOUT Short to Ground
Load Step
V
OUT
V
OUT
1V/DIV
100mV/DIV
AC COUPLED
V
OUT
1V/DIV
I
L
1A/DIV
I
I
L
L
2A/DIV
500mA/DIV
I
LOAD
1A/DIV
3411A G26
3411A G27
3411A G25
40μs/DIV
40μs/DIV
40μs/DIV
V
V
I
= 3.6V
V
V
I
= 3.6V
V
V
I
= 3.6V
IN
OUT
IN
OUT
IN
OUT
= 1.8V
= 0A
= 1.8V
= 0A
= 1.8V
= 250mA to 1.25A
LOAD
LOAD
LOAD
Burst Mode OPERATION
3411afa
6
LTC3411A
PIN FUNCTIONS
SHDN/R (Pin 1): Combination Shutdown and Timing
PGND (Pin 5): Main Power Ground Pin. Connect to the
T
Resistor Pin. The oscillator frequency is programmed by
(–) terminal of C , and (–) terminal of C .
OUT IN
connecting a resistor from this pin to ground. Forcing
PV (Pin 6): Main Supply Pin. Must be closely decoupled
IN
this pin to SV causes the device to be shut down. In
IN
to PGND.
shutdown all functions are disabled.
SV (Pin 7): The Signal Power Pin. All active circuitry
IN
SYNC/MODE (Pin 2): Combination Mode Selection and
is powered from this pin. Must be closely decoupled to
Oscillator Synchronization Pin. This pin controls the op-
SGND. SV must be greater than or equal to PV .
IN
IN
eration of the device. When tied to SV or SGND, Burst
IN
PGOOD (Pin 8): The Power Good Pin. This common drain
logic output is pulled to SGND when the output voltage is
not within 7% of regulation.
Mode operation or pulse skipping mode is selected,
respectively. If this pin is held at half of SV , the forced
IN
continuous mode is selected. The oscillation frequency
can be synchronized to an external oscillator applied to
this pin. When synchronized to an external clock pulse
skip mode is selected.
V
(Pin 9): Receives the feedback voltage from the ex-
FB
ternal resistive divider across the output. Nominal voltage
for this pin is 0.8V.
SGND(Pin3):The Signal Ground Pin. All small-signal com-
ponents and compensation components should be con-
nected to this ground (see Board Layout Considerations).
I
(Pin 10): Error Amplifier Compensation Point. The
TH
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is 0.4V to
1.4V.
SW (Pin 4): The Switch Node Connection to the Inductor.
This pin swings from PV to PGND.
IN
Exposed Pad (Pin 11): Power Ground. Must be soldered
to electrical ground on PCB.
NOMINAL (V)
TYP
ABSOLUTE MAX (V)
PIN
1
NAME
DESCRIPTION
MIN
–0.3
0
MAX
MIN
–0.3
–0.3
MAX
SHDN/R
Shutdown/Timing Resistor
0.8
SV
SV
SV + 0.3
T
IN
IN
IN
2
SYNC/MODE Mode Select/Sychronization Pin
SV + 0.3
IN
3
SGND
SW
Signal Ground
0
4
Switch Node
0
PV
–0.3
PV + 0.3
IN
IN
5
PGND
Main Power Ground
Main Power Supply
Signal Power Supply
Power Good Pin
0
6
PV
SV
–0.3
2.5
0
5.5
5.5
SV
–0.3
–0.3
–0.3
–0.3
–0.3
SV + 0.3
IN
IN
IN
7
6
6
8
PGOOD
IN
9
V
Output Feedback Pin
Error Amplifier Compensation and Run Pin
0
0.8
1.0
1.5
SV + 0.3
IN
FB
10
I
0
SV + 0.3
IN
TH
3411afa
7
LTC3411A
BLOCK DIAGRAM
SV
SGND
3
I
PV
IN
IN
TH
7
10
6
0.8V
PMOS CURRENT
COMPARATOR
VOLTAGE
REFERENCE
I
TH
LIMIT
BCLAMP
+
–
+
–
–
+
9
V
FB
ERROR
AMPLIFIER
V
B
BURST
COMPARATOR
+
–
0.74V
SLOPE
COMPENSATION
4
SW
OSCILLATOR
+
–
LOGIC
0.86V
+
PGOOD
8
–
NMOS
COMPARATOR
–
+
5
PGND
REVERSE
COMPARATOR
1
SHDN/R
2
3411A BD
SYNC/MODE
T
3411afa
8
LTC3411A
OPERATION
switch from continuous operation to the selected mode
when the load current is low.
The LTC3411A uses a constant frequency, current mode
architecture. The operating frequency is determined by the
valueoftheR resistor or can be synchronized to an external
T
To optimize efficiency, the Burst Mode operation can be
selected. When the load is relatively light, the LTC3411A
automaticallyswitchesintoBurstModeoperationinwhich
the PMOS switch operates intermittently based on load
demand. By running cycles periodically, the switching
losses which are dominated by the gate charge losses
of the power MOSFETs are minimized. The main control
loop is interrupted when the output voltage reaches the
desired regulated value. The burst comparator trips when
oscillator. To suit a variety of applications, the selectable
MODE pin allows the user to trade-off noise for efficiency.
The output voltage is set by an external divider returned
to the V pin. An error amplifier compares the divided
FB
output voltage with the reference voltage of 0.8V and ad-
justs the peak inductor current accordingly. Overvoltage
andundervoltagecomparatorswillpullthePGOODoutput
low if the output voltage is not within 7% of its regulated
value. A tripping delay of 40μs and untripping delay of
105μs ensures PGOOD will not glitch due to transient
I
is below approximately 0.5V, shutting off the switch
TH
and reducing the power. The output capacitor and the
inductor supply the power to the load until I rises above
spikes on V
.
TH
OUT
approximately 0.5V, turning on the switch and the main
Main Control Loop
control loop which starts another cycle.
Duringnormaloperation,thetoppowerswitch(P-channel
MOSFET) is turned on at the beginning of a clock cycle.
Currentflowsthroughthisswitchintotheinductorandthe
load, increasing until the peak inductor current reaches
For lower output voltage ripple at low currents, pulse
skipping mode can be used. In this mode, the LTC3411A
continues to switch at a constant frequency down to
very low currents, where it will eventually begin skipping
pulses.
the limit set by the voltage on the I pin. Then the top
TH
switch is turned off, the bottom switch is turned on, and
the energy stored in the inductor forces the current to flow
through the bottom switch and the inductor, out into the
load until the next clock cycle.
Finally, in forced continuous mode, the inductor cur-
rent is constantly cycled which creates a fixed output
voltage ripple at all output current levels. This feature is
desirable in telecommunications since the noise is at a
constant frequency and is thus, easy to filter out. Another
advantage of this mode is that the regulator is capable
of both sourcing current into a load and sinking current
from the output.
The peak inductor current is controlled by the voltage
on the I pin, which is the output of the error amplifier.
TH
The output is developed by the error amplifier comparing
the feedback voltage, V , to the 0.8V reference voltage.
FB
When the load current increases, the output voltage and
Dropout Operation
V
decrease slightly. This decrease in V causes the er-
FB
FB
ror amplifier to increase the I voltage until the average
TH
Whentheinputsupplyvoltagedecreasestowardtheoutput
voltage, the duty cycle increases to 100% which is the
dropout condition. In dropout, the PMOS switch is turned
on continuously with the output voltage being equal to the
input voltage minus the voltage drop across the internal
P-channel MOSFET and the inductor.
inductor current matches the new load current.
ThemaincontrolloopisshutdownbypullingtheSHDN/R
T
pintoSV ,resettingtheinternalsoft-start.Re-enablingthe
IN
maincontrolloopbyreleasingtheSHDN/R pinactivatesthe
T
internal soft-start, which slowly ramps the output voltage
over approximately 0.8ms until it reaches regulation.
Low Supply Operation
Low Current Operation
TheLTC3411Aincorporatesanundervoltagelockoutcircuit
which shuts down the part when the input voltage drops
below about 2.1V to prevent unstable operation.
Three modes are available to control the operation of the
LTC3411A at low currents. All three modes automatically
3411afa
9
LTC3411A
APPLICATIONS INFORMATION
A general LTC3411A application circuit is shown in
Figure 4.Externalcomponentselectionisdrivenbytheload
requirement, and begins with the selection of the inductor
A reasonable starting point for setting ripple current is
ΔI = 0.4•I
,whereI
is1.25A.Thelargest
L
OUT(MAX)
OUT(MAX)
ripplecurrentΔI occursatthemaximuminputvoltage.To
L
L1. Once L1 is chosen, C and C
can be selected.
guarantee that the ripple current stays below a specified
maximum, theinductorvalueshouldbechosenaccording
to the following equation:
IN
OUT
Operating Frequency
Selectionoftheoperatingfrequencyisatrade-offbetween
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
ꢂ
ꢅ
VOUT
fO • ꢀIL
VOUT
VIN(MAX)
L =
• 1ꢁ
ꢄ
ꢇ
ꢃ
ꢆ
The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation
begins when the peak inductor current falls below a level
set by the burst clamp. Lower inductor values result in
higher ripple current which causes this to occur at lower
load currents. This causes a dip in efficiency in the upper
range of low current operation. In Burst Mode operation,
lower inductance values will cause the burst frequency
to increase.
Theoperatingfrequency,f ,oftheLTC3411Aisdetermined
O
by an external resistor that is connected between the R
T
pin and ground. The value of the resistor sets the ramp
current that is used to charge and discharge an internal
timingcapacitorwithintheoscillatorandcanbecalculated
by using the following equation:
5000
T
= 25°C
A
7
–1.6508
4500
4000
3500
3000
2500
2000
1500
1000
500
R = 5 × 10 (f )
(kΩ),
T
O
where f is in kHz, or can be selected using Figure 1.
O
The maximum usable operating frequency is limited by
the minimum on-time and the duty cycle. This can be
calculated as:
VOUT
fO(MAX) ≈ 6.67 •
(MHz)
V
IN(MAX)
0
0
400
800
1200
1600
R
T
(kΩ)
The minimum frequency is internally set at around 200kHz.
3411A F01
Inductor Selection
Figure 1. Frequency vs RT
The operating frequency, f , has a direct effect on the
O
inductorvalue,whichinturninfluencestheinductorripple
Inductor Core Selection
current ΔI :
L
Different core materials and shapes will change the
size/current and price/current relationship of an induc-
tor. Toroid or shielded pot cores in ferrite or permalloy
materials are small and don’t radiate much energy, but
generally cost more than powdered iron core inductors
with similar electrical characteristics. The choice of which
style inductor to use often depends more on the price vs
sizerequirementsandanyradiatedfield/EMIrequirements
ꢂ
OUT ꢅ
V
VIN
ꢆ
VOUT
fO •L
ꢀIL =
• 1ꢁ
ꢄ
ꢇ
ꢃ
The inductor ripple current decreases with larger induc-
tance or frequency, and increases with higher V or V
.
IN
OUT
Accepting larger values of ΔI allows the use of lower
L
inductances, but results in higher output ripple voltage,
greater core loss and lower output capability.
than on what the LTC3411A requires to operate. Table 1
3411afa
10
LTC3411A
APPLICATIONS INFORMATION
shows some typical surface mount inductors that work
diode peak current and average power dissipation so as
not to exceed the diode ratings. The main problem with
Schottkydiodesisthattheirparasiticcapacitancereduces
the efficiency, usually negating the possible benefits for
LTC3411Acircuits.AnotherproblemthataSchottkydiode
can introduce is higher leakage current at high tempera-
tures, which could reduce the low current efficiency.
well in LTC3411A applications.
Table 1. Representative Surface Mount Inductors
MANU-
FACTURER PARTNUMBER
MAXDC
VALUE CURRENT DCR HEIGHT
Toko
A914BYW-1R2M=P3:
1.2μH
2.15A
1.8A
44mΩ 2mm
D52LC
A960AW-1R2M=P3:
D518LC
1.2μH
46mΩ 1.8mm
Remember to keep lead lengths short and observe proper
grounding(seeBoardLayoutConsiderations)toavoidring-
ing and increased dissipation when using a catch diode.
DB3015C-1068AS-1R0N 1.0μH
DB3018C-1069AS-1R0N 1.0μH
DB3020C-1070AS-1R0N 1.0μH
2.1A
2.1A
2.1A
43mΩ 1.5mm
45mΩ 1.8mm
47mΩ 2mm
49mΩ 2mm
22mΩ 3mm
80mΩ 1mm
70mΩ 3mm
120mΩ 1mm
72mΩ 3mm
40mΩ 1.2mm
36mΩ 1.5mm
24mΩ 2mm
Input Capacitor (C ) Selection
IN
A914BYW-2R2M-D52LC 2.2μH 2.05A
In continuous mode, the input current of the converter is a
A915AY-2ROM-D53LC 2.0μH
3.3A
2.1A
2.3A
2.4A
2.1A
2.2A
2.2A
2.1A
square wave with a duty cycle of approximately V /V .
OUT IN
Coilcraft
Sumida
LPO1704-122ML
D01608C-222
1.2μH
2.2μH
2.2μH
1.0μH
1.0μH
1.2μH
1.1μH
1.0μH
1.1μH
Topreventlargevoltagetransients,alowequivalentseries
resistance (ESR) input capacitor sized for the maximum
RMS current must be used. The maximum RMS capacitor
current is given by:
LP01704-222M
CR32-1R0
CR5D11-1R0
CDRH3D14-1R2
CDRH4D18C/LD-1R1
CDRH4D28C/LD-1R0
CDRH4D28C-1R1
CDRH4D28-1R2
CDRH6D12-1R0
CDRH4D282R2
CDC5D232R2
VOUT(V − VOUT
)
IN
IRMS ≈ IMAX
V
IN
3.0A 17.5mΩ 3mm
3.8A 22mΩ 3mm
where the maximum average output current I
equals
MAX
1.2μH 2.56A 23.6mΩ 3mm
1.0μH 2.80A 37.5mΩ 1.5mm
the peak current minus half the peak-to-peak ripple cur-
rent, I = I – ΔI /2.
MAX
LIM
L
2.2μH 2.04A
23mΩ 3mm
30mΩ 2.5mm
27mΩ 1.8mm
29mΩ 3.2mm
32mΩ 2.8mm
24mΩ 5mm
80mΩ 1mm
This formula has a maximum at V = 2V , where
IN
OUT
2.2μH
1.0μH
2.2μH
2.2μH
2.2μH
0.9μH
2.16A
2.6A
3.2A
2.9A
3.2A
1.4A
I
≅ I /2. This simple worst case is commonly used
RMS
OUT
TaiyoYuden NPO3SB1ROM
N06DB2R2M
to design because even significant deviations do not offer
muchrelief. Notethatcapacitormanufacturer’sripplecur-
rent ratings are often based on only 2000 hours lifetime.
This makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required.Severalcapacitorsmayalsobeparalleledtomeet
thesizeorheightrequirementsofthedesign.Anadditional
0.1μF to 1μF ceramic capacitor is also recommended on
N05DB2R2M
Murata
FDK
LQN6C2R2M04
MIPW3226DORGM
Catch Diode Selection
Although unnecessary in most applications, a small
improvement in efficiency can be obtained in a few ap-
plications by including the optional diode D1 shown in
Figure 4, which conducts when the synchronous switch
is off. When using Burst Mode operation or pulse skip
mode, the synchronous switch is turned off at a low
current and the remaining current will be carried by the
optional diode. It is important to adequately specify the
V for high frequency decoupling, when not using an all
IN
ceramic capacitor solution.
Output Capacitor (C ) Selection
OUT
The selection of C
is driven by the required ESR to
OUT
minimizevoltagerippleandloadsteptransients.Typically,
once the ESR requirement is satisfied, the capacitance
3411afa
11
LTC3411A
APPLICATIONS INFORMATION
is adequate for filtering. The output ripple (ΔV ) is
Ceramic Input and Output Capacitors
OUT
determined by:
Higher value, lower cost ceramic capacitors are now be-
coming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them
ideal for switching regulator applications. Because the
LTC3411A’s control loop does not depend on the output
capacitor’s ESR for stable operation, ceramic capacitors
can be used freely to achieve very low output ripple and
small circuit size.
ꢂ
ꢄ
L ꢃ
ꢅ
ꢇ
ꢆ
1
ꢀVOUT ꢁ ꢀI ESR +
8fOCOUT
wheref =operatingfrequency,C
=outputcapacitance
O
OUT
and ΔI = ripple current in the inductor. The output ripple
L
is highest at maximum input voltage since ΔI increases
L
withinputvoltage.WithΔI =0.4•I
theoutputripple
L
OUT(MAX)
will be less than 100mV at maximum V , a minimum C
IN
OUT
However, care must be taken when ceramic capacitors
are used at the input and the output. When a ceramic
capacitor is used at the input and the power is supplied
by a wall adapter through long wires, a load step at the
value of 10μF and f = 1MHz with:
O
ESRC
< 150mΩ
OUT
Once the ESR requirements for C
have been met, the
OUT
output can induce ringing at the input, V . At best, this
IN
RMS current rating generally far exceeds the I
RIPPLE(P-P)
ringing can couple to the output and be mistaken as loop
requirement, except for an all ceramic solution.
instability. At worst, a sudden inrush of current through
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
currenthandlingrequirementoftheapplication.Aluminum
electrolytic, special polymer, ceramic and dry tantalum
capacitors are all available in surface mount packages.
The OS-CON semiconductor dielectric capacitor avail-
able from Sanyo has the lowest ESR(size) product of any
aluminum electrolytic at a somewhat higher price. Special
polymer capacitors, such as Sanyo POSCAP, offer very
low ESR, but have a lower capacitance density than other
types. Tantalum capacitors have the highest capacitance
density, but it has a larger ESR and it is critical that the
capacitors are surge tested for use in switching power
supplies. An excellent choice is the AVX TPS series of
surfacemounttantalums,availableincaseheightsranging
from2mmto4mm.Aluminumelectrolyticcapacitorshave
a significantly larger ESR, and is often used in extremely
cost-sensitive applications provided that consideration is
given to ripple current ratings and long term reliability.
Ceramic capacitors have the lowest ESR and cost but also
have the lowest capacitance density, a high voltage and
temperature coefficient and exhibit audible piezoelectric
effects. In addition, the high Q of ceramic capacitors along
with trace inductance can lead to significant ringing. Other
capacitor types include the Panasonic specialty polymer
(SP) capacitors.
the long wires can potentially cause a voltage spike at V ,
IN
large enough to damage the part.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage charac-
teristics of all the ceramics for a given value and size.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement.Duringaloadstep,theoutputcapacitormust
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation com-
ponents and the output capacitor size. Typically, 3 to 4
cycles are required to respond to a load step, but only in
the first cycle does the output drop linearly. The output
droop, V
, is usually about 2 to 3 times the linear
DROOP
drop of the first cycle. Thus, a good place to start is with
the output capacitor value of approximately:
ΔIOUT
COUT ≈ 2.5
fO • VDROOP
More capacitance may be required depending on the duty
cycle and load step requirements.
In most cases, 0.1μF to 1μF of ceramic capacitors should
also be placed close to the LTC3411A in parallel with the
main capacitors for high frequency decoupling.
3411afa
12
LTC3411A
APPLICATIONS INFORMATION
of how to switch from force continuous mode to pulse
skipping mode when RUN goes low. The parasitic drain
capacitance of a large transistor coupled with a large pull
up resistor results in large RC constants. As RUN goes
low, the transistor drain charges up slowly, gradually de-
creasing the oscillator frequency of the part. This leads to
large inductor current ripples translating into large output
voltage ripples. In some cases, the output voltage could
rise up to dangerous levels.
Inmostapplications,theinputcapacitorismerelyrequired
to supply high frequency bypassing, since the impedance
to the supply is very low. A 10μF ceramic capacitor is
usually enough for these conditions.
Setting the Output Voltage
The LTC3411A develops a 0.8V reference voltage between
the feedback pin, V , and the signal ground as shown in
FB
Figure 4. The output voltage is set by a resistive divider
according to the following formula:
When activatingtheLTC3411A,aninternalsoft-startslowly
ramps the output voltage up until regulation. Soft-start
R2
ꢅ
R1
ꢁ
ꢂ
ꢄ
VOUT ꢀ 0.8V 1+
preventssurgecurrentsfromV bygraduallyrampingthe
ꢃ
ꢆ
IN
output voltage up during start-up. The output will ramp
from zero to full scale over a time period of approximately
0.7ms. This prevents the LTC3411A from having to quickly
charge the output capacitor and thus supplying an exces-
sive amount of instantaneous current.
Keeping the current small (<5μA) in these resistors maxi-
mizes efficiency, but making them too small may allow
stray capacitance to cause noise problems and reduce
the phase margin of the error amp loop.
TheLTC3411Acanstartintoaback-biasedoutputinforced
continuous operation. When the output is pre-biased at
either a higher or lower value than the regulated output
voltage,theLTC3411Awillsinkorsourcecurrentasneeded
to bring the output back into regulation. However, during
soft-start the regulator will always start in pulse skipping
mode ignoring the mode selected with the SYNC/MODE
To improve the frequency response, a feed-forward ca-
pacitor C may also be used. Great care should be taken
F
to route the V line away from noise sources, such as
FB
the inductor or the SW line.
Shutdown and Soft-Start
The SHDN/R pin is a dual purpose pin that sets the oscil-
T
lator frequency and provides a means to shut down the
LTC3411A. This pin can be interfaced with control logic in
several ways, as shown in Figure 2 and Figure 3. In both
configurations, Run = “0” shuts down the LTC3411A and
Run = “1” activates the LTC3411A.
SHDN/R
SV
IN
T
T
R
100k
RUN
3411A F03
Care must be taken when using Figure 3 to shut down
the part in force continuous mode. The pull up resistor
should be as small as the application would allow and
the pull down transistor should be as small as possible
to minimize its parasitic drain capacitance. If possible,
always shut down the part while in pulse skipping mode
or Burst Mode operation. Figure 4 shows an example
Figure 3. SHDN/RT Pin Activated with a Switch
SHDN/R
R
SV
IN
T
1M
T
3V
OFF ON
0V
SHDN/R
T
100k
100k
R
T
SYNC/MODE
RUN
3411A F02
3411A F04
Figure 4. Automatic Mode Change Circuit
Figure 2. SHDN/RT Pin Activated with a Logic Input
3411afa
13
LTC3411A
APPLICATIONS INFORMATION
pin. This prevents the output from discharging to below
the regulation point when soft-starting.
optimizationofthecontrolloopbehaviorbutalsoprovides
a DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling time at this test
point truly reflects the closed loop response. Assuming a
predominantlysecondordersystem,phasemarginand/or
damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin.
Mode Selection and Frequency Synchronization
TheSYNC/MODEpinisamultipurposepinwhichprovides
mode selection and frequency synchronization. Connect-
ing this pin to V enables Burst Mode operation, which
IN
provides the best low current efficiency at the cost of a
higheroutputvoltageripple. Whenthispinisconnectedto
ground,pulseskippingoperationisselectedwhichprovides
the lowest output voltage and current ripple at the cost
of low current efficiency. Applying a voltage that is half
the value of the input voltage results in forced continuous
mode, whichcreatesafixedoutputrippleandiscapableof
sinking up to 0.4A. Since the switching noise is constant
in this mode, it is also the easiest to filter out.
The I external components shown in the circuit on the
TH
front page of this data sheet will provide an adequate star t-
ing point for most applications. The series R-C filter sets
thedominantpole-zeroloopcompensation.Thevaluescan
be modified slightly (from 0.5 to 2 times their suggested
values) to optimize transient response once the final PC
layout is done and the particular output capacitor type
and value have been determined. The output capacitors
need to be selected because the various types and values
determine the loop feedback factor gain and phase. An
output current pulse of 20% to 100% of full load current
having a rise time of 1μs to 10μs will produce output voltage
The LTC3411A can also be synchronized to an external
clock signal by the SYNC/MODE pin. The internal oscilla-
tor frequency should be set to 20% of the external clock
frequency to ensure adequate slope compensation, since
slopecompensationisderivedfromtheinternaloscillator.
During synchronization, the mode is set to pulse skipping
and the top switch turn on is synchronized to the falling
edge of the external clock.
and I pin waveforms that will give a sense of the overall
TH
loop stability without breaking the feedback loop.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, V
im-
OUT
•ESR,where
mediately shif ts by an amount equal to ΔI
LOAD
Checking Transient Response
ESR is the effective series resistance of C . ΔI
also
OUT
LOAD
The OPTI-LOOP® compensation allows the transient re-
OUT
begins to charge or discharge C
generating a feedback
error signal used by the regulator to return V
to its
sponsetobeoptimizedforawiderangeofloadsandoutput
OUT
capacitors. The availability of the I pin not only allows
OPTI-LOOP is a registered trademark of Linear Technology Corporation.
TH
V
IN
+
R5
R6
C6
C
IN
SV
PV
PGOOD
SW
PGOOD
IN
IN
L1
C8
V
OUT
PGND
PGND
D1
OPTIONAL
+
LTC3411A
SYNC/MODE
SGND
C
C5
OUT
C
F
I
V
FB
TH
PGND
PGND
R2
R
SGND PGND SHDN/R
C
T
C
SGND
ITH
R
R1
C
T
C
3411A F05
SGND
SGND
GND
SGND SGND
Figure 5. LTC3411A General Schematic
3411afa
14
LTC3411A
APPLICATIONS INFORMATION
steady-state value. During this recovery time, V
can
In some applications, a more severe transient can be
caused by switching in loads with large (>1μF) input ca-
pacitors. The discharged input capacitors are effectively
OUT
be monitored for overshoot or ringing that would indicate
a stability problem.
put in parallel with C , causing a rapid drop in V . No
OUT
OUT
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phase margin. The gain of the loop increases with R and
the bandwidth of the loop increases with decreasing C.
If R is increased by the same factor that C is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range
of the feedback loop. In addition, a feedforward capacitor
regulator can deliver enough current to prevent this prob-
lem, if the switch connecting the load has low resistance
and is driven quickly. The solution is to limit the turn-on
speed of the load switch driver. A Hot Swap™ controller
is designed specifically for this purpose and usually in-
corporates current limiting, short-circuit protection, and
soft-starting.
Efficiency Considerations
C can be added to improve the high frequency response,
F
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
as shown in Figure 5. Capacitor C provides phase lead by
F
creating a high frequency zero with R2 which improves
the phase margin.
Theoutputvoltagesettlingbehaviorisrelatedtothestability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
inputvoltageV dropstowardV ,theloadstepcapability
does decrease due to the decreasing voltage across the
inductor. Applications that require large load step capabil-
ity near dropout should use a different topology such as
SEPIC, Zeta or single inductor, positive buck/boost.
losses in LTC3411A circuits: 1) V current, 2) switching
IN
IN
OUT
2
losses, 3) I R losses, 4) other losses.
1) The V current is the DC supply current given in the
IN
electrical characteristics which excludes MOSFET driver
andcontrolcurrents. V currentresultsinasmall(<0.1%)
IN
loss that increases with V , even at no load.
IN
1
V
O
= 3.6V
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results
fromswitchingthegatecapacitanceofthepowerMOSFETs.
Each time a MOSFET gate is switched from low to high
IN
= 1MHz
f
0.1
0.01
0.001
to low again, a packet of charge dQ moves from V to
IN
ground. The resulting dQ/dt is a current out of V that is
IN
typically much larger than the DC bias current. In continu-
V
V
V
= 1.2V
= 1.5V
= 1.2V-1.8V
OUT
OUT
ous mode, I = f (QT + QB), where QT and QB are
GATECHG O
the gate charges of the internal top and bottom MOSFET
switches. The gate charge losses are proportional to V
= 1.8V
V
OUT
0.0001
IN
0.1
1
10
100
1000
10000
LOAD CURRENT (mA)
and thus their effects will be more pronounced at higher
supply voltages.
3411A F06
Figure 6. Power Loss vs Load Currrent
Hot Swap is a trademark of Linear Technology Corporation.
3411afa
15
LTC3411A
APPLICATIONS INFORMATION
2
The junction temperature, T , is given by:
3) I R Losses are calculated from the DC resistances of
J
the internal switches, R , and external inductor, R . In
SW
L
T = T
J
+ T
AMBIENT
RISE
continuous mode, the average output current flowing
through inductor L is “chopped” between the internal top
and bottom switches. Thus, the series resistance look-
ing into the SW pin is a function of both top and bottom
As an example, consider the case when the LTC3411A is
in dropout at an input voltage of 3.3V with a load current
of 1A. From the Typical Performance Characteristics
graph of Switch Resistance, the R
resistance of the
DS(ON)
MOSFET R
and the duty cycle (DC) as follows:
DS(ON)
P-channel switch is 0.15Ω. Therefore, power dissipated
R
SW
= (R TOP)(DC) + (R BOT)(1 – DC)
DS(ON) DS(ON)
by the part is:
2
The R
for both the top and bottom MOSFETs can
DS(ON)
P = I • R
= 150mW
D
DS(ON)
beobtainedfromtheTypicalPerformanceCharacteristics
2
TheMS10packagejunction-to-ambientthermalresistance,
θ ,willbeintherangeof100°C/Wto120°C/W.Therefore,
the junction temperature of the regulator operating in a
70°C ambient temperature is approximately:
curves. Thus, to obtain I R losses:
JA
2
I R losses = I 2(R + R )
OUT
SW
L
4)Other“hidden”lossessuchascoppertraceandinternal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important
to include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
T = 0.15 • 120 + 70 = 88°C
J
Remembering that the above junction temperature is
obtained from an R
at 25°C, we might recalculate
DS(ON)
the junction temperature based on a higher R
since
DS(ON)
can be minimized by making sure that C has adequate
IN
it increases with temperature. However, we can safely as-
sume that the actual junction temperature will not exceed
the absolute maximum junction temperature of 125°C.
charge storage and very low ESR at the switching fre-
quency. Other losses including diode conduction losses
duringdead-timeandinductorcorelosseswhichgenerally
account for less than 2% total additional loss.
Design Example
As a design example, consider using the LTC3411A in a
portableapplicationwithaLi-Ionbattery. Thebatterypro-
Thermal Considerations
In a majority of applications, the LTC3411A does not
dissipate much heat due to its high efficiency. However,
in applications where the LTC3411A is running at high
ambient temperature with low supply voltage and high
duty cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150°C,
both power switches will be turned off and the SW node
will become high impedance.
vides a V = 2.5V to 4.2V. The load requires a maximum
IN
of 1.25A in active mode and 10mA in standby mode. The
output voltage is V
= 2.5V. Since the load still needs
OUT
power in standby, Burst Mode operation is selected for
good low load efficiency.
First, calculate the timing resistor for 1MHz operation:
7
3 –1.6508
R = 5 × 10 (10 )
= 557.9k
Use a standard value of 549k. Next, calculate the inductor
value for about 40% ripple current at maximum V :
T
To avoid the LTC3411A from exceeding the maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whetherthepowerdissipatedexceedsthemaximumjunction
temperature of the part. The temperature rise is given by:
IN
ꢁ
ꢄ
2.5V
1MHz • 500mA
2.5V
4.2V
L =
• 1ꢀ
= 2μH
ꢃ
ꢆ
ꢂ
ꢅ
Choosingthecloseststandardinductorvaluefromavendor
of 2.2μH, results in a maximum ripple current of:
T
= P • θ
D JA
RISE
where P is the power dissipated by the regulator and θ
D
JA
2.5V
1MHz • 2.2μ
2.5V
4.2V
ꢂ
ꢃ
ꢅ
ꢆ
is the thermal resistance from the junction of the die to
the ambient temperature.
ꢀIL =
• 1ꢁ
= 460mA
ꢄ
ꢇ
3411afa
16
LTC3411A
APPLICATIONS INFORMATION
For cost reasons, a ceramic capacitor will be used. C
the LTC3411A. These items are also illustrated graphically
in the layout diagram of Figure 7. Check the following in
your layout:
OUT
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:
1. Does the capacitor CIN connect to the power VIN (Pin 6)
andpowerGND(Pin5)ascloseaspossible?Thiscapacitor
provides the AC current to the internal power MOSFETs
and their drivers.
1.25A
1MHz •(5% • 2.5V)
COUT ≈ 2.5
= 25μF
The closest standard value is 22μF. Since the output
impedance of a Li-Ion battery is very low, C is typically
IN
IN
2. Are the C
OUT
and L1 closely connected? The (–) plate of
OUT
10μF. In noisy environments, decoupling SV from PV
IN
C
returns current to PGND and the (–) plate of C .
IN
with an R6/C8 filter of 1Ω/0.1μF may help, but is typically
not needed.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C
and a ground line terminated
OUT
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the
current in these resistors should be kept small. Choosing
2μAwiththe0.8VfeedbackvoltagemakesR1~400k.Aclose
standard 1% resistor value is 412k. Then R2 is 887k.
near SGND (Pin 3). The feedback signal V should be
FB
routed away from noisy components and traces, such as
the SW line (Pin 4), and its trace should be minimized.
4. Keep sensitive components away from the SW pin. The
input capacitor C , the compensation capacitor C and
IN
C
The compensation should be optimized for these compo-
nentsbyexaminingtheloadstepresponsebutagoodplace
to start for the LTC3411A is with a 12.1kΩ and 680pF filter.
The output capacitor may need to be increased depending
on the actual undershoot during a load step.
C
ITH
and all the resistors R1, R2, R , and R should be
T C
routed away from the SW trace and the inductor L1. The
SW pin pad should be kept as small as possible.
5. A ground plane is preferred, but if not available, keep
thesignalandpowergroundssegregatedwithsmallsignal
components returning to the SGND pin at one point which
is then connected to the PGND pin.
ThePGOODpinisacommondrainoutputandrequiresapull-
up resistor. A 100k resistor is used for adequate speed.
Thecircuitonpage1ofthisdatasheetshowsthecomplete
schematic for this design example.
6. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of power
components. These copper areas should be connected to
Board Layout Considerations
one of the input supplies: PV , PGND, SV or SGND.
IN
IN
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
C
IN
V
IN
C
OUT
V
PV
SV
PGND
SW
IN
L1
IN
OUT
R5
LTC3411A
SGND
V
IN
PGOOD
R1
PGOOD
V
SYNC/MODE
SHDN/R
FB
PS
BM
I
TH
T
C4
R2
R
C
R
T
C
ITH
C
C
3411A F07
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 7. LTC3411A Layout Diagram (See Board Layout Checklist)
3411afa
17
LTC3411A
TYPICAL APPLICATIONS
General Purpose Buck Regulator Using Ceramic Capacitors
V
IN
2.5V TO
5.5V
C1
10μF
R5
100k
PGOOD
PGND
PV
IN
L1
SV
PGOOD
SW
IN
2.2μH
V
OUT
RS1
1M
1.2V/1.5V/1.8V
AT 1.25A
LTC3411A
BM
PS
R2 442k
SYNC/MODE
V
FC
FB
I
SHDN/R
T
RS2
1M
TH
1.8V
1.5V
1.2V
C2
22μF
SGND
PGND
C4 22pF
R3
12.1k
R4
549k
R1A
357k
R1B
511k
R1C
887k
C3
680pF
3411A TA02a
SGND
SGND
GND
SGND
PGND
NOTE: IN DROPOUT, THE OUTPUT TRACKS THE INPUT VOLTAGE
C1, C2: TAIYO YUDEN JMK325BJ226MM
L1: TOKO A914BYW-2R2M (D52LC SERIES)
Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
10
0
Burst Mode
OPERATION
V
OUT
100mV/DIV
AC COUPLED
PULSE SKIP
I
L
1A/DIV
I
FORCED CONTINUOUS
LOAD
1A/DIV
3411A TA02c
V
V
O
= 3.6V
= 1.2V
= 1MHz
IN
OUT
40μs/DIV
V
V
I
= 3.6V
IN
f
= 1.2V
OUT
= 100mA TO 1.25A
0.1
1
10
100
1000
10000
LOAD
Burst Mode OPERATION
OUTPUT CURRENT (mA)
3411A TA02b
V
OUT
100mV/DIV
AC COUPLED
I
L
1A/DIV
I
LOAD
1A/DIV
3411A TA02d
40μs/DIV
V
V
= 3.6V
IN
= 1.8V
OUT
I
= 100mA TO 1.25A
LOAD
PULSE SKIPPING MODE
3411afa
18
LTC3411A
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
R = 0.115
0.38 ± 0.10
TYP
6
10
0.675 ±0.05
3.50 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
PACKAGE
OUTLINE
TOP MARK
(SEE NOTE 6)
(DD) DFN 1103
5
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
0.25 ± 0.05
0.50
BSC
2.38 ±0.10
(2 SIDES)
2.38 ±0.05
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD
PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661 Rev E)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.497 ± 0.076
(.0196 ± .003)
0.889 ± 0.127
(.035 ± .005)
10 9
8
7 6
REF
5.23
(.206)
MIN
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
3.20 – 3.45
(.126 – .136)
DETAIL “A”
0° – 6° TYP
0.254
(.010)
GAUGE PLANE
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ± .0015)
TYP
1
2
3
4 5
0.53 ± 0.152
(.021 ± .006)
0.86
(.034)
REF
1.10
(.043)
MAX
RECOMMENDED SOLDER PAD LAYOUT
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ± 0.0508
(.004 ± .002)
0.50
(.0197)
BSC
MSOP (MS) 0307 REV E
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3411afa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresenta-
t ion t h a t t he in ter c onne c t ion o f i t s cir cui t s a s de s cr ib e d her ein w ill no t in fr inge on ex is t ing p a ten t r igh t s.
19
LTC3411A
TYPICAL APPLICATION
1mm Height, 2MHz, Li-Ion to 1.8V Converter
V
IN
2.5V
R5
TO 4.2V
C1
100k
10μF
PV
SV
PGOOD
SW
PGOOD
C4 22pF
IN
V
OUT
1.8V
IN
L1
0.9μH
AT 1.25A
LTC3411A
SYNC/MODE
C2
10μF
× 2
I
TH
V
FB
R2
887k
R1
698k
R3
13.3k
C3
SGND PGND SHDN/R
T
R4
178k
470pF
C1, C2: TAIYO YUDEN JMK107BJ106MA
L1: FDK MIPW3226DORGM
3411A TA04a
Efficiency vs Output Current
100
90
80
70
60
50
40
30
20
10
0
V
OUT
V
OUT
100mV/DIV
AC COUPLED
100mV/DIV
AC COUPLED
I
L
I
L
1A/DIV
1A/DIV
I
LOAD
1A/DIV
I
LOAD
1A/DIV
V
V
V
= 2.7V
= 3.6V
= 4.2V
IN
IN
IN
3411A TA04c
3411A TA04d
40μs/DIV
40μs/DIV
V
f
= 1.8V
OUT
= 2MHz
O
V
V
I
= 3.6V
V
V
I
= 3.6V
IN
OUT
IN
OUT
= 1.8V
= 50mA TO 1.25A
= 1.8V
= 250mA TO 1.25A
0.1
1
10
100
1000
10000
LOAD
LOAD
OUTPUT CURRENT (mA)
3411A TA04b
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ThinSOT is a trademark of Linear Technology Corporation.
3411afa
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20
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