LTC3421EUF#TR [Linear]
LTC3421 - 3A, 3MHz Micropower Synchronous Boost Converter with Output Disconnect; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C;
| 型号： | LTC3421EUF#TR |
| 厂家： | 
Linear |
| 描述： | LTC3421 - 3A, 3MHz Micropower Synchronous Boost Converter with Output Disconnect; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C 开关 |
| 文件： | 总16页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3421
3A, 3MHz Micropower
Synchronous Boost Converter
with Output Disconnect
U
FEATURES
DESCRIPTIO
The LTC®3421 is a high efficiency, current mode, fixed
frequency, step-up DC/DC converter with true output dis-
connect and inrush current limiting. The device includes a
0.10Ω N-channel MOSFET switch and a 0.14Ω P-channel
synchronous rectifier. This product has the ability to sim-
ply program the output voltage, switching frequency, cur-
rent limit, soft-start, Burst Mode threshold and loop
compensation with external passive components.
■
Synchronous Rectification: Up to 96% Efficiency
■
True Output Disconnect
■
Inrush Current Limiting
■
Very Low Quiescent Current: 12µA
■
Up to 1.5A Continuous Output Current
■
Fixed Frequency Operation Up to 3MHz
■
0.5V to 4.5V Input Range
■
2.4V to 5.25V Adjustable Output Voltage
■
Guaranteed 1V Start-Up
Quiescentcurrentisonly12µAduringBurstModeopera-
tion, maximizing battery life in portable applications. The
oscillator frequency can be programmed up to 3MHz and
can be synchronized to an external clock applied to the
SYNCpin. Anopen-drainuncommittedlow-batterycom-
parator is included. The part maintains operation in
applications with a secondary cell powering the output
voltage during shutdown.
■
Programmable Current Limit
■
Programmable Soft-Start
■
Synchronizable Oscillator
Manual or Automatic Burst Mode® Operation
■
■
Low-Battery Comparator
<1µA Shutdown Current
1.22V Reference Output Voltage
Small (4mm × 4mm) Thermally Enhanced QFN
Package
■
■
■
Otherfeaturesinclude:1µAshutdown,antiringingcontrol,
thermal limit and reference output.
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APPLICATIO S
The LTC3421 is available in a small 4mm × 4mm QFN
■
package.
Handheld Computers
■
Cordless Phones
, LTC and LT are registered trademarks of Linear Technology Corporation.
Burst Mode is a registered trademark of Linear Technology Corporation.
■
GPS Receivers
Battery Backup Supplies
■
U
TYPICAL APPLICATIO
L1
4.7µH
V
IN
1.8V TO 3V
2-Cell to 3.3V Efficiency
C1*
2
21
14 15 16
SW SW SW
100
4.7µF
SHDN
V
Burst Mode OPERATION
IN
4
18
V
3.3V
1.2A
OUT
90
80
70
60
50
40
30
20
10
0
ENB
V
OUTS
V
IN
= 3V
V
IN
= 2.4V
3
23
22
7
17
19
20
1
V
V
V
V
REF
OUT
OUT
V
IN
= 2V
340k
200k
LBI
2
CELLS
LBO
SYNC
LTC3421
OUT
FB
C5*
22µF
8
24
9
I
V
C
LIM
470pF
20k
BURST
GND PGND PGNDPGND
10 11 12 13
0.1µF
45.3k
SS
6
R
T
100k
V
f
= 3.3V
OUT
= 1MHz
OSC
5
28k
0.1µF
0.1
1
10
100
1000
3421 TA01
OUTPUT CURRENT (mA)
*LOCATE COMPONENTS CLOSE TO PINS
C1: TAIYO YUDEN JMK212BJ106MM
C5: TAIYO YUDEN JMK325BJ226MM
L1: TDK RLF7030T-4R7M3R4
3421 G02
3421f
1
LTC3421
W W
U W
U
W
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ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
VIN, VOUT, VOUTS Voltage ............................ –0.3V to 6V
BURST, SHDN, SS, ENB, SW,
LBO, LBI, SYNC Voltages .......................... –0.3V to 6V
Operating Temperature Range
(Notes 2, 5)............................................. –40°C to 85°C
Storage Temperature Range ................. –65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
24 23 22 21 20 19
FB
1
2
3
4
5
6
18
17
16
V
V
OUTS
OUT
SHDN
V
SW
REF
25
ENB
15 SW
SW
R
T
14
13 PGND
SS
7
8
9 10 11 12
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
TJMAX = 125°C, θJA = 40°C/W 1 LAYER BOARD,
θJA = 35°C/W 4 LAYER BOARD, θJC = 2.6°C/W
EXPOSED PAD IS GND (PIN 25) MUST BE SOLDERED TO PCB
ORDER PART NUMBER
UF PART MARKING
LTC3421EUF
3421
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 1.2V, VOUT = 3.3V, RT = 28k, unless otherwise noted.
PARAMETER
Minimum V Start-Up Voltage
CONDITIONS
< 1mA
MIN
TYP
MAX
1
UNITS
I
0.88
V
V
IN
LOAD
Minimum V Operating Voltage
(Note 4)
●
0.5
IN
Output Voltage Adjust Range
2.25
2.40
5.25
5.25
V
V
●
●
Feedback Voltage
1.196
1.220
1
1.244
50
V
Feedback Input Current
V
= 1.22V
nA
FB
Quiescent Current—Burst Mode Operation
V = 0V, ENB = 0V (Note 3)
V = 0V, ENB = 2V (Note 3)
C
12
23
20
50
µA
µA
C
Quiescent Current—Shutdown
SHDN = 0V, ENB = 0V
SHDN = 0V, ENB > 1.4V
0.1
0.2
1
2
µA
µA
Quiescent Current—Active
NMOS Switch Leakage
PMOS Switch Leakage
(Note 3)
0.6
0.1
1.1
5
mA
µA
µA
Ω
0.1
10
NMOS Switch On Resistance
PMOS Switch On Resistance
NMOS Current Limit
0.1
0.14
Ω
I
I
Resistor = 105k
Resistor = 36.5k
●
●
1
3
1.5
4.2
A
A
LIM
LIM
Max Duty Cycle
Min Duty Cycle
●
●
84
91
%
%
0
3421f
2
LTC3421
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 1.2V, VOUT = 3.3V, RT = 28k, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
0.85
2.2
TYP
MAX
UNITS
MHz
V
Frequency Accuracy
SYNC Input High
SYNC Input Low
SYNC Input Current
ENB Input High
ENB Input Low
●
●
●
●
●
●
●
1
1.15
0.8
1
V
0.01
µA
V
1.2
0.4
1
V
ENB Input Current
SHDN Input High
µA
V
V
= 0V (Initial Start-Up)
> 2.4V
1.00
0.65
V
V
OUT
OUT
SHDN Input Low
0.25
1
V
µA
V
SHDN Input Current
REF Output Voltage
REF Output Current Range
Error Amp Transconductance
LBI Threshold
●
●
0.01
1.22
1.183
–100
1.257
8
µA
µs
V
45
0.6
Falling Edge
●
●
0.58
0.62
1
LBI Input Current
0.01
µA
LBO Low Voltage
V
V
= 0V, I
= 0V, I
= 1mA
= 20mA
12.0
0.25
50
0.5
mV
V
IN
IN
SINK
SINK
LBO Leakage
V
V
= 5.5V
0.01
2.4
1
5
µA
µA
V
PGOOD
SS Current Source
BURST Threshold Voltage
= 1V
1.2
SS
Falling Edge
0.87
0.97
1.07
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 4: Once V
supply.
is greater than 2.4V, the IC is not dependent on the V
OUT IN
Note 2: The LTC3421E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the 40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 5: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: Current is measured into the V
pin since the supply current is
OUTS
bootstrapped to the output. The current will reflect to the input supply by
(V /V ) • Efficiency. The outputs are not switching.
OUT IN
3421f
3
LTC3421
U W
TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25°C, unless otherwise specified)
Single Cell to 3.3V Efficiency
2-Cell to 3.3V Efficiency
Li-Ion to 5V Efficiency
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
IN
= 1.5V
Burst Mode OPERATION
Burst Mode OPERATION
V
V
V
= 4.2V
= 3.6V
= 2.7V
V
IN
= 3V
V
IN
= 2.4V
IN
IN
IN
Burst Mode
OPERATION
V
IN
= 1.2V
V
= 2V
IN
V
IN
= 1V
V
= 3.3V
= 1MHz
V
f
= 3.3V
OUT
OSC
V
f
= 5V
= 1MHz
OUT
OSC
OUT
OSC
f
= 1MHz
0.1
1
10
100
1000
0.1
1
10
100
1000
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
3421 G01
3421 G02
3421 G03
Burst Mode Operation
Load Transient Response
Inrush Current Control
VOUT
VOUT
VOUT
1V/DIV
50mV/DIV
100mV/DIV
AC COUPLED
AC COUPLED
SW
600mA
IOUT
INDUCTOR
CURRENT
0.5A/DIV
INDUCTOR
CURRENT
0.5A/DIV
50mA
2.5µs/DIV
3421 G04
VIN = 2.4V
VOUT = 3.3V
COUT = 44µF
2.5ms/DIV
3421 G05
VIN = 0V TO 2.4V 500µs/DIV
COUT = 44µF
3421 G06
Efficiency vs Frequency
Efficiency vs VIN
Start-Up Voltage vs Output Current
100
90
80
70
60
50
40
30
20
10
0
100
90
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
V
= 3.3V
OUT
OUT
f = 300kHz
I
= 200mA
80
70
f = 3MHz
f = 1MHz
60
50
V
IN
> V
OUT
40
30
20
10
0
PMOS LDO MODE
V
V
= 2.4V
OUT
IN
= 3.3V
1
3
4
4.5
1.5
2
2.5
3.5
5
1
10
100
1000
100
OUTPUT CURRENT (mA)
0
50
150
200
INPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
3421 G07
3421 G08
3421 G09
3421f
4
LTC3421
U W
TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25°C, unless otherwise specified)
Burst Mode Threshold vs RBURST
FB Voltage
Frequency Accuracy
180
160
140
120
100
80
1.24
1.23
1.22
1.21
1.03
1.01
0.99
0.97
60
OUT OF BURST
40
20
INTO BURST
1.20
0
0.95
–45 –30 –15
0
15 30 45 60 75 90
20
70
120
–45 –30 –15
0
15 30 45 60 75 90
TEMPERATURE (°C)
R
BURST
(kΩ)
TEMPERATURE (°C)
3421 G11
3421 G10
3421 G12
Burst Mode Quiescent Current
Current Limit Accuracy
RDS(ON)
1.70
1.65
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1.25
1.20
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
20
15
10
5
R
LIM
= 105k
PMOS
NMOS
0
–45 –30 –15
0
15 30 45 60 75 90
–45 –30 –15
0
15 30 45 60 75 90
–45 –30 –15
0
15 30 45 60 75 90
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3421 G14
3421 G13
3421 G15
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PI FU CTIO S
FB (Pin 1): Feedback Pin. Connect resistor divider tap
here. The output voltage can be adjusted from 2.4V to
5.25V. The feedback reference voltage is typically 1.220V.
ENB (Pin 4): Reference Output (VREF) and Low-Battery
ComparatorEnable.WhenENB=Low,theVREF outputand
low-battery comparator are disabled, which lowers the
quiescent current by 5µA. When ENB = High, the VREF
output and the low-battery comparator are enabled. Dur-
ing shutdown, if the ENB = High and the output voltage is
pulled up to greater than 2.5V from a secondary source
such as a coin cell through a Schottky diode, the VREF
output and low-battery comparator becomes powered
from the output voltage and enabled.
SHDN (Pin 2): Shutdown Pin. Less than 0.25V on this pin
shuts down the IC. The IC is enabled when the SHDN
voltage is greater than 1V. Once VOUT is above 2.2V,
hysteresis is applied to the pin (–500nA out of the pin)
allowing it to operate at a logic high while the battery can
drop to 0.5V.
VREF (Pin 3): Buffered 1.22V Reference Output. This pin
can source up to 100µA and sink up to 8µA. This pin must
be decoupled with a 0.1µF capacitor for stability.
3421f
5
LTC3421
U
U
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PI FU CTIO S
RT (Pin 5): Connect a resistor to ground to program the
GND(Pin10):SignalGroundPin.Connecttogroundplane
near the RT resistor, error amp compensation compo-
nents and feedback divider.
oscillator frequency according to the formula:
28,100
fOSC
=
PGND (Pins 11 to 13): Source Terminal of Power Internal
N-Channel MOSFET.
RT
where fOSC is in kHz and RT is in kΩ.
SW (Pins 14 to 16): Switch Pin for Inductor Connection.
ForapplicationswhereVOUT >4.3V, aSchottkydiodefrom
SW to VOUT or to a snubber circuit is required to maintain
absolute maximum rating for SW. (see Application Cir-
cuits for 5V).
SS (Pin 6): Soft-Start Pin. Connect a capacitor from this
pin to ground to set the soft-start time according to the
formula:
t(ms) = CSS(µF) • 320
V
OUT (Pins 17, 19 and 20):The output of the synchronous
The nominal soft-start charging current is 2.5µA. The
active range of SS is from 0.8V to 1.6V.
rectifier and bootstrapped power source for the IC. A
ceramic bypass capacitor is required to be very close to
the VOUT and PGND pins of the IC.
SYNC (Pin 7): Oscillator Synchronization Pin. A clock
pulse width of 100ns to 2µs is required to synchronize the
internal oscillator. If not used SYNC should be grounded.
VOUTS (Pin18):VOUT SensePin. ConnectVOUTS directlyto
an output filter capacitor. The top of the feedback divider
network should also be tied to this point.
ILIM (Pin 8): Current Limit Adjust Pin. Connect a resistor
fromthispintogroundtosetthepeakcurrentlimitthresh-
old for the N-channel MOSFET according to the formula
(note that this is the peak current in the inductor):
VIN (Pin 21): Input Supply Pin. Connect this pin to the
input supply and decouple with at least a 4.7µF ceramic
capacitor.
150
R
LBO (Pin 22): Open-Drain Output. This pin pulls low when
the LBI input is below 0.6V. The open-drain output can
sinkupto20mA. DuringBurstModeoperationLBOisonly
active during the time the IC wakes up to service the
output.
ILIM
=
where I is in amps and R is in kΩ.
BURST (Pin 9): Burst Mode Threshold Adjust Pin. A
resistor/capacitor combination from this pin to ground
programs the average load current at which automatic
BurstModeoperationisentered,accordingtotheformula:
LBI (Pin 23): Low-Battery Comparator Input. Typical
threshold voltage is 0.6V with 30mV hysteresis. This
function is enabled when the ENB pin is high. The low-
battery comparator will operate off VIN or VOUT, whichever
is greater.
2
RBURST
=
IBURST
VC (Pin24):ErrorAmpOutput.Afrequencycompensation
network is connected from this pin to ground to compen-
sate the loop. See the section Compensating the Feedback
Loop for guidelines.
where RBURST is in kΩ and IBURST is in amps.
COUT • VOUT
CBURST
≥
10,000
Exposed Pad (Pin 25): Ground. This pin must be soldered
to the PCB and is typically connected through the power
GND plane.
where CBURST(MIN) and COUT are in µF.
For manual control of Burst Mode operation, ground the
BURST pin to force Burst Mode operation or connect it to
VOUT to force fixed frequency PWM mode. Note that the
BURST pin must not be pulled higher than VOUT
.
3421f
6
LTC3421
W
BLOCK DIAGRA
+
1V TO 4.5V
21
14
15
16
18
V
V
IN
SW SW SW
V
OUTS
IN
ANTIRING
WELL
SWITCH
PMOS
V
OUT
V
OUT
V
OUT
V
V
DD
IN
V
OUT
17
19
20
2.40V TO 5.25V
ANTICROSS
CONDUCTION
NMOS
+
–
I
ZERO
AMP
I
SENSE
AMP
R1
CURRENT
LIMIT
+
–
I
LIM
8
6
I
=
C1
LIMIT
SS
R
150k/R
C1
SHDN
2
4
SHUTDOWN
C
ENB
SS
1.22V
+
V
OUT
–
ERROR
AMP
FB
V
CURRENT
COMP
REF
1.22V REF
2%
1
24
9
–
3
+
R2
V
C
+
+
PWM
Σ
LOGIC
C
P
I/3000
R
SLEEP
1%
Z
THERMAL
REG/SHDN
Burst Mode
CONTROL
OFF
BURST
+
–
0.97V/1.05V
–
UV
OV
BURST
COMP
R
T
OSC
5
7
SLOPE COMP
+
–3%
SYNC
SYNC
IN
+
–
V
V
OUT
3%
IN
R1
R2
–
+
LBI
LBO
23
22
0.6V/
0.63V
EXPOSED
PAD
ENB
GND
10
PGND PGND PGND
11 12 13
25
3421 BD
3421f
7
LTC3421
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OPERATIO
LOW VOLTAGE START-UP
Oscillator
The LTC3421 includes an independent start-up oscillator
designedtostart-upatinputvoltagesof0.85Vtypical. The
frequency and peak current limit during start-up are inter-
nally controlled. The device can start-up under some load
(see graph of Start-Up Current vs Input Voltage). Soft-
start and inrush current limiting are provided during start-
up as well as normal mode. The same soft-start capacitor
is used for each operating mode.
The frequency of operation is set through a resistor from
the RT pin to ground. An internally trimmed timing capaci-
tor resides inside the IC. The oscillator can be synchro-
nizedwithanexternalclockappliedtotheSYNCpin. When
synchronizing the oscillator, the free running frequency
must be set to an approximately 30% lower frequency
than the desired synchronized frequency.
Current Sensing
When either VIN or VOUT exceeds 2.25V, the IC enters
normal operating mode. Once the output voltage exceeds
the input by 0.3V, the IC powers itself from VOUT instead
of VIN. At this point the internal circuitry has no depen-
dency on the VIN input voltage, eliminating the require-
mentforalargeinputcapacitor.Theinputvoltagecandrop
as low as 0.5V without affecting circuit operation. The
limiting factor for the application becomes the availability
of the power source to supply sufficient energy to the
output at the low voltages and the maximum duty cycle,
which is clamped at 91% typical.
Lossless current sensing converts the peak current signal
to a voltage to sum in with the internal slope compensa-
tion. This summed signal is compared to the error ampli-
fier output to provide a peak current control command for
the PWM. The slope compensation in the IC is adaptive to
the input voltage and output voltage. Therefore, the con-
verter provides the proper amount of slope compensation
to ensure stability, but not an excess to cause a loss of
phase margin in the converter.
Error Amplifier
The error amplifier is a transconductance amplifier, with
its positive input internally connected to the 1.22V refer-
ence and its negative input connected to FB. A simple
compensation network is placed from COMP to ground.
Internal clamps limit the minimum and maximum error
amplifier output voltage for improved large-signal tran-
sient response. During sleep (in Burst Mode operation),
thecompensationpinishighimpedance;however,clamps
limit the voltage on the external compensation network,
preventing the compensation capacitor from discharging
to zero during the sleep time.
LOW NOISE FIXED FREQUENCY OPERATION
Shutdown
The part is shut down by pulling SHDN below 0.3V, and
activatedbypullingthepininitiallyabove1Vandmaintain-
ing a high state down to 0.5V. Note that the SHDN pin can
be driven above VIN or VOUT as long as it is limited to less
than the absolute maximum rating.
Soft-Start
Thesoft-starttimeisprogrammedwithanexternalcapaci-
tor to ground on the SS pin. An internal current source
charges it with a nominal 2.5µA. The voltage on the SS pin
(in conjunction with the external resistor on the ILIM pin)
isusedtocontrolthepeakcurrentlimituntilthevoltageon
the capacitor exceeds 1.6V, at which point the external
resistor sets the peak current. In the event of a com-
mandedshutdownorathermalshutdown, thecapacitoris
discharged automatically. Note that Burst Mode operation
is inhibited during the soft-start time.
Current Limit
The programmable current limit circuit sets the maximum
peak current. This clamp level is programmed with a
resistor from ILIM to ground. In Burst Mode operation, the
currentlimitisautomaticallysettoanominalvalueof0.6A
peak for optimal efficiency.
150
R
ILIM
=
where I is in amps and R is in kΩ.
t(ms) = CSS(µF) • 320
3421f
8
LTC3421
U
OPERATIO
Zero Current Amplifier
increasing the output capacitance. Another method of
reducing Burst Mode ripple is to place a small feed-
forward capacitor across the upper resistor in the VOUT
feedback divider network.
Thezerocurrentamplifiermonitorstheinductorcurrentto
theoutputandshutsoffthesynchronousrectifieroncethe
current is below 50mA typical, preventing negative induc-
tor current.
During Burst Mode operation, the VC pin is disconnected
from the error amplifier in an effort to hold the voltage on
the external compensation network where it was before
entering Burst Mode operation. To minimize the effects of
leakage current and stray resistance, voltage clamps limit
the min and max voltage on VC during Burst Mode opera-
tion. This minimizes the transient experienced when a
heavy load is suddenly applied to the converter after being
in Burst Mode operation for an extended period of time.
Antiringing Control
The antiringing control places a resistor across the
inductortodamptheringingontheSWpinindiscontinu-
ous conduction mode. The LCSW ringing (L = inductor,
CSW = capacitance on SW pin) is low energy, but can
cause EMI radiation.
VREF
For automatic operation, an RC network should be con-
nected from BURST to ground. The value of the resistor
will control the average load current (IBURST) at which
Burst Mode operation will be entered and exited (there is
hysteresis to prevent oscillation between modes). The
equation given for the capacitor on BURST is for the
minimum value to prevent ripple on BURST from causing
the part to oscillate in and out of Burst Mode operation at
the current where the mode transition occurs.
The internal 1.22V reference is buffered and brought out
to REFOUT. It is active when the ENB pin is pulled high
(above1.4V).Forstability,aminimumofa0.1µFcapacitor
must be placed on the pin. The output can source up to
100µA and sink up to 8µA. For the lowest possible quies-
centcurrentinBurstModeoperation, thereferenceoutput
should be disabled by grounding the ENB pin.
Burst Mode OPERATION
2
RBURST
=
BurstModeoperationcanbeautomaticorusercontrolled.
In automatic operation, the IC will automatically enter
Burst Mode operation at light load and return to fixed
frequency PWM mode for heavier loads. The user can
program the average load current at which the mode
transition occurs using a single resistor.
IBURST
where RBURST is in kΩ and IBURST is in amps.
COUT • VOUT
CBURST
≥
10,000
where CBURST(MIN) and COUT are in µF.
The oscillator is shut down in this mode, since the on time
is determined by the time it takes the inductor current to
reach a fixed peak current and the off time is determined
by the time it takes for the inductor current to return to
zero.
In the event that a sudden load transient causes FB to
deviate by more than 4% from the regulation value, an
internal pull-up is applied to BURST, forcing the part
quickly out of Burst Mode operation. For optimum tran-
sientresponsewhengoingbetweenBurstModeoperation
and PWM mode, the mode should be controlled manually
by the host. This way PWM mode can be commanded
before the load step occurs, minimizing output voltage
droop. For manual control of Burst Mode operation, the
RC network can be eliminated. To force fixed frequency
PWM mode, BURST should be connected to VOUT. To
force Burst Mode operation, BURST should be grounded.
3421f
In Burst Mode operation, the IC delivers energy to the
output until it is regulated and then goes into a sleep mode
where the outputs are off and the IC is consuming only
12µA of quiescent current. In this mode, the output ripple
has a variable frequency component with load current and
will be typically 2% peak-peak. This maximizes efficiency
at very light loads by minimizing switching and quiescent
losses. Burst Mode ripple can be reduced slightly by
9
LTC3421
U
OPERATIO
Simplified Diagram of Automatic Burst Mode Control Circuit
V
CC
1mA
I
/3000
OUT
–
UV
V
REF
–4%
+
SSDONE
SSDONE
–
+
MODE
FB
1
1 = Burst Mode
OPERATION
0 = PWM MODE
0.9V/
1.1V
9
BURST
R
B
C
B
ERROR AMP/
SLEEP COMP
–
+
TO
SLEEP
MODULATOR
V
REF
±1%
3421 TA03
CLAMP
0.5V TO 1V
24 V
C
R
COMP
C
COMP
The circuit connected to BURST should be able to sink or
source up to 2mA. Note that Burst Mode operaton is
inhibited during start-up and soft-start.
0.55
1+ VOUT – V
IO(MAX)
=
in amps
(
)
IN
2 •
V
IN
NotethatifVIN isaboveVOUT –0.3V, thepartwillexitBurst
Mode operation and the synchronous rectifier will be
disabled.
OUTPUT DISCONNECT AND INRUSH LIMITING
The LTC3421 is designed to allow true output disconnect
by eliminating body diode conduction of the internal
P-channelMOSFETrectifier.ThisallowsVOUT togotozero
volts during shutdown without drawing any current from
the input source. It also allows for inrush current limiting
at turn-on, minimizing surge currents seen by the input
supply. Note that to obtain the advantages of output
Note that if the load applied during forced Burst Mode
operation exceeds the current that can be supplied, the
output voltage will start to droop and the part will auto-
maticallycomeoutofBurstModeoperationandenterfixed
frequency mode, raising VOUT. The maximum current that
can be supplied in Burst Mode operation is given by:
3421f
10
LTC3421
U
OPERATIO
disconnect, there must not be any external Schottky
V
OUT pins and use very low ESR/ESL ceramic capacitors,
diodes connected between the SW pins and VOUT
.
tied to a good ground plane. In VOUT > 4.3V applications,
aSchottkydiodeisrequiredfromtheswitchnodestoVOUT
to limit the peak switch voltage to less than 6V unless
some form of external snubbing is employed. (See 5V
Applications section.)
Note: Board layout is extremely critical to minimize volt-
age overshoot on the SW pins due to stray inductance.
Keeptheoutputfiltercapacitorsascloseaspossibletothe
W U U
U
APPLICATIO S I FOR ATIO
COMPONENT SELECTION
where
f = Operating Frequency in MHz
Ripple = Allowable Inductor Current Ripple (Amps
Peak-Peak)
VIN(MIN) = Minimum Input Voltage
V
IN
V
OUT
24
23
22
21
20
19
V
LBI LBO
V
V
V
OUTS
C
IN
OUT OUT
VOUT(MAX) = Maximum Output Voltage
1
2
3
4
FB
V
18
17
16
15
The inductor current ripple is typically set to 20% to 40%
of the maximum inductor current.
SHDN
V
OUT
V
SW
REF
ENB
SW
SW
For high efficiency, choose an inductor with high fre-
quencycorematerial, suchasferrite, toreducecoreloses.
The inductor should have low ESR (equivalent series
resistance) to reduce the I2R losses and must be able to
handlethepeakinductorcurrentwithoutsaturating.Molded
chokes or chip inductors usually do not have enough core
to support peak inductor currents in the 1A to 4A region.
To minimize radiated noise, use a toroidal or shielded
inductor.SeeTable1forsuggestedinductorsuppliersand
Table 2 for a list of capacitor suppliers.
R
T
5
6
14
SS
PGND 13
BURST GND PGND PGND
10 11 12
GND
I
LIM
8
SYNC
7
9
MULTIPLE VIAS
TO GROUND
PLANE
3421 F01
Figure 1. Recommended Component Placement. Traces Carrying
High Current are Direct (PGND, SW, VOUT). Trace Area at FB and
VC are Kept Low. Lead Length to Battery Should be Kept Short.
VIN and VOUT Ceramic Capacitors Should be as Close to the IC
Pins as Possible
Table 1. Inductor Vendor Information
SUPPLIER PHONE
Coilcraft (847) 639-6400 (847) 639-1469 www.coilcraft.com
Coiltronics (561) 241-7876 (516) 241-9339
FAX
WEB SITE
Inductor Selection
Murata
USA:
USA:
www.murata.com
The high frequency operation of the LTC3421 allows the
use of small surface mount inductors. The minimum
inductance value is proportional to the operating fre-
quency and is limited by the following constraints:
(814) 237-1431 (814) 238-0490
(800) 831-9172
Sumida
USA:
(847) 956-0666 (847) 956-0702
Japan: Japan:
81-3-3607-5111 81-3-3607-5144
USA:
www.sumida.com
V
• VOUT(MAX) – V
IN(MIN)
(
)
3
f
IN(MIN)
TDK
(847) 803-6100 (847) 803-6296 www.component.tdk.com
(847) 297-0070 (847) 669-7864 www.toko.com
L > and L >
TOKO
f •Ripple • VOUT(MAX)
3421f
11
LTC3421
W U U
U
APPLICATIO S I FOR ATIO
Output Capacitor Selection
Operating Frequency Selection
The output voltage ripple has two components to it. The
bulk value of the capacitor is set to reduce the ripple due
to charge into the capacitor each cycle. The maximum
ripple due to charge is given by:
Thereareseveralconsiderationsinselectingtheoperating
frequency of the converter. The first is, which are the sen-
sitive frequency bands that cannot tolerate any spectral
noise? Thesecondconsiderationisthephysicalsizeofthe
converter. As the operating frequency goes up, the induc-
torandfiltercapacitorsgodowninvalueandsize.Thetrade
off is in efficiency since the switching losses due to gate
charge are going up proportional with frequency.
IP • V
COUT • VOUT • f
IN
VRBULK
=
where IP = peak inductor current.
Another operating frequency consideration is whether the
application can allow “pulse skipping.” In this mode, the
minimumontimeoftheconvertercannotsupporttheduty
cycle, so the converter ripple will go up and there will be
a low frequency component of the output ripple. In many
applications where physical size is the main criterion,
running the converter in this mode is acceptable. In appli-
cations where it is preferred not to enter this mode, the
maximum operating frequency is given by:
The ESR (equivalent series resistance) is usually the most
dominant factor for ripple in most power converters. The
ripple due to capacitor ESR is simply given by:
V
RCESR = IP • CESR
where CESR = capacitor series resistance.
Low ESR capacitors should be used to minimize output
voltage ripple. For surface mount applications, AVX TPS
seriestantalumcapacitors,SanyoPOSCAPorTaiyoYuden
ceramic capacitors are recommended. For through-hole
applications, Sanyo OS-CON capacitors offer low ESR in a
small package size.
VOUT – V
IN
fMAX_NOSKIP
=
Hz
VOUT • tON(MIN)
where tON(MIN) = minimum on time = 120ns.
Insomelayoutsitmaybenecessarytoplacea1µFlowESR
ceramic capacitor as close to the VOUT and GND pins as
possible.
Thermal Considerations
To deliver the power that the LTC3421 is capable of, it is
imperative that a good thermal path be provided to
dissipate the heat generated within the package. This can
beaccomplishedbytakingadvantageofthelargethermal
padontheundersideoftheIC.Itisrecommendedthatmul-
tiple vias in the printed circuit board be used to conduct
heatawayfromtheICandintoacopperplanewithasmuch
area as possible. In the event that the junction tempera-
turegetstoohigh,thepeakcurrentlimitwillautomatically
bedecreased.Ifthejunctiontemperaturecontinuestorise,
the part will go into thermal shutdown, and all switching
will stop until the temperature drops.
Input Capacitor Selection
The input filter capacitor reduces peak currents drawn
from the input source and reduces input switching noise.
Since the IC can operate at voltages below 0.5V once the
output is regulated, the demand on the input capacitor is
much less. In most applications 1µF per amp of peak input
currentisrecommended.TaiyoYudenoffersverylowESR
ceramic capacitors, for example the 1µF in a 0603 case
(JMK107BJ105MA).
Table 2. Capacitor Vendor Information
SUPPLIER PHONE
FAX
WEB SITE
AVX
(803) 448-9411 (803) 448-1943 www.avxcorp.com
(619) 661-6322 (619) 661-1055 www.sanyovideo.com
(847) 803-6100 (847) 803-6296 www.component.tdk.com
VIN > VOUT Operation
Sanyo
TDK
The LTC3421 will maintain voltage regulation when the
input voltage is above the output voltage. This is achieved
by terminating the switching on the synchronous PMOS
and applying VIN statically on the gate. This will ensure the
Murata
USA:
USA:
www.murata.com
(814) 237-1431 (814) 238-0490
(800) 831-9172
Taiyo Yuden (408) 573-4150 (408) 573-4159 www.t-yuden.com
3421f
12
LTC3421
W U U
APPLICATIO S I FOR ATIO
U
volts • seconds of the inductor will reverse during the time
current is flowing to the output. Since this mode will
dissipate more power in the IC, the maximum output
current is limited in order to maintain an acceptable
junction temperature.
Closing the Feedback Loop
The LTC3421 uses current mode control with internal
adaptiveslopecompensation.Currentmodecontrolelimi-
nates the 2nd order filter due to the inductor and output
capacitor exhibited in voltage mode controllers, and sim-
plifies it to a single pole filter response. The product of the
modulator control to output DC gain and the error amp
open-loop gain gives the DC gain of the system:
125 – TA
IOUT(MAX)
=
40 • V + 1.5 – V
(
(
)
)
IN
OUT
where TA = ambient temperature.
VREF
VOUT
G
DC = GCONTROL_OUTPUT •GEA •
For example at VIN = 4.5V and VOUT = 3.3V, the maximum
output current is 370mA.
2 • V
IN , GEA ≈ 2000
IOUT
GCONTROL
=
Short Circuit
The output filter pole is given by:
TheLTC3421outputdisconnectfeatureallowsoutputshort
circuit while maintaining a maximum set current limit. The
IC has incorporated internal features such as current limit
and thermal shutdown for protection from an excessive
overloadorshortcircuit. Inapplicationsthatrequireapro-
longed short circuit, it is recommended to limit the power
dissipation in the IC to maintain an acceptable junction
temperature. ThecircuitinFigure2willlimitthemaximum
current during a prolonged short by reducing the current
limit value in a short circuit by disconnecting R2 with the
N-channel MOSFET switch. R3 and C1 provide a soft-start
function after a short circuit. Resistor R1 lowers the cur-
rent limit value as VIN rises, maintaining a relatively con-
stant power. The current limit equation for the circuit in
Figure 2 is given by:
IOUT
π • VOUT •COUT
fFILTER_POLE
=
where COUT is the output filter capacitor.
The output filter zero is given by:
1
fFILTER_ZERO
=
2 • π •RESR •COUT
where RESR is the capacitor equivalent series resistance.
A troublesome feature of the boost regulator topology is
the right-half plane zero (RHP) and is given by:
2
V
IN
fRHPZ
=
2 • π •IOUT •L
0.6 V – 0.6
IN
At heavy loads this gain increase with phase lag can occur
at a relatively low frequency. The loop gain is typically
rolled off before the RHP zero frequency.
ILIMIT
=
–
• 250
RLIM
R1
where ILIMIT is in Amps; RLIM and R1 are in kΩ.
The typical error amp compensation is shown in Figure 3.
The equations for the loop dynamics are as follows:
TO V
IN
I
LIM
R1
1M
8
1
R3
10k
fPOLE1
fZERO1
fPOLE2
≈
which is extremely close to DC
2 • π • 20e6 •CC1
VN2222
TO V
OUT
1
R
R2
50k
C1
0.1µF
≈
LIM
100k
2 • π •RZ •CC1
1
2 • π •RZ •CC2
3421 F02
≈
Figure 2. Current Limit Foldback Circuit for
Extended Short Conditions
3421f
13
LTC3421
W U U
U
APPLICATIO S I FOR ATIO
V
OUT
1.22V
+
–
R1
ERROR
AMP
FB
1
R2
V
C
24
C
Z
C
C2
C1
R
3421 F03
Figure 3
U
TYPICAL APPLICATIO
5V Applications
output will provide a peak efficiency improvement but will
negate the output disconnect feature. If output disconnect
is required, the Schottky to an active snubber network is
suggested as shown in Figure 4.
When the output voltage is programmed above 4.3V it is
necessary to add a Schottky diode either from SW to
VOUT, or to a snubber network in order to maintain an
acceptable peak voltage on SW. The Schottky to the
L1
3µH
D1*
V
IN
2.7V TO
4.2V
Li-Ion to 5V Efficiency
C6*
M1
100
1µF
C1*
2
21
14 15 16
90
10µF
V
IN
V
IN
V
IN
= 4.2V
= 3.6V
= 2.7V
SHDN
V
SW SW SW
V
IN
V
5V
1A
OUT
Burst Mode
OPERATION
18
17
19
20
1
4
3
80
70
60
50
40
30
20
10
0
ENB
OUTS
V
REF
V
V
V
OUT
OUT
R5
23
22
7
+
LBI
1.13M
Li-Ion
LBO
SYNC
LTC3421
OUT
FB
C5*
22µF
×2
24
9
8
I
V
C
LIM
C4
470pF
BURST
GND PGND PGNDPGND
10 11 12 13
C3
0.1µF
R1
60k
V
= 5V
= 1MHz
OUT
OSC
SS
6
R
T
R6
365k
R3
10k
f
5
0.1
1
10
100
1000
R4
100k
C2
0.1µF
R2
28k
OUTPUT CURRENT (mA)
3421 G03
3421 F04
*LOCATE COMPONENTS CLOSE TO PINS
C1: TAIYO YUDEN JMK212BJ106MM
C5: TAIYO YUDEN JMK325BJ226MM
D1: MOTOROLA MBR0520L
L1: SUMIDA CDRH6D28-3R0
M1: ZETEX ZXM61P025
Figure 4. Lithium-Ion to 5V at 1A Application with an Active Snubber Circuit
3421f
14
LTC3421
U
PACKAGE DESCRIPTIO
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
0.70 ±0.05
4.50 ± 0.05
3.10 ± 0.05
2.45 ± 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
0.23 TYP
(4 SIDES)
R = 0.115
TYP
0.75 ± 0.05
4.00 ± 0.10
(4 SIDES)
23 24
PIN 1
TOP MARK
(NOTE 5)
0.38 ± 0.10
1
2
2.45 ± 0.10
(4-SIDES)
(UF24) QFN 0603
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
3421f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LTC3421
U
TYPICAL APPLICATIO
Single Cell to 3.3V at 500mA with Secondary Cell Backup During Shutdown. LOWBAT and VREF Output are Enabled
L1
4.7µH
D1
V
IN
1V TO 1.5V
+
3V
C1*
2
21
14 15 16
SW SW SW
SECONDARY CELL
4.7µF
SHDN
V
IN
V
OUT
4
3
18
17
19
20
1
0.1µF
3.3V
ENB
V
OUTS
301k
604k
500mA
V
V
V
V
REF
OUT
OUT
R5
340k
23
22
7
LBI
+
1 CELL
PRIMARY CELL
LOW BAT
OUTPUT
LBO
SYNC
LTC3421
OUT
FB
C5*
22µF
8
24
9
I
V
C
LIM
C4
R6
200k
BURST
GND PGND PGNDPGND
10 11 12 13
470pF
R1
60k
SS
6
R
T
R3
40k
R4
100k
5
C2
0.1µF
R2
28k
C3
0.1µF
3421 TA05
*LOCATE COMPONENTS CLOSE TO PINS
C1: TAIYO YUDEN JMK212BJ106MM
C5: TAIYO YUDEN JMK325BJ226MM
L1: TOKO A916CY-4R7M
Single Cell to 3.3V Efficiency
100
90
80
70
60
50
40
30
20
10
0
V
= 1.5V
IN
Burst Mode OPERATION
V
IN
= 1.2V
V
= 1V
IN
V
= 3.3V
= 1MHz
OUT
OSC
f
0.1
1
10
100
1000
OUTPUT CURRENT (mA)
3421 G01
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1371/LT1371HV
3A (I ), 500kHz, High Efficiency Step-Up DC/DC
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V : 2.7V to 30V, V
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: 35V/42V, I : 4mA, I : <12µA,
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IN
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SD
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IN
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1A (I ), 3MHz, Synchronous Step-Up DC/DC Converter
97% Efficiency, V : 0.5V to 5V, V
: 5.5V, I : 38µA,
Q
SW
IN
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I
: <1µA, MS10
SD
LTC3402
2A (I ), 3MHz, Synchronous Step-Up DC/DC Converter
97% Efficiency, V : 0.5V to 5V, V
: 5.5V, I : 38µA,
OUT(MAX) Q
SW
IN
I
: <1µA, MS10
SD
LTC3425
5A (I ), 8MHz, 4-Phase Synchronous Step-Up
DC/DC Converter
95% Efficiency, V : 0.5V to 4.5V, V
8MHz, Low Ripple in QFN
: 5.25V, I : 12µA,
OUT(MAX) Q
SW
IN
3421f
LT/TP 1103 1K PRINTED IN USA
16 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2003
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