LTC3561EDD#PBF [Linear]
LTC3561 - 1A, 4MHz, Synchronous Step-Down DC/DC Converter; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C;
| 型号： | LTC3561EDD#PBF |
| 厂家： | 
Linear |
| 描述： | LTC3561 - 1A, 4MHz, Synchronous Step-Down DC/DC Converter; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C 开关 光电二极管 |
| 文件： | 总16页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3561
1A, 4MHz, Synchronous
Step-Down DC/DC Converter
U
FEATURES
DESCRIPTIO
■
Uses Tiny Capacitors and Inductor
The LTC®3561 is a constant-frequency, synchronous,
step-down DC/DC converter. Intended for medium power
applications,itoperatesfroma2.63Vto5.5Vinputvoltage
range and has a user configurable operating frequency up
to 4MHz, allowing the use of tiny, low cost capacitors and
inductors 2mm or less in height. The output voltage is
adjustable from 0.8V to 5V. Internal synchronous 0.11Ω
power switches with 1.4A peak current ratings provide
high efficiency. The LTC3561’s current mode architecture
and external compensation allow the transient response
to be optimized over a wide range of loads and output
capacitors.
■
High Frequency Operation: Up to 4MHz
■
High Switch Current: 1.4A
■
Low RDS(ON) Internal Switches: 0.110Ω
■
High Efficiency: Up to 95%
■
VIN: 2.63V to 5.5V
■
Stable with Ceramic Capacitors
■
Current Mode Operation for Excellent Line
and Load Transient Response
Short-Circuit Protected
■
■
Low Dropout Operation: 100% Duty Cycle
■
Low Shutdown Current: IQ ≤ 1µA
■
Low Quiescent Current: 240µA
To further maximize battery life, the P-channel MOSFET is
turned on continuously in dropout (100% duty cycle). The
no-load quiescent current is only 240µA. In shutdown, the
device draws <1µA.
■
Output Voltages from 0.8V to 5V
■
Low Noise Pulse-Skipping Operation
■
Small 8-Pin DFNUPackage
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents,
including 5481178, 6127815, 6304066, 6498466, 6580258, 6611131.
APPLICATIO S
■
Wireless LAN Power
Notebook Computers
Digital Cameras
Cellular Phones
■
■
■
■
Board Mounted Power Supplies
U
TYPICAL APPLICATIO
Step-Down 2.5V/1A Regulator
Efficiency and Power Loss vs Load Current
V
IN
2.63V TO 5.5V
100
95
90
85
80
75
70
65
60
55
50
1000
EFFICIENCY
22µF
PV
IN
100
SV
IN
2.2µH
V
LTC3561
OUT
2.5V/1A
I
SW
TH
POWER LOSS
887k
22µF
SHDN/R
V
FB
T
10
1
13k
1000pF
SGND
PGND
324k
V
V
= 3.3V
412k
IN
OUT
= 1MHz
= 2.5V
f
O
3561 F01
NOTE: IN DROPOUT, THE OUTPUT TRACKS
THE INPUT VOLTAGE.
10
100
LOAD CURRENT (mA)
1000
3561 TA01
3561f
1
LTC3561
W W U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
PVIN, SVIN Voltages .....................................–0.3V to 6V
VFB, SHDN/RT Voltages ................ –0.3V to (VIN + 0.3V)
ITH Voltage................................................–0.3V to 1.4V
SW Voltage ................................... –0.3V to (VIN + 0.3V)
Operating Ambient Temperature Range
SHDN/R
1
2
3
4
8
7
6
5
I
TH
T
SGND
SW
V
FB
9
SV
IN
IN
PGND
PV
(Note 2) .................................................. –40°C to 85°C
Junction Temperature (Notes 5, 8) ....................... 125°C
Storage Temperature Range ................. –65°C to 125°C
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W, θJC = 3°C/W
EXPOSED PAD (PIN 9) MUST BE SOLDERED TO GROUND
DD PART MARKING
LCJJ
ORDER PART NUMBER
LTC3561EDD
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T = 25°C. V = 3.3V, R = 324k unless otherwise specified. (Note 2)
A
IN
T
SYMBOL
PARAMETER
CONDITIONS
MIN
2.625
TYP
MAX
5.5
±0.1
0.816
0.2
UNITS
V
µA
V
%/V
%
%
V
IN
Operating Voltage Range
Feedback Pin Input Current
Feedback Voltage
Reference Voltage Line Regulation
Output Voltage Load Regulation
I
(Note 3)
(Note 3)
FB
V
FB
●
0.784
0.8
0.04
0.02
–0.02
∆V
∆V
V
IN
= 2.7V to 5V
LINEREG
I
I
= 0.36, (Note 3)
= 0.84, (Note 3)
●
●
0.2
–0.2
LOADREG
TH
TH
g
Error Amplifier Transconductance
I
Pin Load = ±5µA (Note 3)
800
µS
m(EA)
TH
I
Input DC Supply Current (Note 4)
Active Mode
Shutdown
S
V
V
= 0.75V
SHDN/RT
240
0.1
350
1
µA
µA
FB
= 3.3V
V
Shutdown Threshold High
Active Oscillator Resistor
V
– 0.6 V – 0.4
V
Ω
SHDN/RT
IN
IN
324k
1M
f
Oscillator Frequency
R = 324k
0.85
1.4
1
1.15
4
MHz
MHz
OSC
T
(Note 7)
I
R
Peak Switch Current Limit
I
= 1.3
TH
1.7
0.11
0.11
0.01
2.5
A
Ω
Ω
µA
V
LIM
Top Switch On-Resistance (Note 6)
Bottom Switch On-Resistance (Note 6)
Switch Leakage Current
V
IN
V
IN
V
IN
V
IN
= 3.3V
= 3.3V
= 6V, V
0.15
0.15
1
DS(ON)
I
V
= 0V, V = 0V
FB
SW(LKG)
ITH/RUN
Undervoltage Lockout Threshold
Ramping Down
2.375
2.625
UVLO
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. No pin shall exceed 6V.
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: The LTC3561 is tested in a feedback loop which servos V to the
FB
midpoint for the error amplifier (V = 0.6V).
ITH
Note 2: The LTC3561E is guaranteed to meet specified performance from
0°C to 85°C. Specifications over the –40°C to 85°C operating ambient
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
3561f
2
LTC3561
ELECTRICAL CHARACTERISTICS
Note 8: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 5: T is calculated from the ambient T and power dissipation P
J
A
D
according to the following formula:
LTC3561EDD: T = T + (P • 43°C/W)
J
A
D
Note 6: Switch on-resistance is guaranteed by correlation to wafer level
measurements.
Note 7: 4MHz operation is guaranteed by design but not production tested
and is subject to duty cycle limitations (see Applications Information).
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs V
Load Step
Switching Waveforms
IN
100
95
90
85
80
75
70
65
60
I
= 0.4A
= 1.0A
OUT
OUT
VOUT
100mV/
DIV
VOUT
10mV/
DIV
I
IL1
0.4A/
DIV
IL1
100mA/
DIV
VIN = 3.3V
VOUT = 2.5V
ILOAD = 50mA
2µs/DIV
3561 G02.eps
VIN = 3.3V
VOUT = 2.5V
ILOAD = 0.20A TO 1A
CIRCUIT OF FIGURE 6
40µs/DIV
3561 G06.eps
V
= 2.5V
OUT
CIRCUIT OF FIGURE 6
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
CIRCUIT OF FIGURE 6
V
IN
(V)
3561 G05
Load Regulation
Line Regulation
Frequency vs V
IN
0.4
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
10
V
V
= 3.3V
OUT
V
T
= 1.8V
V
I
A
= 1.8V
= 1A
IN
OUT
A
OUT
OUT
= 25°C
8
6
0.3
0.2
= 2.5V
= 25°C
T
4
0.1
2
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–2
–4
–6
–8
–10
I
= 1.0A
OUT
I
= 400mA
OUT
1
10
100
1000
10000
2
3
4
5
6
2
3
4
5
6
LOAD CURRENT (mA)
V
(V)
V
(V)
IN
IN
3561 G07
3561 G08
3561 G09
3561f
3
LTC3561
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TYPICAL PERFOR A CE CHARACTERISTICS
Frequency Variation
vs Temperature
Efficiency vs Frequency
R
vs V
IN
DS(ON)
10
8
100
95
120
115
110
105
100
95
V
= 3.3V
T
= 25°C
IN
V
A
= 2.5V
OUT
OUT
A
I
= 500mA
= 25°C
6
T
4
SYNCHRONOUS SWITCH
2
0
–2
–4
–6
–8
–10
MAIN SWITCH
90
85
90
2.5
0
1
2
3
4
–50 –25
0
25
50
75 100 125
3
3.5
4
4.5
(V)
5
5.5
6
FREQUENCY (MHz)
TEMPERATURE (°C)
V
IN
3561 G10
3561 G12
3561 G11
U
U
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PI FU CTIO S
SHDN/RT (Pin 1): Combination Shutdown and Timing
Resistor Pin. The oscillator frequency is programmed by
connecting a resistor from this pin to ground. Forcing this
pin to SVIN causes the device to be shut down. In
shutdown all functions are disabled.
PVIN (Pin 5): Main Supply Pin. Must be closely decoupled
to PGND.
SVIN (Pin 6): The Signal Power Pin. All active circuitry is
powered from this pin. Must be closely decoupled to
SGND. SVIN must be greater than or equal to PVIN.
SGND (Pin 2): The Signal Ground Pin. All small signal
components and compensation components should be
connected to this ground (see Board Layout
Considerations).
VFB (Pin 7): Receives the feedback voltage from the
external resistive divider across the output. Nominal
voltage for this pin is 0.8V.
ITH (Pin 8): Error Amplifier Compensation Point. The
current comparator threshold increases with this control
voltage. Nominal voltage range for this pin is 0V to 1.5V.
SW (Pin 3): The Switch Node Connection to the Inductor.
This pin swings from PVIN to PGND.
PGND (Pin 4): Main Power Ground Pin. Connect to the
(–) terminal of COUT, and (–) terminal of CIN.
Exposed Pad (Pin 9): Thermal Connection to PCB. This
pin should be soldered to ground to achieve rated
thermal performance.
3561f
4
LTC3561
W
BLOCK DIAGRA
SV
SGND
2
I
PV
IN
IN
TH
6
8
5
PMOS CURRENT
COMPARATOR
0.8V
VOLTAGE
REFERENCE
I
TH
LIMIT
+
–
+
–
–
+
7
V
FB
ERROR
AMPLIFIER
V
B
SLOPE
COMPENSATION
3
SW
OSCILLATOR
+
–
LOGIC
NMOS
COMPARATOR
+
–
4
PGND
REVERSE
COMPARATOR
1
SHDN/R
3561 BD
T
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OPERATIO
The LTC3561 uses a constant frequency, current mode
architecture. The operating frequency is determined by
the value of the RT resistor.
low load currents, the inductor current becomes discontinu-
ous, and pulses may be skipped to maintain regulation.
ThemaincontrolloopisshutdownbypullingtheSHDN/RT
pin to SVIN. A digital soft-start is enabled after shutdown,
which will slowly ramp the peak inductor current up over
1024 clock cycles or until the output reaches regulation,
whicheverisfirst.Soft-startcanbelengthenedbyramping
the voltage on the ITH pin (see Applications Information
section).
The output voltage is set by an external divider returned to
the VFB pin. An error amplifier compares the divided
outputvoltagewithareferencevoltageof0.8Vandadjusts
the peak inductor current accordingly.
Main Control Loop
Duringnormaloperation,thetoppowerswitch(P-channel
MOSFET) is turned on at the beginning of a clock cycle
when the VFB voltage is below the reference voltage. The
current into the inductor and the load increases until the
current limit is reached. The switch turns off and energy
storedintheinductorflowsthroughthebottomswitch(N-
channel MOSFET) into the load until the next clock cycle.
Dropout Operation
When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100% which is
the dropout condition. In dropout, the PMOS switch is
turned on continuously with the output voltage being
equal to the input voltage minus the voltage drops across
the internal P-channel MOSFET and the inductor.
The peak inductor current is controlled by the voltage on
the ITH pin, which is the output of the error amplifier. This
amplifier compares the VFB pin to the 0.8V reference.
When the load current increases, the VFB voltage de-
creasesslightlybelowthereference.Thisdecreasecauses
the error amplifier to increase the ITH voltage until the
average inductor current matches the new load current. At
Low Supply Operation
TheLTC3561incorporatesanundervoltagelockoutcircuit
which shuts down the part when the input voltage drops
below about 2.5V to prevent unstable operation.
3561f
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LTC3561
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APPLICATIO S I FOR ATIO
A general LTC3561 application circuit is shown in
Figure 4. External component selection is driven by the
load requirement, and begins with the selection of the
inductor L1. Once L1 is chosen, CIN and COUT can be
selected.
Themaximumusableoperatingfrequencyislimitedbythe
minimum on-time and the duty cycle. This can be calcu-
lated as:
fO(MAX) ≈ 6.67 • (VOUT / VIN(MAX)) (MHz)
The minimum frequency is limited by leakage and noise
coupling due to the large resistance of RT.
Operating Frequency
Selection of the operating frequency is a tradeoff between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
Inductor Selection
Although the inductor does not influence the operating
frequency, the inductor value has a direct effect on ripple
current. The inductor ripple current ∆IL decreases with
higher inductance and increases with higher VIN or VOUT
:
⎛
⎞
VOUT
fO•L
VOUT
VIN
∆IL =
• 1−
Theoperatingfrequency, fO, oftheLTC3561isdetermined
by an external resistor that is connected between the RT
pin and ground. The value of the resistor sets the ramp
current that is used to charge and discharge an internal
timingcapacitorwithintheoscillatorandcanbecalculated
by using the following equation:
⎜
⎟
⎠
⎝
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple,
greater core losses, and lower output current capability.
A reasonable starting point for setting ripple current is
∆IL = 0.4 × IOUT(MAX), where IOUT(MAX) is 1A. The largest
ripplecurrent∆IL occursatthemaximuminputvoltage.To
guarantee that the ripple current stays below a specified
maximum, theinductorvalueshouldbechosenaccording
to the following equation:
−1.08
RT = 9.78•1011
f
Ω
( )
( O)
or can be selected using Figure 1.
4.5
T
= 25°C
A
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
⎛
⎞
VOUT
fO• ∆IL
VOUT
VIN(MAX)
L =
• 1−
⎜
⎟
⎝
⎠
Inductor Core Selection
Different core materials and shapes will change the size/
current and price/current relationship of an inductor. Tor-
oid or shielded pot cores in ferrite or permalloy materials
are small and do not radiate much energy, but generally
cost more than powdered iron core inductors with similar
electrical characteristics. The choice of which style induc-
tor to use often depends more on the price vs size require-
ments and any radiated field/EMI requirements than on
whattheLTC3561requirestooperate.Table1showssome
typical surface mount inductors that work well in LTC3561
applications.
0
0
500
1500
1000
R
(kΩ)
T
3561 F02
Figure 1. Frequency vs R
T
3561f
6
LTC3561
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APPLICATIO S I FOR ATIO
Table 1. Representative Surface Mount Inductors
Output Capacitor (COUT) Selection
MANU-
FACTURER PART NUMBER
MAX DC
The selection of COUT is driven by the required ESR to
minimizevoltagerippleandloadsteptransients.Typically,
once the ESR requirement is satisfied, the capacitance is
adequate for filtering. The output ripple (∆VOUT) is deter-
mined by:
VALUE CURRENT DCR HEIGHT
Toko
A914BYW-2R2M-D52LC 2.2µH
2.05A 49mΩ 2mm
Coilcraft
Coilcraft
Sumida
D01608C-222
2.2µH
2.2µH
2.2µH
2.2µH
2.2µH
2.2µH
2.2µH
2.2µH
2.3A
70mΩ 3mm
LP01704-222M
CDRH2D18/HP-2R2
2.4A 120mΩ 1mm
1.6A
2.9A
3.2A
48mΩ 2mm
32mΩ 2.8mm
24mΩ 5mm
Taiyo Yuden N05DB2R2M
⎛
⎞
⎟
1
Murata
Cooper
TDK
LQN6C2R2M04
SD3112-2R2
∆VOUT ≈ ∆IL ESR +
⎜
8fOCOUT
⎝
⎠
1.1A 140mΩ 1.2mm
1.0A 100mΩ 1.0mm
VLF3010AT-2R2M1R0
B82470A1222M
where f = operating frequency, COUT = output capacitance
and ∆IL = ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆IL increases
with input voltage. With ∆IL = 0.3 • ILIM the output ripple
will be less than 100mV at maximum VIN and fO = 1MHz
with:
EPCO
1.6A
90mΩ 1.2mm
Input Capacitor (CIN) Selection
In continuous mode, the input current of the converter is
a square wave with a duty cycle of approximately VOUT
/
VIN. To prevent large voltage transients, a low equivalent
series resistance (ESR) input capacitor sized for the maxi-
mum RMS current must be used. The maximum RMS
capacitor current is given by:
ESRCOUT < 150mΩ
Once the ESR requirements for COUT have been met, the
RMS current rating generally far exceeds the IRIPPLE(P-P)
requirement, except for an all ceramic solution.
VOUT (V − VOUT
)
In surface mount applications, multiple capacitors may
havetobeparalleledtomeetthecapacitance, ESRorRMS
current handling requirement of the application. Alumi-
num electrolytic, special polymer, ceramic and dry tanta-
lum capacitors are all available in surface mount pack-
ages. The OS-CON semiconductor dielectric capacitor
available from Sanyo has the lowest ESR(size) product of
any aluminum electrolytic at a somewhat higher price.
Specialpolymercapacitors,suchasSanyoPOSCAP,offer
very low ESR, but have a lower capacitance density than
other types. Tantalum capacitors have the highest capaci-
tance density, but it has a larger ESR and it is critical that
the capacitors are surge tested for use in switching power
supplies. An excellent choice is the AVX TPS series of
surface mount tantalums, available in case heights rang-
ing from 2mm to 4mm. Aluminum electrolytic capacitors
have a significantly larger ESR, and is often used in
extremely cost-sensitive applications provided that con-
sideration is given to ripple current ratings and long term
reliability. Ceramic capacitors have the lowest ESR and
cost but also have the lowest capacitance density, a high
voltage and temperature coefficient and exhibit audible
IN
IRMS ≈ IMAX
V
IN
where the maximum average output current IMAX equals
the peak current minus half the peak-to-peak ripple cur-
rent, IMAX = ILIM – ∆IL/2.
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst case is commonly used
to design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple
current ratings are often based on only 2000 hours life-
time. This makes it advisable to further derate the capaci-
tor, or choose a capacitor rated at a higher temperature
thanrequired. Severalcapacitorsmayalsobeparalleledto
meet the size or height requirements of the design. An
additional 0.1µF to 1µF ceramic capacitor is also recom-
mended on VIN for high frequency decoupling, when not
using an all ceramic capacitor solution.
3561f
7
LTC3561
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APPLICATIO S I FOR ATIO
piezoelectric effects. In addition, the high Q of ceramic
capacitors along with trace inductance can lead to signifi-
cant ringing. Other capacitor types include the Panasonic
specialty polymer (SP) capacitors.
are required to respond to a load step, but only in the first
cycle does the output drop linearly. The output droop,
V
DROOP, is usually about 2 to 3 times the linear drop of the
first cycle. Thus, a good place to start is with the output
capacitor size of approximately:
In most cases, 0.1µF to 1µF of ceramic capacitors should
also be placed close to the LTC3561 in parallel with the
main capacitors for high frequency decoupling.
∆IOUT
COUT ≈ 2.5
fO •VDROOP
Ceramic Input and Output Capacitors
More capacitance may be required depending on the duty
cycle and load step requirements.
Higher value, lower cost ceramic capacitors are now
becomingavailableinsmallercasesizes.Thesearetempt-
ing for switching regulator use because of their very low
ESR. Unfortunately, the ESR is so low that it can cause
loop stability problems. Solid tantalum capacitor ESR
generatesaloop“zero”at5kHzto50kHzthatisinstrumen-
tal in giving acceptable loop phase margin. Ceramic ca-
pacitors remain capacitive to beyond 300kHz and usually
resonate with their ESL before ESR becomes effective.
Also, ceramic caps are prone to temperature effects which
requires the designer to check loop stability over the
operating temperature range. To minimize their large
temperature and voltage coefficients, only X5R or X7R
ceramic capacitors should be used. A good selection of
ceramiccapacitorsisavailablefromTaiyoYuden,TDKand
Murata.
In most applications, the input capacitor is merely re-
quired to supply high frequency bypassing, since the
impedance to the supply is very low. A 10µF ceramic
capacitor is usually enough for these conditions.
Setting the Output Voltage
The LTC3561 develops a 0.8V reference voltage between
the feedback pin, VFB, and the signal ground as shown in
Figure 4. The output voltage is set by a resistive divider
according to the following formula:
R2
R1
⎛
⎝
⎞
⎟
⎠
VOUT ≈ 0.8V 1+
⎜
Keeping the current small (<5µA) in these resistors maxi-
mizes efficiency, but making them too small may allow
stray capacitance to cause noise problems and reduce the
phase margin of the error amp loop.
Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires,suchasfromawalladapter,aloadstepattheoutput
can induce ringing at the VIN pin. At best, this ringing can
couple to the output and be mistaken as loop instability. At
worst, the ringing at the input can be large enough to
damage the part.
To improve the frequency response, a feed-forward ca-
pacitor CF may also be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement.Duringaloadstep,theoutputcapacitormust
instantaneously supply the current to support the load
untilthefeedbackloopraisestheswitchcurrentenoughto
support the load. The time required for the feedback loop
to respond is dependent on the compensation compo-
nentsandtheoutputcapacitorsize. Typically, 3to4cycles
Shutdown and Soft-Start
The SHDN/RT pin is a dual purpose pin that sets the
oscillator frequency and provides a means to shut down
the LTC3561. This pin can be interfaced with control logic
in several ways, as shown in Figure 2(a) and Figure 2(b).
The ITH pin is primarily for loop compensation, but it can
also be used to increase the soft-start time. Soft-start
3561f
8
LTC3561
U
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APPLICATIO S I FOR ATIO
done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because the various types and values determine
theloopfeedbackfactorgainandphase. Anoutputcurrent
pulseof20%to100%offullloadcurrenthavingarisetime
of 1µs to 10µs will produce output voltage and ITH pin
waveforms that will give a sense of the overall loop
stability without breaking the feedback loop.
reduces surge currents from VIN by gradually increasing
the peak inductor current. Power supply sequencing can
also be accomplished using this pin. The LTC3561 has an
internal digital soft-start which steps up a clamp on ITH
over 1024 clock cycles, as can be seen in Figure 3.
The soft-start time can be increased by ramping the
voltage on ITH during start-up as shown in Figure 2(c). As
the voltage on ITH ramps through its operating range the
internal peak current limit is also ramped at a proportional
linear rate.
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, VOUT
immediately shifts by an amount equal to ∆ILOAD • ESR,
Checking Transient Response
where ESR is the effective series resistance of COUT
.
∆ILOAD also begins to charge or discharge COUT generat-
The OPTI-LOOP compensation allows the transient re-
sponse to be optimized for a wide range of loads and
output capacitors. The availability of the ITH pin not only
allows optimization of the control loop behavior but also
provides a DC coupled and AC filtered closed loop re-
sponsetestpoint.TheDCstep,risetimeandsettlingatthis
test point truly reflects the closed loop response. Assum-
ing a predominantly second order system, phase margin
and/ordampingfactorcanbeestimatedusingthepercent-
age of overshoot seen at this pin. The bandwidth can also
be estimated by examining the rise time at the pin.
ing a feedback error signal used by the regulator to return
V
V
OUT to its steady-state value. During this recovery time,
OUT canbemonitoredforovershootorringingthatwould
indicate a stability problem.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phase margin. The gain of the loop increases with R and
the bandwidth of the loop increases with decreasing C. If
R is increased by the same factor that C is decreased, the
zero frequency will be kept the same, thereby keeping the
phase the same in the most critical frequency range of the
feedback loop. In addition, a feedforward capacitor CF can
be added to improve the high frequency response, as
shown in Figure 5. Capacitor CF provides phase lead by
creatingahighfrequencyzerowithR2whichimprovesthe
phase margin.
The ITH external components shown in the front page
circuit will provide an adequate starting point for most
applications. The series R-C filter sets the dominant pole-
zero loop compensation. The values can be modified
slightly (from 0.5 to 2 times their suggested values) to
optimize transient response once the final PC layout is
SHDN/R
SHDN/R
SV
IN
T
T
R
T
R
T
1M
VIN
2V/DIV
RUN
RUN
TH
3561 F03a
3561 F03b
VOUT
2V/DIV
(2a)
(2b)
RUN OR V
I
IN
IL
R1
R
C
D1
500mA/DIV
VIN = 3.3V
VOUT = 2.5V
RL = 1.4Ω
C1
C
C
3561 F03c
200µs/DIV
3411 F04.eps
(2c)
Figure 2. SHDN/R Pin Interfacing and External Soft-Start
Figure 3. Digital Soft-Start
T
3561f
9
LTC3561
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APPLICATIO S I FOR ATIO
produce the most improvement. Percent efficiency can be
expressed as:
The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance. For a detailed
explanation of optimizing the compensation components,
including a review of control loop theory, refer to Linear
Technology Application Note 76.
%Efficiency = 100% – (L1 + L2 + L3 + ...)
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3561 circuits: 1) LTC3561 VIN current,
2) switching losses, 3) I2R losses, 4) other losses.
Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
input voltage VIN drops toward VOUT, the load step capa-
bility does decrease due to the decreasing voltage across
the inductor. Applications that require large load step
capability near dropout should use a different topology
such as SEPIC, Zeta or single inductor, positive buck/
boost.
1) The VIN current is the DC supply current given in the
electricalcharacteristicswhichexcludesMOSFETdriver
and control currents. VIN current results in a small
(<0.1%) loss that increases with VIN, even at no load.
In some applications, a more severe transient can be
caused by switching in loads with large (>1uF) input
capacitors.Thedischargedinputcapacitorsareeffectively
put in parallel with COUT, causing a rapid drop in VOUT. No
regulator can deliver enough current to prevent this
problem, if the switch connecting the load has low resis-
tanceandisdrivenquickly.Thesolutionistolimittheturn-
on speed of the load switch driver. A hot swap controller
is designed specifically for this purpose and usually incor-
poratescurrentlimiting, short-circuitprotection, andsoft-
starting.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current re-
sults from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from VIN to ground. The resulting dQ/dt is a current out
of VIN that is typically much larger than the DC bias
current. In continuous mode, IGATECHG = fO(QT + QB),
whereQTandQBarethegatechargesoftheinternaltop
and bottom MOSFET switches. The gate charge losses
are proportional to VIN and thus their effects will be
more pronounced at higher supply voltages.
3)I2RLossesarecalculatedfromtheDCresistancesofthe
internal switches, RSW, and external inductor, RL. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the internal
top and bottom switches. Thus, the series resistance
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
V
IN
2.63V
+
TO 5.5V
R6
C6
C
IN
SV
IN
PV
SW
V
OUT
IN
L1
D1
PGND
PGND
C8
C
+
F
OPTIONAL
C
OUT
C5
LTC3561
PGND
I
TH
V
FB
PGND
PGND
R2
SGND PGND SHDN/R
R
C
T
R1
C
ITH
R
T
C
C
3561 F05
Figure 4. LTC3561 General Schematic
3561f
10
LTC3561
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APPLICATIO S I FOR ATIO
looking into the SW pin is a function of both top and
bottom MOSFET RDS(ON) and the duty cycle (DC) as
follows:
As an example, consider the case when the LTC3561 is in
dropout at an input voltage of 3.3V with a load current of
1A. From the Typical Performance Characteristics graph
of Switch Resistance, the RDS(ON) resistance of the
P-channel switch is 0.11Ω. Therefore, power dissipated
by the part is:
RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteris-
tics curves. Thus, to obtain I2R losses:
PD = I2 • RDS(ON) = 110mW
TheDD8packagejunction-to-ambientthermalresistance,
θJA, will be in the range of about 43°C/W. Therefore, the
junction temperature of the regulator operating in a 70°C
ambient temperature is approximately:
I2R losses = IOUT2(RSW + RL)
4) Other “hidden” losses such as copper trace and internal
battery resistances can account for additional efficiency
degradationsinportablesystems. Itisveryimportantto
include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that CIN has adequate
charge storage and very low ESR at the switching
frequency. Other losses including diode conduction
losses during dead-time and inductor core losses gen-
erally account for less than 2% total additional loss.
TJ = 0.11 • 43 + 70 = 74.7°C
Remembering that the above junction temperature is
obtained from an RDS(ON) at 25°C, we might recalculate
the junction temperature based on a higher RDS(ON) since
it increases with temperature. However, we can safely
assume that the actual junction temperature will not
exceed the absolute maximum junction temperature of
125°C.
Thermal Considerations
Design Example
In a majority of applications, the LTC3561 does not dissi-
pate much heat due to its high efficiency. However, in
applicationswheretheLTC3561isrunningathighambient
temperature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both power
switches will be turned off and the SW node will become
high impedance.
As a design example, consider using the LTC3561 in a
portable application with a Li-Ion battery (refer to Figure 4
for reference designation). The battery provides a VIN
=
2.5V to 4.2V. The load requires a maximum of 1A in active
mode and 10mA in standby mode. The output voltage is
V
OUT = 2.5V.
First, calculate the timing resistor:
−1.08
R = 9.78•1011 1MHz
= 323.8k
To avoid the LTC3561 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determinewhetherthepowerdissipatedexceedsthemaxi-
mum junction temperature of the part. The temperature
rise is given by:
(
)
T
Use a standard value of 324k. Next, calculate the inductor
value for about 40% ripple current at maximum VIN:
2.5V
2.5V
4.2V
⎛
⎞
L =
• 1−
= 2.5µH
⎜
⎟
⎠
⎝
1MHz • 400mA
TRISE = PD • θJA
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to the
ambient temperature.
Choosing the closest inductor from a vendor of 2.2µH,
results in a maximum ripple current of:
2.5V
1MHz •2.2µ
2.5V
4.2V
⎛
⎝
⎞
⎟
⎠
The junction temperature, TJ, is given by:
TJ = TRISE + TAMBIENT
∆IL
=
• 1−
= 460mA
⎜
3561f
11
LTC3561
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APPLICATIO S I FOR ATIO
For cost reasons, a ceramic capacitor will be used. COUT
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:
graphically in the layout diagram of Figure 5. Check
the following in your layout:
1. Does the capacitor CIN connect to the power VIN (Pin 5)
and power GND (Pin 4) as close as possible? This
capacitor provides the AC current to the internal power
MOSFETs and their drivers.
1A
COUT ≈ 2.5
= 20µF
1MHz •(5%•2.5V)
The closest standard value is 22µF. Since the output
impedance of a Li-Ion battery is very low, CIN is typically
10µF. In noisy environments, decoupling SVIN from PVIN
with an R6/C8 filter of 1Ω/0.1µF may help, but is typically
not needed.
2. Are the COUT and L1 closely connected? The (–) plate of
COUT returns current to PGND and the (–) plate of CIN.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of COUT and a ground line termi-
nated near SGND (Pin 2). The feedback signal VFB
should be routed away from noisy components and
traces, such as the SW line (Pin 3), and its trace should
be minimized.
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the
current in these resistors should be kept small. Choosing
2µA with the 0.8V feedback voltage makes R1~400k. A
close standard 1% resistor is 412k and R2 is then 887k.
4. Keep sensitive components away from the SW pin. The
input capacitor CIN, the compensation capacitor CC and
The compensation should be optimized for these compo-
nents by examining the load step response but a good
place to start for the LTC3561 is with a 13kΩ and 1000pF
filter. The output capacitor may need to be increased
depending on the actual undershoot during a load step.
C
ITH and all the resistors R1, R2, RT, and RC should be
routed away from the SW trace and the inductor L1.
5. Agroundplaneispreferred, butifnotavailable, keepthe
signal and power grounds segregated with small signal
components returning to the SGND pin at one point
which is then connected to the PGND pin.
The circuit in Figure 6 shows the complete schematic for
this design example.
6. Flood all unused areas on all layers with copper.
Floodingwithcopperwillreducethetemperatureriseof
power components. These copper areas should be
connected to one of the input supplies: PVIN, PGND,
SVIN or SGND.
Board Layout Considerations
When laying out the printed circuit board, the follow-
ing checklist should be used to ensure proper oper-
ation of the LTC3561. These items are also illustrated
C
IN
V
IN
C
OUT
PV
SV
PGND
SW
IN
L1
V
OUT
IN
LTC3561
V
SGND
FB
C4
R2
I
TH
SHDN/R
T
R1
R3
R
T
C3
3561 F06
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 5. LTC3561 Layout Diagram (See Board Layout Checklist)
3561f
12
LTC3561
U
TYPICAL APPLICATIO S
V
IN
2.63V TO
5.5V
C1
10µF
Efficiency vs Load Current
L1
PV
IN
100
90
80
70
60
50
40
30
20
10
0
2.2µH
V
OUT
SW
SV
1.8V/2.5V/3.3V
AT 1A
IN
R2 887K
LTC3561
V
FB
I
SHDN/R
TH
T
3.3V
2.5V
1.8V
C2
22µF
SGND
PGND
C4 22pF
R3
13k
R4
324k
R1A
280k
R1B
412k
R1C
698k
C3
1000pF
V
= 3.3V
IN
V
= 2.5V
OUT
NOTE: IN DROPOUT, THE OUTPUT TRACKS THE INPUT VOLTAGE
C1, C2: TAIYO YUDEN JMK325BJ226MM
L1: TOKO A914BYW-2R2M (D52LC SERIES)
f
= 1MHz
O
3561 F07a
1
10
100
1000
LOAD CURRENT (mA)
3561 F07b
Figure 6. General Purpose Buck Regulator Using Ceramic Capacitors
Small Footprint Buck
Efficiency and V
Ripple
OUT
C1
100
90
80
70
60
50
40
60
50
40
30
20
10
0
10µF
V
V
OUT
= 3.3V
IN
IN
2.63V
V
= 1.2V
TO 5.5V
PV
SV
PGND
SW
L1
2.2µH
IN
IN
D1
1.2V
AT 1.0A
LTC3561
C4
22pF
R2
C2
22µF
EFFICIENCY
V
SGND
FB
100k
I
SHDN/R
T
TH
R1
200k
R3
10k
R4
324k
V
RIPPLE
OUT
C3
470pF
1
10
100
1000
I
(mA)
LOAD
3561 TA03
3561 TA02
C1: AVX 06034D106M
C2: AVX 08054D226M
L1: SUMIDA CDRH2D18/HP-2R2
3561f
13
LTC3561
U
TYPICAL APPLICATIO S
All Ceramic 2-Cell to 3.3V and 1.8V Converters
V
IN
= 2V TO 3V
L1
4.7µH
D1
V
OUT
3.3V
120mA/1A
C5
LTC3402
10µF
V
SW
OUT
IN
1M
SHDN
V
+
SV
PV
IN
IN
2
L2
CELLS
MODE/SYNC FB
2.2µH
LTC3561
V
SW
OUT
I
TH
604k
1.8V/1A
PGOOD
V
C
C2
C6
22µF
887k
C1
10µF
1000pF
10pF
44µF
V
FB
R
T
GND
SHDN/R
(2 × 22µF)
T
13k
10pF
SGND
PGND
49.9k
47k
412k
324k
1000pF
3561 TA06
C1: TAIYO YUDEN JMK212BJ106MG
C2: TAIYO YUDEN JMK325BJ226MM
C5, C6: TAIYO YUDEN JMK325BJ226MM
D1: ON SEMICONDUCTOR MBRM120LT3
L1: TOKO A916CY-4R7M
L2: TOKO A914BYW-2R2M (D52LC SERIES)
0 = FIXED FREQ
1 = Burst Mode OPERATION
Efficiency and V
Ripple
OUT
100
90
80
70
60
50
40
V
= 2.4V
IN
3.3V
1.8V
1
10
100
1000
I
(mA)
LOAD
3561 TA07
3561f
14
LTC3561
U
PACKAGE DESCRIPTIO
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115
0.38 ± 0.10
TYP
5
8
0.675 ±0.05
3.5 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PACKAGE
OUTLINE
(DD8) DFN 1203
4
1
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.25 ± 0.05
0.50 BSC
0.50
BSC
2.38 ±0.05
(2 SIDES)
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
3561f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LTC3561
U
TYPICAL APPLICATIO
Efficiency vs Load Current
1mm Height, 2MHz, Li-Ion to 1.8V Converter
100
90
80
70
60
50
40
V
= 1.8V
OUT
V
IN
2.63V
PV
IN
V
OUT
TO 4.2V
SW
L1
1.8V
C1
AT 1A
SV
IN
10µF
C4 10pF
1µH
C2
3.6V
LTC3561
2 x 10µF
I
V
FB
TH
2.7V
R2
294k
R1
200k
R3
10k
C7
47pF
SGND PGND SHDN/R
T
4.2V
100
R4
154k
C3
1000pF
3561 TA04
1
10
I
1000
C1, C2: AVX 08056D106M
L1: TDK VLF3010ATIR5NIRZ
(mA)
LOAD
3561 TA05
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ThinSOT is a trademark of Linear Technology Corporation.
3561f
LT 0406 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
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© LINEAR TECHNOLOGY CORPORATION 2006
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