LTC3605AEUF#PBF [Linear]
LTC3605A - 20V, 5A Synchronous Step-Down Regulator; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C;
| 型号： | LTC3605AEUF#PBF |
| 厂家： | 
Linear |
| 描述： | LTC3605A - 20V, 5A Synchronous Step-Down Regulator; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C 开关 |
| 文件： | 总22页 (文件大小：414K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3605A
20V, 5A Synchronous
Step-Down Regulator
FeaTures
DescripTion
The LTC®3605A is a high efficiency, monolithic synchro-
nous buck regulator using a phase lockable controlled
on-time constant frequency, current mode architecture.
PolyPhase operation allows multiple LTC3605A regula-
tors to run out of phase while using minimal input and
output capacitance. The operating supply voltage range
is from 20V down to 4V, making it suitable for dual, triple
or quadruple lithium-ion battery inputs as well as point
of load power supply applications from a 12V or 5V rail.
n
High Efficiency: Up to 96%
n
5A Output Current
n
4V to 20V V Range
IN
n
Integrated Power N-Channel MOSFETs
(70mΩ Top and 35mΩ Bottom)
n
n
n
n
n
Adjustable Frequency 800kHz to 4MHz
PolyPhase® Operation (Up to 12 Phases)
Output Tracking
0.6V 1% Reference Accuracy
Current Mode Operation for Excellent Line and Load
Transient Response
Shutdown Mode Draws Less Than 15µA Supply Current
LTC3605: 15V Absolute Maximum V
LTC3605A: 22V Absolute Maximum V
The LTC3605A Is Pin Compatible with the LTC3605
Available in 24-Pin (4mm × 4mm) QFN Package
Theoperatingfrequencyisprogrammablefrom800kHzto
4MHz with an external resistor. The high frequency capa-
bility allows the use of small surface mount inductors. For
switching noise sensitive applications, it can be externally
synchronized from 800kHz to 4MHz. The PHMODE pin
allows user control of the phase of the outgoing clock
signal. The unique constant frequency/controlled on-time
architecture is ideal for high step-down ratio applications
that are operating at high frequency while demanding
fast transient response. Two internal phase-lock loops
synchronize the internal oscillator to the external clock
and also servos the regulator on-time to lock on to either
the internal clock or the external clock if it’s present.
n
n
n
n
n
IN
IN
applicaTions
n
Point of Load Power Supply
n
Portable Instruments
n
Distributed Power Systems
Battery-Powered Equipment
L, LT, LTC, LTM, PolyPhase, OPTI-LOOP, Linear Technology and the Linear logo are registered
trademarks of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Protected by U.S. Patents, including 5481178, 5847554, 6580258, 6304066,
6476589, 6774611.
n
Typical applicaTion
Efficiency and Power Loss
High Efficiency 1MHz, 5A Step-Down Regulator
100
90
10
1
V
= 3.3V
OUT
V
IN
4V TO 20V
80
22µF
×2
PV
SV
IN
IN
70
CLKOUT INTV
CC
60
50
2.2µF
1µH
CLKIN
BOOST
PGOOD
0.1µF
40
30
20
10
0
LTC3605A
V
OUT
SW
0.1
0.01
3.3V
V
11.5k
2.55k
ON
FB
47µF
V
RUN
V
V
V
= 8V
= 12V
= 20V
IN
IN
IN
IN
×2
ITH
RT
16k
PGND
0.01
0.1
1
10
162k
220pF
LOAD CURRENT (A)
3605A TA01b
3605A TA01a
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For more information www.linear.com/LTC3605A
LTC3605A
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
TOP VIEW
PV , SV , SW Voltage.............................. –0.3V to 22V
IN
IN
SW Transient Voltage..................................–2V to 24.5V
BOOST Voltage ..........................–0.3V to PV + INTV
IN
CC
24 23 22 21 20 19
RUN Voltage............................................... –0.3V to 22V
RT
PHMODE
MODE
1
2
3
4
5
6
18 PV
17 PV
IN
IN
V
Voltage............................................... –0.3V to SV
CC
ON
IN
INTV Voltage ......................................... –0.3V to 3.6V
SW
16
15 SW
SW
25
PGND
FB
ITH, RT, CLKOUT, PGOOD Voltage ........–0.3V to INTV
CLKIN, PHMODE, MODE Voltage ..........–0.3V to INTV
TRACK/SS, FB Voltage..........................–0.3V to INTV
Operating Junction Temperature Range
CC
CC
CC
TRACK/SS
ITH
14
13 SW
7
8
9 10 11 12
(Note 2).................................................. –40°C to 125°C
Storage Temperature Range .................. –65°C to 125°C
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
T
JMAX
= 125°C, θ = 37°C/W
JA
EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB
http://www.linear.com/product/LTC3605A#orderinfo
orDer inForMaTion
LEAD FREE FINISH
LTC3605AEUF#PBF
LTC3605AIUF#PBF
TAPE AND REEL
PART MARKING*
3605A
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3605AEUF#TRPBF
LTC3605AIUF#TRPBF
24-Lead (4mm × 4mm) Plastic QFN
24-Lead (4mm × 4mm) Plastic QFN
–40°C to 125°C
–40°C to 125°C
3605A
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ ≈ TA = 25°C (Note 2). VIN = 12V unless otherwise noted.
SYMBOL
PARAMETER
SV Supply Range
CONDITIONS
MIN
4
TYP
MAX
20
UNITS
SV
V
V
IN
IN
IN
PV
V
Power Supply Range
1.2
20
IN
I
Q
Input DC Supply Current
Active
(Note 3)
Mode = 0, R = 162k
1.5
11
5
40
mA
µA
T
Shutdown
V
IN
=12V, RUN = 0
l
l
l
V
Feedback Reference Voltage
Feedback Voltage Line Regulation
Feedback Voltage Load Regulation
Feedback Pin Input Current
Error Amplifier Transconductance
Minimum On-Time
ITH =1.2V (Note 4)
V = 4V to 20V, ITH = 1.2V
IN
0.594
1.15
0.600
0.001
0.1
0.606
0.03
0.3
V
%/V
%
FB
DV
DV
FB(LINE)
FB(LOAD)
I
FB
30
nA
g
m
(EA)
ITH = 1.2V
1.35
40
1.6
mS
ns
t
t
ON(MIN)
OFF(MIN)
Minimum Off-Time
70
ns
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For more information www.linear.com/LTC3605A
LTC3605A
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ ≈ TA = 25°C (Note 2). VIN = 12V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Positive Inductor Valley Current Limit
Negative Inductor Valley Current Limit
5
6
–5
7.5
A
A
LIM
R
R
Top Power NMOS On-Resistance
INTV = 3.3V
70
35
150
60
mΩ
mΩ
TOP
CC
Bottom Power NMOS On-Resistance
INTV = 3.3V
CC
BOTTOM
UVLO
V
V
V
INTV Undervoltage Lockout
INTV Falling
2.4
2.6
0.25
2.8
V
V
CC
CC
Threshold
INTV Hysteresis (Rising)
CC
Run Threshold 2 (I ≥ 1mA)
RUN Rising
RUN Rising
1.1
0.45
1.2
0.6
1.3
0.75
V
V
RUN
Q
Run Threshold 1 (I ≥ 100µA)
Q
Internal V Voltage
4V < V < 20V
3.2
3.3
0.5
10
3.4
V
%
%
INTVCC
CC
IN
DV
INTV Load Regulation
I
= 0mA to 20mA
LOAD
INTVCC
CC
OV
Output Overvoltage
PGOOD Upper Threshold
V
FB
V
FB
V
FB
Rising
7
13
–7
UV
Output Undervoltage
PGOOD Lower Threshold
Falling
–13
–10
%
DV
PGOOD Hysteresis
Returning
1.5
12
%
Ω
FB(HYS)
PGOOD
PGOOD
TRACK/SS
OSC
R
PGOOD Pull-Down Resistance
PGOOD Leakage
25
2
I
I
f
0.54V < V < 0.66V
µA
FB
TRACK Pull-Up Current
Oscillator Frequency
CLKIN Threshold
2.5
1
4
µA
l
R = 162k
T
0.85
1
1.2
0.3
MHz
CLKIN
CLKIN V
CLKIN V
V
V
IL
IH
V
V
Overvoltage Lockout Threshold
V
IN
V
IN
Rising
Falling
22.8
20.8
23.5
21.5
24.2
22.1
V
V
VIN_OV
IN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. Absolute Maximum Ratings are those values
beyond which the life of a device may be impaired.
Note 3: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 4: The LTC3605A is tested in a feedback loop that adjusts V to
FB
achieve a specified error amplifier output voltage (ITH).
Note 5: T is calculated from the ambient temperature T and
J
A
Note 2: The LTC3605A is tested under pulsed load conditions such that
power dissipation as follows: T = T + P • (37°C/W). See Thermal
J
A
D
T ≈ T . The LTC3605AE (E-grade) is guaranteed to meet specifications
J
A
Considerations section.
from 0°C to 85°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3605AI (I-grade) is guaranteed over the full –40°C to 125°C operating
temperature range.
Note 6: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
The junction temperature (T ) is calculated from the ambient temperature
J
(T ) and power dissipation (P ) according to the formula:
A
D
T = T + (P • θ °C/W)
J
A
D
JA
where θ is the package thermal impedance. Note that the maximum
JA
ambient temperature is determined by specific operating conditions
in conjunction with board layout, the rated thermal package thermal
resistance and other environmental factors.
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For more information www.linear.com/LTC3605A
LTC3605A
Typical perForMance characTerisTics TA = 25°C unless otherwise specified.
Shutdown Current vs VIN
Efficiency vs Load Current
Quiescent Current vs VIN
100
90
2.0
1.5
1.0
0.5
0
20
15
10
5
V
SW
= 12V
= 1MHz
IN
f
80
70
60
50
40
30
20
10
0
V
V
V
= 3.3V
= 2.5V
= 1.8V
OUT
OUT
OUT
0
0
4
8
12
16
20
0
4
8
12
16
20
0.01
0.1
1
10
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
LOAD CURRENT (A)
3605A G01
3605A G02
3605A G03
RDS(ON) vs Temperature
Load Regulation
IINTVCC Current vs Frequency
1.5
1.0
0.5
0
120
100
80
60
40
20
0
25
20
V
V
= 12V
OUT
MODE = 3.3V
NO LOAD
IN
= 1.2V
INTERNAL ITH
COMPENSATION
(ITH = 3.3V)
f = 1MHz
MODE = INTV
CC
TOP FET
15
BOTTOM FET
10
5
EXTERNAL ITH
COMPENSATION
–0.5
–1.0
–1.5
0
80 105
–45 –20
5
30 55
130
0
3
I
4
5
6
7
1
2
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
TEMPERATURE (°C)
(A)
FREQUENCY (MHz)
OUT
3605A G05
3605A G06
3605A G04
Load Step
(External ITH Compensation)
Load Step
(Internal ITH Compensation)
Output Tracking
V
V
OUT
OUT
100mV/DIV
100mV/DIV
AC-COUPLED
AC-COUPLED
I
I
L
L
5A/DIV
V
5A/DIV
TRACK
V
FB
I
I
LOAD
LOAD
5A/DIV
5A/DIV
3605A G08
3605A G07
3605A G09
V
V
I
= 12V
20µs/DIV
V
V
I
= 12V
20µs/DIV
V
V
= 12V
500µs/DIV
IN
OUT
IN
OUT
IN
OUT
= 1.2V
= 0.4A
= 1.2V
= 0.4A
= 1.2V
LOAD
LOAD
ITH = 3.3V
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For more information www.linear.com/LTC3605A
LTC3605A
Typical perForMance characTerisTics TA = 25°C unless otherwise specified.
Switching Frequency vs RT
Switch Leakage vs VIN
Efficiency vs VIN
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
350
300
96
94
92
90
V
= 3.3V
OUT
250
I
= 1A
LOAD
200
150
100
50
88
86
I
= 5A
LOAD
84
82
80
0
0
6
10 12 14 16 18 20
(V)
2
4
8
5
10
20
0
50 100 150 200 250
500
0
15
(V)
25
300 350 400 450
V
R
T
(kΩ)
IN
V
IN
3605A G11
3605A G10
3505A G12
Frequency vs VON Voltage
Current Limit Foldback
INTVCC Load Regulation
101
100
99
98
97
96
95
94
93
92
91
90
120
100
80
3.0
2.5
T
= 25°C
A
V
= 20V
= 162k
IN
T
R
2.0
1.5
1.0
60
40
20
0
0.5
0
0
40
60
80 100 120 140
0.4
(V)
0.6
0.7
20
0
0.1
0.2 0.3
V
0.5
0
2
4
6
8
10 12 14 16 18
(V)
INTV OUTPUT CURRENT (mA)
V
CC
FB
ON
3605A G15
3605A G14
3605A G13
RUN Pin Threshold vs Temperature
DCM Operation
CCM Operation
1.30
1.25
1.20
1.15
CLKOUT
2V/DIV
CLKOUT
2V/DIV
V
SW
V
SW
5V/DIV
5V/DIV
I
L
I
L
1.10
1.05
1.00
2A/DIV
2A/DIV
3605A G18
3605A G17
V
V
= 20V
400ns/DIV
V
V
= 20V
400ns/DIV
IN
OUT
IN
OUT
= 2.5V
= 2.5V
MODE = 3.3V
= 0A
MODE = 0V
= 0A
I
OUT
I
60
TEMPERATURE (°C)
110
–40 –15
10
35
85
OUT
L1 = 0.5µH
L1 = 0.5µH
3605A G16
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For more information www.linear.com/LTC3605A
LTC3605A
pin FuncTions
RT (Pin 1): Oscillator Frequency Programming Pin. Con-
nect an external resistor (between 200k to 40k) from RT
to SGND to program the frequency from 800kHz to 4MHz.
Since the synchronization range is 30% of set frequency,
be sure that the set frequency is within this percentage
range of the external clock to ensure frequency lock.
V
(Pin 9): On-Time Voltage Input. Voltage trip point for
ON
the on-time comparator. Tying this pin to the output volt-
age makes the on-time proportional to V and keeps the
OUT
switching frequency constant at different V . However,
OUT
when V is <0.6V or >6V, then switching frequency will
ON
no longer remain constant.
PHMODE (Pin 2): Control Input to Phase Selector. Deter-
PGND (Pin 10, Exposed Pad Pin 25): Power Ground.
Return path of internal power MOSFETs. Connect this
pin to the negative terminals of the input capacitor and
output capacitor. The exposed pad must be soldered to
the PCB ground for electrical contact and rated thermal
performance.
mines the phase relationship between internal oscillator
and CLKOUT. Tie it to INTV for 2-phase operation, tie it
CC
to SGND for 3-phase operation, and tie it to INTV /2 for
CC
4-phase operation.
MODE (Pin 3): Operation Mode Select. Tie this pin to
INTV to force continuous synchronous operation at all
SW (Pins 11 to 16): Switch Node Connection to External
CC
outputloads.TyingittoSGNDenablesdiscontinuousmode
Inductor. Voltage swing of SW is from a diode voltage
operation at light loads. Do not float this pin.
drop below ground to PV .
IN
FB (Pin 4): Output Feedback Voltage. Input to the error
amplifierthatcomparesthefeedbackvoltagetotheinternal
0.6V reference voltage. This pin is normally connected to
a resistive divider from the output voltage.
PV (Pins 17, 18): Power V . Input voltage to the on-
IN
IN
chip power MOSFETs.
SV (Pin 19): Signal V . Filtered input voltage to the
IN
IN
on-chip 3.3V regulator. Connect a (1Ω to 10Ω) resistor
TRACK/SS (Pin 5): Output Tracking and Soft-Start Pin.
Allows the user to control the rise time of the output volt-
age. Putting a voltage below 0.6V on this pin bypasses
the internal reference input to the error amplifier, instead
it servos the FB pin to the TRACK voltage. Above 0.6V,
the tracking function stops and the internal reference
resumes control of the error amplifier. There’s an internal
between SV and PV and bypass to GND with a 0.1µF
IN
IN
capacitor.
BOOST (Pin 20): Boosted Floating Driver Supply for Inter-
nal Top Power MOSFET. The (+) terminal of the bootstrap
capacitor connects here. This pin swings from a diode
voltage drop below INTV up to PV + INTV .
CC
IN
CC
INTV (Pin 21): Internal 3.3V Regulator Output. The
2.5µA pull-up current from INTV on this pin, so putting
CC
CC
internal power drivers and control circuits are powered
from this voltage. Decouple this pin to power ground with
a minimum of 1µF low ESR ceramic capacitor.
a capacitor here provides soft-start function.
ITH (Pin 6): Error Amplifier Output and Switching Regu-
lator Compensation Point. The current comparator’s trip
threshold is linearly proportional to this voltage, whose
normal range is from 0.3V to 1.8V. Tying this pin to IN-
SGND (Pin 22): Signal Ground Connection.
CLKOUT (Pin 23): Output Clock Signal for PolyPhase
Operation. The phase of CLKOUT with respect to CLKIN
is determined by the state of the PHMODE pin. CLKOUT’s
TV activates internal compensation and output voltage
CC
positioning, raising V
value at I
to 1.5% higher than the nominal
OUT
= 0 and 1.5% lower at I
= 5A.
OUT
OUT
peak-to-peak amplitude is INTV to GND.
CC
RUN (Pin 7): Run Control Input. Enables chip operation
by tying RUN above 1.2V. Tying it below 1.1V shuts down
the part.
CLKIN (Pin 24): External Synchronization Input to Phase
Detector.ThispinisinternallyterminatedtoSGNDwith20k.
The phase-locked loop will force the top power NMOS’s
turn on signal to be synchronized with the rising edge of
the CLKIN signal.
PGOOD (Pin 8): Output Power Good with Open-Drain
Logic. PGOOD is pulled to ground when the voltage on the
FB pin is not within 10% of the internal 0.6V reference.
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For more information www.linear.com/LTC3605A
LTC3605A
block DiagraM
V
OUT
V
ON
MODE
3
9
0.6V
6V
100K
35pF
3pF
PV
IN
SV
IN
1Ω
3.3V
REG
19
C
C
IN
17-18
IN2
I
ON
PLL-SYNC
( 30ꢀ%
I
ON
INTV
21
CC
OST
V
I
VON
t
ON
=
(0.64pF%
R
S
V
ION
BOOST
20
IN
INTV
Q
x =
CC
C
B
TG
M1
12 x OSC
RT
R
SW
L1
ON
20k
V
1
OUT
SWITCH
LOGIC
+
–
+
PHMODE
11–16
AND
T
I
REV
2
I
CMP
C
D
B
OUT
ANTI-
SHOOT
THROUGH
+
SENSE
SENSE
–
CLKIN
24
–
OSC
PLL-SYNC
( 30ꢀ%
RUN
OV
CLKOUT
23
BG
M2
C
VCC
–3.3µA TO 6.7µA
PGND
100k
3pF
35pF
10, 25
FOLDBACK
DISABLED
AT START-UP
3.3µA
8
PGOOD
0µA TO 10µA
0.3V
+
–
FOLDBACK
x 4 + 0.6
1
180k
R2
R1
0.66V
–
+
Q2 Q4
OV
FB
4
I
THB
Q6
Q1
–
+
SGND
22
UV
0.54V
INT
VCC
SS
RUN
–
–
+
+
+ EA+
2.5µA
–
0.6V
1.2V
0.6V
REF
ITH
TRACK/SS
RUN
C
C
SS
C1
6
7
5
R
C
3605A BD
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For more information www.linear.com/LTC3605A
LTC3605A
operaTion
Main Control Loop
condition except during start-up when the TRACK pin is
ramping up to 0.6V.
The LTC3605A is a current mode monolithic step-down
regulator. In normal operation, the internal top power
MOSFET is turned on for a fixed interval determined by
a one-shot timer, OST. When the top power MOSFET
turns off, the bottom power MOSFET turns on until the
Foldback current limiting is provided if the output is
shorted to ground. As V drops to zero, the maximum
FB
sense voltage allowed across the bottom power MOSFET
is lowered to approximately 40% of the original value to
reduce the inductor valley current.
current comparator, I
, trips, restarting the one-shot
CMP
timer and initiating the next cycle. Inductor current is de-
termined by sensing the voltage drop across the bottom
power MOSFET’s VDS. The voltage on the ITH pin sets
the comparator threshold corresponding to the inductor
valley current. The error amplifier, EA, adjusts this ITH
RUN Threshold
Pulling the RUN pin to ground forces the LTC3605A into
its shutdown state, turning off both power MOSFETs and
most of its internal control circuitry. Bringing the RUN pin
above 0.6V turns on the internal reference only, while still
keeping the power MOSFETs off. Further increasing the
RUN voltage above 1.2V turns on the entire chip.
voltage by comparing the feedback signal, V , from the
FB
output voltage with that of an internal 0.6V reference. If
theloadcurrentincreases, itcausesadropinthefeedback
voltage relative to the internal reference. The ITH voltage
then rises until the average inductor current matches that
of the load current.
INTV Regulator
CC
An internal low dropout (LDO) regulator produces the
3.3V supply that powers the drivers and the internal bias
circuitry. The INTV can supply up to 100mA RMS and
At low load current, the inductor current can drop to zero
and become negative. This is detected by current reversal
CC
comparator, I , which then shuts off the bottom power
must be bypassed to ground with a minimum of 1µF
ceramiccapacitor. Goodbypassingisnecessarytosupply
thehightransientcurrentsrequiredbythepowerMOSFET
gate drivers. Applications with high input voltage and high
switchingfrequencywillincreasedietemperaturebecause
of the higher power dissipation across the LDO. Connect-
REV
MOSFET,resultingindiscontinuousoperation.Bothpower
MOSFETswillremainoffwiththeoutputcapacitorsupplying
the load current until the ITH voltage rises above the zero
current level (0.6V) to initiate another cycle. Discontinu-
ous mode operation is disabled by tying the MODE pin to
INTV , which forces continuous synchronous operation
ing a load to the INTV pin is not recommended since
CC
CC
regardless of output load.
it will further push the LDO into its RMS current rating
while increasing power dissipation and die temperature.
The operating frequency is determined by the value of the
R resistor, which programs the current for the internal
T
V Overvoltage Protection
IN
oscillator.Aninternalphase-lockloopservostheoscillator
frequency to an external clock signal if one is present on
theCLKINpin.Anotherinternalphase-lockloopservosthe
switching regulator on-time to track the internal oscillator
to force constant switching frequency.
In order to protect the internal power MOSFET devices
againsttransientvoltagespikes, theLTC3605Aconstantly
monitors the V pin for an overvoltage condition. When
IN
V rises above 23.5V, the regulator suspends operation
IN
by shutting off both power MOSFETs. Once V drops
IN
Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback volt-
below 21.5V, the regulator immediately resumes normal
operation. The regulator does not execute its soft-start
function when exiting an overvoltage condition.
age, V , exits a 10% window around the regulation
FB
point. Continuous operation is forced during OV and UV
3605afg
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LTC3605A
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PV /SV Voltage Differential
Programming Switching Frequency
IN
IN
SV should be tied to PV with a low pass filter of 1Ω
Connecting a resistor from the RT pin to SGND programs
the switching frequency from 800kHz to 4MHz according
to the following formula:
IN
IN
to 10Ω and 0.1μF. For applications where PV and SV
IN
IN
are tied to vastly different voltage potentials, though the
output voltage will remain in regulation, there will be an
1.6e11
RT (W)
Frequency (Hz)=
offset in the internal on-time generator such that if SV
IN
is different than PV by more than 50% of the PV volt-
IN
IN
age, the resulting switching frequency will deviate from
The internal PLL has a synchronization range of 30%
around its programmed frequency. Therefore, during
external clock synchronization be sure that the external
clock frequency is within this 30% range of the RT pro-
grammed frequency.
the frequency programmed by the R resistor and/or the
T
externalclocksynchronizationfrequency.Insuchapplica-
tions, in order to return the switching frequency back to
the original desired frequency, R resistor value can be
T
adjusted accordingly. However, the better alternative is
to tie the V pin to a voltage different than that of V
Output Voltage Tracking and Soft-Start
ON
OUT
in order to negate the offset of the V differential. For
IN
TheLTC3605Aallowstheusertoprogramitsoutputvoltage
ramp rate by means of the TRACK/SS pin. An internal 2µA
instance,ifSV is6VandPV is12V,theresultingswitch-
IN
IN
ing frequency may be slower than what’s programmed
by the R resistor. Tying the V pin to a voltage half of
pulls up the TRACK/SS pin to INTV . Putting an external
CC
T
ON
capacitor on TRACK/SS enables soft starting the output
to prevent current surge on the input supply. For output
tracking applications, TRACK/SS can be externally driven
byanothervoltagesource.From0Vto0.6V,theTRACK/SS
voltagewilloverridetheinternal0.6Vreferenceinputtothe
erroramplifier,thusregulatingthefeedbackvoltagetothat
ofTRACK/SSpins.Duringthisstart-uptime,theLTC3605A
will operate in discontinuous mode. When TRACK/SS is
above 0.6V, tracking is disabled and the feedback voltage
will regulate to the internal reference voltage.
V
OUT
will negate the V offset and return the switching
frequency back to normal.
IN
Output Voltage Programming
The output voltage is set by an external resistive divider
according to the following equation:
V
OUT
= 0.6V • (1 + R2/R1)
The resistive divider allows the V pin to sense a fraction
FB
of the output voltage as shown in Figure 1.
Output Power Good
V
OUT
When the LTC3605A’s output voltage is within the 10%
window of the regulation point, which is reflected back as
C
R2
FF
FB
a V voltage in the range of 0.54V to 0.66V, the output
FB
voltage is good and the PGOOD pin is pulled high with
an external resistor. Otherwise, an internal open-drain
pull-down device (12Ω) will pull the PGOOD pin low.
To prevent unwanted PGOOD glitches during transients
R1
LTC3605A
SGND
3605A F01
Figure 1. Setting the Output Voltage
or dynamic V
changes, the LTC3605A’s PGOOD fall-
OUT
ing edge includes a blanking delay of approximately 52
switching cycles.
3605afg
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LTC3605A
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Multiphase Operation
example, then the output will drop out of regulation. The
minimum input voltage to avoid dropout is:
For output loads that demand more than 5A of current,
multiple LTC3605As can be cascaded to run out of phase
to provide more output current. The CLKIN pin allows the
LTC3605A to synchronize to an external clock ( 30% of
frequency programmed by RT) and the internal phase-
locked-loop allows the LTC3605A to lock onto CLKIN’s
phaseaswell. TheCLKOUT signalcanbeconnected to the
CLKIN pin of the following LTC3605A stage to line up both
the frequency and the phase of the entire system. Tying
t
ON + tOFF(MIN)
VIN(MIN) = VOUT •
tON
Conversely, the minimum on-time is the smallest dura-
tion of time in which the top power MOSFET can be in
its “on” state. This time is typically 40ns. In continuous
mode operation, the minimum on-time limit imposes a
minimum duty cycle of:
the PHMODE pin to INTV , SGND or INTV /2 generates
CC
CC
DC
= f • t
MIN
ON(MIN)
a phase difference (between CLKIN and CLKOUT) of 180
degrees, 120 degrees, or 90 degrees respectively, which
corresponds to 2-phase, 3-phase or 4-phase operation. A
total of 12 phases can be cascaded to run simultaneously
out of phase with respect to each other by programming
the PHMODE pin of each LTC3605A to different levels.
where t
is the minimum on-time. As the equation
ON(MIN)
shows, reducing the operating frequency will alleviate the
minimum duty cycle constraint.
In the rare cases where the minimum duty cycle is sur-
passed,theoutputvoltagewillstillremaininregulation,but
theswitchingfrequencywilldecreasefromitsprogrammed
value. Thisisanacceptableresultinmanyapplications, so
this constraint may not be of critical importance in most
cases. High switching frequencies may be used in the
design without any fear of severe consequences. As the
sections on inductor and capacitor selection show, high
switchingfrequenciesallowtheuseofsmallerboardcom-
ponents, thus reducing the size of the application circuit.
Internal/External ITH Compensation
During single phase operation, the user can simplify the
loop compensation by tying the I pin to INTV to en-
TH
CC
able internal compensation. This connects an internal 30k
resistor in series with a 40pF capacitor to the output of
theerroramplifier(internalITHcompensationpoint)while
also activating output voltage positioning such that the
outputvoltagewillbe1.5%aboveregulationatnoloadand
1.5% below regulation at full load. This is a trade-off for
simplicityinsteadofOPTI-LOOP® optimization,whereITH
components are external and are selected to optimize the
looptransientresponsewithminimumoutputcapacitance.
C and C
IN
Selection
OUT
The input capacitance, C , is needed to filter the trapezoi-
IN
dal wave current at the drain of the top power MOSFET.
To prevent large voltage transients from occurring, a low
ESR input capacitor sized for the maximum R current
MS
Minimum Off-Time and Minimum On-Time
Considerations
should be used. The maximum R current is given by:
MS
VOUT
V
IN
VOUT
Theminimumoff-time,t
,isthesmallestamountof
OFF(MIN)
I
RMS ≅IOUT(MAX)
– 1
time that the LTC3605A is capable of turning on the bot-
tom power MOSFET, tripping the current comparator and
turning the power MOSFET back off. This time is generally
about 70ns. The minimum off-time limit imposes a maxi-
V
IN
This formula has a maximum at V = 2V , where
IN
OUT
I
≅ I /2. This simple worst-case condition is com-
RMS
OUT
mum duty cycle of t /(t + t
). If the maximum
OFF(MIN)
ON ON
monlyusedfordesignbecauseevensignificantdeviations
do not offer much relief. Note that ripple current ratings
from capacitor manufacturers are often based on only
2000 hours of life which makes it advisable to further
duty cycle is reached, due to a dropping input voltage for
3605afg
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For more information www.linear.com/LTC3605A
LTC3605A
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derate the capacitor, or choose a capacitor rated at a
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
IN
higher temperature than required.
V input. Atbest, thisringingcancoupletotheoutputand
Several capacitors may also be paralleled to meet size or
height requirements in the design. For low input voltage
applications, sufficient bulk input capacitance is needed
to minimize transient effects during output load changes.
be mistaken as loop instability. At worst, a sudden inrush
of current through the long wires can potentially cause
a voltage spike at V large enough to damage the part.
IN
When choosing the input and output ceramic capacitors,
choose the X5R and X7R dielectric formulations. These
dielectrics have the best temperature and voltage char-
acteristics of all the ceramics for a given value and size.
The selection of C
is determined by the effective series
OUT
resistance(ESR)thatisrequiredtominimizevoltageripple
and load step transients as well as the amount of bulk
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement.Duringaloadstep,theoutputcapacitormust
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
looptorespondisdependentonthecompensationandthe
output capacitor size. Typically, 3 to 4 cycles are required
to respond to a load step, but only in the first cycle does
the load transient response. The output ripple, DV , is
determined by:
OUT
⎛
⎜
⎝
⎞
⎟
⎠
1
DVOUT < DIL
+ESR
8 • f •C
OUT
The output ripple is highest at maximum input voltage
since DI increases with input voltage. Multiple capaci-
L
tors placed in parallel may be needed to meet the ESR
and RMS current handling requirements. Dry tantalum,
special polymer, aluminum electrolytic, and ceramic
capacitors are all available in surface mount packages.
Special polymer capacitors are very low ESR but have
lower capacitance density than other types. Tantalum
capacitors have the highest capacitance density but it is
important to only use types that have been surge tested
foruseinswitchingpowersupplies.Aluminumelectrolytic
capacitors have significantly higher ESR, but can be used
in cost-sensitive applications provided that consideration
is given to ripple current ratings and long-term reliability.
CeramiccapacitorshaveexcellentlowESRcharacteristics
and small footprints. Their relatively low value of bulk
capacitance may require multiples in parallel.
the output drop linearly. The output droop, V
, is
DROOP
usually about 2 to 3 times the linear drop of the first cycle.
Thus, a good place to start with the output capacitor value
is approximately:
DIOUT
fO • VDROOP
COUT ≈ 2.5
More capacitance may be required depending on the duty
cycle and load step requirements.
Inmostapplications,theinputcapacitorismerelyrequired
tosupplyhighfrequencybypassing,sincetheimpedanceto
the supply is very low. A 22µF ceramic capacitor is usually
enough for these conditions. Place this input capacitor as
close to the PV pins as possible.
IN
Using Ceramic Input and Output Capacitors
Inductor Selection
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input
Given the desired input and output voltages, the inductor
valueandoperatingfrequencydeterminetheripplecurrent:
⎛
⎞
⎟
VOUT
VOUT
⎜
⎝
DIL =
1–
⎜
⎟
f •L
V
IN(MAX)
⎠
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For more information www.linear.com/LTC3605A
LTC3605A
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Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a trade-off between
component size, efficiency and operating frequency.
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Different core materials and shapes will change the size/
currentandprice/currentrelationshipofaninductor.Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price versus size requirements
and any radiated field/EMI requirements. New designs for
surface mount inductors are available from Toko, Vishay,
NEC/Tokin, Cooper, TDK and Wurth Elektronik. Refer to
Table 1 for more details.
A reasonable starting point is to choose a ripple current
that is about 2.5A. This is especially important at low V
OUT
operation where V
is 1.8V or below. Care must be
OUT
given to choose an inductance value that will generate a
big enough current ripple (1.5A to 2.5A) so that the chip’s
valleycurrentcomparatorhasenoughsignal-to-noiseratio
toforceconstantswitchingfrequency.Meanwhile,alsonote
that the largest ripple current occurs at the highest V . To
IN
guarantee that ripple current does not exceed a specified
Checking Transient Response
maximum, the inductance should be chosen according to:
The OPTI-LOOP compensation allows the transient re-
sponse to be optimized for a wide range of loads and
output capacitors. The availability of the ITH pin not
only allows optimization of the control loop behavior but
also provides a DC-coupled and AC-filtered closed-loop
response test point. The DC step, rise time and settling
at this test point truly reflects the closed-loop response.
Assuming a predominantly second order system, phase
margin and/or damping factor can be estimated using the
percentage of overshoot seen at this pin.
⎛
⎞
VOUT
f • DIL(MAX)
VOUT
V
IN(MAX)
⎜
⎟
L =
• 1–
⎜
⎝
⎟
⎠
However, the inductor ripple current must not be so large
thatitsvalleycurrentlevel(–∆I /2)canexceedthenegative
L
current limit, which can be as low as –3.5A. If the negative
current limit is exceeded in forced continuous mode of op-
eration, V
can get charged to above the regulation level
OUT
until the inductor current no longer exceeds the negative
current limit. In such instances, choose a larger inductor
value to reduce the inductor ripple current. The alternative
The ITH external components shown in the circuit on the
first page of this data sheet provides an adequate starting
point for most applications. The series R-C filter sets the
dominant pole zero loop compensation. The values can
be modified slightly (from 0.5 to 2 times their suggested
values) to optimize transient response once the final PC
layout is done and the particular output capacitor type
and value have been determined. The output capacitors
needtobeselectedbecausetheirvarioustypesandvalues
determine the loop feedback factor gain and phase. An
output current pulse of 20% to 100% of full load current
having a rise time of 1µs to 10µs will produce output volt-
age and ITH pin waveforms that will give a sense of the
overall loop stability without breaking the feedback loop.
is to reduce the R resistor value to increase the switching
frequency in order to reduce the inductor ripple current.
T
Once the value for L is known, the type of inductor must
be selected. Actual core loss is independent of core size
for a fixed inductor value, but is very dependent on the
inductance selected. As the inductance or frequency in-
creases, core losses decrease. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses will increase.
Ferrite designs have very low core losses and are pre-
ferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard”, which means that
inductancecollapsesabruptlywhenthepeakdesigncurrent
Switchingregulatorstakeseveralcyclestorespondtoastep
in load current. When a load step occurs, V
immediately
OUT
3605afg
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LTC3605A
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Table 1. Inductor Selection Table
shifts by an amount equal to DI
• ESR, where ESR is
LOAD
the effective series resistance of C . DI
also begins
OUT
LOAD
INDUCTANCE DCR
MAX CURRENT
DIMENSIONS
HEIGHT
to charge or discharge C
generating a feedback error
OUT
Vishay IHLP-2525CZ-01 Series
signalusedbytheregulatortoreturnV toitssteady-state
OUT
0.33µH
0.47µH
0.68µH
0.82µH
1.0µH
4.1mW
6.5mW
9.4mW
11.8mW
14.2mW
18A
13.5A
11A
10A
9A
6.7mm × 7mm
3mm
value. During this recovery time, V can be monitored for
overshootorringingthatwouldindicateastabilityproblem.
OUT
The initial output voltage step may not be within the band-
width of the feedback loop, so the standard second order
overshoot/DC ratio cannot be used to determine phase
margin. The gain of the loop increases with the R and the
bandwidth of the loop increases with decreasing C. If R
is increased by the same factor that C is decreased, the
zero frequency will be kept the same, thereby keeping the
phase the same in the most critical frequency range of the
Vishay IHLP-1616BZ-11 Series
0.22µH
0.47µH
4.1mW
15mW
12A
7A
4.3mm × 4.7mm 2.0mm
Toko FDV0620 Series
0.20µH
0.47µH
1µH
4.5mW
12.4A
9A
7mm × 7.7mm
2.0mm
8.3mW
feedback loop. In addition, a feedforward capacitor, C ,
FF
18.3mW
5.7A
can be added to improve the high frequency response, as
NEC/Tokin MLC0730L Series
shown in Figure 1. Capacitor C provides phase lead by
FF
0.47µH
0.75µH
1µH
4.5mW
7.5mW
9mW
16.6A
12.2A
10.6A
6.9mm × 7.7mm 3.0mm
creating a high frequency zero with R2 which improves
the phase margin.
Theoutputvoltagesettlingbehaviorisrelatedtothestability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
Cooper HCP0703 Series
0.22µH
0.47µH
0.68µH
0.82µH
1µH
2.8mW
4.2mW
5.5mW
8mW
23A
17A
15A
13A
11A
9A
7mm × 7.3mm
3.0mm
10mW
14mW
Insomeapplications,amoreseveretransientcanbecaused
by switching in loads with large (>10µF) input capacitors.
Thedischargedinputcapacitorsareeffectivelyputinparal-
1.5µH
TDK RLF7030 Series
1µH
8.8mW
6.4A
6.1A
5.4A
6.9mm × 7.3mm 3.2mm
lel with C , causing a rapid drop in V . No regulator
OUT
OUT
1.5µH
2.2µH
9.6mW
12mW
can deliver enough current to prevent this problem, if
the switch connecting the load has low resistance and is
driven quickly. The solution is to limit the turn-on speed of
the load switch driver. A Hot Swap controller is designed
specifically for this purpose and usually incorporates
currentlimiting, short-circuitprotectionandsoft-starting.
Würth Elektronik WE-HC 744312 Series
0.25µH
0.47µH
0.72µH
1µH
2.5mW
3.4mW
7.5mW
9.5mW
10.5mW
18A
16A
12A
11A
9A
7mm × 7.7mm
3.8mm
Efficiency Considerations
1.5µH
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
3605afg
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For more information www.linear.com/LTC3605A
LTC3605A
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produce the most improvement. Percent efficiency can
be expressed as:
3. Other “hidden” losses such as transition loss and cop-
per trace and internal load resistances can account for
additional efficiency degradations in the overall power
system. It is very important to include these “system”
level losses in the design of a system. Transition loss
arises from the brief amount of time the top power
MOSFET spends in the saturated region during switch
nodetransitions.TheLTC3605Ainternalpowerdevices
switch quickly enough that these losses are not signifi-
cantcomparedtoothersources. Otherlossesincluding
diodeconductionlossesduringdead-timeandinductor
core losses which generally account for less than 2%
total additional loss.
% Efficiency = 100%–(L1 + L2 + L3 +…)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, threemainsourcesusuallyaccountformostofthe
losses in LTC3605A circuits: 1) I R losses, 2) switching
and biasing losses, 3) other losses.
2
2
1. I R losses are calculated from the DC resistances of
the internal switches, R , and external inductor, R .
SW
L
In continuous mode, the average output current flows
through inductor L but is “chopped” between the
internal top and bottom power MOSFETs. Thus, the
series resistance looking into the SW pin is a function
Thermal Considerations
In a majority of applications, the LTC3605A does not dis-
sipatemuchheatduetoitshighefficiencyandlowthermal
resistance of its exposed-back QFN package. However, in
applications where the LTC3605A is running at high ambi-
of both top and bottom MOSFET R
cycle (DC) as follows:
and the duty
DS(ON)
R
SW
= (R
TOP)(DC) + (R
BOT)(1-DC)
DS(ON)
DS(ON)
ent temperature, high V , high switching frequency and
IN
TheR
forboththetopandbottomMOSFETscanbe
maximum output current load, the heat dissipated may
exceed the maximum junction temperature of the part.
If the junction temperature reaches approximately 160°C,
bothpowerswitcheswillbeturnedoffuntilthetemperature
drops about 15°C cooler.
DS(ON)
obtained from the Typical Performance Characteristics
2
curves. Thus to obtain I R losses:
2
2
I R losses = I
(R + R )
SW L
OUT
2. The INTV current is the sum of the power MOSFET
CC
ToavoidtheLTC3605Afromexceedingthemaximumjunc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum junc-
tiontemperatureofthepart.Thetemperatureriseisgivenby:
driver and control currents. The power MOSFET driver
current results from switching the gate capacitance of
thepowerMOSFETs.EachtimeapowerMOSFETgateis
switchedfromlowtohightolowagain,apacketofcharge
dQ moves from INTV to ground. The resulting dQ/dt
CC
is a current out of INTV that is typically much larger
CC
T
RISE
= P • θ
D JA
than the DC control bias current. In continuous mode,
As an example, consider the case when the LTC3605A is
used in applications where V = 12V, I = 5A, f = 1MHz,
I
= f(Q + Q ), where Q and Q are the gate
GATECHG
T B T B
IN
OUT
charges of the internal top and bottom power MOSFETs
V
= 1.8V. The equivalent power MOSFET resistance
OUT
and f is the switching frequency. Since INTV is a low
CC
R
SW
is:
dropout regulator output powered by V , its power
IN
loss equals:
⎛
⎞
⎟
⎠
VOUT
VOUT
RSW =RDS(ON)Top •
+RDS(ON)Bot 1–
⎜
P
LDO
= V • I
IN INTVCC
V
V
⎝
IN
IN
Refer to the I
vs Frequency curve in the Typical
1.8
10.2
12
INTVCC
= 70mW •
+35mW •
Performance Characteristics for typical INTV current
CC
12
= 40.25mW
at various frequencies.
3605afg
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For more information www.linear.com/LTC3605A
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The V current during 1MHz force continuous operation
Junction Temperature Measurement
IN
with no load is about 11mA, which includes switching
and internal biasing current loss, transition loss, inductor
core loss and other losses in the application. Therefore,
the total power dissipated by the part is:
The junction-to-ambient thermal resistance will vary de-
pending on the size and amount of heat sinking copper
on the PCB board where the part is mounted, as well as
the amount of air flow on the device. One of the ways to
measure the junction temperature directly is to use the
internal junction diode on one of the pins (PGOOD) to
measure its diode voltage change based on ambient
temperature change. First remove any external passive
component on the PGOOD pin, then pull out 100µA from
the PGOOD pin to turn on its internal junction diode and
bias the PGOOD pin to a negative voltage. With no output
current load, measure the PGOOD voltage at an ambient
temperature of 25°C, 75°C and 125°C to establish a slope
relationship between the delta voltage on PGOOD and
deltaambienttemperature.Oncethisslopeisestablished,
then the junction temperature rise can be measured as a
function of power loss in the package with corresponding
outputloadcurrent.Keepinmindthatdoingsowillviolate
absolute maximum voltage ratings on the PGOOD pin,
however, with the limited current, no damage will result.
2
P = I
D
• R + V • I (No Load)
SW IN VIN
OUT
2
= 25A • 40.25mΩ + 12V • 11mA = 1.14W
TheQFN4mm×4mmpackagejunction-to-ambientthermal
resistance, θ , is around 37°C/W. Therefore, the junction
JA
temperature of the regulator operating in a 25°C ambient
temperature is approximately:
T = 1.14W • 37°C/W + 25°C = 67°C
J
Remembering that the above junction temperature is
obtained from an R
at 25°C, we might recalculate
DS(ON)
the junction temperature based on a higher R
since
DS(ON)
it increases with temperature. Redoing the calculation
assuming that R increased 15% at 67°C yields a new
SW
junction temperature of 72°C. If the application calls for
a higher ambient temperature and/or higher switching
frequency, careshouldbetakentoreducethetemperature
rise of the part by using a heat sink or air flow. Figure 2
is a temperature derating curve based on the DC1215
demo board.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3605A (refer to Figure 3). Check the following in
your layout:
6
5
4
3
2
1. Do the capacitors C connect to the power PV and
IN
IN
power PGND as close as possible? These capacitors
provide the AC current to the internal power MOSFETs
and their drivers.
2. Are C
and L1 closely connected? The (–) plate of
OUT
V
V
SW
= 12V
= 3.3V
= 1MHz
C
returns current to PGND and the (–) plate of C .
IN
OUT
OUT
IN
1
0
f
3. The resistive divider, R1 and R2, must be connected
DC1215 DEMO BOARD
60 80
AMBIENT TEMPERATURE (°C)
between the (+) plate of C
and a ground line termi-
OUT
20
100
120
140
40
nated near SGND. The feedback signal V should be
FB
3605A F02
routed away from noisy components and traces, such
as the SW line, and its trace should be minimized. Keep
R1 and R2 close to the IC.
Figure 2. Load Current vs Ambient Temperature
3605afg
15
For more information www.linear.com/LTC3605A
LTC3605A
operaTion
C
IN
L1
GND
V
IN
V
OUT
V
IN
V
OUT
C
OUT
GND
3605A F03b
3605A F03a
Figure 3a. Sample PCB Layout—Topside
Figure 3b. Sample PCB Layout—Bottom Side
Because efficiency is important at both high and low load
current, discontinuous mode operation will be utilized.
4. Solder the Exposed Pad (Pin 25) on the bottom of the
package to the PGND plane. Connect this PGND plane
to other layers with thermal vias to help dissipate heat
from the LTC3605A.
First select from the characteristic curves the correct R
T
resistorvaluefor2MHzswitchingfrequency.Basedonthat
R should be 80.6k. Then calculate the inductor value for
T
5. Keep sensitive components away from the SW pin. The
about 50% ripple current at maximum V :
IN
R resistor, the compensation capacitor C and C
T
C
ITH
CC
⎛
⎜
⎝
⎞⎛
⎟⎜
⎠⎝
⎞
⎟
⎠
and all the resistors R1, R3 and R , and the INTV
1.8V
2MHz• 2.5A
1.8V
13.2V
C
L =
1–
= 0.31µH
bypass capacitor, should be placed away from the SW
trace and the inductor L1. Also, the SW pin pad should
be kept as small as possible.
The nearest standard value inductor would be 0.33µH.
will be selected based on the ESR that is required to
6. A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small-
signal components returning to the SGND pin which is
thenconnectedtothePGNDpinatthenegativeterminal
C
OUT
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, two
47µF ceramic capacitors will be used.
of the output capacitor, C
.
OUT
C should be sized for a maximum current rating of:
IN
Flood all unused areas on all layers with copper, which
reducesthetemperatureriseofpowercomponents.These
copper areas should be connected to PGND.
1/2
⎛
⎜
⎝
⎞⎛
1.8V 13.2V
13.2V 1.8V
⎞
IRMS = 5A
– 1 = 1.7A
⎟
⎟⎜
⎠⎝
⎠
Design Example
Decoupling the PV pins with two 22µF ceramic capaci-
IN
tors is adequate for most applications.
As a design example, consider using the LTC3605A in an
application with the following specifications:
V
= 10.8V to 13.2V, V
OUT(MIN)
= 1.8V, I
= 5A,
IN
OUT
OUT(MAX)
I
= 500mA, f = 2MHz
3605afg
16
For more information www.linear.com/LTC3605A
LTC3605A
Typical applicaTions
12V to 1.2V 1MHz Buck Regulator
C1
0.1µF
10Ω
19
D1
2.2µF
V
IN
4V TO 20V
C
IN
24
23
22
21
20
22µF
CLKIN CLKOUT SGND INTV BOOST SV
×2
CC
IN
0.1µF
1
2
3
4
5
6
18
17
16
15
14
13
RT
PV
IN
IN
162k
PHMODE
MODE
FB
PV
SW
SW
SW
L1 0.68µH
LTC3605A
V
1.2V
5A
OUT
47pF
4.99k
4.99k
TRACK/SS
C
OUT
12k
330pF
47µF
ITH
SW
SW
×2
10pF
0.1µF
RUN PGOOD
V
PGND SW
10 11
ON
7
8
9
12
SV
IN
100k
PGND
SGND
3605A TA02
C1: AVX 0805ZD225MAT2A
D1: CENTRAL SEMI CMDSH-3
L1: VISHAY IHLP-2525CZERR68-M01
C
C
: TDK C4532X5RIC226M
IN
OUT
: TDK C3216X5ROJ476M
3605afg
17
For more information www.linear.com/LTC3605A
LTC3605A
Typical applicaTions
12V, 10A 2-Phase Single Output Regulator
0.1µF
C1
2.2µF
D1
10Ω
V
IN
4V TO 20V
C
IN1
24
23
22
21
CC
20
19
IN
22µF
CLKIN CLKOUT SGND INTV BOOST SV
×2
0.1µF
1
2
3
4
5
18
17
16
15
14
13
RT
PV
PV
IN
162k
PHMODE
MODE
FB
IN
SW
SW
SW
L1 1.5µH
LTC3605A
V
3.3V
10A
OUT
100pF
10k
TRACK/SS
C
OUT1
6
47µF
ITH
SW
SW
2.21k
×2
5.4k
0.1µF
RUN PGOOD
V
PGND SW
10 11
ON
470pF
10pF
7
8
9
12
SV
IN
100k
PGND
SGND
0.1µF
C2
2.2µF
D2
10Ω
19
C
IN2
24
23
22
21
20
22µF
×2
CLKIN CLKOUT SGND INTV BOOST SV
CC
IN
0.1µF
1
2
3
4
5
6
18
17
16
15
14
13
RT
PV
PV
IN
162k
PHMODE
MODE
FB
IN
SW
SW
SW
L2 1.5µH
LTC3605A
TRACK/SS
C
OUT2
ITH
SW
SW
47µF
5.4k
RUN PGOOD
V
ON
PGND SW
10 11
470pF
10pF
7
8
9
12
SV
IN
C1, C2: AVX 0805ZD225MAT2A
PGND
SGND
C
C
, C : TDK C4532X5RIC226M
IN1 IN2
3605A TA03
, C
OUT1 OUT2
: TDK C3216X5ROJ476M
D1, D2: CENTRAL SEMI CMDSH-3
L1, L2: VISHAY IHLP-2525CZER1R5-M01
12V, 10A, 2-Phase Efficiency
12V, 10A, 2-Phase Load Step
100
90
80
70
60
50
40
30
20
10
0
V
OUT
100mV/DIV
AC-COUPLED
DCM
CCM
I
L1
2A/DIV
I
L2
2A/DIV
3605A TA03c
20µs/DIV
0.1
1
10
LOAD CURRENT (A)
3605A TA03b
3605afg
18
For more information www.linear.com/LTC3605A
LTC3605A
Typical applicaTions
Dual Output Tracking Application
C1
0.1µF
10Ω
19
D1
2.2µF
V
IN1
4V TO 20V
C
IN1
24
23
22
21
20
22µF
CLKIN CLKOUT SGND INTV BOOST SV
CC
×2
IN
0.1µF
1
2
3
4
5
18
17
16
15
14
13
RT
PV
IN
IN
162k
PHMODE
MODE
FB
PV
SW
SW
SW
L1 0.33µH
LTC3605A
V
1.8V
5A
OUT1
7.5k
TRACK/SS
16.2k
6
C
OUT1
47µF
ITH
SW
SW
2.49k
4.99k
100pF
10pF
0.1µF
RUN PGOOD
V
PGND SW
10 11
ON
7
8
9
12
SV
IN1
100k
PGND
SGND
C2
2.2µF
0.1µF
D2
10Ω
19
V
IN2
4V TO 20V
C
IN2
24
23
22
21
20
22µF
CLKIN CLKOUT SGND INTV BOOST SV
CC
×2
IN
0.1µF
1
2
3
4
5
6
18
17
16
15
14
13
RT
PV
IN
IN
162k
PHMODE
MODE
FB
PV
SW
SW
SW
L2 0.33µH
LTC3605A
V
1.2V
5A
OUT2
4.99k
TRACK/SS
16.2k
C
OUT2
47µF
ITH
SW
SW
4.99k
100pF
10pF
RUN PGOOD
V
PGND SW
10 11
ON
7
8
9
12
SV
IN2
100k
PGND
SGND
3605A TA04
C1, C2: AVX 0805ZD225MAT2A
D1, D2: CENTRAL SEMI CMDSH-3
L1, L2: VISHAY IHLP-2525CZERR33-M01
C
, C : TDK C4532X5RIC226M
IN1 IN2
C
, C
OUT1 OUT2
: TDK C3216X5ROJ476M
Dual Output Tracking Waveform
V
OUT1
500mV/DIV
V
OUT2
500mV/DIV
3605A TA04b
500µs/DIV
V
V
OUT1
= 12V
IN
= 1.8V, V
= 1.2V
= 80mA
OUT1 OUT2
= 80mA, I
I
OUT2
3605afg
19
For more information www.linear.com/LTC3605A
LTC3605A
package DescripTion
Please refer to http://www.linear.com/product/LTC3605A#packaging for the most recent package drawings.
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-ꢀ697 Rev B)
0.70 0.05
4.50 0.05
3.ꢀ0 0.05
2.45 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
R = 0.ꢀꢀ5
PIN ꢀ NOTCH
R = 0.20 TYP OR
0.35 × 45° CHAMFER
0.75 0.05
4.00 0.ꢀ0
(4 SIDES)
TYP
23 24
PIN ꢀ
TOP MARK
(NOTE 6)
0.40 0.ꢀ0
ꢀ
2
2.45 0.ꢀ0
(4-SIDES)
(UF24) QFN 0ꢀ05 REV B
0.200 REF
0.25 0.05
0.50 BSC
0.00 – 0.05
NOTE:
ꢀ. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3605afg
20
For more information www.linear.com/LTC3605A
LTC3605A
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
12/12 Updated V
specification.
3
2, 3
3
VIN_OV
B
09/13 Clarified conditions for electrical specifications.
Clarified specifications in the Electrical Characteristics section.
Clarified TRACK/SS pin description.
6
Clarified schematics.
7, 17
8
Clarified the Main Control Loop description and added RUN Threshold section header.
04/15 Clarified negative valley current limit parameter.
Added negative valley current limit explanation.
08/15 Added “Do not float this pin” to MODE pin function.
11/15 Changed RUN Voltage Abs Max Rating
Enhanced Inductor Selection section
C
3
11
6
D
E
2
11
9
F
02/16 Added new section on PV /SV Voltage Differential
IN IN
G
09/16 Modified Block Diagram
7
3605afg
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
21
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC3605A
Typical applicaTion
–3.6V Negative Converter
C
IN
0.1µF
10Ω
22µF
C1
2.2µF
D1
×2
V
IN
3V TO 16V
24
23
22
21
CC
20
19
IN
CLKIN CLKOUT SGND INTV BOOST SV
0.1µF
1
2
3
4
5
18
17
16
15
14
13
RT
PV
PV
IN
162k
PHMODE
MODE
FB
IN
SW
SW
SW
L1 1µH
LTC3605A
24.9k
4.99k
TRACK/SS
16.2k
6
C
OUT
I
SW
SW
TH
47µF
470pF
47pF
0.1µF
×2
RUN PGOOD
V
PGND SW
10 11
ON
7
8
9
12
SV
IN
100k
V
OUT
–3.6V
2A
3605A TA05
–3.6V Negative Converter Efficiency
100
–3.6V Negative Converter
90
80
70
60
50
40
30
20
10
0
DCM
SW
CCM
I
L
2A/DIV
3605A TA05c
V
V
LOAD
= 12V
400ns/DIV
IN
= –3.6V
= 2A
OUT
I
0.01
0.1
1
10
LOAD CURRENT (A)
3605A TA05b
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
95% Efficiency, V : 4V to 15V, V
LTC3605
15V, 5A (I ), 4MHz, Synchronous Step-Down DC/DC Converter
= 0.6V, I = 2mA,
OUT(MIN) Q
OUT
IN
I
< 1µA, 4mm × 4mm QFN-24
SD
LTC3603
15V, 2.5A (I ), 3MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, V : 4.5V to 15V, V
= 0.6V, I = 75µA,
Q
OUT
IN
OUT(MIN)
I
< 1µA, 3mm × 3mm QFN-16, MSE16
SD
LTC3414/
LTC3416
4A (I ), 4MHz, Synchronous Step-Down DC/DC Converters
95% Efficiency, V : 2.25V to 5.5V, V
= 0.8V, I = 64µA,
OUT(MIN) Q
OUT
IN
I
< 1µA, TSSOP-20E
SD
LTC3415
LTC3608
LTC3610
LTC3611
7A (I ), 1.5MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, V : 2.5V to 5.5V, V
= 0.6V, I = 450µA,
OUT
IN
OUT(MIN) Q
I
< 1µA, 5mm × 7mm QFN-38
SD
18V, 8A (I ) 1MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, V : 4V to 18V, V
= 0.6V, I = 900µA,
Q
OUT
IN
OUT(MIN)
OUT(MIN)
OUT(MIN)
I
< 15µA, 7mm × 8mm QFN-52
SD
24V, 12A (I ), 1MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, V : 4V to 24V, V
= 0.6V, I = 900µA,
Q
OUT
IN
I
< 15µA, 9mm × 9mm QFN-64
SD
32V, 10A (I ), 1MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, V : 4V to 32V, V
= 0.6V, I = 900µA,
Q
OUT
IN
I
< 15µA, 9mm × 9mm QFN-64
SD
3605afg
LT 0916 REV G • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
22
●
●
LINEAR TECHNOLOGY CORPORATION 2012
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3605A
相关型号：
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LTC3605A - 20V, 5A Synchronous Step-Down Regulator; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C
Linear
LTC3605EUF#PBF
LTC3605 - 15V, 5A Synchronous Step-Down Regulator; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C
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