LTC3616IUDD#PBF [Linear]
LTC3616 - 6A, 4MHz Monolithic Synchronous Step-Down DC/DC Converter; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C;
| 型号： | LTC3616IUDD#PBF |
| 厂家： | 
Linear |
| 描述： | LTC3616 - 6A, 4MHz Monolithic Synchronous Step-Down DC/DC Converter; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C 开关 输出元件 |
| 文件： | 总28页 (文件大小：525K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3616
6A, 4MHz Monolithic
Synchronous Step-Down
DC/DC Converter
DescripTion
FeaTures
The LTC®3616 is a low quiescent current monolithic syn-
chronous buck regulator using a current mode, constant
n
6A Output Current
n
2.25V to 5.5V Input Voltage Range
Low Output Ripple Burst Mode® Operation: I = 75µA frequency architecture. The no-load DC supply current
n
Q
n
n
n
n
n
±±1 Output Voltage Accuracy
in sleep mode is only 70µA while maintaining the output
voltage (Burst Mode operation) at no load, dropping to
zero current in shutdown. The 2.25V to 5.5V input supply
voltage range makes the LTC3616 ideally suited for single
Li-Ionaswellasfixedlowvoltageinputapplications.100%
duty cycle capability provides low dropout operation,
extending the operating timein battery-powered systems.
Output Voltage Down to 0.6V
High Efficiency: Up to 951
Low Dropout Operation: 100% Duty Cycle
Programmable Slew Rate on SW Node Reduces
Noise and EMI
n
n
Adjustable Switching Frequency: Up to 4MHz
Optional Active Voltage Positioning (AVP) with
Internal Compensation
The operating frequency is externally programmable up to
4MHz, allowing the use of small surface mount inductors.
For switching noise-sensitive applications, the LTC3616
can be synchronized to an external clock at up to 4MHz.
n
Selectable Pulse-Skipping/Forced Continuous/Burst
Mode Operation with Adjustable Burst Clamp
Programmable Soft-Start
n
n
n
n
ForcedcontinuousmodeoperationintheLTC3616reduces
noiseandRFinterference.Adjustablecompensationallows
the transient response to be optimized over a wide range
of loads and output capacitors.
Inputs for Start-Up Tracking or External Reference
DDR Memory Mode, I
= 3A
OUT
Available in a 24-Pin 3mm × 5mm QFN
Thermally Enhanced Package
The internal synchronous switch increases efficiency and
eliminates the need for an external catch diode, saving
external components and board space. The LTC3616
is offered in a leadless 24-pin 3mm × 5mm thermally
enhanced QFN package.
applicaTions
n
Point-of-Load Supplies
n
Distributed Power Supplies
n
Portable Computer Systems
n
DDR Memory Termination
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 6580258, 5481178, 5994885, 6304066, 6498466, 6611131.
n
Handheld Devices
Efficiency and Power Loss
Typical applicaTion
vs Load Current
100
V
IN
2.7V TO 5.5V
90
22µF
×4
SV
PV
80
70
60
50
40
30
20
10
0
1
IN
IN
RUN
SRLIM/DDR
TRACK/SS
RT/SYNC
0.1
0.01
0
220nH
V
2.5V
6A
OUT
LTC3616
SW
SGND
PGND
PGOOD
ITH
47µF
×2
MODE
V
FB
665k
3616 TA01a
V
V
V
= 2.8V
= 3.3V
= 5V
IN
IN
IN
210k
V
= 2.5V
10
OUT
1
100
1000
10000
OUTPUT CURRENT (mA)
3616 TA01b
3616fc
1
For more information www.linear.com/LTC3616
LTC3616
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note ±)
TOP VIEW
PV , SV Voltages ..................................... –0.3V to 6V
IN
IN
SW Voltage ................................. –0.3V to (PV + 0.3V)
IN
ITH, RT/SYNC Voltages............... –0.3V to (SV + 0.3V)
IN
24 23 22 21
SRLIM, TRACK/SS Voltages ....... –0.3V to (SV + 0.3V)
IN
MODE, RUN, V Voltages .......... –0.3V to (SV + 0.3V)
FB
IN
SRLIM/DDR
RT/SYNC
SGND
PGOOD
RUN
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
PGOOD Voltage............................................ –0.3V to 6V
Operating Junction Temperature Range
SV
IN
(Notes 2, 11) .......................................... –55°C to 150°C
Storage Temperature.............................. –65°C to 150°C
Reflow Peak Body Temperature (QFN)..................260°C
PV
IN
PV
IN
25
SW
SW
SW
SW
SW
SW
SW
SW
9
10 11 12
UDD PACKAGE
24-LEAD (3mm × 5mm) PLASTIC QFN
= 150°C, θ = 38°C/W
T
JMAX
JA
EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
LTC3616EUDD#PBF
LTC3616IUDD#PBF
LTC3616HUDD#PBF
LTC3616MPUDD#PBF
TAPE AND REEL
PART MARKING*
LDYG
PACKAGE DESCRIPTION
24-Lead (3mm × 5mm) Plastic QFN
TEMPERATURE RANGE
–40°C to 125°C
LTC3616EUDD#TRPBF
LTC3616IUDD#TRPBF
LTC3616HUDD#TRPBF
LDYG
24-Lead (3mm × 5mm) Plastic QFN
24-Lead (3mm × 5mm) Plastic QFN
24-Lead (3mm × 5mm) Plastic QFN
–40°C to 125°C
–40°C to 150°C
–55°C to 150°C
LDYG
LTC3616MPUDD#TRPBF LDYG
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3616fc
2
For more information www.linear.com/LTC3616
LTC3616
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VIN = 3.3V, RT/SYNC = SVIN unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
2.25
1.7
TYP
MAX
UNITS
l
V
V
Operating Voltage Range
Undervoltage Lockout Threshold
5.5
V
IN
l
l
SV Ramping Down
V
V
UVLO
IN
SV Ramping Up
2.25
IN
V
FB
Feedback Voltage Internal Reference
(Note 3) V
= SV , V = 0V
IN DDR
TRACK
0°C < T < 85°C
0.594
0.591
0.589
0.6
0.606
0.609
0.609
V
V
V
J
l
l
–40°C < T < 125°C
J
–55°C < T < 150°C
J
Feedback Voltage External Reference
(Note 7)
(Note 3) V
(Note 3) V
= 0.3V, V
= SV
= SV
0.275
0.475
0.300
0.500
0.325
0.525
30
V
V
TRACK
TRACK
DDR
IN
IN
= 0.5V, V
DDR
l
I
Feedback Input Current
Line Regulation
V
= 0.6V
FB
nA
FB
∆V
LINEREG
SV = PV = 2.25V to 5.5V
IN IN
(Notes 3, 4) TRACK/SS = SV
IN
l
l
–40°C < T < 125°C
0.2
0.3
%/V
%/V
J
–55°C < T < 150°C
J
∆V
Load Regulation
ITH from 0.5V to 0.9V (Notes 3, 4)
0.25
2.6
%
%
LOADREG
V
V
V
= SV (Note 5)
IN
ITH
I
Active Mode
Sleep Mode
= 0.5V, V
= 0.7V, V
= SV (Note 6)
1100
75
µA
µA
S
FB
MODE
IN
= 0V, ITH = SV
100
FB
MODE
IN
(Note 5)
V
= 0.7V, V
= 0V (Note 4)
130
0.1
35
175
1
µA
µA
FB
MODE
Shutdown
SV = PV = 5.5V, V
= 0V
IN
IN
RUN
R
Top Switch On-Resistance
Bottom Switch On-Resistance
Top Switch Current Limit
PV = 3.3V (Note 10)
mΩ
mΩ
DS(ON)
IN
PV = 3.3V (Note 10)
25
IN
I
Sourcing (Note 8), V = 0.5V
LIM
FB
Duty Cycle <35%
10.5
7.6
12
–8
13.5
–11
A
A
Duty Cycle = 100%
Bottom Switch Current Limit
Sinking (Note 8), V = 0.7V,
–6
A
FB
Forced Continuous Mode
g
Error Amplifier Transconductance
–5µA < I < 5µA (Note 4)
200
30
µS
µA
m(EA)
ITH
I
Error Amplifier Maximum Output
Current
(Note 4)
EAO
t
SS
Internal Soft-Start Time
V
from 0.06V to 0.54V,
FB
0.65
1.2
1.9
ms
TRACK/SS = SV
IN
V
Enable Internal Soft-Start
(Note 7 )
0.62
60
V
µs
Ω
TRACK/SS
t
Soft-Start Discharge Time at Start-Up
TRACK/SS_DIS
R
TRACK/SS Pull-Down Resistor at
Start-Up
200
ON(TRACK/SS_DIS)
l
l
f
Oscillator Frequency
RT/SYNC = 370k
= SV
0.8
1.8
0.3
1.2
.
1
1.2
2.7
4
MHz
MHz
MHz
V
OSC
Internal Oscillator Frequency
Synchronization Frequency Range
SYNC Level High
V
2.25
RT/SYNC
IN
f
SYNC
V
RT/SYNC
SYNC Level Low
0.3
1
V
I
Switch Leakage Current
DDR Option Enable Voltage
SV = PV = 5.5V, V = 0V
RUN
0.1
µA
V
SW(LKG)
IN
IN
V
SV – 0.3
IN
DDR
3616fc
3
For more information www.linear.com/LTC3616
LTC3616
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TJ = 25°C (Note 2). VIN = 3.3V, RT/SYNC = SVIN unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Internal Burst Mode Operation
Pulse-Skipping Mode
0.3
V
V
V
V
MODE
(Note 9)
SV – 0.3
IN
Forced Continuous Mode
External Burst Mode Operation
Power Good Voltage Windows
1.1
SV • 0.58
IN
0.45
0.8
PGOOD
TRACK/SS = SV , Entering Window
IN
V
V
Ramping Up
–3
3
–6
6
%
%
FB
FB
Ramping Down
TRACK/SS = SV , Leaving Window
IN
V
V
Ramping Up
9
–9
11
–11
%
%
FB
FB
Ramping Down
t
Power Good Blanking Time
Power Good Pull-Down On-Resistance
RUN Voltage
Entering and Leaving Window
70
8
105
17
140
33
µs
Ω
PGOOD
R
PGOOD
RUN
l
l
V
Input High
Input Low
1
V
V
0.4
Note ±: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3616 is tested under pulsed load conditions such that T ≈
T . The LTC3616E is guaranteed to meet specifications from 0°C to 85°C
A
Note 3: This parameter is tested in a feedback loop which servos V to
FB
the midpoint for the error amplifier (V = 0.75V).
ITH
Note 4: External compensation on ITH pin.
Note 5: Tying the ITH pin to SV enables the internal compensation and
IN
J
AVP mode.
Note 6: Dynamic supply current is higher due to the internal gate charge
junction temperature. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization
and correlation with statistical process controls. The LTC3616I is
guaranteed to meet specifications over the –40°C to 125°C operating
junction temperature, the LTC3616H is guaranteed to meet specifications
over the –40°C to 150°C operating junction temperature range and the
LTC36146MP is guaranteed and tested to meet specifications over the
full –55°C to 150°C operating junction temperature range. High junction
temperatures degrade operating lifetimes; operating lifetime is derated
for temperature greater than 125°C. Note that the maximum ambient
temperature consistent with these specifications is determined by specific
operating conditions in conjunction with board layout, the rated package
thermal impedance and other environmental factors.
being delivered at the switching frequency.
Note 7: See description of the TRACK/SS pin in the Pin Functions section.
Note 8: In sourcing mode the average output current is flowing out of SW
pin. In sinking mode the average output current is flowing into the SW Pin.
Note 9: See description of the MODE pin in the Pin Functions section.
Note ±0: Guaranteed by correlation and design to wafer level
measurements for QFN packages.
Note ±±: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 150°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
The junction temperature (T ) is calculated from the ambient temperature
J
(T ) and power dissipation (P ) according to the formula: T = T + (P
A
D
J
A
D
• θ °C/W), where θ is the package thermal impedance. The maximum
JA
JA
ambient temperature is determined by specific operating conditions in
conjunction with board layout, the rated package thermal resistance and
other environmental factors.
3616fc
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For more information www.linear.com/LTC3616
LTC3616
Typical perForMance characTerisTics VIN = 3.3V, RT/SYNC = SVIN unless otherwise noted.
Efficiency vs Load Current
Burst Mode Operation (VMODE = 0V)
Efficiency vs Load Current
Burst Mode Operation (VMODE = 0V)
Efficiency vs Load Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
= 1.8V
V
= 1.8V, V = 3.3V
IN
V
= 1.2V
OUT
OUT
OUT
V
V
V
= 2.5V
= 3.3V
= 5V
V
V
V
= 2.5V
= 3.3V
= 5V
Burst Mode OPERATION
IN
IN
IN
IN
IN
IN
PULSE-SKIPPING
FORCED CONTINUOUS
1
10
100
1000
10000
1
10
100
1000
10000
1
10
100
1000
10000
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
3616 G01
3616 G02
3616 G03
Efficiency vs Frequency
Burst Mode Operation
(VMODE = 0V), IOUT = 2A
Efficiency vs Input Voltage
Burst Mode Operation
(VMODE = 0V)
Load Regulation
(VIN = 3.3V, VOUT = ±.8V)
95
94
93
92
91
90
89
88
87
86
85
84
83
82
1.5
1.3
100
90
80
70
60
50
40
30
FORCED CONTINUOUS MODE
PULSE-SKIPPING MODE
INTERNAL Burst Mode OPERATION
V
V
= 3.3V
OUT
V
= 1.8V
IN
OUT
= 1.8V
1.1
0.9
0.7
0.5
0.3
I
I
I
I
= 6mA
0.1
OUT
OUT
OUT
OUT
150nH
330nH
470nH
= 600mA
= 2A
–0.1
–0.3
= 6A
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0
2000 3000 4000 5000 6000
OUTPUT CURRENT (mA)
1000
2.5
3
3.5
4
4.5
5
5.5
FREQUENCY (MHz)
INPUT VOLTAGE (V)
3616 G05
3616 G06
3616 G04
Line Regulation
Burst Mode Operation
Pulse-Skipping Mode Operation
0.3
0.2
V
V
OUT
OUT
0.1
20mV/DIV
20mV/DIV
0
–0.1
–0.2
–0.3
I
L
I
L
1A/DIV
1A/DIV
3616 G08
3616 G09
V
I
= 1.8V
= 150mA
= 0V
20µs/DIV
V
I
= 1.8V
= 150mA
= 3.3V
20µs/DIV
2.20
3.30 3.85 4.40
INPUT VOLTAGE (V)
4.95 5.50
2.75
OUT
OUT
MODE
OUT
OUT
MODE
V
V
3616 G07
3616fc
5
For more information www.linear.com/LTC3616
LTC3616
Typical perForMance characTerisTics VIN = 3.3V, RT/SYNC = SVIN unless otherwise noted.
Load Step Transient in
Pulse-Skipping Mode
Load Step Transient in
Burst Mode Operation
Forced Continuous Mode Operation
V
OUT
20mV/DIV
V
V
OUT
OUT
200mV/DIV
200mV/DIV
I
L
500mA/DIV
I
LOAD
I
LOAD
5A/DIV
5A/DIV
3616 G11
3616 G12
3616 G10
100µs/DIV
100µs/DIV
V
= 1.8V
1µs/DIV
OUT
OUT
V
LOAD
= 1.8V
V
LOAD
= 1.8V
OUT
OUT
I
= 100mA
I
= 100mA TO 6A, V
= 3.3V
I
= 100mA TO 6A, V
= 0V
MODE
MODE
V
= 1.5V
MODE
COMPENSATION FIGURE 1
COMPENSATION FIGURE 1
Load Step Transient in Forced
Continuous Mode Sourcing and
Sinking Current
Load Step Transient in Forced
Continuous Mode without AVP Mode
Load Step Transient in Forced
Continuous Mode with AVP Mode
V
V
V
OUT
200mV/DIV
OUT
OUT
200mV/DIV
200mV/DIV
I
I
I
LOAD
5A/DIV
LOAD
LOAD
5A/DIV
5A/DIV
3616 G13
3616 G14
3616 G15
100µs/DIV
100µs/DIV
100µs/DIV
= –3A TO 6A, V = 1.5V
V
LOAD
= 1.8V
V
LOAD
= 1.8V
V
= 1.8V
OUT
OUT
OUT
I
= 100mA TO 6A, V
= 1.5V
I
= 100mA TO 6A, V
= 1.5V
I
LOAD
MODE
MODE
MODE
COMPENSATION FIGURE 1
COMPENSATION FIGURE 1
Tracking Up/Down in
Forced Continuous Mode,
Non DDR Mode
Internal Start-Up in Forced
Continuous Mode
Sinking Current
RUN
10V/DIV
V
OUT
100mV/DIV
V
OUT
PGOOD
10V/DIV
1V/DIV
V
SW
2V/DIV
OUT
V
TRACK/SS
500mV/DIV
500mV/DIV
I
L
I
L
PGOOD
2V/DIV
2A/DIV
2A/DIV
3616 G18
3616 G16
3616 G17
2ms/DIV
1µs/DIV
500µs/DIV
V
= 1.8V
= –3A, V
V
= 1.8V
= 0A, V
OUT
OUT
OUT
OUT
V
= 0V TO 1.8V
OUT
OUT
I
= 1.5V
I
= 1.5V
MODE
MODE
I
= 3A, V
= 0V TO 0.7V
TRACK/SS
V
= 1.5V, V
= 0V
DDR
MODE
3616fc
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For more information www.linear.com/LTC3616
LTC3616
Typical perForMance characTerisTics VIN = 3.3V, RT/SYNC = SVIN unless otherwise noted.
Tracking Up/Down in Forced
Continuous Mode, DDR Pin Tied
to SVIN
Reference Voltage
vs Temperature
Switch On-Resistance
vs Input Voltage
0.05
0.04
0.03
0.02
0.01
0
0.606
0.604
V
OUT
MAIN SWITCH
500mV/DIV
0.602
0.600
0.598
SYNCHRONOUS SWITCH
V
TRACK/SS
200mV/DIV
PGOOD
2V/DIV
0.596
0.594
3616 G19
2ms/DIV
2.5
3.0
3.5
4.0
4.5
5.0
5.5
–60 –40 –20
0
20 40 60 80 100 120 140 160
V
= 0V TO 1.2V
OUT
OUT
INPUT VOLTAGE (V)
TEMPERATURE (°C)
I
= 3A, V
= 0V TO 0.4V
TRACK/SS
3616 G21
V
= 1.5V, V
= 3.3V
SRLIM/DDR
3616 G20
MODE
Switch On-Resistance
vs Temperature
Frequency vs Resistor on
RT/SYNC Pin
Frequency vs Temperature
1.0
0.5
0.050
0.045
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0
4500
4000
3500
3000
2500
2000
1500
1000
500
MAIN SWITCH
0
–0.5
–1.0
–1.5
SYNCHRONOUS SWITCH
0
–60 –40 –20
0
20 40 60 80 100 120 140 160
–60 –40 –20
0
20 40 60
140 160
80 100 120
0
200 400 600
1400
800 1000 1200
TEMPERATURE (°C)
TEMPERATURE (°C)
RESISTOR ON RT/SYNC PIN (kΩ)
3616 G24
3616 G22
3616 G23
Switch Leakage vs Temperature,
Main Switch
Switch Leakage vs Temperature,
Synchronous Switch
Frequency vs Input Voltage
1.0
0.5
14000
12000
10000
8000
6000
4000
2000
0
16000
14000
12000
10000
8000
6000
4000
2000
0
V
IN
V
IN
V
IN
= 2.25V
= 3.3V
= 5.5V
V
V
V
= 2.25V
= 3.3V
= 5.5V
IN
IN
IN
0
–0.5
–1.0
–1.5
–2.0
–2.5
2.25
40
TEMPERATURE (°C)
20 40
0
2.75 3.25
3.75 4.25 4.75 5.25
INPUT VOLTAGE (V)
–60
–10
90
140
–60 –40 –20
60 80 100 120 140 160
TEMPERATURE (°C)
3616 G25
3616 G27
3616 G27
3616fc
7
For more information www.linear.com/LTC3616
LTC3616
Typical perForMance characTerisTics VIN = 3.3V, RT/SYNC = SVIN unless otherwise noted.
Dynamic Supply Current vs Input
Voltage without AVP Mode
Dynamic Supply Current vs
VOUT Short to GND,
Forced Continuous Mode
Temperature without AVP Mode
100
10
1
100
10
1
FORCED CONTINUOUS MODE
FORCED CONTINUOUS MODE
V
OUT
500mV/DIV
PULSE-SKIPPING MODE
Burst Mode OPERATION
PULSE-SKIPPING MODE
Burst Mode OPERATION
I
L
5A/DIV
0.1
0.1
0.01
0.01
3616 G30
100µs/DIV
–60 –40 –20
0
20 40 60 80 100 120 140 160
2.25 2.75 3.25 3.75 4.25 4.75 5.25
V
= 1.8V
= 0A
MODE
OUT
OUT
TEMPERATURE (°C)
INPUT VOLTAGE (V)
I
3616 G29
3616 G28
V
= 1.5V
Start-Up from Shutdown with
Prebiased Output
(Forced Continuous Mode)
Output Voltage During Sinking
vs Input Voltage (VOUT = ±.8V,
0.47µH Inductor)
1.88
PGOOD
5V/DIV
1.86
1.84
1.82
1.80
1.78
1.76
1.74
V
OUT
500mV/DIV
–3A, 2MHz, 120°C
–3A, 2MHz, 25°C
I
L
5A/DIV
3616 G31
50µs/DIV
= 2.2V
= 0A
2.25
2.75
3.25
4
4.5
5.25
PREBIASED V
OUT
OUT
INPUT VOLTAGE (V)
V
V
= 1.2V, I
OUT
MODE
3616 G32
= 1.5V
3616fc
8
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LTC3616
pin FuncTions
SRLIM/DDR (Pin ±): Slew Rate Limit. Tying this pin to
ground selects maximum slew rate. Minimum slew rate
is selected when the pin is open. Connecting a resistor
from SRLIM/DDR to ground allows the slew rate to be
FB voltage leaves the power good window for more than
100µs the PGOOD pin is pulled down.
InDDRmode(DDR=V ), thepowergoodwindowmoves
IN
in relation to the actual TRACK/SS pin voltage. During
continuously adjusted. If SRLIM/DDR is tied to S , DDR
VIN
up/down tracking the PGOOD pin is always pulled down.
mode is selected. In DDR mode the slew rate limit is set
In shutdown the PGOOD output will actively pull down
and may be used to discharge the output capacitors via
an external resistor.
to maximum.
RT/SYNC (Pin 2): Oscillator Frequency. This pin provides
three ways of setting the constant switching frequency:
MODE (Pin 2±): Mode Selection. Tying the MODE pin
1. Connecting a resistor from RT/SYNC to ground will set
the switching frequency based on the resistor value.
to SV or SGND enables pulse-skipping mode or Burst
IN
Mode operation (with an internal Burst Mode clamp),
2. Driving the RT/SYNC pin with an external clock signal
will synchronize the LTC3616 to the applied frequency.
Theslopecompensationisautomaticallyadaptedtothe
external clock frequency.
respectively. If this pin is held at slightly higher than half
of SV , forced continuous mode is selected. Connecting
IN
this pin to an external voltage selects Burst Mode opera-
tion with the burst clamp set to the pin voltage. See the
Operation section for more details.
3. Tying the RT/SYNC pin to SV enables the internal
IN
2.25MHz oscillator frequency.
V
(Pin 22): Voltage Feedback Input Pin. Senses the
FB
feedbackvoltagefromtheexternalresistivedivideracross
the output.
SGND (Pin 3): Signal Ground. All small-signal and com-
pensation components should connect to this ground,
which in turn should connect to PGND at a single point.
ITH (Pin 23): Error Amplifier Compensation. The current
comparator’s threshold increases with this control volt-
age. Tying this pin to SVIN enables internal compensation
and AVP mode.
PV (Pins 4, ±0, ±±, ±7): Power Input Supply. PV
IN
IN
connects to the source of the internal P-channel power
MOSFET. This pin is independent of SV and may be con-
IN
nected to the same voltage or to a lower voltage supply.
TRACK/SS (Pin 24): Track/External Soft-Start/External
Reference. Start-up behavior is programmable with the
TRACK/SS pin:
SW (Pins 5, 6, 7, 8, ±3, ±4, ±5, ±6): Switch Node. Con-
nection to the inductor. These pins connect to the drains
of the internal synchronous power MOSFET switches.
1. Tying this pin to SV selects the internal soft-start
IN
circuit.
NC (Pins 9, ±2): Can be connected to ground or left open.
2. External soft-start timing can be programmed with a
SV (Pin ±8): Signal Input Supply. This pin powers the
IN
capacitor to ground and a resistor to SV .
IN
internal control circuitry and is monitored by the under-
voltage lockout comparator.
3. TRACK/SS can be used to force the LTC3616 to track
the start-up behavior of another supply.
RUN(Pin±9):EnablePin. Forcingthispintogroundshuts
downtheLTC3616.Inshutdown,allfunctionsaredisabled
and the chip draws <1µA of supply current.
The pin can also be used as external reference input. See
theApplicationsInformationsectionformoreinformation.
PGOOD (Pin 20): Power Good. This open-drain output is
pulled down to SGND on start-up and while the FB voltage
is outside the power good voltage window. If the FB volt-
age increases and stays inside the power good window
for more than 100µs the PGOOD pin is released. If the
PGND (Exposed Pad Pin 25): Power Ground. This pin
connects to the source of the internal N-channel power
MOSFET. This pin should be connected close to the (–)
terminal of C and C
.
IN
OUT
3616fc
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For more information www.linear.com/LTC3616
LTC3616
FuncTional block DiagraM
SV
SGND
RT/SYNC
ITH
PV PV PV PV
IN
IN
IN
IN
IN
ITH SENSE
COMPARATOR
+
–
BANDGAP
AND
BIAS
RUN
INTERNAL
COMPENSATION
CURRENT
SENSE
OSCILLATOR
SV – 0.3V
IN
R
PMOS CURRENT
COMPARATOR
–
+
ITH
LIMIT
+
–
FOLDBACK
AMPLIFIER
–
+
0.3V
SLOPE
COMPENSATION
ERROR
AMPLIFIER
0.6V
BURST
COMPARATOR
+
–
–
+
V
SW
SW
SW
SW
SW
SW
SW
SW
SLEEP
FB
DRIVER
+
MODE
TRACK/SS
SOFT-START
0.555V
+
–
LOGIC
REVERSE
+
–
COMPARATOR
+
–
I
REV
0.645V
PGND
PGOOD
EXPOSED PAD
SRLIM/DDR
MODE
3616 BD
3616fc
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For more information www.linear.com/LTC3616
LTC3616
operaTion
Main Control Loop
Mode Selection
The LTC3616 is a monolithic, constant frequency, current
mode step-down DC/DC converter. During normal opera-
tion, the internal top power switch (P-channel MOSFET) is
turned on at the beginning of each clock cycle. Current in
the inductor increases until the current comparator trips
and turns off the top power switch. The peak inductor cur-
rent at which the current comparator trips is controlled by
the voltage on the ITH pin. The error amplifier adjusts the
voltage on the ITH pin by comparing the feedback signal
The MODE pin is used to select one of four different
operating modes:
Mode Selection Voltage
SV
IN
PS
FC
PULSE-SKIPPING MODE ENABLE
SV – 0.3V
IN
SV • 0.58
IN
FORCED CONTINUOUS MODE ENABLE
1.1V
from a resistor divider on the V pin with an internal 0.6V
FB
0.8V
Burst Mode ENABLE—EXTERNAL CLAMP,
CONTROLLED BY VOLTAGE APPLIED AT
MODE PIN
BM
EXT
reference. When the load current increases, it causes a
reduction in the feedback voltage relative to the reference.
The error amplifier raises the ITH voltage until the average
inductor current matches the new load current. Typical
voltage range for the ITH pin is from 0.1V to 1.05V with
0.45V corresponding to zero current.
0.45V
0.3V
BM
Burst Mode ENABLE—INTERNAL CLAMP
SGND
3616 OP01
Burst Mode Operation—Internal Clamp
Connecting the MODE pin to SGND enables Burst Mode
operation with an internal clamp. In Burst Mode operation
the internal power switches operate intermittently at light
loads. This increases efficiency by minimizing switching
losses. During the intervals when the switches are idle,
the LTC3616 enters sleep state where many of the internal
circuits are disabled to save power. During Burst Mode
operation,theminimumpeakinductorcurrentisinternally
clamped and the voltage on the ITH pin is monitored by
the burst comparator to determine when sleep mode is
enabled and disabled. When the average inductor current
is greater than the load current, the voltage on the ITH pin
drops. As the ITH voltage falls below the internal clamp,
the burst comparator trips and enables sleep mode. Dur-
ing sleep mode, the power MOSFETs are held off and the
load current is solely supplied by the output capacitor.
When the output voltage drops, the top power switch is
turned back on and the internal circuits are re-enabled.
This process repeats at a rate that is dependent on the
load current.
When the top power switch shuts off, the synchronous
power switch (N-channel MOSFET) turns on until either
the bottom current limit is reached or the next clock cycle
begins. The bottom current limit is typically set at –8A for
forced continuous mode and 0A for Burst Mode operation
and pulse-skipping mode.
The operating frequency defaults to 2.25MHz when
RT/SYNC is connected to SV , or can be set by an ex-
IN
ternal resistor connected between the RT/SYNC pin and
ground, or by a clock signal applied to the RT/SYNC pin.
The switching frequency can be set from 300kHz to 4MHz.
Overvoltage and undervoltage comparators pull the
PGOOD output low if the output voltage varies more than
7.5% (typical) from the set point.
3616fc
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LTC3616
operaTion
Burst Mode Operation—External Clamp
Dropout Operation
ConnectingtheMODEpintoavoltageintherangeof0.45V
to0.8VenablesBurstModeoperationwithexternalclamp.
Duringthismodeofoperationtheminimumvoltageonthe
ITH pin is externally set by the voltage on the MODE pin.
Astheinputsupplyvoltageapproachestheoutputvoltage,
the duty cycle increases toward the maximum on-time.
Further reduction of the supply voltage forces the main
switch to remain on for more than one cycle, eventually
reaching 100% duty cycle. The output voltage will then be
determined by the input voltage minus the voltage drop
across the internal P-channel MOSFET and the inductor.
Pulse-Skipping Mode Operation
Pulse-skipping mode is similar to Burst Mode operation,
but the LTC3616 does not disable power to the internal
circuitry during sleep mode. This improves output voltage
ripple but uses more quiescent current, compromising
light load efficiency.
Low Supply Operation
The LTC3616 is designed to operate down to an input
supplyvoltageof2.25V.Animportantconsiderationatlow
input supply voltages is that the R
of the P-channel
DS(ON)
Tying the MODE pin to SV enables pulse-skippingmode.
IN
andN-channelpowerswitchesincreases. Theusershould
calculate the power dissipation when the LTC3616 is used
at 100% duty cycle with low input voltages to ensure that
thermal limits are not exceeded. See the Typical Perfor-
mance Characteristics graphs.
As the load current decreases, the peak inductor current
will be determined by the voltage on the ITH pin until the
ITHvoltagedropsbelowthevoltagelevelcorrespondingto
0A. At this point, the peak inductor current is determined
by the minimum on-time of the current comparator. If
the load demand is less than the average of the minimum
on-time inductor current, switching cycles will be skipped
to keep the output voltage in regulation.
Short-Circuit Protection
Thepeakinductorcurrentatwhichthecurrentcomparator
shuts off the top power switch is controlled by the voltage
on the ITH pin.
Forced Continuous Mode
In forced continuous mode the inductor current is con-
stantly cycled which creates a minimum output voltage
ripple at all output current levels.
If the output current increases, the error amplifier raises
the ITH pin voltage until the average inductor current
matches the new load current. In normal operation the
LTC3616 clamps the maximum ITH pin voltage at ap-
proximately 1.05V which corresponds typically to 12A
peak inductor current.
Connecting the MODE pin to a voltage in the range of
1.1V to SV • 0.58 will enable forced continuous mode
IN
operation.
Whentheoutputisshortedtoground,theinductorcurrent
decays very slowly during a single switching cycle. The
LTC3616 uses two techniques to prevent current runaway
from occurring.
At light loads, forced continuous mode operation is less
efficient than Burst Mode or pulse-skipping operation, but
may be desirable in some applications where it is neces-
sary to keep switching harmonics out of the signal band.
Forced continuous mode must be used if the output is
required to sink current.
3616fc
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LTC3616
operaTion
Iftheoutputvoltagedropsbelow50%ofitsnominalvalue,
the clamp voltage at ITH pin is lowered causing the maxi-
mum peak inductor current to decrease gradually with the
output voltage. When the output voltage reaches 0V the
clamp voltage at the ITH pin drops to 40% of the clamp
voltage during normal operation. The short-circuit peak
inductor current is determined by the minimum on-time
of the LTC3616, the input voltage and the inductor value.
This foldback behavior helps in limiting the peak inductor
currentwhentheoutputisshortedtoground.Itisdisabled
duringinternalorexternalsoft-startandtrackingup/down
operation (see the Applications Information section).
A secondary limit is also imposed on the valley inductor
current. If the inductor current measured through the
bottom MOSFET increases beyond 12A typical, the top
power MOSFET will be held off and switching cycles will
be skipped until the inductor current is reduced.
applicaTions inForMaTion
The basic LTC3616 application circuit is shown in Figure 1.
ramp current that is used to charge and discharge an
internal timing capacitor within the oscillator and can be
calculated by using the following equation:
Operating Frequency
3.82 •1011Hz
Selectionoftheoperatingfrequencyisatrade-offbetween
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
RT =
Ω – 16kΩ
fOSC Hz
( )
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage.
Although frequencies as high as 4MHz are possible, the
minimum on-time of the LTC3616 imposes a minimum
limit on the operating duty cycle. The minimum on-time
is typically 60ns; therefore, the minimum duty cycle is
equal to 60ns•f (Hz)•100%.
OSC
The operating frequency of the LTC3616 is determined
by an external resistor that is connected between the RT/
SYNC pin and ground. The value of the resistor sets the
Tying the RT/SYNC pin to SV sets the default internal
IN
operating frequency to 2.25MHz 20%.
V
IN
2.25V TO 5.5V
C
IN1
R
22µF
SS
SV
RUN
PV
IN
IN
2M
×4
TRACK/SS SRLIM/DDR
RT/SYNC
L1
220nH
C
SS
V
1.8V
6A
OUT
R
T
22nF
LTC3616
SW
SGND
PGND
R
130k
C
C
C
OUT2
100µF
OUT1
PGOOD
ITH
15k
47µF
C
R1
392k
MODE
V
C1
FB
C
C
10pF
470pF
3616 F01
(OPT)
R2
196k
Figure ±. ±.8V, 6A Step-Down Regulator
3616fc
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For more information www.linear.com/LTC3616
LTC3616
applicaTions inForMaTion
Frequency Synchronization
Inductor Selection
The LTC3616’s internal oscillator can be synchronized to
an external frequency by applying a square wave clock
signaltotheRT/SYNCpin.Duringsynchronization,thetop
switch turn-on is locked to the falling edge of the external
frequency source. The synchronization frequency range
is 300kHz to 4MHz. During synchronization all operation
modes can be selected.
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ∆I increases with higher V and decreases
L
IN
with higher inductance:
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎞
⎟
⎠
VOUT
VOUT
∆I =
• 1–
⎜
L
f
•L
V
⎝
IN
SW
It is recommended that the regulator is powered down
(RUN pin to ground) before removing the clock signal on
theRT/SYNCpininordertoreduceinductorcurrentripple.
Having a lower ripple current reduces the core losses
in the inductor, the ESR losses in the output capacitors
and the output voltage ripple. A reasonable starting point
for selecting the ripple current is ∆I = 0.3 • I
.
AC coupling should be used if the external clock generator
cannotprovideacontinuousclocksignalthroughoutstart-
up, operation and shutdown of the LTC3616. The size of
L
OUT(MAX)
The largest ripple current occurs at the highest V . To
IN
guarantee that the ripple current stays below a specified
maximum, theinductorvalueshouldbechosenaccording
to the following equation:
capacitor C
depends on parasitic capacitance on the
SYNC
RT/SYNC pin and is typically in the range of 10pF to 22pF.
⎛
⎞
⎛
⎞
⎟
⎠
VOUT
fSW • ∆IL(MAX)
VOUT
⎜
⎟
L =
• 1–
⎜
V
IN
⎜
⎟
LTC3616
V
⎝
IN
⎝
⎠
SV
f
IN
OSC
2.25MHz
RT/SYNC
The inductor value will also have an effect on Burst Mode
operation. The transition to low current operation begins
whenthepeakinductorcurrentfallsbelowalevelsetbythe
burst clamp. Lower inductor values result in higher ripple
current which causes this to occur at lower load currents.
This causes a dip in efficiency in the upper range of low
current operation. In Burst Mode operation, lower induc-
tance values will cause the burst frequency to increase.
V
IN
LTC3616
SV
IN
f
∝1/R
T
0.4V
OSC
RT/SYNC
SGND
R
T
V
IN
LTC3616
SV
IN
f
OSC
1/T
RT/SYNC
SGND
P
Inductor Core Selection
1.2V
0.3V
Once the value forL is known, the type ofinductormust be
selected. Actual core loss is independent of core size for
fixed inductor value, but it is very dependent on the induc-
tanceselected.Astheinductanceincreases,corelossesde-
crease.Unfortunately,increasedinductancerequiresmore
turns ofwire and therefore, copperlosses willincrease.
T
P
V
IN
LTC3616
SV
C
SYNC
IN
f
OSC
1/T
RT/SYNC
SGND
P
R
T
3616 F02
Figure 2. Setting the Switching Frequency
3616fc
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LTC3616
applicaTions inForMaTion
Table ±. Representative Surface Mount Inductors
Ferrite designs have very low core losses and are pre-
ferred at high switching frequencies, so design goals
can concentrate on copper loss and preventing satura-
tion. Ferrite core material saturates “hard,” meaning
that inductance collapses abruptly when the peak design
current is exceeded. This results in an abrupt increase in
inductor ripple current and consequently output voltage
ripple. Do not allow a ferrite core to saturate and select
external inductors respecting the temperature range of
the application!
INDUCTANCE
(μH)
DCR
(mΩ)
MAX
CURRENT (A)
DIMENSIONS
(mm)
HEIGHT
(mm)
Vishay IHLP-2525CZ-0±
0.10
0.15
0.20
0.22
0.33
0.47
1.5
1.9
2.4
2.5
3.5
4
60
52
41
40
30
26
6.5 × 6.9
6.5 × 6.9
6.5 × 6.9
6.5 × 6.9
6.5 × 6.9
6.5 × 6.9
3
3
3
3
3
3
Sumida CDMC6D28 Series
Different core materials and shapes will change the size/
currentandprice/currentrelationshipofaninductor.Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price versus size requirements
and any radiated field/EMI requirements. Table 1 shows
some typical surface mount inductors that work well in
LTC3616 applications.
0.2
0.3
2.5
3.2
4.2
21.7
15.4
13.6
7.25 × 4.4
7.25 × 4.4
7.25 × 4.4
3
3
3
0.47
Cooper HCP0703 Series
0.22
0.47
0.68
2.8
4.2
5.5
23
17
15
7 × 7.3
7 × 7.3
7 × 7.3
3.0
3.0
3.0
Würth Electronik WE-HC7443±2 Series
0.25
0.47
2.5
3.4
18
16
7 × 7.7
7 × 7.7
3.8
3.8
Input Capacitor (C ) Selection
Coilcraft SLC7530 Series
IN
0.100
0.188
0.272
0.350
0.400
0.123
0.100
0.100
0.100
0.100
20
21
14
11
8
7.5 × 6.7
7.5 × 6.7
7.5 × 6.7
7.5 × 6.7
7.5 × 6.7
3
3
3
3
3
In continuous mode, the source current of the top P-
channel MOSFET is a square wave of duty cycle V /V .
OUT IN
To prevent large voltage transients, a low ESR capacitor
sized for the maximum RMS current must be used at V .
IN
The maximum RMS capacitor current is given by:
⎛
⎜
⎝
⎞
VOUT
V
IN
V
OUT
IRMS =IOUT(MAX)
•
•
– 1
⎟
⎠
V
IN
This formula has a maximum at V = 2V , where I =
RMS
IN
OUT
I
/2.Thissimpleworst-caseconditioniscommonlyused
OUT
fordesignbecauseevensignificantdeviationsdonotoffer
muchrelief.Notethatripplecurrentratingsfromcapacitor
manufacturers are often based on only 2000 hours of life
which makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required. Generally select the capacitors respecting the
temperature range of the application! Several capacitors
may also be paralleled to meet size or height requirements
in the design.
3616fc
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LTC3616
applicaTions inForMaTion
Output Capacitor (C ) Selection
Ceramic capacitors are prone to temperature effects
which require the designer to check loop stability over
the operating temperature range. To minimize their large
temperature and voltage coefficients, only X5R or X7R
ceramic capacitors should be used.
OUT
The selection of C
is typically driven by the required
OUT
ESR to minimize voltage ripple and load step transients
(low ESR ceramic capacitors are discussed in the next
section). Typically, once the ESR requirement is satisfied,
the capacitance is adequate for filtering. The output ripple
Whenaceramiccapacitorisusedattheinputandthepower
is being supplied through long wires, such as from a wall
adapter, a load step at the output can induce ringing at
∆V
is determined by:
OUT
⎛
⎜
⎝
⎞
⎟
⎠
1
the V pin. At best, this ringing can couple to the output
∆VOUT ≤ ∆I • ESR+
IN
L
8 • fSW •COUT
and be mistaken as loop instability. At worst, the ringing
at the input can be large enough to damage the part.
where f
= operating frequency, C
L
= output capaci-
OUT
OSC
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement.Duringaloadstep,theoutputcapacitormust
instantaneouslysupplythecurrenttosupporttheloaduntil
thefeedbackloopraisestheswitchcurrentenoughtosup-
port the load. The time required for the feedback loop to
respond is dependent on the compensation components
and the output capacitor size. Typically, 3 to 4 cycles are
requiredtorespondtoaloadstep,butonlyinthefirstcycle
tance and ∆I = ripple current in the inductor. The output
ripple is highest at maximum input voltage since ∆I
increases with input voltage.
L
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or RMS
currenthandlingrequirementoftheapplication.Aluminum
electrolytic, special polymer, ceramic and dry tantalum
capacitors are all available in surface mount packages.
does the output drop linearly. The output droop, V
,
DROOP
Tantalumcapacitorshavethehighestcapacitancedensity,
but can have higher ESR and must be surge tested for
use in switching power supplies. Aluminum electrolytic
capacitors have significantly higher ESR, but can often
be used in extremely cost-sensitive applications provided
that consideration is given to ripple current ratings and
long-term reliability.
is usually about 2 to 4 times the linear drop of the first
cycle; however, this behavior can vary depending on the
compensation component values. Thus, a good place to
start is with the output capacitor size of approximately:
3.5 • ∆IOUT
fSW • VDROOP
COUT
≈
Ceramic Input and Output Capacitors
This is only an approximation; more capacitance may
be needed depending on the duty cycle and load step
requirements.
Ceramic capacitors have the lowest ESR and can be cost
effective, but also have the lowest capacitance density,
high voltage and temperature coefficients, and exhibit
audible piezoelectric effects. In addition, the high Q of
ceramic capacitors along with trace inductance can lead
to significant ringing.
Inmostapplications,theinputcapacitorismerelyrequired
to supply high frequency bypassing, since the impedance
to the supply is very low.
They are attractive for switching regulator use because
of their very low ESR, but great care must be taken when
using only ceramic input and output capacitors.
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LTC3616
applicaTions inForMaTion
Output Voltage Programming
Pulse-skippingmode,whichisacompromisebetweenlow
output voltage ripple and efficiency, can be implemented
The output voltage is set by an external resistive divider
according to the following equation:
by connecting MODE to SV . This sets I
to 0A. In
IN
BURST
this condition, the peak inductor current is limited by the
minimum on-time of the current comparator. The low-
est output voltage ripple is achieved while still operating
discontinuously. During very light output loads, pulse-
skipping allows only a few switching cycles to skip while
maintaining the output voltage in regulation.
⎛
⎞
⎟
⎠
R1
R2
VOUT = 0.6 • 1+
V
⎜
⎝
The resistive divider allows pin V to sense a fraction of
FB
the output voltage as shown in Figure 1.
Burst Clamp Programming
Internal and External Compensation
If the voltage on the MODE pin is less than 0.8V, Burst
Mode operation is enabled.
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC load current.
If the voltage on the MODE pin is less than 0.3V, the in-
ternal default burst clamp level is selected. The minimum
voltage on the ITH pin is typically 525mV (internal clamp).
When a load step occurs, V
shifts by an amount equal
OUT
to∆I
,whereESRistheeffectiveseriesresistance
also begins to charge or discharge C
LOAD(ESR)
of C . ∆I
,
OUT
LOAD
OUT
If the voltage is between 0.45V and 0.8V, the voltage on
generatingthefeedbackerrorsignalthatforcestheregula-
tor to adapt to the current change and return V to its
the MODE pin (V
) is equal to the minimum voltage
BURST
OUT
on the ITH pin (external clamp) and determines the burst
clamp level I (typically from 0A to 7A).
steady-state value. During this recovery time V
can
OUT
BURST
be monitored for excessive overshoot or ringing, which
would indicate a stability problem. The availability of the
ITH pin allows the transient response to be optimized over
a wide range of output capacitance.
When the ITH voltage falls below the internal (or external)
clamp voltage, the sleep state is enabled.
Astheoutputloadcurrentdrops,thepeakinductorcurrent
decreases to keep the output voltage in regulation. When
the output load current demands a peak inductor current
The ITH external components (R and C ) shown in Fig-
C
C
ure 1 provide adequate compensation as a starting point
for most applications. The values can be modified slightly
to optimize transient response once the final PCB layout
is done and the particular output capacitor type and value
have been determined. The output capacitors need to be
selected because the various types and values determine
the loop gain and phase. The gain of the loop will be in-
that is less than I
, the burst clamp will force the peak
BURST
inductor current to remain equal to I
regardless of
BURST
further reductions in the load current.
Since the average inductor current is greater than the out-
put load current, the voltage on the ITH pin will decrease.
When the ITH voltage drops, sleep mode is enabled in
which both power switches are shut off along with most
of the circuitry to minimize power consumption. All cir-
cuitry is turned back on and the power switches resume
operationwhentheoutputvoltagedropsoutofregulation.
creased by increasing R and the bandwidth of the loop
C
will be increased by decreasing C . If R is increased by
C
C
the same factor that C is decreased, the zero frequency
C
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system. The external capaci-
The value for I
is determined by the desired amount
BURST
of output voltage ripple. As the value of I
increases,
BURST
the sleep period between pulses and the output voltage
ripple increase. Note that for very high V voltage
tor, C , (Figure 1) is not needed for loop stability, but it
C1
BURST
helps filter out any high frequency noise that may couple
settings, the power good comparator may trip, since the
outputripplemaygetbiggerthanthepowergoodwindow.
onto that node.
3616fc
17
For more information www.linear.com/LTC3616
LTC3616
applicaTions inForMaTion
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
If the ITH pin is tied to SV , the active voltage position-
IN
ing (AVP) mode and internal compensation are selected.
AVP mode intentionally compromises load regulation by
reducing the gain of the feedback circuit, resulting in an
outputvoltagethatvarieswithloadcurrent. Whentheload
currentsuddenlyincreases, theoutputvoltagestartsfrom
a level slightly higher than nominal so the output voltage
can droop more and stay within the specified voltage
range. When the load current suddenly decreases the
output voltage starts at a level lower than nominal so the
output voltage can have more overshoot and stay within
the specified voltage range (see Figures 3 and 4).
with C , causing a rapid drop in V . No regulator can
OUT
OUT
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. More output
capacitance may be required depending on the duty cycle
and load step requirements.
AVP Mode
Fast load transient response, limited board space and low
cost are typical requirements of microprocessor power
supplies. A microprocessor has typical full load step with
veryfastslewrate.Thevoltageatthemicroprocessormust
be held to about 0.1V of nominal in spite of these load
current steps. Since the control loop cannot respond this
fast, the output capacitors must supply the load current
until the control loop can respond.
Thebenefitisalowerpeak-to-peakoutputvoltagedeviation
for a given load step without having to increase the output
filter capacitance. Alternatively, the output voltage filter
capacitance can be reduced while maintaining the same
peak to peak transient response. Due to the reduced loop
gain in AVP mode, no external compensation is required.
Normally, several capacitors in parallel are required to
meet microprocessor transient requirements. Capacitor
ESR and ESL primarily determine the amount of droop or
overshoot in the output voltage.
DDR Mode
TheLTC3616canbothsourceandsinkcurrentiftheMODE
pin is configured to forced continuous mode.
Currentsinkingistypicallylimitedto3Afor1MHzfrequency
and a0.47µH inductor, but can belowerathigher frequen-
cies and low output voltages. If higher ripple current can
be tolerated, smaller inductor values can increase the sink
current limit. See the Typical Performance Characteristics
curves for more information.
ConsidertheLTC3616withoutAVP withabankoftantalum
output capacitors. If a load step with very fast slew rate
occurs, the voltage excursion will be seen in both direc-
tions, for full load to minimum load transient and for the
minimum load to full load transient.
V
OUT
100mV/DIV
V
OUT
200mV/DIV
I
L
I
L
1A/DIV
1A/DIV
3616 F03
3616 F04
V
V
I
= 3.3V
50µs/DIV
V
V
I
= 3.3V
50µs/DIV
IN
OUT
IN
OUT
= 1.8V
= 1.8V
= 100mA TO 3A
= 1.5V
= 100mA TO 3A
= 1.5V
LOAD
LOAD
MODE
V
V
MODE
COMPENSATION FIGURE 1
V
= 3.3V
ITH
OUTPUT CAPACITOR VALUE FIGURE 1
Figure 3. Load Step Transient Forced
Continuous Mode (AVP Inactive)
Figure 4. Load Step Transient Forced
Continuous Mode with AVP Mode
3616fc
18
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LTC3616
applicaTions inForMaTion
In addition, tying the SRLIM/DDR pin to SV , lower
for ten microseconds in order to discharge the external
capacitor. This discharging time is typically adequate
for capacitors up to about 33nF. If a larger capacitor is
required, connect the external soft-start resistor to the
RUN pin.
IN
external reference voltage and tracking output voltage
between channels are possible. See the Output Voltage
Tracking and External Reference Input sections.
Soft-Start
Regardless of either internal or external soft-start state,
the MODE pin is ignored and soft-start will always be in
pulse-skipping mode. In addition, the PGOOD pin is kept
low and foldback of the switching frequency is disabled.
TheRUNpinprovidesameanstoshutdowntheLTC3616.
Tying the RUN pin to SGND places the LTC3616 in a low
quiescent current shutdown state (I < 1µA).
Q
When the LTC3616 is enabled by pulling the RUN pin
high, the chip enters a soft start-up state. The type of soft
start-up behavior is set by the TRACK/SS pin:
Programmable Switch Pin Slew Rate
Asswitchingfrequenciesrise,itisdesirabletominimizethe
transitiontimerequiredwhenswitchingtominimizepower
losses and blanking time for the switch to settle. However,
fast slewing of the switch node results in relatively high
external radiated EMI and high on chip supply transients,
which can cause problems for some applications.
1. Tying TRACK/SS to SV selects the internal soft-start
IN
circuit. This circuit ramps the output voltage to the final
value within 1ms.
2. If a longer soft-start period is desired, it can be set
externally with a resistor and capacitor on the TRACK/
SSpinasshowninFigure1.TheTRACK/SSpinreduces
The LTC3616 allows the user to control the slew rate of
the switching node SW by using the SRLIM/DDR pin.
Tying this pin to ground selects the fastest slew rate. The
slowest slew rate is selected when the pin is open. Con-
necting a resistor (between 10k and 100k) from SRLIM
pin to ground adjusts the slew rate between the maximum
and minimum values. The reduced dV/dt of the switch
node results in a significant reduction of the supply and
ground ringing, as well as lower radiated EMI.
the value of the internal reference at V until TRACK/
FB
SSispulledabove0.6V.Theexternalsoft-startduration
can be calculated by using the following formula:
⎛
⎞
⎟
⎠
SV
IN
tSS =R •C •ln
⎜
SS
SS
SV – 0.6V
⎝
IN
3. The TRACK/SS pin can be used to track the output
voltage of another supply.
Particularattentionshouldbeusedwithveryhighswitching
frequencies. Using the slowest slew rate (SRLIM open)
can reduce the minimum duty cycle capability.
Each time the RUN pin is tied high and the LTC3616 is
turned on, the TRACK/SS pin is internally pulled down
10k
100k
OPEN
OPEN
100k
10k
3616 F05
2ns/DIV
2ns/DIV
V
V
SW
= 3.3V
= 1.8V
= 2.25MHz
V
V
= 3.3V
= 1.8V
= 2.25MHz
IN
OUT
IN
OUT
f
f
SW
Figure 5. Slew Rate at SW Pin vs SRLIM/DDR Resistor: Open, ±00k, ±0k
3616fc
19
For more information www.linear.com/LTC3616
LTC3616
applicaTions inForMaTion
Output Voltage Tracking Input
V
V
OUT1
OUT2
If the DDR pin is not tied to SV , once V
exceeds
IN
TRACK/SS
0.6V, the run state is entered and the MODE selection,
power good and current foldback circuits are enabled.
In the run state, the TRACK/SS pin can be used for track-
ing down/up the output voltage of another supply. If the
V
drops below 0.6V, the LTC3616 enters the
TRACK/SS
down tracking state and V
is referenced to the TRACK/
OUT
TIME
SS voltage. If the TRACK/SS pin drops below 0.2V, the
switching frequency is reduced to ensure that the mini-
mum duty cycle limit does not prevent the output from
following the TRACK/SS pin. The run state will resume if
(6a) Coincident Tracking
V
V
OUT1
OUT2
V
again exceeds 0.6V and V
is referenced to
TRACK/SS
OUT
the internal precision reference (see Figure 8).
Through the TRACK/SS pin, the output voltage can be set
up for either coincident or ratiometric tracking, as shown
in Figure 6.
3616 F06
TIME
To implement the coincident tracking behavior in Fig-
ure 6a, connect an extra resistive divider to the output
of the master channel and connect its midpoint to the
TRACK/SS pin for the slave channel. The ratio of this
divider should be selected to be the same as that of the
slavechannel’sfeedbackdivider(Figure 7a).Inthistrack-
ing mode, the master channel’s output must be set higher
than slave channel’s output. To implement the ratiometric
tracking behavior in Figure 6b, different resistor divider
values must be used as specified in Figure 7b.
(6b) Ratiometric Tracking
Figure 6. Two Different Modes of Output Voltage Tracking
V
OUT1
V
OUT2
R4
R4
R3
V
IN
V
V
FB1
FB2
R2
R2
R2
LTC3616
TRACK/SS2
LTC3616
TRACK/SS1
Forcoincidentstart-up, thevoltagevalueattheTRACK/SS
pin for the slave channel needs to reach the final reference
value after the internal soft-start time (around 1ms). The
master start-up time needs to be adjusted with an external
capacitor and resistor to ensure this.
R4 ≤ R3
3616 F07a
LTC3616 CHANNEL 2
SLAVE
LTC3616 CHANNEL 1
MASTER
Figure 7a. Setup for Coincident Tracking
V
OUT1
V
OUT2
External Reference Input (DDR Mode)
R1
R2
R5
R3 R1/R2 < R5/R6
If the DDR pin is tied to SV (DDR mode), the run state is
IN
V
V
FB1
FB2
entered when V
exceeds 0.3V and tracking down
TRACK/SS
R6
R4
LTC3616
TRACK/SS2
LTC3616
TRACK/SS1
behaviorispossibleiftheV
voltageisbelow0.6V.
TRACK/SS
V
IN
This allows TRACK/SS to be used as an external reference
between 0.3V and 0.6V if desired. During the run state in
DDR mode, the power good window moves in relation
LTC3616 CHANNEL 2
SLAVE
LTC3616 CHANNEL 1
MASTER
3616 F07b
Figure 7b. Setup for Ratiometric Tracking
3616fc
20
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LTC3616
applicaTions inForMaTion
Efficiency Considerations
to the actual TRACK/SS pin voltage if the voltage value
is between 0.3V and 0.6V. Note: if TRACK/SS voltage is
0.6V, either the tracking circuit or the internal reference
can be used.
Theefficiencyofaswitchingregulatorisequaltotheoutput
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
During up/down tracking the output current foldback is
disabled and the PGOOD pin is always pulled down (see
Figure 9).
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
0.6V
PIN
V
FB
VOLTAGE
0V
0.6V
TRACK/SS
PIN VOLTAGE
0.2V
0V
V
IN
RUN PIN
VOLTAGE
0V
V
IN
SV PIN
IN
VOLTAGE
0V
TIME
SHUTDOWN SOFT-START
RUN STATE
REDUCED
SWITCHING
FREQUENCY
RUN STATE
STATE
STATE
> 1ms
3616 F08
t
SS
DOWN
TRACKING TRACKING
STATE STATE
UP
Figure 8. DDR Pin Not Tied to SVIN
0.45V
0.3V
V
PIN
FB
VOLTAGE
0V
EXTERNAL
VOLTAGE
REFERENCE 0.45V
0.45V
0.3V
TRACK/SS
PIN VOLTAGE
0.2V
0V
V
IN
RUN PIN
VOLTAGE
0V
V
IN
SV PIN
IN
VOLTAGE
0V
TIME
SHUTDOWN SOFT-START
STATE STATE
> 1ms
RUN STATE
REDUCED
SWITCHING
FREQUENCY
RUN STATE
3616 F09
t
SS
DOWN
TRACKING
STATE
UP
TRACKING
STATE
Figure 9. DDR Pin Tied to SVIN. Example DDR Application
3616fc
21
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LTC3616
applicaTions inForMaTion
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
However, in applications where the LTC3616 is running
at high ambient temperature with low supply voltage and
high duty cycles, such as in dropout, the heat dissipated
mayexceedthemaximumjunctiontemperatureofthepart.
If the junction temperature reaches approximately 170°C,
both power switches will be turned off and the SW node
will become high impedance.
2
the losses: V quiescent current and I R losses. The V
IN
IN
quiescent current loss dominates the efficiency loss at
2
very low load currents whereas the I R loss dominates
the efficiency loss at medium to high load currents. In a
typical efficiency plot, the efficiency curve at very low load
currents can be misleading since the actual power lost is
usually of no consequence.
To prevent the LTC3616 from exceeding the maximum
junction temperature, some thermal analysis is required.
The temperature rise is given by:
1. TheV quiescentcurrentisduetotwocomponents:the
IN
DCbiascurrentasgivenintheElectricalCharacteristics
and the internal main switch and synchronous switch
gate charge currents. The gate charge current results
fromswitchingthegatecapacitanceoftheinternalpower
MOSFET switches. Each time the gate is switched from
low to high to low again, a packet of charge dQ moves
T
= (P )(θ )
D JA
RISE
where P is the power dissipated by the regulator and
D
θ
is the thermal resistance from the junction of the die
JA
to the ambient temperature. The junction temperature,
T , is given by:
J
from V to ground. The resulting dQ/dt is the current
IN
T = T + T
RISE
J
A
out of V due to gate charge, and it is typically larger
IN
where T is the ambient temperature.
A
than the DC bias current. Both the DC bias and gate
chargelossesareproportionaltoV ;thus, theireffects
IN
As an example, consider the case when the LTC3616 is in
dropout at an input voltage of 3.3V with a load current of
6A at an ambient temperature of 70°C. From the Typical
Performance Characteristics graph of Switch Resistance,
will be more pronounced at higher supply voltages.
2
2. I R losses are calculated from the resistances of the
internal switches, R , and external inductor, R . In
SW
L
the R
resistance of the P-channel switch is 0.035Ω.
DS(ON)
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
Therefore, power dissipated by the part is:
2
P = (I ) • R
= 1.26W
D
OUT
DS(ON)
For the QFN package, the θ is 38°C/W.
JA
top and bottom MOSFET R
(DC) as follows:
and the duty cycle
DS(ON)
Therefore, the junction temperature of the regulator op-
erating at 70°C ambient temperature is approximately:
R
= (R )(DC) + (R )(1 – DC)
DS(ON)TOP DS(ON)BOT
SW
T = 1.26W • 38°C/W + 70°C = 118°C
J
The R
for both the top and bottom MOSFETs can
DS(ON)
be obtained from the Typical Performance Character-
We cansafelyassumethattheactualjunctiontemperature
will not exceed the absolute maximum junction tempera-
ture of 125°C.
2
istics curves. To obtain I R losses, simply add R to
SW
R and multiply the result by the square of the average
L
output current.
Note that for very low input voltage, the junction tempera-
ture will be higher due to increased switch resistance,
Other losses including C and C
ESR dissipative
OUT
IN
losses and inductor core losses generally account for
R
. It is not recommended to use full load current
DS(ON)
less than 2% of the total loss.
for high ambient temperature and low input voltage.
To maximize the thermal performance of the LTC3616 the
exposed pad should be soldered to a ground plane. See
the PCB Layout Board Checklist.
Thermal Considerations
In most applications, the LTC3616 does not dissipate
much heat due to its high efficiency.
3616fc
22
For more information www.linear.com/LTC3616
LTC3616
applicaTions inForMaTion
Design Example
Finally, define the soft start-up time choosing the proper
value for the capacitor and the resistor connected to
As a design example, consider using the LTC3616 in an
application with the following specifications:
TRACK/SS. If we set minimum t = 5ms and a resistor
SS
of 2MΩ, the following equation can be solved with the
V = 2.25V to 5.5V, V
= 1.8V, I
= 6A, I
OUT(MAX) OUT(MIN)
maximum SV = 5.5V :
IN
OUT
IN
= 200mA, f = 2.6MHz.
5ms
CSS =
= 21.6nF
Efficiency is important at both high and low load current,
so Burst Mode operation will be utilized.
⎛
⎜
⎝
⎞
⎟
⎠
5.5V
5.5V – 0.6V
2MΩ •In
First, calculate the timing resistor:
3.8211Hz
The standard value of 22nF guarantees the minimum soft-
start up time of 5ms.
RT =
k – 16k = 130kΩ
2.6MHz
Figure 1 shows the schematic for this design example.
Next, calculate the inductor value for about 30% ripple
PC Board Layout Checklist
current at maximum V :
IN
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3616:
⎛
⎜
⎝
⎞ ⎛
⎞
⎟
⎠
1.8V
2.6MHz • 2A
1.8V
5.5V
L =
• 1–
= 0.233µH
⎟ ⎜
⎠ ⎝
Using a standard value of 0.22µH inductor results in a
maximum ripple current of:
1. Agroundplaneisrecommended.Ifagroundplanelayer
is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the SGND pin at one point which is then connected
to the PGND pin close to the LTC3616.
⎛
⎞
⎟
⎛
⎞
⎟
⎠
1.8V
1.8V
5.5V
∆I =
• 1–
= 2.12A
⎜
⎜
L
⎝
2.6MHz• 0.22µH
⎝
⎠
2. Connect the (+) terminal of the input capacitor(s), C ,
C
will be selected based on the ESR that is required
IN
OUT
ascloseaspossibletothePV pin, andthe(–)terminal
to satisfy the output voltage ripple requirement and the
bulk capacitance needed for loop stability. For this design,
a 150µF (or 47µF plus 100µF) ceramic capacitor is used
with a X5R or X7R dielectric.
IN
as close as possible to the exposed pad, PGND. This
capacitorprovidestheACcurrentintotheinternalpower
MOSFETs.
3. Keep the switching node, SW, away from all sensitive
small-signal nodes.
Assumingworst-caseconditionsofV =2V ,C should
IN
OUT IN
be selected for a maximum current rating of:
4. Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
powercomponents. ConnectthecopperareastoPGND
(exposed pad) for best performance.
⎛
⎜
⎝
⎞
1.8V
3.6V
3.6V
1.8V
I
RMS = 6A •
•
– 1 = 3A
⎟
RMS
⎠
Decoupling PV with four 22µF capacitors is adequate
IN
for most applications.
5. Connect the V pin directly to the feedback resistors.
FB
The resistor divider must be connected between V
and SGND.
OUT
IfwesetR2=196k, thevalueofR1cannowbedetermined
by solving the following equation.
⎛
⎜
⎝
⎞
1.8V
0.6V
R1 = 196k •
−1
⎟
⎠
A value of 392k will be selected for R1.
3616fc
23
For more information www.linear.com/LTC3616
LTC3616
Typical applicaTions
General Purpose Buck Regulator Using Ceramic Capacitors, 2.25MHz
V
IN
2.25V TO 5.5V
22µF
×4
R
F
24Ω
C
F
1µF
SV
RUN
PV
IN
R
IN
SS
4.7M
SRLIM/DDR
TRACK/SS
RT/SYNC
C
SS
L1
10nF
0.22µH
LTC3616
V
1.8V
6A
R4
100k
OUT
SW
SGND
PGND
R
15k
C
C
C
O2
100µF
O1
PGOOD
PGOOD
ITH
MODE
47µF
C
C
C1
10pF
C
R5A
1M
R1
392k
V
FB
470pF
C3
22pF
R2
196k
R5B
1M
3616 TA02a
L1: VISHAY IHLP-2525CZ-01 220nH
Efficiency vs Output Current
Load Step Forced Continuous Mode
100
90
80
70
60
50
40
30
20
10
0
V
= 1.8V, V = 3.3V
IN
OUT
V
OUT
200mV/DIV
I
OUT
5A/DIV
V
V
V
V
= 2.5V
= 3.3V
= 4V
IN
IN
IN
IN
3616 TA02c
V
V
= 3.3V
50µs/DIV
IN
= 1.8V
OUT
OUT
= 5.5V
I
= 100mA TO 3A
= 1.5V
V
MODE
1
10
100
1000
10000
OUTPUT CURRENT (mA)
3616 TA02b
3616fc
24
For more information www.linear.com/LTC3616
LTC3616
Typical applicaTions
Master and Slave for Coincident Tracking Outputs Using a ±MHz External Clock
V
IN
2.25V TO 5.5V
22µF
×4
R
F1
4.7M
10nF
24Ω
C
F1
1µF
SV
PV
IN
IN
RUN
CHANNEL 1
MASTER
TRACK/SS SRLIM/DDR
RT/SYNC
1MHz
CLOCK
L1
0.47µH
LTC3616
SW
V
1.8V
6A
OUT1
R5
100k
R
C1
C
C
O12
100µF
O11
PGOOD
PGOOD
ITH
SGND
PGND
15k
47µF
C
C
C2
10pF
C1
R1
MODE
V
FB
4.7M
4.7M
R3
470pF
715k
464k
C3
22pF
R2
357k
R4
464k
R
22µF
×4
F2
24Ω
C
F2
1µF
SV
PV
IN
IN
RUN
TRACK/SS
RT/SYNC
CHANNEL 2
SLAVE
SRLIM/DDR
L2
0.47µH
LTC3616
V
1.2V
6A
OUT2
R7
100k
SW
SGND
PGND
R
C2
C
C
O22
100µF
O21
PGOOD
PGOOD
ITH
15k
47µF
C
C
C4
10pF
C3
R5
301k
MODE
V
FB
470pF
C7
22pF
R6
301k
L1, L2: VISHAY IHLP-2525CZ-01 470nH
3616 TA03a
Coincident Start-Up
Coincident Tracking Up/Down
V
V
OUT1
OUT2
V
OUT1
500mV/DIV
500mV/DIV
V
OUT2
3616 TA03b
3616 TA03c
2ms/DIV
200ms/DIV
3616fc
25
For more information www.linear.com/LTC3616
LTC3616
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UDD Package
24-Lead Plastic QFN (3mm × 5mm)
(Reference LTC DWG # 05-08-1833)
0.70 0.05
3.50 0.05
2.ꢀ0 0.05
ꢀ.50 REF
3.65 0.05
ꢀ.65 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
3.50 REF
4.ꢀ0 0.05
5.50 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN ꢀ NOTCH
R = 0.20 OR 0.25
× 45° CHAMFER
0.75 0.05
ꢀ.50 REF
23
R = 0.05 TYP
3.00 0.ꢀ0
24
0.40 0.ꢀ0
PIN ꢀ
TOP MARK
(NOTE 6)
ꢀ
2
3.65 0.ꢀ0
ꢀ.65 0.ꢀ0
5.00 0.ꢀ0
3.50 REF
(UDD24) QFN 0808 REV Ø
0.200 REF
0.00 – 0.05
0.25 0.05
0.50 BSC
R = 0.ꢀꢀ5
TYP
BOTTOM VIEW—EXPOSED PAD
NOTE:
ꢀ. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.ꢀ5mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3616fc
26
For more information www.linear.com/LTC3616
LTC3616
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
4/11
Added V specification in the Electrical Characteristics section.
4
RUN
B
11/13 Add H and MP grades and applicable temperature range references.
Modified Note 2.
Throughout
4
7, 8
15
15
3
Modified Typical Performance Characteristics graphs.
Modified Inductor Core Selection section.
Modified Input Capacitor Selection section.
C
4/14
Modified the top switch current limit specification.
3616fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC3616
Typical applicaTion
DDR Termination With Ratiometric Tracking of VDD, ±MHz
Ratiometric Start-Up
V
IN
3.3V
V
DD
C1
22µF
×4
SV
RUN
TRACK/SS
RT/SYNC
PV
IN
IN
V
V
TT
DD
500mV/DIV
SRLIM/DDR
1.8V
R6
562k
R3
R8
100k
L1
LTC3616
365k
0.33µH
V
TT
R7
187k
PGOOD
PGOOD
ITH
SW
0.9V
3A
C4
C5
47µF
R
C
6k
3616 TA04b
100µF
500µs/DIV
SGND
PGND
V
FB
C
C
C1
10pF
C
R1
200k
MODE
2.2nF
R4
1M
C3
22pF
R2
200k
R5
1M
L1: COILCRAFT DO3316T
3616 TA04a
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
95% Efficiency, V
LTC3418
5.5V, 8A (I ), 4MHz, Synchronous Step-Down DC/DC
= 2.25V, V
= 5.5V, V
= 0.8V,
= 0.6V,
OUT
IN(MIN)
IN(MAX)
OUT(MIN)
Converter
I = 380µA, I <1µA, 5mm × 7mm QFN-38 Package
Q SD
LTC3415
5.5V, 7A (I ), 1.5MHz, Synchronous Step-Down DC/DC
95% Efficiency, V
= 2.5V, V
= 5.5V, V
IN(MAX) OUT(MIN)
OUT
IN(MIN)
Converter
I = 450µA, I <1µA, 5mm × 7mm QFN-38 Package
Q SD
LTC3414/
LTC3416
5.5V, 4A (I ), 4MHz, Synchronous Step-Down DC/DC
95% Efficiency, V
= 2.25V, V
= 5.5V, V
= 0.8V,
=
OUT
IN(MIN)
IN(MAX)
OUT(MIN)
OUT(MIN)
Converter
I = I = 64µA, I <1µA, TSSOP20E Package
Q Q SD
LTC3413
LTC3412A
LTC3612
5.5V, 3A (I
Sink/Source), 2MHz, Monolithic Synchronous
90% Efficiency, V
= 2.25V, V
= 5.5V, V
IN(MAX)
OUT
IN(MIN)
Regulator for DDR/QDR Memory Termination
V
REF
/2, I = 280µA, I <1µA, TSSOP16E Package
Q
SD
5.5V, 2.5A (I ), 4MHz, Synchronous Step-Down DC/DC
95% Efficiency, V
I = 60µA, I <1µA, 4mm × 4mm QFN-16 TSSOP16E Package
Q SD
= 2.5V, V
= 5.5V, V
= 0.8V,
OUT(MIN)
OUT
IN(MIN)
IN(MAX)
Converter
5.5V, 3A (I ), 4MHz, Synchronous Step-Down DC/DC
95% Efficiency, V
I = 70µA, I <1µA, 3mm × 4mm QFN-20 TSSOP20E Package
Q SD
= 2.25V, V
= 5.5V, V
= 0.6V,
OUT
IN(MIN)
IN(MAX)
OUT(MIN)
Converter
3616fc
LT 0414 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
LINEAR TECHNOLOGY CORPORATION 2010
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3616
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