LTC3646 [Linear]
17V, 1A Synchronous Step-Down Regulator with 3.5μA Quiescent Current; 17V , 1A同步降压型稳压器,带有3.5μA静态电流型号: | LTC3646 |
厂家: | Linear |
描述: | 17V, 1A Synchronous Step-Down Regulator with 3.5μA Quiescent Current |
文件: | 总16页 (文件大小:240K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC3621/LTC3621-2
17V, 1A Synchronous
Step-Down Regulator with
3.5µA Quiescent Current
FeaTures
DescripTion
The LTC®3621/LTC3621-2 is a high efficiency 17V, 1A
synchronousmonolithicstep-downregulator.Theswitch-
ing frequency is fixed to 1MHz or 2.25MHz. The regulator
features ultralow quiescent current and high efficiencies
n
Wide V Range: 2.7V to 17V
IN
n
Wide V
Range: 0.6V to V
OUT
IN
n
n
n
n
n
n
n
95% Max Efficiency
Low I < 3.5µA, Zero-Current Shutdown
Q
Constant Frequency (1MHz/2.25MHz)
over a wide V
range.
OUT
Full Dropout Operation with Low I
1A Rated Output Current
Q
The step-down regulator operates from an input voltage
range of 2.7V to 17V and provides an adjustable output
1ꢀ Output Voltage Accuracy
range from 0.6V to V while delivering up to 1A of output
IN
Current Mode Operation for Excellent Line and Load
Transient Response
current. A user-selectable mode input is provided to allow
the user to trade off ripple noise for light load efficiency;
Burst Mode operation provides the highest efficiency at
light loads, while pulse-skipping mode provides the low-
est voltage ripple.
Pulse-Skipping, Forced Continuous, Burst Mode®
Operation
n
n
n
n
Internal Compensation and Soft-Start
Overtemperature Protection
Compact 6-Lead DFN (2mm × 3mm) Package or
8-Lead MSOPE Package with Power Good Output
and Independent SGND Pin
List of LTC3621 Options
PART NAME
LTC3621
FREQUENCY
1.00MHz
V
OUT
Adjustable
Adjustable
LTC3621-2
2.25MHz
applicaTions
L, LT, LTC, LTM, Burst Mode, Linear Technology and the Linear logo are registered trademarks
and Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents, including 5481178, 6580258,
6498466, 6611131, 6177787, 5705919, 5847554.
n
Portable-Handheld Scanners
Automotive Applications
n
n
Emergency Radio
Typical applicaTion
Efficiency and Power Loss vs Load
2.5V VOUT with 400mA Burst Clamp, fSW = 1MHz
100
90
80
70
60
50
40
30
20
10
0
1.0
4.7µH
V
2.5V
1A
EFFICIENCY
OUT
V
IN
V
SW
IN
2.7V TO 17V
0.1
10µF
604k
191k
22pF
LTC3621
RUN
FB
22µF
MODE
3621 TA01a
0.01
0.001
0.0001
INTV
CC
GND
1µF
POWER LOSS
0.01
V
= 12V
IN
0.0001
0.001
0.1
1
LOAD CURRENT (A)
3621 TA01b
3621f
1
For more information www.linear.com/LTC3621
LTC3621/LTC3621-2
absoluTe MaxiMuM raTings (Note 1)
V Voltage (Note 2)................................... 17V to –0.3V
INTV , PGOOD Voltages ............................ 6V to –0.3V
IN
CC
SW Voltage DC................................. V + 0.3V to –0.3V
Operating Junction Temperature Range
IN
Transient (Note 2)...................................19V to –2.0V
RUN Voltage................................................ V to –0.3V
(Note 3).................................................. –40°C to 125°C
Storage Temperature Range .................. –65°C to 125°C
IN
MODE, FB Voltages...................................... 6V to –0.3V
pin conFiguraTion
TOP VIEW
TOP VIEW
6
5
4
MODE
INTV
SW
1
2
3
SW
1
2
3
4
8 SGND
7 MODE
6 INTV
7
GND
V
IN
9
GND
V
IN
CC
RUN
CC
5 FB
PGOOD
RUN
FB
MS8E PACKAGE
8-LEAD PLASTIC MSOP
= 125°C, θ = 40°C/W, θ = 10°C/W
JA JC
EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
DCB PACKAGE
T
JMAX
6-LEAD (2mm × 3mm) PLASTIC DFN
T
= 125°C, θ = 64°C/W, θ = 9.6°C/W
JA JC
EXPOSED PAD (PIN 7) IS GND, MUST BE SOLDERED TO PCB
JMAX
orDer inForMaTion
LEAD FREE FINISH
LTC3621EDCB#PBF
LTC3621IDCB#PBF
TAPE AND REEL
PART MARKING*
LGDG
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3621EDCB#TRPBF
LTC3621IDCB#TRPBF
LTC3621EMS8E#TRPBF
LTC3621IMS8E#TRPBF
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
8-Lead Plastic MSOP
LGDG
LTC3621EMS8E#PBF
LTC3621IMS8E#PBF
LTC3621EDCB-2#PBF
LTC3621IDCB-2#PBF
LTC3621EMS8E-2#PBF
LTC3621IMS8E-2#PBF
LTGDH
LTGDH
8-Lead Plastic MSOP
LTC3621EDCB-2#TRPBF LGHY
LTC3621IDCB-2#TRPBF LGHY
6-Lead (2mm × 3mm) Plastic DFN
6-Lead (2mm × 3mm) Plastic DFN
8-Lead Plastic MSOP
LTC3621EMS8E-2#TRPBF LTGHZ
LTC3621IMS8E-2#TRPBF LTGHZ
8-Lead Plastic MSOP
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TJ = 25°C. VIN = 12V, unless otherwise noted. (Notes 3, 6)
SYMBOL
PARAMETER
CONDITIONS
MIN
2.7
TYP
MAX
UNITS
V
V
Operating Voltage
Operating Voltage
Input Quiescent Current
17
V
V
IN
0.6
V
IN
OUT
VIN
I
Shutdown Mode, V
= 0V
0
3.5
1.5
0.1
4.5
µA
µA
mA
RUN
Burst Mode Operation
Forced Continuous Mode
(Note 4), V < 0.6V
FB
3621f
2
For more information www.linear.com/LTC3621
LTC3621/LTC3621-2
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TJ = 25°C. VIN = 12V, unless otherwise noted. (Notes 3, 6)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Regulated Feedback Voltage
0.594
0.591
0.6
0.6
0.606
0.609
V
V
FB
l
I
FB Input Current
10
nA
ꢀ/V
ꢀ
FB
ΔV
ΔV
Reference Voltage Line Regulation
Output Voltage Load Regulation
V
= 2.7V to 17V (Note 5)
0.01
0.1
0.015
LINE(REG)
LOAD(REG)
IN
(Note 5)
I
NMOS Switch Leakage
PMOS Switch Leakage
0.1
0.1
1
1
µA
µA
LSW
R
NMOS On-Resistance
PMOS On-Resistance
V
IN
= 5V
0.15
0.37
Ω
Ω
DS(ON)
l
D
Maximum Duty Cycle
Minimum On-Time
V
V
= 0.5V, V
= 0.7V, V
= 1.5V
= 1.5V
100
60
ꢀ
MAX
FB
MODE
MODE
t
ns
ON(MIN)
FB
V
RUN
RUN Input High Threshold
RUN Input Low Threshold
1.0
V
V
0.3
I
RUN Input Current
V
RUN
= 12V
0
20
nA
RUN
V
Pulse-Skipping Mode
Burst Mode Operation
Forced Continuous Mode
0.3
V
V
V
MODE
V
– 0.4
INTVCC
1.0
V
– 1.0
INTVCC
I
t
I
MODE Input Current
Internal Soft-Start Time
Peak Current Limit
V
= 3.6V
0
10
nA
MODE
MODE
0.5
ms
SS
1.44
1.30
1.60
1.76
1.80
A
A
LIM
l
l
V
V
V
V
V
V
V
V
Undervoltage Lockout
V
IN
Ramping Up
2.4
2.6
250
19
2.7
V
mV
V
UVLO
INTVCC
INTVCC
Undervoltage Lockout Hysteresis
UVLO(HYS)
OVLO
Overvoltage Lockout Rising
18
20
IN
IN
Overvoltage Lockout Hysteresis
300
mV
OVLO(HYS)
OSC
f
Oscillator Frequency
2.25MHz Parts
1MHz Parts
2.25MHz Parts
1MHz Parts
2.05
0.92
1.8
2.45
1.08
2.6
MHz
MHz
MHz
MHz
l
l
2.25
1.00
0.82
1.16
V
V
LDO Output Voltage
V > 4V
IN
3.3
3.6
7.5
3.9
11
V
ꢀ
Ω
INTVCC
INTVCC
ΔV
Power Good Range
Power Good Resistance
PGOOD Delay
PGOOD
R
PGOOD R
at 500µA
275
350
PGOOD
DS(ON)
t
PGOOD Low to High
PGOOD High to Low
0
32
Cycles
Cycles
PGOOD
I
PGOOD Leakage Current
100
nA
PGOOD
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
temperature range. Note that the maximum ambient temperature
consistent with these specifications is determined by specific operating
conditions in conjunction with board layout, the rated package thermal
impedance and other environmental factors.
Note 2: Transient absolute maximum voltages should not be applied for
more than 4ꢀ of the switching duty cycle.
Note 4: The quiescent current in forced continuous mode does not include
switching loss of the power FETs.
Note 3: The LTC3621 is tested under pulsed load conditions such that
Note 5: The LTC3621 is tested in a proprietary test mode that connects V
to the output of error amplifier.
FB
T ≈ T . The LTC3621E is guaranteed to meet specifications from
J
A
0°C to 85°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3621I is guaranteed over the –40°C to 125°C operating junction
Note 6: T is calculated from the ambient, T , and power dissipation, P ,
according to the following formula:
J
A
D
T = T + (P • θ )
JA
J
A
D
3621f
3
For more information www.linear.com/LTC3621
LTC3621/LTC3621-2
Typical perForMance characTerisTics TJ = 25°C, unless otherwise noted.
Efficiency vs Load Current
(Burst Mode Operation)
VIN Supply Current
vs Input Voltage
Efficiency vs Load at Dropout
Operation
100
90
80
70
60
50
40
30
20
10
0
5
4
3
100
90
80
70
60
50
40
30
20
10
0
Burst Mode
OPERATION
SLEEP
FORCED
CONTINUOUS
MODE
2
1
0
V
V
V
= 2.5V
= 3.3V
= 5V
OUT
OUT
OUT
V
= 5V
V
= 12V
IN
IN
SD
FREQUENCY = 2.25MHz
0.01 0.1
LOAD CURRENT (A)
FREQUENCY = 2.25MHz
0.001 0.01
LOAD CURRENT (A)
0.1
1
0
2
4
6
8
10 12 14 16 18 20
0.0001
0.001
1
INPUT VOLTAGE (V)
3621 G01
3621 G03
3621 G02
Burst Mode Operation
Pulse-Skipping Mode Operation
Load Step
SW
5V/DIV
SW
5V/DIV
V
OUT
100mV/DIV
V
V
OUT
AC-COUPLED
50mV/DIV
OUT
I
L
AC-COUPLED
50mV/DIV
500mA/DIV
I
I
I
LOAD
L
L
500mA/DIV
500mA/DIV
500mA/DIV
3621 G04
3621 G05
3621 G06
4µs/DIV
4µs/DIV
40µs/DIV
V
V
= 12V
V
V
= 12V
V
V
LOAD
= 12V
IN
IN
OUT
IN
OUT
= 3.3V
= 3.3V
= 3.3V
OUT
Burst Mode OPERATION
= 50mA
PULSE SKIP MODE
= 10mA
I
= 0.05A
I
I
OUT
OUT
L = 2.2µH
L = 2.2µH
Oscillator Frequency
vs Temperature
Soft-Start Operation
Efficiency vs Input Voltage
96
94
92
90
88
86
84
82
80
78
76
74
72
70
2.50
2.45
2.40
2.35
2.30
2.25
2.20
2.15
2.10
2.05
2.00
V
OUT
= 2.5V
RUN
5V/DIV
I
= 1A
I
LOAD
L
0.5A/DIV
V
OUT
1V/DIV
I
= 10mA
LOAD
PGOOD
2V/DIV
3621 G07
400µs/DIV
50
TEMPERATURE (°C)
100 125
3621 G09
–50 –25
0
25
75
0
20
5
10
INPUT VOLTAGE (V)
15
3621 G08
3621f
4
For more information www.linear.com/LTC3621
LTC3621/LTC3621-2
Typical perForMance characTerisTics TJ = 25°C, unless otherwise noted.
Oscillator Frequency
vs Supply Voltage
Reference Voltage
vs Temperature
Efficiency vs Load at 1MHz
100
90
80
70
60
50
40
30
20
10
0
2.50
2.45
2.40
2.35
2.30
2.25
2.20
2.15
2.10
2.05
2.00
600.5
600.0
599.5
599.0
598.5
598.0
597.5
V
V
V
= 2.5V
= 3.3V
= 5V
OUT
OUT
OUT
V
= 12V
IN
50
TEMPERATURE (°C)
100
150
12
SUPPLY VOLTAGE (V)
–100
–50
0
0.0001
0.001
0.01
0.1
1
2
7
17
LOAD CURRENT (A)
3621 G16
3521 G11
3621 G10
RDS(ON) vs Input Voltage
RDS(ON) vs Temperature
Load Regulation
700
600
600
550
500
450
400
350
300
250
200
150
100
5
4
V
V
= 12V
IN
OUT
= 3.3V
FORCED CONTINUOUS MODE
3
TOP FET
2
500
400
1
TOP FET
0
–1
–2
–3
–4
–5
300
200
100
BOTTOM FET
BOTTOM FET
0
2
4
6
8
10 12 14 16 18 20
–50
0
25
50
75 100 125
0
1500
–25
500
1000
INPUT VOLTAGE (V)
TEMPERATURE (°C)
LOAD CURRENT (mA)
3621 G14
3621 G12
3621 G13
VIN Supply Current
vs Temperature
Switch Leakage
vs Temperature
Line Regulation
0.5
0.3
6
5
4
3
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
SLEEP
BOTTOM FET
0.1
–0.1
–0.3
–0.5
2
1
0
SHUTDOWN
50
TEMPERATURE (°C)
TOP FET
0
100 125
0
1314151617
–50 –25
0
25
75
1 2 3 4 5 6 7 8 9 101112
INPUT VOLTAGE (V)
–50 –25
0
25
125
50
75 100
TEMPERATURE (°C)
3621 G15
3521 G17
3621 G18
3621f
5
For more information www.linear.com/LTC3621
LTC3621/LTC3621-2
pin FuncTions (DFN/MSOP)
SW(Pin1/Pin1):SwitchNodeConnectiontotheInductor
of the Step-Down Regulator.
PGOOD (Pin 4, MSOP Package Only): V
lation Indicator.
within Regu-
OUT
V (Pin2/Pin2):InputVoltageoftheStep-DownRegulator.
INTV (Pin5/Pin6):LowDropoutRegulator.Bypasswith
IN
CC
at least 1µF to Ground.
RUN (Pin 3/Pin 3): Logic Controlled RUN Input. Do not
leave this pin floating. Logic high activates the step-down
regulator.
MODE (Pin 6/Pin 7): Burst Mode Select of the Step-Down
Regulator. Tie MODE to INTV for Burst Mode operation
CC
with a 400mA peak current clamp, tie MODE to GND for
FB (Pin 4/Pin 5): Feedback Input to the Error Amplifier
of the Step-Down Regulator. Connect a resistor divider
tap to this pin. The output voltage can be adjusted from
pulse skipping operation, and tie MODE to a voltage be-
tween 1V and V
– 1V for forced continuous mode.
INTVCC
0.6V to V by:
GND (Exposed Pad Pin 7/Pin 9): Ground Backplane for
PowerandSignalGround.MustbesolderedtoPCBground.
IN
V
OUT
= 0.6V • [1 + (R1/R2)]
SGND (Pin 8, MSOP Package Only): Signal Ground.
block DiagraM
V
IN
0.8ms
SOFT-START
SLOPE
COMPENSATION
ERROR
AMPLIFIER
BURST
AMPLIFIER
MAIN
I-COMPARATOR
+
+
–
+
–
+
–
0.6V
FB
V
CLK
MODE
INTV
OSCILLATOR
OVERCURRENT
COMPARATOR
V
– 5V
IN
SW
CC
BUCK
LOGIC
+
–
LDO
AND
GATE DRIVE
RUN
INTV
CC
PGOOD
+
–
REVERSE
COMPARATOR
GND
MS8E PACKAGE ONLY
3621 BD
3621f
6
For more information www.linear.com/LTC3621
LTC3621/LTC3621-2
operaTion
The LTC3621 uses a constant-frequency, peak current
mode architecture. It operates through a wide V range
and regulates with ultralow quiescent current. The opera-
tion frequency is set at either 2.25MHz or 1MHz. To suit
a variety of applications, the selectable MODE pin allows
the user to trade off output ripple for efficiency.
400mA, even if the output of the error amplifier demands
less.Thus,whentheswitcherisonatrelativelylightoutput
loads, FB voltage will rise and cause the ITH voltage to
drop. Once the ITH voltage goes below 0.2V, the switcher
goes into its sleep mode with both power switches off.
The switcher remains in this sleep state until the external
load pulls the output voltage below its regulation point.
During sleep mode, the part draws an ultralow 3.5µA of
IN
The output voltage is set by an external divider returned to
the FB pin. An error amplifier compares the divided output
voltage with a reference voltage of 0.6V and adjusts the
peak inductor current accordingly. In the MS8E package,
overvoltage and undervoltage comparators will pull the
PGOOD output low if the output voltage is not within 7.5ꢀ
of the programmed value. The PGOOD output will go high
immediately after achieving regulation and will go low 32
clock cycles after falling out of regulation.
quiescent current from V .
IN
To minimize V
ripple, pulse-skipping mode can be
OUT
selected by grounding the MODE pin. In the LTC3621,
pulse-skipping mode is implemented similarly to Burst
Mode operation with the peak inductor current set to be
at about 66mA. This results in lower output voltage ripple
than in Burst Mode operation with the trade-off being
slightly lower efficiency.
Main Control Loop
Forced Continuous Mode Operation
Duringnormaloperation,thetoppowerswitch(P-channel
MOSFET) is turned on at the beginning of a clock cycle.
The inductor current is allowed to ramp up to a peak level.
Once that level is reached, the top power switch is turned
off and the bottom switch (N-channel MOSFET) is turned
on until the next clock cycle. The peak current level is con-
trolledbytheinternallycompensatedITHvoltage,whichis
the output of the error amplifier. This amplifier compares
the FB voltage to the 0.6V internal reference. When the
load current increases, the FB voltage decreases slightly
below the reference, which causes the error amplifier to
increase the ITH voltage until the average inductor current
matches the new load current.
Aside from the two discontinuous-conduction modes,
the LTC3621 also has the ability to operate in the forced
continuous mode by setting the MODE voltage between
1V and V
– 1V. In forced continuous mode, the
INTVCC
switcher will switch cycle by cycle regardless of what
the output load current is. If forced continuous mode is
selected, the minimum peak current is set to be –133mA
in order to ensure that the part can operate continuously
at zero output load.
High Duty Cycle/Dropout Operation
Whentheinputsupplyvoltagedecreasestowardstheoutput
voltage, the duty cycle increases and slope compensation
is required to maintain the fixed switching frequency. The
LTC3621 has internal circuitry to accurately maintain the
The main control loop is shut down by pulling the RUN
pin to ground.
Low Current Operation
peak current limit (I ) of 1.6A even at high duty cycles.
LIM
Twodiscontinuous-conductionmodes(DCMs)areavailable
to control the operation of the LTC3621 at low currents.
Both modes, Burst Mode operation and pulse-skipping,
automatically switch from continuous operation to the
selected mode when the load current is low.
As the duty cycle approaches 100ꢀ, the LTC3621 enters
dropout operation. During dropout, if force continuous
mode is selected, the top PMOS switch is turned on
continuously, and all active circuitry is kept alive. How-
ever, if Burst Mode operation or pulse-skipping mode is
selected, the part will transition in and out of sleep mode
depending on the output load current. This significantly
reduces the quiescent current, thus prolonging the use
of the input supply.
To optimize efficiency, Burst Mode operation can be se-
lected by tying the MODE pin to INTV . In Burst Mode
CC
operation, the peak inductor current is set to be at least
3621f
7
For more information www.linear.com/LTC3621
LTC3621/LTC3621-2
operaTion
V Overvoltage Protection
IN
below 2.7V. As the input voltage rises slightly above the
undervoltage threshold, the switcher will begin its basic
In order to protect the internal power MOSFET devices
against transient voltage spikes, the LTC3621 constantly
operation. However, the R
of the top and bottom
DS(ON)
switch will be slightly higher than that specified in the
monitors the V pin for an overvoltage condition. When
IN
electrical characteristics due to lack of gate drive. Refer
V rises above 19V, the regulator suspends operation by
IN
to graph of R
versus V for more details.
IN
DS(ON)
shutting off both power MOSFETs. Once V drops below
IN
18.7V, the regulator immediately resumes normal opera-
tion. The regulator executes its soft-start function when
exiting an overvoltage condition.
Soft-Start
TheLTC3621hasaninternal800µssoft-startramp.During
start-up soft-start operation, the switcher will operate in
pulse-skipping mode.
Low Supply Operation
TheLTC3621incorporatesanundervoltagelockoutcircuit
which shuts down the part when the input voltage drops
applicaTions inForMaTion
Output Voltage Programming
VOUT
V
IN
VOUT
IRMS ≅IOUT(MAX)
–1
For non-fixed output voltage parts, the output voltage is
set by external resistive divider according to the following
equation:
V
IN
This formula has a maximum at V = 2V , where:
IN
OUT
IOUT
2
R2
R1
IRMS
≅
VOUT =0.6V • 1+
This simple worst-case condition is commonly used for
design because even significant deviations do not offer
muchrelief.Notethatripplecurrentratingsfromcapacitor
manufacturers are often based on only 2000 hours of life
which makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required.Severalcapacitorsmayalsobeparalleledtomeet
size or height requirements in the design. For low input
voltage applications, sufficient bulk input capacitance is
needed to minimize transient effects during output load
changes.
The resistive divider allows the FB pin to sense a fraction
of the output voltage as shown in Figure 1.
V
OUT
R2
C
FF
FB
R1
LTC3621
SGND
3621 F01
Figure 1. Setting the Output Voltage
Input Capacitor (C ) Selection
IN
Output Capacitor (C ) Selection
OUT
The input capacitance, C , is needed to filter the square
IN
The selection of C
is determined by the effective series
OUT
wave current at the drain of the top power MOSFET. To
prevent large voltage transients from occurring, a low
ESR input capacitor sized for the maximum RMS current
should be used. The maximum RMS current is given by:
resistance(ESR)thatisrequiredtominimizevoltageripple
and load step transients as well as the amount of bulk
capacitance that is necessary to ensure that the control
3621f
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For more information www.linear.com/LTC3621
LTC3621/LTC3621-2
applicaTions inForMaTion
loop is stable. Loop stability can be checked by viewing
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement.Duringaloadstep,theoutputcapacitormust
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. Typically, five cycles are required to
respond to a load step, but only in the first cycle does the
the load transient response. The output ripple, ∆V , is
OUT
determined by:
1
V
< I
∆
+ESR
∆
L
OUT
8•f•COUT
The output ripple is highest at maximum input voltage
output voltage drop linearly. The output droop, V
, is
DROOP
since ∆I increases with input voltage. Multiple capaci-
L
usually about three times the linear drop of the first cycle.
Thus, a good place to start with the output capacitor value
is approximately:
tors placed in parallel may be needed to meet the ESR
and RMS current handling requirements. Dry tantalum,
special polymer, aluminum electrolytic, and ceramic
capacitors are all available in surface mount packages.
Special polymer capacitors are very low ESR but have
lower capacitance density than other types. Tantalum
capacitors have the highest capacitance density but it is
important to only use types that have been surge tested
foruseinswitchingpowersupplies.Aluminumelectrolytic
capacitors have significantly higher ESR, but can be used
in cost-sensitive applications provided that consideration
is given to ripple current ratings and long-term reliability.
CeramiccapacitorshaveexcellentlowESRcharacteristics
and small footprints.
∆IOUT
COUT =3
f•VDROOP
More capacitance may be required depending on the duty
cycle and load-step requirements. In most applications,
the input capacitor is merely required to supply high
frequency bypassing, since the impedance to the supply
is very low. A 10μF ceramic capacitor is usually enough
for these conditions. Place this input capacitor as close
to the IN pin as possible.
Output Power Good
Using Ceramic Input and Output Capacitors
In the MS8E package, when the LTC3621’s output voltage
is within the 7.5ꢀ window of the regulation point, the
output voltage is good and the PGOOD pin is pulled high
withanexternalresistor.Otherwise,aninternalopen-drain
pull-down device (275Ω) will pull the PGOOD pin low.
To prevent unwanted PGOOD glitches during transients
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
or dynamic V
changes, the LTC3621’s PGOOD fall-
OUT
ing edge includes a blanking delay of approximately 32
switching cycles.
V input. Atbest, thisringingcancoupletotheoutputand
IN
Inductor Selection
be mistaken as loop instability. At worst, a sudden inrush
Given the desired input and output voltages, the inductor
valueandoperatingfrequencydeterminetheripplecurrent:
of current through the long wires can potentially cause
a voltage spike at V large enough to damage the part.
IN
When choosing the input and output ceramic capacitors,
choose the X5R and X7R dielectric formulations. These
dielectrics have the best temperature and voltage char-
acteristics of all the ceramics for a given value and size.
VOUT
f•L
VOUT
V
IN(MAX)
∆IL =
1–
3621f
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LTC3621/LTC3621-2
applicaTions inForMaTion
Lower ripple current reduces power losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a trade-off between
component size, efficiency and operating frequency.
Checking Transient Response
Theregularloopresponsecanbecheckedbylookingatthe
loadtransientresponse. Switchingregulatorstakeseveral
cyclestorespondtoastepinloadcurrent.Whenaloadstep
occurs, V
immediatelyshiftsbyanamountequaltothe
OUT
∆I
• ESR, where ESR is the effective series resistance
LOAD
A reasonable starting point is to choose a ripple current
of C . ∆I
also begins to charge or discharge C
OUT
LOAD
OUT
that is about 40ꢀ of I
. To guarantee that ripple
OUT(MAX)
generatingafeedbackerrorsignalusedbytheregulatorto
current does not exceed a specified maximum, the induc-
tance should be chosen according to:
return V to its steady-state value. During this recovery
OUT
OUT
time, V
can be monitored for overshoot or ringing that
would indicate a stability problem.
VOUT
f•∆IL(MAX)
VOUT
V
IN(MAX)
L=
1–
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phase margin. In addition, a feedforward capacitor can
be added to improve the high frequency response, as
Once the value for L is known, the type of inductor must
be selected. Actual core loss is independent of core size
for a fixed inductor value, but is very dependent on the
inductance selected. As the inductance or frequency in-
creases, core losses decrease. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses will increase. Copper losses also increase
as frequency increases.
shown in Figure 1. Capacitor C provides phase lead by
FF
creating a high frequency zero with R2, which improves
the phase margin.
Theoutputvoltagesettlingbehaviorisrelatedtothestability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to application Note 76.
Ferrite designs have very low core losses and are pre-
ferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard”, which means that
inductancecollapsesabruptlywhenthepeakdesigncurrent
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Insomeapplications,amoreseveretransientcanbecaused
by switching in loads with large (>1µF) input capacitors.
The discharge input capacitors are effectively put in paral-
lel with C , causing a rapid drop in V . No regulator
OUT
OUT
can deliver enough current to prevent this problem if the
switchconnectingtheloadhaslowresistanceandisdriven
quickly. The solution is to limit the turn-on speed of the
load switch driver. A Hot Swap™ controller is designed
specifically for this purpose and usually incorporates
currentlimiting, short-circuitprotectionandsoft-starting.
Different core materials and shapes will change the size/
currentandprice/currentrelationshipofaninductor.Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price versus size requirements
and any radiated field/EMI requirements. New designs for
surface mount inductors are available from Toko, Vishay,
NEC/Tokin, Cooper, TDK and Würth Electronik. Refer to
Table 1 for more details.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100ꢀ.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
3621f
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LTC3621/LTC3621-2
applicaTions inForMaTion
Table 1. Inductor Selection Table
INDUCTANCE
(µH)
DCR
(mΩ)
MAX CURRENT
(A)
DIMENSIONS
(mm)
HEIGHT
(mm)
INDUCTOR
MANUFACTURER
IHLP-1616BZ-11 Series
1.0
2.2
4.7
24
61
95
4.5
3.25
1.7
4.3 × 4.7
4.3 × 4.7
4.3 × 4.7
2
2
2
Vishay
www.vishay.com
IHLP-2020BZ-01 Series
FDV0620 Series
1
18.9
45.6
79.2
108
113
139
18
37
51
68
7
5.4 × 5.7
5.4 × 5.7
5.4 × 5.7
5.4 × 5.7
5.4 × 5.7
5.4 × 5.7
6.7 × 7.4
6.7 × 7.4
6.7 × 7.4
6.7 × 7.4
2
2
2
2
2
2
2
2
2
2
2.2
3.3
4.7
5.6
6.8
4.2
3.3
2.8
2.5
2.4
1
5.7
4
3.2
2.8
Toko
www.toko.com
2.2
3.3
4.7
MPLC0525L Series
HCP0703 Series
1
16
24
40
6.4
5.2
4.1
11
9
8
6
5.5
4.5
4
6.2 × 5.4
6.2 × 5.4
6.2 × 5.4
7 × 7.3
7 × 7.3
7 × 7.3
7 × 7.3
7 × 7.3
7 × 7.3
7 × 7.3
2.5
2.5
2.5
3
3
3
3
3
3
3
NEC/Tokin
1.5
2.2
www.nec-tokin.com
1
9
Cooper Bussmann
www.cooperbussmann.com
1.5
2.2
3.3
4.7
6.8
8.2
14
18
28
37
54
64
RLF7030 Series
1
8.8
9.6
12
20
31
45
6.4
6.1
5.4
4.1
3.4
2.8
6.9 × 7.3
6.9 × 7.3
6.9 × 7.3
6.9 × 7.3
6.9 × 7.3
6.9 × 7.3
3.2
3.2
3.2
3.2
3.2
3.2
TDK
www.tdk.com
1.5
2.2
3.3
4.7
6.8
WE-TPC 4828 Series
1.2
1.8
2.2
2.7
3.3
3.9
4.7
17
20
23
27
30
47
52
3.1
2.7
4.8 × 4.8
4.8 × 4.8
4.8 × 4.8
4.8 × 4.8
4.8 × 4.8
4.8 × 4.8
4.8 × 4.8
2.8
2.8
2.8
2.8
2.8
2.8
2.8
Würth Elektronik
www.we-online.com
2.5
2.35
2.15
1.72
1.55
produce the most improvement. Percent efficiency can
be expressed as:
through inductor L but is “chopped” between the
internal top and bottom power MOSFETs. Thus, the
series resistance looking into the SW pin is a function
ꢀ Efficiency = 100ꢀ – (L1 + L2 + L3 +…)
of both top and bottom MOSFET R
cycle (DC) as follows:
and the duty
DS(ON)
where L1, L2, etc. are the individual losses as a percent-
age of input power. Although all dissipative elements in
the circuit produce losses, three main sources usually
R
SW
= (R )(DC) + (R )(1 – DC)
DS(ON)TOP DS(ON)BOT
2
account for most of the losses in LTC3621 circuits: 1) I R
TheR
forboththetopandbottomMOSFETscanbe
DS(ON)
losses, 2) switching and biasing losses, 3) other losses.
obtained from the Typical Performance Characteristics
2
curves. Thus to obtain I R losses:
2
1. I R losses are calculated from the DC resistances of
2
2
the internal switches, R , and external inductor, R .
I R losses = I
(R + R )
SW
L
OUT SW L
In continuous mode, the average output current flows
3621f
11
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2. The switching current is the sum of the MOSFET driver
andcontrolcurrents.ThepowerMOSFETdrivercurrent
resultsfromswitchingthegatecapacitanceofthepower
MOSFETs. Each time a power MOSFET gate is switched
from low to high to low again, a packet of charge dQ
moves from IN to ground. The resulting dQ/dt is a cur-
rent out of IN that is typically much larger than the DC
To avoid the LTC3621 from exceeding the maximum junc-
tion temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
T
RISE
= P • θ
D JA
control bias current. In continuous mode, I
=
GATECHG
As an example, consider the case when the LTC3621
is used in applications where V = 12V, I = 1A,
f(Q + Q ), where Q and Q are the gate charges of
T
B
T
B
the internal top and bottom power MOSFETs and f is
the switching frequency. The power loss is thus:
IN
OUT
f = 2.25MHz, V
= 1.8V. The equivalent power MOSFET
OUT
resistance R is:
SW
Switching Loss = I
• V
IN
GATECHG
V
V
V
OUT
The gate charge loss is proportional to V and f and
IN
RSW =RDS(ON)TOP
•
OUT +RDS(ON)BOT • 1–
V
thus their effects will be more pronounced at higher
IN
IN
supply voltages and higher frequencies.
1.8V
12V
1.8V
12V
=370mΩ•
=183mΩ
+150mΩ • 1–
3. Other “hidden” losses such as transition loss and cop-
per trace and internal load resistances can account for
additional efficiency degradations in the overall power
system. It is very important to include these “system”
level losses in the design of a system. Transition loss
arises from the brief amount of time the top power
MOSFET spends in the saturated region during switch
node transitions. The LTC3621 internal power devices
switch quickly enough that these losses are not sig-
nificant compared to other sources. These losses plus
other losses, including diode conduction losses during
dead-time and inductor core losses, generally account
for less than 2ꢀ total additional loss.
The V current during 2.25MHz force continuous opera-
IN
tion with no load is about 5mA, which includes switching
and internal biasing current loss, transition loss, inductor
core loss and other losses in the application. Therefore,
the total power dissipated by the part is:
2
P = I
D
• R + V • I
SW IN IN(Q)
= 1A • 183mΩ + 12V • 5mA
OUT
2
= 243mW
TheDFN2mm× 3mmpackagejunction-to-ambientthermal
Thermal Conditions
resistance, θ , is around 64°C/W. Therefore, the junction
JA
temperature of the regulator operating in a 25°C ambient
In a majority of applications, the LTC3621 does not dis-
sipatemuchheatduetoitshighefficiencyandlowthermal
resistance of its exposed pad package. However, in ap-
plications where the LTC3621 is running at high ambient
temperature is approximately:
T = 0.243W • 64°C/W + 25°C = 40.6°C
J
Remembering that the above junction temperature is
temperature, high V , high switching frequency, and
IN
obtained from an R
at 25°C, we might recalculate
DS(ON)
maximum output current load, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 160°C,
bothpowerswitcheswillbeturnedoffuntilthetemperature
drops about 15°C cooler.
the junction temperature based on a higher R
since
DS(ON)
it increases with temperature. Redoing the calculation
assuming that R increased 5ꢀ at 40.6°C yields a new
SW
3621f
12
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LTC3621/LTC3621-2
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junction temperature of 41.1°C. If the application calls
for a higher ambient temperature and/or higher switching
frequency, careshould betaken to reduce thetemperature
rise of the part by using a heat sink or forced air flow.
Design Example
As a design example, consider using the LTC3621 in an
application with the following specifications:
V = 10.8V to 13.2V
IN
Board Layout Considerations
V
OUT
= 3.3V
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3621 (refer to Figure 3). Check the following in
your layout:
I
I
f
= 1A
= 0A
OUT(MAX)
OUT(MIN)
= 2.25MHz
SW
1. Do the capacitors C connect to the V and GND as
IN
IN
Because efficiency and quiescent current is important at
both 500mA and 0A current states, Burst Mode operation
will be utilized.
close as possible? These capacitors provide the AC
currenttotheinternalpowerMOSFETsandtheirdrivers.
2. Are C
and L closely connected? The (–) plate of
OUT
Given the internal oscillator of 2.25MHz, we can calcu-
late the inductor value for about 40ꢀ ripple current at
C
returns current to GND and the (–) plate of C .
OUT
IN
maximum V :
3. The resistive divider, R1 and R2, must be connected
IN
between the (+) plate of C
and a ground line ter-
OUT
3.3V
2.25MHz •0.4A
3.3V
13.2V
1–
minated near GND. The feedback signal V should be
L=
=2.75µH
FB
routed away from noisy components and traces, such
as the SW line, and its trace should be minimized. Keep
R1 and R2 close to the IC.
Given this, a 2.7µH or 3.3µH inductor would suffice.
will be selected based on the ESR that is required to
C
OUT
4. Solder the exposed pad (Pin 7 for DFN, Pin 9 for MSOP)
onthebottomofthepackagetotheGNDplane.Connect
this GND plane to other layers with thermal vias to help
dissipate heat from the LTC3621.
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, a
22µF ceramic capacitor will be used.
C should be sized for a maximum current rating of:
IN
5. Keep sensitive components away from the SW pin. The
1/2
input capacitor, C , feedback resistors, and INTV
IN
CC
3.3V 13.2V
IRMS =1A
–1 =0.43A
bypass capacitors should be routed away from the SW
trace and the inductor.
13.2V 3.3V
Decoupling the V pin with 10µF ceramic capacitors is
6. A ground plane is preferred.
IN
adequate for most applications.
7. Flood all unused areas on all layers with copper, which
reduces the temperature rise of power components.
These copper areas should be connected to GND.
3621f
13
For more information www.linear.com/LTC3621
LTC3621/LTC3621-2
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)
0.70 ±0.05
1.65 ±0.05
3.55 ±0.05
(2 SIDES)
2.15 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
1.35 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
2.00 ±0.10
(2 SIDES)
0.40 ± 0.10
TYP
R = 0.05
TYP
4
6
3.00 ±0.10 1.65 ± 0.10
(2 SIDES)
(2 SIDES)
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
PIN 1 NOTCH
R0.20 OR 0.25
× 45° CHAMFER
(DCB6) DFN 0405
3
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
1.35 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3621f
14
For more information www.linear.com/LTC3621
LTC3621/LTC3621-2
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MS8E Package
8-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1662 Rev J)
BOTTOM VIEW OF
EXPOSED PAD OPTION
1.88
(.074)
1
0.29
REF
1.88 ± 0.102
(.074 ± .004)
1.68
(.066)
0.889 ± 0.127
(.035 ± .005)
0.05 REF
DETAIL “B”
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
1.68 ± 0.102
(.066 ± .004)
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
DETAIL “B”
8
NO MEASUREMENT PURPOSE
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.65
(.0256)
BSC
0.52
(.0205)
REF
0.42 ± 0.038
(.0165 ± .0015)
8
7 6 5
TYP
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4
0.53 ± 0.152
(.021 ± .006)
1.10
(.043)
MAX
0.86
(.034)
REF
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.1016 ± 0.0508
(.004 ± .002)
0.65
(.0256)
BSC
MSOP (MS8E) 0911 REV J
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
3621f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC3621/LTC3621-2
Typical applicaTion
5VOUT with 400mA Burst Mode Operation, 2.25MHz
L1
3.3µH
V
V
IN
OUT
V
SW
LTC3621-2
IN
12V
5V
C
C
OUT
C
R3
FB
IN
22pF
22µF
10µF
187k
RUN
3621 TA02
FB
MODE
R4
25.5k
INTV
CC
C1
1µF
GND
1.2VOUT, Forced Continuous Mode, 1MHz
L1
3.3µH
2.7V TO 17V
1.2V
V
IN
V
SW
V
OUT
IN
C2
22µF
C3
10µF
R1
604k
C3
LTC3621
RUN
22pF
FB
MODE
R5
604k
INTV
CC
C1
1µF
GND
V 1V
3621 TA03
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
95ꢀ Efficiency, V : 4V to 40V, V
LTC3646/
40V, 1A (I ), 3MHz Synchronous Step-Down
= 0.6V, I = 140µA, I < 8µA,
OUT(MIN) Q SD
OUT
IN
LTC3646-1
DC/DC Converter
3mm × 4mm DFN-14, MSOP-16E Packages
LTC3600
LTC3601
LTC3603
1.5A, 15V, 4MHz Synchronous Rail-to-Rail Single
Resistor Step-Down Regulator
95ꢀ Efficiency, V : 4V to 15V, V = 0V, I = 700µA, I < 1µA,
IN
OUT(MIN)
Q
SD
3mm × 3mm DFN-12, MSOP-12E Packages
15V, 1.5A (I ) 4MHz Synchronous Step-Down
95ꢀ Efficiency, V : 4.5V to 15V, V = 0.6V, I = 300µA, I < 1µA,
OUT
IN
OUT(MIN)
Q
SD
DC/DC Converter
4mm × 4mm QFN-20, MSOP-16E Packages
15V, 2.5A (I ) 3MHz Synchronous Step-Down
95ꢀ Efficiency, V : 4.5V to 15V, V = 0.6V, I = 75µA, I < 1µA,
OUT
IN
OUT(MIN)
Q
SD
DC/DC Converter
4mm × 4mm QFN-20, MSOP-16E Packages
LTC3633/
LTC3633A
15V, Dual 3A (I ) 4MHz Synchronous Step-Down
95ꢀ Efficiency, V : 3.6V to 15V, V = 0.6V, I = 500µA, I < 15µA,
OUT
IN
OUT(MIN)
Q
SD
DC/DC Converter
4mm × 5mm QFN-28, TSSOP-28E Packages. A Version Up to 20V
IN
LTC3605/
LTC3605A
15V, 5A (I ) 4MHz Synchronous Step-Down
95ꢀ Efficiency, V : 4V to 15V, V
= 0.6V, I = 2mA, I < 15µA,
OUT(MIN) Q SD
OUT
IN
DC/DC Converter
4mm × 4mm QFN-24 Package. A Version Up to 20V
IN
LTC3604
15V, 2.5A (I ) 4MHz Synchronous Step-Down
95ꢀ Efficiency, V : 3.6V to 15V, V
= 0.6V, I = 300µA, I < 14µA,
OUT(MIN) Q SD
OUT
IN
DC/DC Converter
3mm × 3mm QFN-16, MSOP-16E Packages
LTC1877
600mA (I ) 550kHz Synchronous Step-Down
V : 2.7V to 10V, V
IN
= 0.8V, I = 10µA, I < 1µA, MSOP-8 Package
OUT
OUT(MIN)
O
SD
DC/DC Converter
LT8610/LT8611 42V, 2.5A (I ) Synchronous Step-Down
96ꢀ Efficiency, V : 3.4V to 42V, V
= 0.97V, I = 2.5µA, I < 1µA,
OUT(MIN) Q SD
OUT
IN
DC/DC Converter
MSOP-16E Package
3621f
LT 0313 • PRINTED IN USA
16 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2013
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC3621
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