LTC3676IUJ#TRPBF [Linear]
LTC3676/LTC3676-1 - Power Management Solution for Application Processors; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C;型号: | LTC3676IUJ#TRPBF |
厂家: | Linear |
描述: | LTC3676/LTC3676-1 - Power Management Solution for Application Processors; Package: QFN; Pins: 40; Temperature Range: -40°C to 85°C |
文件: | 总38页 (文件大小:508K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC3676/LTC3676-1
Power Management Solution
for Application Processors
FeaTures
DescripTion
2
The LTC®3676 is a complete power management solution
for advanced portable application processor-based sys-
tems. The device contains four synchronous step-down
DC/DC converters for core, memory, I/O, and system
on-chip (SoC) rails and three 300mA LDO regulators for
low noise analog supplies. The LTC3676-1 has a 1.ꢀA
buck regulator configured to support DDR termination
n
Quad I C Adjustable High Efficiency Step Down
DC/DC Converters: 2.5A, 2.5A, 1.5A, 1.5A
n
Three 300mA LDO Regulators (Two Adjustable)
n
DDR Power Solution with V and VTTR Reference
TT
n
n
n
n
n
n
n
n
n
Pushbutton ON/OFF Control with System Reset
2
Independent Enable Pin-Strap or I C Sequencing
Programmable Autonomous Power-Down Control
Dynamic Voltage Scaling
2
plus a VTTR reference output. An I C serial port is used
Power Good and Reset Functions
Selectable 2.2ꢀMHz or 1.12MHz Switching Frequency
Always Alive 2ꢀmA LDO Regulator
12µA Standby Current
Low Profile 40-Lead 6mm 6mm QFN and 48-Lead
Exposed Pad LQFP
to control regulator enables, power-down sequencing,
output voltage levels, dynamic voltage scaling, operating
modes and status reporting.
Regulator start-up is sequenced by connecting outputs to
2
enable pins in the desired order or via the I C port. System
power-on, power-off and reset functions are controlled by
2
pushbutton interface, pin inputs, or I C.
applicaTions
The LTC3676 supports i.MX, PXA and OMAP processors
with eight independent rails at appropriate power levels.
Other features include interface signals such as the VSTB
pin that toggles between programmed run and standby
output voltages on up to four rails simultaneously. The
device is available in a 40-lead 6mm 6mm QFN and
48-lead exposed pad LQFP packages.
n
Supports Freescale i.MX6, ARM Cortex, and Other
Application Processors
n
Handheld Instruments and Scanners
n
Portable Industrial and Medical Devices
n
Automotive Infotainment
n
High End Consumer Devices
n
Multi-Rail Systems
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
of Analog Devices, Inc. All other trademarks are the property of their respective owners.
Typical applicaTion
V
IN
2.7V TO 5.5V
Start-Up Sequence
V
1.5µH
1.5µH
1.5µH
1.5µH
IN
V
V
ARM
RTC
3V
WAKE
LDO1
SW3
LTC3676-1
LDO2
1.38V
2.5A
25mA
5V/DIV
1µF
1µF
1µF
47µF
47µF
47µF
47µF
V
DD(HIGH)
V
SOC
V
DD(HIGH)
2.97V
300mA
SW2
SW4
SW1
1.38V
1.5A
V
LDO3
ARM
1V/DIV
1V/DIV
V
V
1.5V
2.5A
(V )
LDO3
1.8V
DDR DDQ
V
AND V
SOC
LDO3
LDO4
300mA
V
DDR
AND V
V
TT
3V
V
TT
TTR
1/2 V
1.5A
DDQ
300mA
1µF
6
VTTR (1/2 V
WAKE
)
ENABLES VTTR
PWR_ON WAKE
DDQ
3676 TA01b
1ms/DIV
ON
PGOOD
2
2
TO µPROCESSOR
I C
GND
3676 TA01a
3676ff
1
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
absoluTe MaxiMuM raTings (Note 1)
V , DV , SW1, SW2, SW3, SW4............... –0.3V to 6V
WAKE, RSTO, PWR_ON, IRQ, VTTR,
IN
DD
SW1, SW2, SW3, SW4
VDDQIN ....................................................... –0.3V to 6V
(Transient t < 1µs, Duty Cycle < ꢀ%)............... –2V to 7V
SDA, SCL ......................................–0.3V to DV + 0.3V
Operating Junction Temperature Range
(Notes 2, 3)............................................ –40°C to 1ꢀ0°C
Storage Temperature Range ......................–6ꢀ to 1ꢀ0°C
DD
PV , PV , PV , PV , V ,
IN1
IN2
IN3
IN4 IN_L2
V
, V
.................................. –0.3V to V + 0.3V
IN_L3 IN_L4
IN
LDO1, FB_L1, LDO2, FB_L2, LDO3, LDO4, FB_L4,
FB_B1, FB_B2, FB_B3, FB_B4, PGOOD, VSTB, EN_B1,
EN_B2, EN_B3, EN_B4, EN_L2, EN_L3, EN_L4, ON,
pin conFiguraTion
LTC3676
LTC3676-1
TOP VIEW
TOP VIEW
40 39 38 37 36 35 34 33 32 31
40 39 38 37 36 35 34 33 32 31
FB_L2
1
2
3
4
5
6
7
8
9
30
29
28
27
FB_L2
1
2
3
4
5
6
7
8
9
30
29
28
27
EN_L2
ON
EN_L2
ON
V
V
IN_L2
IN_L2
LDO2
LDO3
LDO2
LDO3
LDO1
LDO1
V
V
IN
IN
V
V
26 FB_L1
25
26 FB_L1
25
IN_L3
IN_L3
41
GND
41
GND
LDO4
LDO4
FB_B2
24 FB_B1
23
FB_B2
24 FB_B1
V
V
IN_L4
IN_L4
FB_L4
EN_L4
VDDQIN
VTTR
23
22
21
FB_B4
22 FB_B3
21
FB_B4
FB_B3
EN_L3 10
EN_L3 10
PWR_ON
PWR_ON
11 12 13 14 15 16 17 18 19 20
11 12 13 14 15 16 17 18 19 20
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
T
= 1ꢀ0°C, = 33°C/W, = 2°C/W
T
= 1ꢀ0°C, = 33°C/W, = 2°C/W
JMAX
JA
JC
JMAX JA JC
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
LTC3676
LTC3676-1
TOP VIEW
TOP VIEW
NC
1
2
3
4
5
6
7
8
9
36 NC
NC
1
2
3
4
5
6
7
8
9
36 NC
FB_L2
35 EN_L2
34 ON
FB_L2
35 EN_L2
34 ON
V
V
IN_L2
IN_L2
LDO2
33 LDO1
LDO2
33 LDO1
LDO3
32 V
LDO3
32 V
IN
IN
49
GND
V
V
31 FB_L1
30 FB_B2
29 FB_B1
28 FB_B4
27 FB_B3
26 PWR_ON
25 NC
49
GND
IN_L3
V
V
31 FB_L1
30 FB_B2
29 FB_B1
28 FB_B4
27 FB_B3
26 PWR_ON
25 NC
IN_L3
LD04
LD04
IN_L4
IN_L4
FB_L4
VDDQIN
EN_L4 10
EN_L3 11
NC 12
VTTR 10
EN_L3 11
NC 12
LXE PACKAGE
48-LEAD (7mm × 7mm) PLASTIC LQFP
LXE PACKAGE
48-LEAD (7mm × 7mm) PLASTIC LQFP
T
= 1ꢀ0°C, = 19°C/W, = 3°C/W
T
= 1ꢀ0°C, = 19°C/W, = 3°C/W
JMAX
JA
JC
JMAX JA JC
EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB
3676ff
2
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
orDer inForMaTion
http://www.linear.com/product/LTC3676#orderinfo
LEAD FREE FINISH
LTC3676EUJ#PBF
LTC3676IUJ#PBF
LTC3676HUJ#PBF
LTC3676EUJ-1#PBF
LTC3676IUJ-1#PBF
LTC3676HUJ-1#PBF
TAPE AND REEL
PART MARKING*
LTC3676UJ
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 12ꢀ°C
–40°C to 12ꢀ°C
–40°C to 1ꢀ0°C
–40°C to 12ꢀ°C
–40°C to 12ꢀ°C
–40°C to 1ꢀ0°C
LTC3676EUJ#TRPBF
LTC3676IUJ#TRPBF
LTC3676HUJ#TRPBF
LTC3676EUJ-1#TRPBF
LTC3676IUJ-1#TRPBF
LTC3676HUJ-1#TRPBF
40-Lead (6mm 6mm) Plastic QFN
40-Lead (6mm 6mm) Plastic QFN
40-Lead (6mm 6mm) Plastic QFN
40-Lead (6mm 6mm) Plastic QFN
40-Lead (6mm 6mm) Plastic QFN
40-Lead (6mm 6mm) Plastic QFN
LTC3676UJ
LTC3676UJ
LTC3676UJ-1
LTC3676UJ-1
LTC3676UJ-1
LEAD FREE FINISH
LTC3676ELXE#PBF
LTC3676ILXE#PBF
LTC3676HLXE#PBF
LTC3676ELXE-1#PBF
LTC3676ILXE-1#PBF
LTC3676HLXE-1#PBF
TRAY
PART MARKING*
LTC3676LXE
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 12ꢀ°C
–40°C to 12ꢀ°C
–40°C to 1ꢀ0°C
–40°C to 12ꢀ°C
–40°C to 12ꢀ°C
–40°C to 1ꢀ0°C
LTC3676ELXE#PBF
LTC3676ILXE#PBF
LTC3676HLXE#PBF
LTC3676ELXE-1#PBF
LTC3676ILXE-1#PBF
LTC3676HLXE-1#PBF
48-Lead (7mm 7mm) Plastic eLQFP
48-Lead (7mm 7mm) Plastic eLQFP
48-Lead (7mm 7mm) Plastic eLQFP
48-Lead (7mm 7mm) Plastic eLQFP
48-Lead (7mm 7mm) Plastic eLQFP
48-Lead (7mm 7mm) Plastic eLQFP
LTC3676LXE
LTC3676LXE
LTC3676LXE-1
LTC3676LXE-1
LTC3676LXE-1
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in ꢀ00 unit reels through
designated sales channels with #TRMPBF suffix.
3676ff
3
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_L2 = VIN_L3
VIN_L4 = DVDD = 3.8V. All regulators disabled unless otherwise noted.
=
PARAMETER
CONDITIONS
MIN
TYP
MAX
ꢀ.ꢀ
UNITS
V
l
l
Operating Input Supply Voltage, V
2.7
IN
V
Standby Current
PWR_ON = 0V
12
21
µA
IN
Step-Down Switching Regulators 1, 2, 3 and 4
Output Voltage Range
V
FB
PV
V
IN
Burst Mode® V Quiescent Current
V
FB
V
FB
V
FB
= 8ꢀ0mV (Note ꢀ)
= 8ꢀ0mV (Note ꢀ)
= 0V (Note ꢀ)
23
120
170
ꢀ0
200
300
µA
µA
µA
l
l
l
IN
Pulse-Skipping Mode V Quiescent Current
IN
Forced Continuous V Quiescent Current
IN
Feedback Pin Input Current
Maximum Duty Cycle
V
FB
V
FB
= 8ꢀ0mV
= 0V
–0.0ꢀ
100
0.0ꢀ
µA
%
SW Pull-Down Resistance
Feedback Reference Soft-Start Rate
Regulator Disabled
62ꢀ
0.8
Ω
(Note 6)
V/ms
mV
l
l
l
High Feedback Regulation Voltage (V
)
DVBxA[4:0] = DVBxB[4:0] = 11111,
788
714
404
800
812
736
421
FB
V
= 2.7V to ꢀ.ꢀV
IN
Default Feedback Regulation Voltage (V
)
DVBxA[4:0] = DVBxB[4:0] = 11001,
= 2.7V to ꢀ.ꢀV
72ꢀ
412.ꢀ
12.ꢀ
mV
mV
mV
FB
V
IN
Low Feedback Regulation Voltage (V
)
DVBxA[4:0] = DVBxB[4:0] = 00000,
= 2.7V to ꢀ.ꢀV
FB
V
IN
Feedback LSB Step Size
Switching Frequency
l
l
BUCKx[2] = 0
BUCKx[2] = 1
1.7
0.8ꢀ
2.2ꢀ
1.12ꢀ
2.7
1.3ꢀ
MHz
MHz
1.5A Step-Down Switching Regulators 1 and 2
PMOS Current Limit
l
2
A
mΩ
mΩ
PMOS On-Resistance (Note 7)
NMOS On-Resistance (Note 7)
2.5A Step-Down Switching Regulators 3 and 4
PMOS Current Limit
160
80
l
3.0
A
mΩ
mΩ
PMOS On-Resistance (Note 7)
NMOS On-Resistance (Note 7)
120
70
Step-Down Switching Regulator 1 and VTTR (LTC3676-1)
l
l
l
Buck 1 Feedback Regulation Voltage
VTTR Output Voltage
VDDQIN = 1.ꢀV
VTTR – 10
VTTR
VTTR + 10
mV
mV
mA
mA
VDDQIN = 1.ꢀV
0.49•VDDQIN 0.5•VDDQIN 0.51•VDDQIN
VTTR Maximum Output Current
–10
10
I
VTTR Enabled
1
VIN
LDO Regulators 2, 3 and 4
Feedback Reference Soft-Start Rate
Output Pull-Down Resistance
LDO Regulator 1
10
V/ms
Ω
Regulator Disabled
62ꢀ
Output Voltage Range
V
V
IN
FB_L1
l
Feedback Regulation Voltage (V
Line Regulation
)
689
72ꢀ
761
mV
FB_L1
I
= 1mA, V
= 1.2V,
0.1ꢀ
%/V
LDO1
IN
LDO1
V
= 2.7V to ꢀ.ꢀV
Load Regulation
I
= 0.1mA to 2ꢀmA,
= 3.3V
0.1
%
LDO1
LDO1
V
3676ff
4
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_L2 = VIN_L3
VIN_L4 = DVDD = 3.8V. All regulators disabled unless otherwise noted.
=
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
mA
l
Available Output Current
Short-Circuit Output Current Limit
Dropout Voltage (Note 4)
Feedback Pin Input Current
LDO Regulator 2
2ꢀ
6ꢀ
100
280
0.0ꢀ
mA
I
= 2ꢀmA, V
= 3.3V
200
mV
LDO1
LDO1
V
FB_L1
= 8ꢀ0mV
–0.0ꢀ
1.7
µA
l
l
V
Input Voltage
V
IN
V
V
IN_L2
LDO2 Output Voltage Range
Available Output Current
I
= 1mA
V
V
IN_L2
LDO2
FB_L2
300
mA
l
l
V
IN_L2
V
IN_L2
Quiescent Current
Shutdown Current
Regulator Enabled, I
= 0A
LDO2
12
0
2ꢀ
1
µA
µA
Regulator Disabled
l
l
V
Quiescent Current
Regulator Enabled
ꢀ0
8ꢀ
µA
V
IN
Feedback Regulation Voltage (V
Line Regulation
)
0.707
0.72ꢀ
0.01
0.01
0.743
FB_L2
I
I
=1mA, V = 2.7V to ꢀ.ꢀV
%/V
%
LDO2
IN
Load Regulation
= 1mA to 300mA
LDO2
Short-Circuit Current Limit
Dropout Voltage (Note 4)
770
mA
I
I
= 300mA, V
= 300mA, V
= 2.ꢀV
= 1.2V
210
4ꢀ0
260
61ꢀ
mV
mV
LDO2
LDO2
LDO2
LDO2
Feedback Pin Input Current
V
FB_L2
= 72ꢀmV
–0.0ꢀ
0.0ꢀ
µA
LDO Regulator 3
l
l
l
V
Input Voltage
2.3ꢀ
1.746
300
V
V
V
IN_L3
IN
Output Voltage
V
= V , I
= 1mA
1.8
1.8ꢀ4
IN_L3
IN LDO3
Available Output Current
mA
l
l
V
IN_L3
V
IN_L3
Quiescent Current
Shutdown Current
Regulator Enabled, I
= 0A
LDO3
14
0
2ꢀ
1
µA
µA
Regulator Disabled
l
V
Quiescent Current
Regulator Enabled
ꢀ0
8ꢀ
µA
%/V
%
IN
Line Regulation
I
I
=1mA, V = 2.7V to ꢀ.ꢀV
0.01
0.0ꢀ
LDO3
LDO3
IN
Load Regulation
= 1mA to 300mA
Short-Circuit Current Limit
Dropout Voltage (Note 4)
LDO Regulator 4
770
3ꢀ0
mA
mV
I
= 300mA, V = 1.8V
LDO3
280
LDO3
l
l
V
Input Voltage
1.7
V
V
V
V
IN_L4
IN
LDO4 Output Voltage Range (LTC3676)
Feedback Regulation Voltage (LTC3676) (V
Output Voltage (LTC3676-1)
I
I
= 1mA
V
V
IN_L4
LDO4
FB_L4
)
0.707
0.72ꢀ
0.743
FB_L4
l
l
l
l
= 1mA, LDOB[4:3] = 00
1.164
2.42ꢀ
2.716
2.91
1.2
2.ꢀ
2.8
3.0
1.236
2.ꢀ7ꢀ
2.884
3.09
V
V
V
V
LDO4
LDOB[4:3] = 01
LDOB[4:3] = 10
LDOB[4:3] = 11
l
Available Output Current
300
mA
l
l
V
IN_L4
V
IN_L4
Quiescent Current
Shutdown Current
Regulator Enabled, I
= 0A
LDO4
12
0
2ꢀ
1
µA
µA
Regulator Disabled
l
V
IN
Quiescent Current
Regulator Enabled
ꢀ0
8ꢀ
µA
Line Regulation
I
=1mA, V = 2.7V to ꢀ.ꢀV
0.01
%/V
LDO4
IN
3676ff
5
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_L2 = VIN_L3
VIN_L4 = DVDD = 3.8V. All regulators disabled unless otherwise noted.
=
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Load Regulation (LTC3676)
Load Regulation (LTC3676-1)
I
= 1mA to 300mA
0.01
0.0ꢀ
%
%
LDO4
Short-Circuit Current Limit
Dropout Voltage (Note 4)
770
mA
I
I
= 300mA, V
= 300mA, V
= 2.ꢀV
= 1.2V
210
4ꢀ0
260
61ꢀ
mV
mV
LDO4
LDO4
LDO4
LDO4
Feedback Pin Input Current (LTC3676)
Enable Inputs
V
FB_L4
= 72ꢀmV
–0.0ꢀ
0.0ꢀ
µA
l
l
l
Threshold Rising
All Enables Low
One Enable High
0.7ꢀ
0.7
1.2
V
Threshold Falling
0.4
Precision Threshold
Input Pull-Down Resistance
VSTB, PWR_ON Inputs
Threshold
One or More Enables
0.370
0.400
4.ꢀ
0.430
V
MΩ
l
0.370
0.400
4.ꢀ
0.430
V
Pull-Down Resistance
Pushbutton Interface
MΩ
l
l
ON Threshold Rising
ON Threshold Falling
0.7ꢀ
0.7
1.2
1
V
V
0.4
–1
ON Input Current
ON = V
µA
µA
IN
ON = 0V
–40
ꢀ0
0.2
400
10
ꢀ0
1
ON Low Time to IRQ Low
ms
µs
ON High Time to IRQ High
ON Low Time to WAKE High
ON Low Time to Hard Reset
ms
sec
ms
sec
sec
sec
ms
ms
CNTRL[6] = 0
IRQ Minimum Pulse Width
IRQ Blanking from WAKE Low
Minimum WAKE Low Time
1
WAKE High Time with PWR_ON = 0V
PWR_ON High to WAKE High
PWR_ON Low to WAKE Low
Status Output Pins (WAKE, PGOOD, RSTO, IRQ)
WAKE Output Low Voltage
ꢀ
3
3
I
= 3mA
= 3.8V
0.1
0.1
0.4
0.1
0.4
0.1
V
µA
V
WAKE
WAKE Output High Leakage Current
PGOOD Output Low Voltage
V
–0.1
–0.1
WAKE
I
= 3mA
= 3.8V
PGOOD
PGOOD Output High Leakage Current
V
µA
PGOOD
PGOOD Threshold Rising
PGOOD Threshold Falling
–6
–8
%
%
RSTO Output Low Voltage
I
= 3mA
= 3.8V
0.1
0.4
0.1
V
RSTO
RSTO Output High Leakage Current
V
–0.1
–0.1
µA
RSTO
LDO1 Power Good Threshold Rising
LDO1 Power Good Threshold Falling
–7.ꢀ
–10
%
%
IRQ Output Low Voltage
I
= 3mA
= 3.8V
0.1
0.4
0.1
V
IRQ
IRQ Output High Leakage Current
V
µA
IRQ
3676ff
6
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
elecTrical characTerisTics The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_L2 = VIN_L3
VIN_L4 = DVDD = 3.8V. All regulators disabled unless otherwise noted.
=
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
Undervoltage Lockout Rising
Undervoltage Lockout Falling
2.ꢀꢀ
2.4ꢀ
2.6ꢀ
V
V
2.3ꢀ
Undervoltage Warning
CNTRL[4:2] = 000 (POR Default)
CNTRL[4:2] = 001
CNTRL[4:2] = 010
CNTRL[4:2] = 011
CNTRL[4:2] = 100
CNTRL[4:2] = 101
CNTRL[4:2] = 110
CNTRL[4:2] = 111
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
V
V
V
V
V
V
V
V
SYMBOL
PARAMETER
DV Input Supply Voltage
CONDITIONS
MIN
TYP
MAX
UNITS
2
I C Port
l
DV
VDD
1.6
ꢀ.ꢀ
1
V
µA
V
DD
I
DV Quiescent Current
DD
SCL/SDA = 0kHz
0.3
1
DVDD
DV
VDD_UVLO
DV UVLO Level
DD
ADDRESS
LTC3676 Device Address
LTC3676-1 Device Address
0111100[R/W]
0111101[R/W]
V
V
SDA/SCL Input Threshold Rising
SDA/SCL Input Threshold Falling
SDA/SCL High Input Current
SDA/SCL Low Input Current
SDA Output Low Voltage
70
30
0
%DV
%DV
IH
DD
IL
DD
I
IH
I
IL
SDA = SCL = ꢀ.ꢀV
SDA = SCL = 0V
–1
–1
1
1
µA
µA
V
0
V
I
= 3mA
SDA
0.4
400
OL_SDA
SCL
f
t
Clock Operating Frequency
kHz
µs
Bus Free Time Between Stop and Start
Condition
1.3
BUF
t
t
t
t
t
t
t
t
t
t
t
Hold Time After Repeated Start Condition
Repeated Start Condition Setup Time
Stop Condition Setup Time
Data Hold Time Output
0.6
µs
µs
µs
ns
ns
ns
µs
µs
ns
ns
ns
HD_STA
SU_STA
SU_STO
HD_DAT(O)
HD_DAT(I)
SU_DAT
LOW
0.6
0.6
0
0
900
Data Hold Time Input
Data Setup Time
100
SCL Clock Low Period
1.3
SCL Clock High Period
0.6
HIGH
Clock/Data Fall Time
C = Capacitance of BUS Line (pF)
20 + 0.1C
20 + 0.1C
300
300
ꢀ0
f
B
B
B
Clock/Data Rise Time
C = Capacitance of BUS Line (pF)
B
r
Input Spike Suppression Pulse Width
SP
Note 1: Stresses beyond those listed Under Absolute Maximum ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum rating condition for extended periods may affect device
reliability and lifetime.
degrade operating lifetimes; operating lifetime is derated for junction
temperatures greater than 12ꢀ°C. The junction temperature (T in °C) is
J
calculated from the ambient temperature (T in °C) and power dissipation
A
(P , in Watts), and package to junction ambient thermal impedance
D
(J in Watts/°C ) according to the formula:
A
Note 2: The LTC3676 is tested under pulsed load conditions such that
T ≈ T . The LTC3676E is guaranteed to meet specifications from
T = T + (P • J ).
J A D A
J
A
0°C to 8ꢀ°C junction temperature. Specifications over the –40°C to
12ꢀ°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3676I is guaranteed over the –40°C to 12ꢀ°C operating junction
temperature range and the LTC3676H is guaranteed over the full –40°C to
1ꢀ0°C operating junction temperature range. High junction temperatures
Note that the maximum ambient temperature consistent with these
specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal impedance and
other environmental factors.
3676ff
7
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
elecTrical characTerisTics
Note 3: The LTC3676 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 1ꢀ0°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 6: Soft-Start measured in test mode with regulator error amplifier in
unity-gain mode.
Note 7: The switching regulator PMOS and NMOS on-resistance is
guaranteed by correlation to wafer level measurements.
Note 4: Dropout voltage is defined as (V – V
) for LDO1 or
LDO1
IN
(V
– V ) for other LDOs when V is 3% lower than V
LDOx LDOx LDOx
IN_Lx
measured with V = V
= 4.3V.
IN
IN_Lx
Typical perForMance characTerisTics VIN = 3.8V, TA = 25°C unless otherwise noted
Step-Down Switching Regulator
IVIN vs VIN
Standby IVIN vs VIN
LDO2 to LDO4 IVIN vs VIN
900
800
700
600
500
400
300
200
100
16
14
12
10
8
250
200
150
100
50
PULSE-SKIPPING MODE
ENABLE FOUR BUCKS
ENABLE 3 LDOs
ENABLE THREE BUCKS
ENABLE 2 LDOs
ENABLE 1 LDO
ENABLE TWO BUCKS
ENABLE ONE BUCK
6
4
2
0
0
0
3.5
4.0
4.5
5.0
2.5
3.0
5.5
2.50
3.50
4.50
5.50
2.5
3.0
3.5
4.0
5.5
4.5
5.0
VOLTAGE (V)
VOLTAGE (V)
V
(V)
IN
3676 G01
3676 G02
3676 G03
Step-Down Switching Regulator
IVIN vs VIN
Input Supply Current
vs Temperature
Oscillator Frequency
vs Temperature
180
160
140
120
100
80
2.30
2.25
1200
1000
Burst Mode OPERATION
ALL REGULATORS ENABLED
ENABLE FOUR BUCKS
ENABLE THREE BUCKS
PULSE-SKIPPING
2.20
2.15
800
600
ENABLE TWO BUCKS
ENABLE ONE BUCK
Burst Mode OPERATION
STANDBY
60
2.10
2.05
2.00
400
200
0
40
20
0
–50
0
50
TEMPERATURE (°C)
100
150
2.5
3.0
3.5
4.0
5.5
–50
0
50
100
150
4.5
5.0
VOLTAGE (V)
TEMPERATURE (°C)
3676 G06
3676 G04
3676 G05
3676ff
8
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
Typical perForMance characTerisTics
Oscillator Frequency Change
vs VIN
Step-Down Switching Regulators 1
and 2 Efficiency vs IOUT
Step-Down Switching Regulators 1
and 2 Efficiency vs IOUT
0.8
0.6
100
90
100
90
80
70
60
80
0.4
BURST
BURST
70
0.2
60
PULSE
PULSE
SKIPPING
50
0
50
40
SKIPPING
40
–0.2
–0.4
–0.6
–0.8
FORCED
FORCED
CONTINUOUS
30
20
10
0
30
CONTINUOUS
20
V
V
= 3.3V
V
IN
V
OUT
= 5V
IN
OUT
10
0
= 1.2V
= 1.2V
3.5
4.0
(V)
4.5
5.0
2.5
3.0
5.5
1
100
LOAD CURRENT (mA)
1000
1
100
LOAD CURRENT (mA)
1000
10
10
V
IN
3676 G07
3676 G08
3676 G09
Step-Down Switching Regulators 3
and 4 Efficiency vs IOUT
Buck RDS(ON) vs Temperature
Buck RDS(ON) vs VIN
200
180
160
140
120
100
80
100
90
250
200
150
100
50
V
= 3.3V
IN
PULSE-SKIPPING MODE
BUCK 1, 2 PMOS
80
70
60
V
= 2.5V
OUT
BUCK 1, 2 PMOS
V
= 1.2V
OUT
BUCK 3, 4 PMOS
BUCK 1, 2 NMOS
BUCK 3, 4 PMOS
BUCK 1, 2 NMOS
50
40
BUCK 3, 4 NMOS
60
30
20
10
0
BUCK 3, 4 NMOS
40
20
0
0
2.5
3.5
4.5
5.5
1
100
10
LOAD CURRENT (mA)
1000
50
TEMPERATURE (°C)
–50
0
100
150
V
(V)
IN
3676 G12
3676 G10
3676 G11
Step-Down Switching Regulator
Current Limit vs Temperature
LTC3676-1 VDDQIN, VTTR and
VTT Start-Up
Step-Down Switching Regulator
Load Step
4.5
4.0
PGOOD
5V/DIV
BUCK 3, 4
V
= 1.2V
OUT
VDDQIN
1V/DIV
100mV/DIV
500mA/DIV
3.5
3.0
I
= 0.5A TO 1.5A
LOAD
VTTR
1V/DIV
BUCK 1, 2
VTT (BUCK1)
1V/DIV
2.5
2.0
1.5
3676 G14
3676 G15
400µs/DIV
C
OUT
= 44µF
10µs/DIV
–50
0
50
100
150
TEMPERATURE (°C)
3676 G13
3676ff
9
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
Typical perForMance characTerisTics
LDO1 Dropout Voltage
LDO1 Short-Circuit Current
vs Temperature
vs Temperature
LTC3676-1 VTT Load Step
400
350
300
250
200
150
100
50
80
75
70
65
60
55
50
45
40
I
= 25mA
LTC3676-1
LDO1
V
= 0.75V
TT
V
V
= 1.8V
= 3.3V
100mV/DIV
1A/DIV
LDO1
LDO1
I
= –1.2A TO 1.2A
LOAD
3676 G16
C
= 88µF
40µs/DIV
OUT
0
50
TEMPERATURE (°C)
–55
0
100
150
50
–55
0
100
150
TEMPERATURE (°C)
3676 G17
3676 G18
LDO2 to LDO4 Dropout Voltage
vs Temperature
LDO1 Load Step Response
450
400
350
300
250
200
150
100
50
I
= 200mA
LDO
V
= 1.2V
1.2V
LDO
V
LDO1
50mV/DIV
V
V
= 1.8V
= 3.3V
20mA
LDO
LDO
I
LDO1
10mA/DIV
1mA
3676 G19
40µs/DIV
0
50
TEMPERATURE (°C)
–50
0
100
150
3676 G20
LDO2 to LDO4 Short-Circuit
Current vs Temperature
LDO2 to LDO4 Load Step Response
800
750
700
650
600
550
500
450
400
350
300
V
= 1.8V
LDO
50mV/DIV
I
= 220mA
LOAD
100mA/DIV
10mA
3676 G22
10µs/DIV
–50
0
50
100
150
TEMPERATURE (°C)
3676 G21
3676ff
10
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
(QFN/LQFP)
pin FuncTions
FB_L2 (Pin 1/Pin 2): Feedback Input for LDO2. Set full-
scale output voltage using a resistor divider connected
from LDO2 to this pin to ground.
SW4 (Pin 11/Pin 14): Switch Pin for Step-Down Switch-
ing Regulator 4. Connect one side of step-down switching
regulator 4 inductor to this pin.
2
V
(Pin 2/Pin 3): Power Input for LDO2. This pin
DV (Pin 12/Pin 15): Supply Voltage for I C Serial Port.
IN_L2
DD
2
should be bypassed to ground with a 1μF or greater
This pin sets the logic reference level of SCL and SDA I C
2
ceramic capacitor.Voltage on V should not exceed
voltage on V pin.
pins. DV resets I C registers to power-on state when
IN_L2
DD
driven to <1V. SCL and SDA logic levels are scaled to
IN
DV . Connect a 0.1µF decoupling capacitor from this
DD
LDO2 (Pin 3/Pin 4): Output Voltage of LDO2. Nominal
output voltage is set with a resistor feedback divider that
servos to a fixed 72ꢀmV reference. This pin must be by-
passed to ground with a 1µF or greater ceramic capacitor.
pin to ground.
2
SDA (Pin 13/Pin 16): Data Pin for the I C Serial Port. The
I C logic levels are scaled with respect to DV .
2
DD
2
LDO3 (Pin 4/Pin 5): Output Voltage of LDO3. Nominal
output voltage is a fixed 1.8V. This pin must be bypassed
to ground with a 1µF or greater ceramic capacitor.
SCL (Pin 14/Pin 17): Clock Pin for the I C Serial Port. The
2
I C logic levels are scaled with respect to DV .
DD
PV (Pin15/Pin18):PowerInputforStep-DownSwitch-
IN4
V
(Pin 5/Pin 6): Power Input for LDO3. This pin
ing Regulator 4. Tie this pin to V supply. This pin should
IN_L3
IN
should be bypassed to ground with a 1µF or greater
be bypassed to ground with a 10μF or greater ceramic
ceramic capacitor.Voltage on V should not exceed
voltage on V pin.
capacitor.
IN_L3
IN
PV (Pin16/Pin19):PowerInputforStep-DownSwitch-
IN3
LDO4 (Pin 6/Pin 7): Output Voltage of LDO4. Nominal
output voltage is set with a resistor feedback divider that
servos to a fixed 72ꢀmV reference. This pin must be by-
passed to ground with a 1µF or greater ceramic capacitor.
ing Regulator 3. Tie this pin to the V supply. This pin
IN
should be bypassed to ground with a 10μF or greater
ceramic capacitor.
EN_B4 (Pin 17/Pin 20): Enable Step-Down Switching
Regulator4.Activehighinputenablesstep-downswitching
regulator 4. A weak pull-down pulls EN_B4 low when left
floating.
V
(Pin 7/Pin 8): Power Input for LDO4. This pin
IN_L4
should be bypassed to ground with a 1μF or greater
ceramic capacitor.Voltage on V should not exceed
voltage on V pin.
IN_L4
IN
EN_B3 (Pin 18//Pin 21): Enable Step-Down Switching
Regulator3.Activehighinputenablesstep-downswitching
regulator 3. A weak pull-down pulls EN_B3 low when left
floating.
FB_L4 (Pin 8/Pin 9): Feedback Input for LTC3676 LDO4.
Set full-scale output voltage using a resistor divider con-
nected from LDO4 to this pin to ground.
VDDQIN (Pin 8/Pin 9): V Sense Input for LTC3676-1.
VSTB (Pin 19/Pin 22): Voltage Standby. When VSTB is
low, the DAC registers are selected by command register
bit DVBxA[ꢀ]. When VSTB is high, the DAC registers are
forced to DVBxB registers. Tie VSTB to ground if unused.
DD
Tie DDR memory V supply to this pin.
DD
EN_L4 (Pin 9/Pin 10): Enable LDO4 Input for LTC3676.
Active high enables LDO4. A weak pull-down pulls EN_L4
low when left floating.
SW3 (Pin 20/Pin 23): Switch Pin for Step-Down Switch-
ing Regulator 3. Connect one side of step-down switching
regulator 3 inductor to this pin.
VTTR (Pin9/Pin10):DDRV OutputPinforLTC3676-1.
REF
Buffered reference equal to one-half VDDQIN voltage on
Pin 8.
PWR_ON(Pin21/Pin26):ExternalPowerOn.Handshaking
pin to acknowledge successful power-on sequence.
PWR_ON must be driven high within five seconds of
WAKE going high to keep power on. PWR_ON can be
EN_L3 (Pin 10/Pin 11): Enable LDO3 Input. Active high
enables LDO3. A weak pull-down pulls EN_L3 low when
left floating.
3676ff
11
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
pin FuncTions
used to activate the WAKE output by driving high. Drive
low to shut down WAKE.
IRQ(Pin32/Pin39):InterruptRequestOutput.Open-drain
driver is pulled low for power good, undervoltage, and
overtemperature warning and fault conditions. Clear IRQ
FB_B3 (Pin 22/Pin 27): Feedback Input for Step-Down
Switching Regulator 3. Set full-scale output voltage using
resistor divider connected from the output of step-down
switching regulator 3 to this pin to ground.
2
by writing to the I C CLIRQ command register.
WAKE (Pin 33/Pin 40): System Wake Up. Open-drain
driver output releases high when signaled by pushbutton
activation or PWR_ON input. It may be used to initiate
a pin-strapped power-up sequence by connecting to a
regulator enable pin.
FB_B4 (Pin 23/Pin 28): Feedback Input for Step-Down
Switching Regulator 4. Set full-scale output voltage using
resistor divider connected from the output of step-down
switching regulator 4 to this pin to ground.
EN_B2 (Pin 34/Pin 41): Enable Step-Down Switching
Regulator 2. Active high input enables step-down switching
regulator 2. Aweak pull-down pulls EN_B2 low when left floating.
FB_B1 (Pin 24/Pin 29): Feedback Input for Step-Down
Switching Regulator 1. Set full-scale output voltage using
resistor divider connected from the output of step-down
switching regulator 1 to this pin to ground.
PV (Pin35/Pin42):PowerInputforStep-DownSwitch-
IN2
ing Regulator 2. Tie this pin to V supply. This pin should
IN
be bypassed to ground with a 10μF or greater ceramic
FB_B2 (Pin 25/Pin 30): Feedback Input for Step-Down
Switching Regulator 2. Set full-scale output voltage using
resistor divider connected from the output of step-down
switching regulator 2 to this pin to ground.
capacitor.
PV (Pin 36/Pin 43): Power Input for Step-Down Switching
IN1
Regulator1.TiethispintoV supply.Thispinshouldbebypassed
IN
to ground with a 10μF or greater ceramic capacitor.
FB_L1 (Pin 26/Pin 31): Feedback Input for LDO1. Set
output voltage using a resistor divider connected from
LDO1 to this pin to ground.
EN_B1 (Pin 37/Pin 44): Enable Step-Down Switching
Regulator 1. Active high enables step-down switching
regulator1. TheLTC3676-1EN_B1pinenablesbothVTTR
output and switching regulator 1. A week pull-down pulls
EN_B1 low when left floating.
V (Pin 27/Pin 32): Supply Voltage Input. This pin should
IN
be bypassed to ground with a 1μF or greater ceramic
capacitor. All switching regulator PV supplies should
IN
be tied to V .
RSTO (Pin 38/Pin 45): Reset Output. Open-drain output
pulls low when the always-on regulator LDO1 is below
regulation or during a hard reset initiated by a pushbutton
input or command registers.
IN
LDO1 (Pin 28/Pin 33): Always On LDO1 Output. This pin
providesanalways-onsupplyvoltageusefulforlightloads
such as a watchdog microprocessor or a real time clock.
Connect a 1μF capacitor from LDO1 to ground.
PGOOD (Pin 39/Pin 46): Power Good Output. Open-drain
output pulls low when any enabled regulator falls below
power good threshold or during dynamic voltage slew
unless disabled in command register. Pulls low when all
regulators are disabled.
ON (Pin 29/Pin 34): Pushbutton Input. A weak internal
pull-up forces ON high when left floating. A normally open
pushbutton is connected from ON to ground forcing a low
state when pushed.
SW1 (Pin 40/Pin 47): Switch Pin for Step-Down Switch-
ing Regulator 1. Connect one side of step-down switching
regulator 1 inductor to this pin.
EN_L2 (Pin 30/Pin 35): Enable LDO2 Input. Active high
enables LDO2. A weak pull-down pulls EN_L2 low when
left floating.
GND (Exposed Pad Pin 41/Pin 49): Ground. The exposed
pad must be connected to a continuous ground plane of
the printed circuit board by multiple interconnect vias
directly under the LTC3676 to maximize electrical and
SW2 (Pin 31/Pin 38): Switch Pin for Step-Down Switch-
ing Regulator 2. Connect one side of step-down switching
regulator 2 inductor to this pin.
thermal conduction.
3676ff
12
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
block DiagraM—lTc3676
PV
IN1
V
LDO1
EN
IN
BUCK1
BUCK2
BUCK3
BUCK4
725mV
DEFAULT = 725mV
V
REF
DAC
DAC
DAC
DAC
SW1
RANGE = 800mV
TO 412.5mV
LDO1
FB_L1
EN
OK
FB_B1
ON
WAKE
PV
IN2
DEFAULT = 725mV
V
PUSHBUTTON
ON/OFF
CONTROL
REF
SW2
RANGE = 800mV
TO 412.5mV
PWR_ON
EN
OK
RSTO
FB_B2
PV
IN3
EN_B1
EN_B2
EN_B3
EN_B4
EN_L2
EN_L3
EN_L4
DEFAULT = 725mV
V
REF
SW3
RANGE = 800mV
TO 412.5mV
PRECISION ENABLE
THRESHOLD AND
SEQUENCE DELAY
EN
OK
FB_B3
7
7
7
PV
IN4
DEFAULT = 725mV
V
REF
DV
DD
SW4
RANGE = 800mV
TO 412.5mV
2
SDA
SCL
I C COMMAND
REGISTERS
EN
OK
FB_B4
IRQ
V
IN_L2
LDO2
LDO3
V
REF
FAULT DETECTION
725mV
UNDER VOLTAGE
OVER TEMPERATURE
PGOOD
LDO2
EN
OK
FB_L2
VSEL
VA 4x5
VB 4x5
V
IN_L3
V
REF
LDO3
5
5
5
5
EN
OK
VSTB
DYNAMIC VOLTAGE
SCALING CONTROL
V
IN_L4
LDO4
V
REF
LDO4
EN
OK
FB_L4
GND
(EXPOSED PAD)
3676 BD
3676ff
13
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
block DiagraM—lTc3676-1
PV
IN1
V
LDO1
EN
IN
BUCK1
BUCK2
BUCK3
BUCK4
725mV
V
REF
SW1
LDO1
FB_L1
EN
OK
FB_B1
ON
WAKE
PV
IN2
DEFAULT = 725mV
V
PUSHBUTTON
ON/OFF
CONTROL
REF
DAC
DAC
DAC
SW2
RANGE = 800mV
TO 412.5mV
PWR_ON
EN
OK
RSTO
FB_B2
PV
IN3
EN_B1
EN_B2
EN_B3
EN_B4
EN_L2
EN_L3
DEFAULT = 725mV
V
REF
SW3
RANGE = 800mV
TO 412.5mV
PRECISION ENABLE
THRESHOLD AND
SEQUENCE DELAY
EN
OK
FB_B3
7
7
PV
IN4
DEFAULT = 725mV
V
REF
VTTR
SW4
RANGE = 800mV
TO 412.5mV
VDDQIN
EN
OK
VDDQIN/2
FB_B4
V
IN_L2
LDO2
LDO3
V
REF
DV
DD
7
725mV
2
SDA
SCL
I C COMMAND
LDO2
REGISTERS
EN
OK
FB_L2
IRQ
V
IN_L3
V
REF
FAULT DETECTION
UNDER VOLTAGE
OVER TEMPERATURE
LDO3
PGOOD
EN
OK
VSEL
VA 4x5
VB 4x5
V
IN_L4
LDO4
V
REF
5
5
5
VSTB
DYNAMIC VOLTAGE
SCALING CONTROL
LDO4
EN
OK
GND
(EXPOSED PAD)
36761 BD
3676ff
14
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
operaTion
INTRODUCTION
PVINB1
VTTR
VDDQIN
The LTC3676 is a complete power management solution
for portable microprocessors and peripheral devices. It
generates a total of eight voltage rails for supplying power
to the processor core, DDR memory, I/O, always-on real-
time clock and HDD functions. Supplying the voltage rails
are an always-on low quiescent current 2ꢀmA LDO, two
2.ꢀA step-down regulators, two 1.ꢀA step-down regula-
tors,andthree300mAlowdropoutregulators.Supporting
the multiple regulators is a highly configurable power-on
sequencingcapability,dynamicvoltagescalingDACoutput
voltage control, a pushbutton interface controller, control
BUCK1
SW1
VDDQIN/2
R1
VDDQIN/2
DDR
REF
C
FB
C
OUT
ERROR
AMP
FB_B1
3676 F01
Figure 1. VTT Buck Regulator and VTTR Reference Block Diagram
Always-On 25mA Low Dropout Regulator
TheLTC3676includesalowquiescentcurrentlowdropout
regulatorthatremainspoweredwheneveravalidsupplyis
present on V . The always-on LDO1 remains active until
2
IN
via an I C interface, and extensive status and interrupt
V
drops below 2.0V (typical). This is below the 2.ꢀV
IN
outputs.
undervoltagethresholdineffectfortherestoftheLTC3676
circuits. The always-on LDO is used to provide power to a
standbymicrocontroller,real-timeclock,orotherkeep-alive
circuits. The LDO is guaranteed to support a 2ꢀmA load. A
1µFlowimpedanceceramicbypasscapacitorfromLDO1to
GND is required for compensation. A power good monitor
pullsRSTOlowwheneverLDO1is8%belowitsregulation
target. LDO1 has current limit circuitry to protect from
short circuit and overloading. The output voltage of LDO1
is set with a resistor divider connected from LDO1 output
pin to the feedback pin FB_L1, as shown in Figure 2. The
output voltage is calculated using the following formula:
The LTC3676-1 supports DDR memory applications by
replacing the LTC3676 LDO4 feedback and enable pins
with VDDQIN and VTTR pins. The DDR V supply is
DD
connected to the LTC3676-1 VDDQIN pin. A buffered DDR
termination voltage equal to one half the voltage on VD-
DQIN is output on VTTR. The VTTR voltage is connected
internally on the LTC3676-1 to the reference side of the
Buck1 error amplifier. When Buck1 is configured with a
gain of one, its output can be used as at DDR termination
supply. Table 1 shows the functional differences between
the LTC3676 and LTC3676-1.
Table 1. Functional Differences LTC3676 vs LTC3676-1
R1
R2
⎛
⎝
⎞
VLDO1= 725• 1+
mV
( )
⎜
⎟
⎠
LTC3676
LTC3676-1
Buck1 Default
Frequency
2.2ꢀMHz
1.12ꢀMHz
300mA Low Dropout Regulators
Buck1 Default
Mode
Pulse-Skipping
Forced Continuous
Three LDO regulators on the LTC3676 will each deliver
up to 300mA output. Each LDO regulator has separate
input supply to help manage power loss in the LDO output
Buck1 Output
External Resistor Divider. External Unity Gain.
Slewing DAC Reference
VTTR Reference
2
2
LDO4 Enable
LDO4 Output
EN_L4 Pin or I C
I C
2
devices.TheLDOregulatorsareenabledbypininputorI C
2
External Resistor Divider. I C Select 1 of 4 Fixed
command register. When disabled, the regulator outputs
are pulled to ground through a 62ꢀΩ resistor. A low ESR
1µF ceramic capacitor should be tied from the LDO output
to ground. The 300mA LDO regulators have current limit
72ꢀmV Reference
External Resistor Divider
Enable LDO4.
—
Outputs
FB_L4 Pin
EN_L4 Pin
VDDQIN Pin
—
—
Connect to DDR Memory
Supply
control circuits. The LDO input voltages, V
, V
,
IN_L2 IN_L3
VTTR Pin
—
Buffered Output Equals
One-Half VDDQIN
and V
must be at potential of V or less.
IN_L4
IN
2
The LDO regulator I C command register controls are
shown in Table 2 and Table 3.
2
I C Device
Write = 0x78
Read = 0x79
Write = 0x7A
Read = 0x7B
Address
3676ff
15
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
operaTion
LTC3676 Resistor Programmable LDO2 and LDO4
output is 1.2V with selectable outputs of 2.ꢀV, 2.8V, and
3.0V. LDO4isenabledonlythroughthecommandregister
bit LDOB[2].
LDO2andLDO4outputvoltagesareprogrammedbyresis-
tor dividers tied from the LDO output pin to the feedback
pin as shown in Figure 2. The output voltage is calculated
using the following formula:
LDO4 Command Register Controls
Table 3. LDO4 Control Command Register Settings
COMMAND
REGISTER[BIT] VALUE SETTING
R1
R2
⎛
⎞
VLDO = 725• 1+
mV
(
)
⎜
⎟
⎠
⎝
LDOB[0]
LDOB[1]
0* Do Not Keep Alive LDO4 in Standby
Keep Alive LDO4 in Standby
1
V
IN
0* Enable LDO4 at Any Output Voltage
Enable LDO4 Only if Output Voltage is <300mV
0.725V
+
–
1
LDO
FB
LDOB[2]
(LTC3676)
0* LDO4 Disabled if EN_L4 is Low
1 LDO4 Enabled
R1
1µF
LDOB[2]
(LTC3676-1)
0* LDO4 Disabled
1 LDO4 Enabled
R2
LDOB[4:3]
(LTC3676-1)
00* LDO4 Output = 1.2V
3676 F02
LDOB[4:3]
01
10
11
LDO4 Output = 2.ꢀV
LDO4 Output = 2.8V
LDO4 Output = 3V
Figure 2. LDO1, LDO2 and LDO4 Application Circuit
(LTC3676-1)
LDOB[4:3]
(LTC3676-1)
Fixed Output LDO3
LDOB[4:3]
(LTC3676-1)
Regulator LDO3 has a fixed voltage output of 1.8V.
*denotes default power-on value.
Table 2. LDO2 and LDO3 Control Command Register Settings
COMMAND
REGISTER[BIT] VALUE SETTING
STEP-DOWN SWITCHING REGULATORS
LDOA[0]
LDOA[1]
LDOA[2]
LDOA[3]
LDOA[4]
LDOA[ꢀ]
0* Do Not Keep Alive LDO2 in Standby
Keep Alive LDO2 in Standby
The LTC3676 contains four buck regulators. Two of the
buck regulators are capable of delivering up to 2.ꢀA load
current and the other two can deliver up to 1.ꢀA each. The
regulatorshaveforwardandreversecurrentlimiting, soft-
start, and switch slew rate control for lower radiated EMI.
1
0* Enable LDO2 at Any Output Voltage
Enable LDO2 Only if Output Voltage is <300mV
1
0* LDO2 Disabled if EN_L2 is Low
LDO2 Enable
1
0* Do Not Keep Alive LDO3 in Standby
Keep Alive LDO3 in Standby
The LTC3676 buck regulators are capable of 100% duty
cycle,ordropout,regulation.Whenindropouttheregulator
1
0* Enable LDO3 at Any Output Voltage
Enable LDO3 0nly if Output Voltage is <300mV
1
outputvoltageisequaltoPV minustheloadcurrenttimes
IN
0* LDO3 Disabled if EN_L3 is Low
LDO3 Enabled
R
oftheconvertersPMOSdeviceandinductorDCR.
DS(ON)
1
2
Each buck regulator is enabled using its enable pin or I C
command register control. Operating modes, start-up op-
tion, referencevoltage, andswitchslewratearecontrolled
*denotes default power-on value.
LDO4 Operation LTC3676-1
2
using the I C port.
LDO4 on the LTC3676-1 has neither enable nor feedback
pins. There are four LDO4 output voltages selectable by
command register bits LDOB[4:3]. The power-on default
2
The buck converter I C command register controls are
shown in Table 4, Table ꢀ, Table 6, and Table 7.
3676ff
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For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
operaTion
Operating Modes
voltage of 72ꢀmV. Typical values for R1 are in the range
of 40k to 1M. Capacitor C cancels the pole created by
FB
The buck regulators can operate in either pulse-skipping,
Burst Mode operation, or forced continuous mode. In
pulse-skipping setting the regulator will skip pulses at
light loads but will operate at constant frequency. In Burst
Mode setting the regulator operates in Burst Mode opera-
tion at light loads and in constant frequency PWM mode
at higher load. In forced continuous setting the inductor
current is allowed to be less than zero over the full range
of duty cycles. In forced continuous operation the buck
regulator has the ability to sink output current. Because
the regulator is switching every cycle regardless of output
load, forced continuous mode results in the least output
voltage ripple at light load.
the feedback resistors and the input capacitance on the
FB pin and helps to improve load step transient response.
A value of 10pF is recommended.
Inductor Selection
The choice of step-down switching regulator inductor
influences the efficiency and output voltage ripple of the
converter. A larger inductor improves efficiency since the
peakcurrentisclosertotheaverageoutputcurrent.Larger
inductors generally have higher series resistance that
counterstheefficiencyadvantageofreducedpeakcurrent.
Inductorripplecurrentisafunctionofswitchingfrequency,
inductance, V , and V
as shown in this equation:
IN
OUT
Output Voltage Programming
⎛
⎞
1
f•L
VOUT
Eachofthestep-downconvertersusesadynamicallyslew-
ing DAC for its reference. The output voltage of the DAC
ΔIL =
•VOUT • 1–
⎜
⎟
V
⎝
⎠
IN
2
referenceisselectableusingaꢀ-bitI Ccommandregister.
A good starting design point is to use an inductor that
gives ripple equal to 30% output current. Select an induc-
tor with a DC current rating at least 1.ꢀ times larger than
the maximum load current to ensure the inductor does
not saturate.
The output voltage is set by using a resistor divider con-
nected from the step-down switching regulator output to
its feedback pin as shown in Figure 3. The output voltage
is calculated using the following formula:
R1
R2
⎛
⎝
⎞
VOUT = 1+
• DVBx •12.5+412.5 mV
( ) (
)
⎜
⎟
⎠
Input and Output Capacitor Selection
Low ESR ceramic capacitors should be used at both the
output and input supply of the switching regulators. Only
XꢀR or X7R ceramic capacitors should be used since they
have better temperature and voltage stability than other
ceramic types.
DVBx is the decimal value of the ꢀ-bit binary number in
2
the I C command registers. The default DAC input code is
11001 (2ꢀ in decimal) which corresponds to a reference
PV
IN
Operating Frequency
TheswitchingfrequencyofeachoftheLTC3676switching
EN
SW
2
PWM
CONTROL
regulators may be set using the I C command registers.
2
C
OUT
MODE
Thedefaultswitchingfrequencyis2.2ꢀMHzandtheselect-
able frequency is 1.12ꢀMHz. Operation at lower frequency
improves efficiency by reducing internal gate charge and
switching losses at the expense of a larger inductor.
C
FB
R1
R2
FB
5
The lowest duty cycle of the step-down converter is de-
termined by minimum on-time. Minimum on-time is the
shortest time duration that the converter can turn its top
PMOS on and off again. The time is the sum of gate charge
3676ff
DAC
DEFAULT
725mV
3676 F03
Figure 3. Step-Down Switching Regulator Application Circuit
17
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
operaTion
time plus internal delays of the peak current sense and
PWM control. If the converters duty cycle will be 20% or
less at 2.2ꢀMHz it is recommended to use the 1.12ꢀMHz
setting to avoid minimum duty cycle. If the duty cycle falls
below the minimum on-time of the converter, the output
voltage ripple will increase as the converter skips cycles.
Table 4. Buck1 Control Command Register
COMMAND
REGISTER[BIT]
VALUE SETTING
BUCK1[0]
0*
1
Switch Slew Rate Normal
Switch Slew Rate Fast
BUCK1[1]
0*
1
Do Not Keep Enabled in Device Standby
Keep Enabled in Device Standby
The default setting for the LTC3676-1 Buck1 switching
frequency is 1.12ꢀMHz to ensure minimum on time ef-
fects are avoided at DDR termination reference voltages.
BUCK1[2]
(LTC3676)
0*
1
Switching Frequency 2.2ꢀMHz
Switching Frequency 1.12ꢀMHz
BUCK1[2]
(LTC3676-1)
0*
1
Switching Frequency 1.12ꢀMHz
Switching Frequency 2.2ꢀMHz
BUCK1[3]
BUCK1[4]
BUCK1[6:ꢀ]
0*
1
Clock Phase 1
Clock Phase 2
Phase Selection
0*
1
Enable at Any Output Voltage
Enable Only if Output Voltage Is <300mV
To reduce the cycle by cycle peak current drawn by the
switching regulators, the clock phase at which each of the
LTC3676 buck’s PMOS switch turns on can be set using
00* Pulse-Skipping Mode
01
10
Burst Mode Operation
Forced Continuous Mode
2
I C command register settings.
BUCK1[7]
0*
1
Buck1 Disabled if EN_B1 Pin Is Low
Buck1 Enabled
φ1
φ2
φ1
φ2
2.25MHz
*denotes default power on-value.
Table 5. Buck2 Control Command Register
COMMAND
REGISTER[BIT]
φ1
1.125MHz
3676 F04
VALUE SETTING
BUCK2[0]
0*
1
Switch Slew Rate Normal
Switch Slew Rate Fast
Figure 4. Phase Settings Full- and Half-Speed Buck Clock
BUCK2[1]
BUCK2[2]
BUCK2[3]
BUCK2[4]
BUCK2[6:ꢀ]
0*
1
Do Not Keep Enabled in Device Standby
Keep Enabled in Device Standby
Switch Slew Rate Control
0*
1
Switching Frequency 2.2ꢀMHz
Switching Frequency 1.12ꢀMHz
To helpreduceEMItheswitchrisetimeofeachbuckregula-
tor is slew limited by default. A faster setting is selectable
0*
1
Clock Phase 1
Clock Phase 2
2
using the I C buck command registers. The faster setting
will improve efficiency if limited edge rate is not required.
0*
1
Enable at Any Output Voltage
Enable Only if Output Voltage Is <300mV
Soft-Start
00* Pulse-Skipping Mode
01
10
Burst Mode Operation
Forced Continuous Mode
To reduce inrush current at start-up each buck regulator
soft starts when enabled. When enabled the internal ref-
erence voltage is ramped from ground to the level of the
slewing DAC output at a rate of 0.8V/ms. During soft-start
the converter is forced to pulse-skipping mode regardless
of command register mode settings.
BUCK2[7]
0*
1
Buck2 Disabled if EN_B2 Pin Is Low
Buck2 Enabled
*denotes default power-on value.
3676ff
18
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LTC3676/LTC3676-1
operaTion
Dynamic Voltage Scaling
Table 6. Buck3 Control Command Register
COMMAND
Table 8 shows the command registers used to control
dynamicvoltagescaling(DVS)ofthestep-downswitching
regulators input reference DAC. The command register
bits DVB1A[4:0] and DVB1B[4:0] store two ꢀ-bit inputs
to the DAC reference for Buck1. The bit stored in com-
mand register DVB1A[ꢀ] selects either the ꢀ bits stored
in DVB1A[4:0] or DVB1B[4:0] DAC as input to the DAC
reference. Buck2, Buck3, and Buck4 operate the same
way using their assigned “A” and “B” command registers
shown in Table 8. When the DAC detects a change in its
input code it automatically slews to the new value at a rate
REGISTER[BIT]
VALUE SETTING
BUCK3[0]
0*
1
Switch Slew Rate Normal
Switch Slew Rate Fast
BUCK3[1]
BUCK3[2]
BUCK3[3]
BUCK3[4]
BUCK3[6:ꢀ]
0*
1
Do Not Keep Enabled in Device Standby
Keep Enabled in Device Standby
0*
1
Switching Frequency 2.2ꢀMHz
Switching Frequency 1.12ꢀMHz
0*
1
Clock Phase 1
Clock Phase 2
0*
1
Enable at Any Output Voltage
Enable Only if Output Voltage Is <300mV
00* Pulse-Skipping Mode
01
10
2
of 3.ꢀmV/µs. A DVS can be initiated using the I C select
bit or using the VSTB pin.
Burst Mode Operation
Forced Continuous Mode
BUCK3[7]
0*
1
Buck3 Disabled if EN_B3 Pin Is Low
Buck3 Enabled
The LTC3676 VSTB pin HIGH selects the ꢀ bits stored in
all four DVBx “B” registers. This facilitates a simultaneous
DAC slew between the values in the “A” registers and the
values in the “B” registers. The VSTB pin is logically ORed
*denotes default power-on value.
Table 7. Buck4 Control Command Register
COMMAND
2
2
REGISTER[BIT]
VALUE SETTING
with the I C command register bit. If the I C select bit is
already set high, the “B” registers are already selected and
VSTB will have no effect. If no change in output is desired
using the VSTB pin, set the value in the “A” register equal
to the value in the “B”.
BUCK4[0]
0*
1
Switch Slew Rate Normal
Switch Slew Rate Fast
BUCK4[1]
BUCK4[2]
BUCK4[3]
BUCK4[4]
BUCK4[6:ꢀ]
0*
1
Do Not Keep Enabled in Device Standby
Keep Enabled in Device Standby
0*
1
Switching Frequency 2.2ꢀMHz
Switching Frequency 1.12ꢀMHz
Command register bits DVB1B[ꢀ], DVB2B[ꢀ], DVB3B[ꢀ],
and DVB4B[ꢀ] control whether the PGOOD status pin is
pulled low while the DAC output is slewing. The default
command register setting is to pull PGOOD pin low dur-
ing DAC slew. During the DVS, PGOOD will be held low
for just the duration of the DVS and the PGSTAT register
is not affected.
0*
1
Clock Phase 1
Clock Phase 2
0*
1
Enable at Any Output Voltage
Enable Only if Output Voltage Is <300mV
00* Pulse-Skipping Mode
01
10
Burst Mode Operation
Forced Continuous Mode
BUCK4[7]
0*
1
Buck4 Disabled if EN_B4 Pin Is Low
Buck4 Enabled
*denotes default power-on value.
V
OUT
200mV/DIV
SLEWING DAC REFERENCE OPERATION
Each LTC3676 step-down switching regulators error am-
plifier reference voltage is supplied by a ꢀ-bit DAC with
an output voltage range of 412.ꢀmV to 800mV in 12.ꢀmV
PGOOD
5V/DIV
VSTB
5V/DIV
2
steps. One of two ꢀ-bit codes stored in I C command
registers is selected for input to the DAC. When a change
in code is detected by the DAC control circuits, the output
of the DAC is slewed at 3.ꢀmV/µs to the new value.
3676 F05
100µs/DIV
Figure 5. Dynamic Voltage Scaling
3676ff
19
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
operaTion
Table 8. Buck1, Buck2, Buck3, and Buck4 Slewing DAC Control
Command Registers
V
IN
HIGH
COMMAND
ENABLE
INHIBITED AND
WAKE LOW
REGISTER[BIT]
DVB1A[4:0]
DVB1A[ꢀ]
VALUE SETTING
POR/HRST
bbbbb Buck1 Reference DAC Input A
0*
1
Select DVB1A[4:0]
Select DVB1B[4:0]
ON 400ms
OR PWR_ON
DVB1B[4:0]
DVB1B[ꢀ]
bbbbb Buck1 Reference DAC Input B
ENABLE
ALLOWED AND
WAKE HIGH
0*
1
Pull PGOOD Low Slewing Buck1
Do Not Pull PGOOD Slewing Buck1
5 SEC
PWR_ON
TIMER
DVB2A[4:0]
DVB2A[ꢀ]
bbbbb Buck2 Reference DAC Input A
0*
1
Select DVB2A[4:0]
Select DVB2B[4:0]
DVB2B[4:0]
DVB2B[ꢀ]
bbbbb Buck2 Reference DAC Input B
0*
1
Pull PGOOD Low Slewing Buck2
Do Not Pull PGOOD Slewing Buck2
ON 400ms
OR PWR_ON
STANDBY
ON
ON 10 SEC
DVB3A[4:0]
DVB3A[ꢀ]
bbbbb Buck3 Reference DAC Input A
2
OR I C HRST
0*
1
Select DVB3A[4:0]
Select DVB3B[4:0]
ON 10 SEC
2
OR I C HRST
PWR_ON
OR FAULT
DVB3B[4:0]
DVB3B[ꢀ]
bbbbb Buck3 Reference DAC Input B
0*
1
Pull PGOOD Low Slewing Buck3
Do Not Pull PGOOD Slewing Buck3
1 SEC OFF
TIMER
STANDBY
1 SEC OFF
TIMER
HRST
3676 F06
ON 10 SEC
DVB4A[4:0]
DVB4A[ꢀ]
bbbbb Buck4 Reference DAC Input A
2
OR I C HRST
0*
1
Select DVB4A[4:0]
Select DVB4B[4:0]
DVB4B[4:0]
DVB4B[ꢀ]
bbbbb Buck4 Reference DAC Input B
Figure 6. LTC3676 Operating Mode State Diagram
0*
1
Pull PGOOD Low Slewing Buck4
Do Not Pull PGOOD Slewing Buck4
Power Up Using Pushbutton
*denotes default power-on value.
When the ON pin is held low for 400ms the WAKE pin is
pulledhigh,enablepinsarerecognized,andthefivesecond
PWR_ON timer is started. If in the ON state and PWR_ON
is low or a fault is detected, then WAKE is brought low and
after a 1 second power-down time, the STANDBY state
is entered. In STANDBY, the enable bits in the command
registers are cleared and enable pins are ignored. Table 9
shows the control of command registers, enables, and
WAKE at each state.
PUSHBUTTON OPERATION
Operating Mode State Diagram
Figure 6 shows the state diagram of the LTC3676 enable
and sequence controller. First application of power to
V
IN
pin brings the controller to the power-on reset/hard
2
reset (POR/HRST) state. In this state the I C command
registers have been set to their default values, only LDO1
is operating, and the device is waiting for pushbutton or
PWR_ON inputs. Regulator enable pins and command
register enable bits are ignored in POR/HRST state. In the
The ꢀ second power-on state is intended for the system to
detectthatpowerrailsarecorrectandeitherdrivePWR_ON
pin high or set command register bit CNTRL[7] high to
keep the rails active. If there were a system level problem
POR/HRST state V draws typically 12µA.
IN
3676ff
20
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LTC3676/LTC3676-1
operaTion
status register bit, the controller can detect a pushbutton
request. If a power-down into standby state is desired
then the controller should drive PWR_ON low and set
command register bit CNTRL[7] low.
ON (PB)
400ms
WAKE
<5 SEC
Button Status Indication
PWR_ON
µC/µP CONTROL
2
3676 F07
(PIN OR I C)
When a pushbutton pulls ON low for ꢀ0ms in the ON state,
IRQ is pulled low and the PB status bit in the IRQSTAT[0]
status register is set. IRQ and the IRQSTAT status bit are
active while ON is low or for a minimum of ꢀ0ms.
Figure 7. Power Up Using Pushbutton
keeping the processor from driving PWR_ON, then the
LTC3676 will pull WAKE low, shut off all regulators, and
enter the STANDBY state. The STANDBY state is also a
low power, 12µA (typical) state.
Power Up and Down with PWR_ON
The PWR_ON pin is an alternative way to power up the
LTC3676 instead of using the ON pin. When PWR_ON is
driven high or command register CNTRL[7] is set high,
WAKE is pulled HIGH and the LTC3676 passes through
the ꢀ second PWR_ON timer to the ON state. Figure 9
shows PWR_ON and WAKE timing. WAKE stays high for
a minimum of ꢀ seconds.
Table 9. Register, Enable, WAKE Control During Operating
Mode State Control
STATE
REGISTERS ENABLES
WAKE
LOW
POR/HRST DEFAULT
ꢀ SEC PWR_ON TIMER
ON
R/W
R/W
R/W
Inhibited
Allowed
Allowed
HIGH
HIGH
1 SEC OFF TIMER HRST
Set to POR Sequence Down LOW
Defaults
5 SEC
PWR_ON
(PIN OR I C)
µC/µP CONTROL
2
2
1 SEC OFF TIMER
STANDBY
I C Enable Sequence Down LOW
and SW
Mode Bits
Cleared
3ms
3ms
WAKE
3676 F09
STANDBY
R/W
Inhibited
LOW
Figure 9. Power Up and Down with PWR_ON
Power Down Using Pushbutton
When in the ON state, the system controller is responsible
for deciding what action to take when a pushbutton event
occurs. By monitoring the IRQ status pin and IRQSTAT[0]
POWER ON SEQUENCING
Enable Pin Operation
<10 SEC
The LTC3676 enable pins facilitate pin-strapping output
railstoenablepinstoup-sequencetheLTC3676regulators
in any order. Figure 10 shows an example of pin-strapped
sequence connections. The enable pins normally have a
0.8V (typical) input voltage threshold.
ON (PB)
50ms
IRQ
IRQSTAT[0]
WAKE
If any enable is driven high, the remaining enable input
thresholds switches to an accurate 400mV threshold. To
ensure separation of the sequenced rails, there is a built-
in 4ꢀ0µs delay from the enable pin threshold crossing to
the internal enable of the regulator. Figure 11 shows the
start-up timing of the example shown in Figure 10.
3ms
PWR_ON
µC/µP CONTROL
2
(PIN OR I C)
3676 F08
Figure 8. Power-Down Using Pushbutton
3676ff
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LTC3676/LTC3676-1
operaTion
bits, or the operating state of the LTC3676. A hard reset
or fault shutdown resets the keep alive bits.
LTC3676
EN_B1
EN_B2
EN_B3
EN_B4
EN_L2
EN_L3
EN_L4
ON
WAKE
SW1
SW2
SW3
SW4
LDO2
LDO3
LDO4
V
IN
POWER OFF SEQUENCING
V
B1
V
B2
V
B3
V
B4
V
L2
V
L3
V
L4
= 1.2V
= 1.8V
= 2.5V
= 1.2V
= 1.2V
= 1.8V
= 2.8V
Sequence down command registers SQD1 and SQD2
are used to set the time, relative to WAKE falling, that a
regulator is disabled either by lowering PWR_ON, or a
fault induced shutdown. Table 10 shows register settings
for SQD1 and SQD2.
PWR_ON
PWR_ON
3676 F10
Table 10.Sequence Down Control Command Register Settings
COMMAND
Figure 10. Pin-Strapped Power-On Sequence Application
REGISTER[BIT]
VALUE SETTING
SQD1[1:0]
00*
01
Disable Buck1 at Falling WAKE
WAKE
1.2V
1.8V
450µs
Disable Buck1 at Falling WAKE + 100ms
Disable Buck1 at Falling WAKE + 200ms
Disable Buck1 at Falling WAKE + 300ms
0.4V
0.4V
10
V
B1
B2
11
450µs
SQD1[3:2]
SQD1[ꢀ:4]
SQD1[7:6]
SQD2[1:0]
SQD2[3:2]
SQD2[ꢀ:4]
00*
01
10
11
Disable Buck2 at Falling WAKE
V
2.5V
1.2V
Disable Buck2 at Falling WAKE + 100ms
Disable Buck2 at Falling WAKE + 200ms
Disable Buck2 at Falling WAKE + 300ms
V
V
B3
B4
00*
01
10
11
Disable Buck3 at Falling WAKE
1.2V
1.8V
2.8V
450µs
Disable Buck3 at Falling WAKE + 100ms
Disable Buck3 at Falling WAKE + 200ms
Disable Buck3 at Falling WAKE + 300ms
V
V
L2
L3
00*
01
10
11
Disable Buck4 at Falling WAKE
Disable Buck4 at Falling WAKE + 100ms
Disable Buck4 at Falling WAKE + 200ms
Disable Buck4 at Falling WAKE + 300ms
3676 F11
V
L4
00*
01
10
11
Disable LDO2 at Falling WAKE
Figure 11. Pin-Strapped Power-On Sequence
Disable LDO2 at Falling WAKE + 100ms
Disable LDO2 at Falling WAKE + 200ms
Disable LDO2 at Falling WAKE + 300ms
Software Control Mode
00*
01
10
11
Disable LDO3 at Falling WAKE
Disable LDO3 at Falling WAKE + 100ms
Disable LDO3 at Falling WAKE + 200ms
Disable LDO3 at Falling WAKE + 300ms
Once a power-up sequence is completed, each regulator
may be enabled and disabled individually by the system
as needed for power management requirements by using
the command register bit CNTRL[ꢀ]. When CNTRL[ꢀ] is
set high the regulators ignore the state of their enable pins
00*
01
10
11
Disable LDO4 at Falling WAKE
Disable LDO4 at Falling WAKE + 100ms
Disable LDO4 at Falling WAKE + 200ms
Disable LDO3 at Falling WAKE + 300ms
2
and respond only to I C command register bit settings.
*denotes default power-on value.
The software control mode bit is reset in the one second
standby and hard reset timer states so a pin strapped
sequence begins at the next LTC3676 power on.
Figure 12 shows an example of a shutdown sequence. In
this example, the bits in command registers SQD1 and
SQD2 are set so that LDO2, LDO3, and LDO4 shut off at
the same time as WAKE. Buck2 and Buck4 shut off 100ms
after WAKE. Buck3 shuts off 200ms after wake and Buck1
shuts off 300ms after WAKE.
Keep Alive Operation
Each regulator has a dedicated command register keep
alive bit that, when set, forces a regulator to be enabled
regardless of the enable pins, command register enable
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Over Temperature
WAKE
1.2V
300ms
To prevent thermal damage the LTC3676 incorporates an
overtemperature (OT) circuit. When the die temperature
reaches 1ꢀꢀ°C the OT circuits create a FAULT condition
that forces the LTC3676 into standby. When the OT cir-
cuit detects the temperature falls below 140°C the FAULT
condition is cleared. The LTC3676 also has an OT warning
circuit that indicates the die temperature is approaching
the OT fault threshold. The OT warning threshold is user
programmable as shown in Table 12.
V
V
B1
B2
200ms
1.8V
2.5V
1.2V
100ms
V
V
B3
B4
1.2V
1.8V
2.8V
V
V
V
L2
L3
L4
Table 12. Overtemperature Warning Threshold Command
Register Settings
COMMAND
REGISTER[BIT]
VALUE OT WARNING THRESHOLD
CNTRL[1:0]
00*
01
10°C Below OT Fault
20°C Below OT Fault
30°C Below OT Fault
40°C Below OT Fault
10
11
3676 F12
*denotes default power-on value.
Figure 12. Power-Down Sequence
PGOOD Status Pin
FAULT DETECTION AND REPORTING
The PGOOD open-drain status pin is pulled low when all
regulatorsaredisabled.PGOODisreleasedwhenallenabled
regulator outputs are above 93% of programmed value.
When any enabled regulator output falls below 92% of its
programmed value for longer than ꢀ0µs the PGOOD pin is
pulled low. The ꢀ0µs transient filter on PGOOD prevents
PGOOD glitches due to transients. If the error condition
persistsforlongerthan20ms,theIRQpinispulledlowand
status register IRQSTAT bit 2 is set to indicate a persistent
PGOOD fault. The PGOOD pin is held low for the duration
of the low output condition plus 1ms. Figure 13 shows the
timing of PGOOD during enable and fault events.
The LTC3676 has fault detection circuits that monitor
for V undervoltage, die overtemperature, and regulator
IN
output undervoltage. Status of the fault detect circuits is
indicated by the IRQ and PGOOD pins and the IRQSTAT
and PGSTAT status registers.
V Undervoltage
IN
The undervoltage (UV) circuit monitors the input supply
voltage, V , and when the voltage falls below 2.4ꢀV cre-
IN
ates a FAULT condition that forces the LTC3676 into the
standby state. The LTC3676 also provides a (UV) warning
that is triggered at user programmable V voltages as
IN
shown in Table 11.
Table 11. Undervoltage Warning Threshold Command Register
Settings
ENx
450µs
COMMAND
REGISTER[BIT]
50µs
50µs
V
OUTx
VALUE
FALLING V THRESHOLD
1ms
1ms
IN
20ms
CNTRL[4:2]
000*
001
010
011
100
101
110
111
2.7V
2.8V
2.9V
3.0V
3.1V
3.2V
3.3V
3.4V
PGOOD
IRQ
3676 F13
Figure 13. Output Low Voltage PGOOD and IRQ Timing
*denotes default power-on value.
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PGSTAT and MSKPG Registers
Table 14. Power Good Status Masking Command Register
COMMAND
The power good status of each regulator is accessible
REGISTER[BIT]
VALUE
2
throughtheLTC3676I Cinterfacebyreadingthecontents
MSKPG [0]
0
1*
Mask Buck1 PGOOD Status
Pass Buck1 PGOOD Status
ofthePGSTATstatusregister. Table13showsthePGSTAT
register contents. The data in the PGSTATL register is held
for the length of the low voltage condition plus 1ms. The
data in the PGSTATRT register is held only for the duration
of the low voltage condition.
MSKPG [1]
MSKPG [2]
MSKPG [3]
MSKPG [ꢀ]
MSKPG [6]
MSKPG [7]
0
Mask Buck2 PGOOD Status
Pass Buck2 PGOOD Status
1*
0
1*
Mask Buck3 PGOOD Status
Pass Buck3 PGOOD Status
0
1*
Mask Buck4 PGOOD Status
Pass Buck4 PGOOD Status
Table 13. Power Good Status Register
STATUS
0
1*
Mask LDO2 PGOOD Status
Pass LDO2 PGOOD Status
REGISTER[BIT]
VALUE
REGULATOR OUTPUT LOW STATUS
0
1*
Mask LDO3 PGOOD Status
Pass LDO3 PGOOD Status
PGSTAT[0]
0
1
Buck1 Output Low
Buck1 Output OK
0
1*
Mask LDO4 PGOOD Status
Pass LDO4 PGOOD Status
PGSTAT[1]
PGSTAT[2]
PGSTAT[3]
PGSTAT[4]
PGSTAT[ꢀ]
PGSTAT[6]
PGSTAT[7]
0
1
Buck2 Output Low
Buck2 Output OK
*denotes default power-on value.
0
1
Buck3 Output Low
Buck3 Output OK
0
1
Buck4 Output Low
Buck4 Output OK
IRQ Status Pin
The IRQ pin is pulled and latched low when undervoltage,
overtemperature or persistent PGOOD events occur. The
IRQ pin is cleared by addressing the CLIRQ command
register or by holding ON low for ꢀ0ms.
0
1
LDO1 Output Low
LDO1 Output OK
0
1
LDO2 Output Low
LDO2 Output OK
0
1
LDO3 Output Low
LDO3 Output OK
Table 15. Interrupt Request Status Register
STATUS
0
1
LDO4 Output Low
LDO4 Output OK
REGISTER[BIT]
VALUE
IRQSTAT REGISTER BIT MEANING
Pushbutton Status Active (Real Time)
Hard Reset Occurred
IRQSTAT [0]
0
1
EachregulatorhasacorrespondingbitintheMSKPGstatus
register as shown in Table 14. When set, a bit blocks the
PGOOD pin from being pulled low in the event of a low
output voltage fault from its matching regulator. Setting
a bit in the MSKPG command register does not mask the
status in the PGSTAT status register.
IRQSTAT [1]
IRQSTAT [2]
IRQSTAT [3]
IRQSTAT [4]
IRQSTAT [ꢀ]
IRQSTAT [6]
0
1
0
1
PGOOD Timeout Occurred
0
1
Undervoltage Warning
0
1
Undervoltage Standby Occurred
Overtemperature Warning
0
1
0
1
Overtemperature Standby Occurred
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IRQSTAT and MSKIRQ Registers
2
all I C command register bits to their default power-on
state. Table 17 shows the command register control of
hard reset function.
The bits in the MSKIRQ command register are set to mask
warning, fault, and pushbutton status reporting to the IRQ
pin. When set to mask, the IRQ pin is not pulled low as a
result of a fault or warning. Even though the IRQ pin is not
pulled low the masked bit is set in the IRQSTAT register.
When undervoltage, overtemperature faults, and hard
reset signals are masked, the IRQ pin is not pulled low
but LTC3676 state controller is pushed into the STANDBY
or POR/HRST state. Accessing the CLIRQ status register
clears the latched bits in the IRQSTAT status register and
releases the IRQ pin.
Table 17. Hard Reset Time Control Command Register
COMMAND
REGISTER[BIT]
VALUE
SETTING
CNTRL[6]
0*
1
10 seconds
ꢀ seconds
*denotes default power-on value.
A hard reset command will push the LTC3676 state con-
troller through the 1 second HRST timer state and into
the POR/HRST state.
Table 16. Interrupt Request Mask Command Register
COMMAND
Fault Shutdown
An undervoltage or overtemperature fault will push the
LTC3676 state controller through the 1 second standby
timer state and into standby state. If a down sequence
is selected in the command registers, it will be executed
during the 1 second power down interval.
REGISTER[BIT]
VALUE
MSKIRQ [0]
0*
1
Pass Pushbutton Status
Mask Pushbutton Status
MSKIRQ [2]
MSKIRQ [3]
MSKIRQ [4]
MSKIRQ [ꢀ]
MSKIRQ [6]
0*
1
Pass PGOOD Timeout
Mask PGOOD Timeout
0*
1
Pass Undervoltage Warning
Mask Undervoltage Warning
LTC3676-1 Operation
0*
1
Pass Undervoltage Shutdown
Mask Undervoltage Shutdown
The LTC3676-1 option supports DDR memory operation
by generating a DDR termination reference and supply
rail equal to one-half the voltage applied to VDDQIN Pin 8.
0*
1
Pass Overtemperature Warning
Mask Overtemperature Warning
0*
1
Pass Overtemperature Shutdown
Mask Overtemperature Shutdown
An internal resistive divider creates a reference voltage of
one-half the voltage on VDDQIN. This reference is used
*denotes default power-on value.
by the V reference buffer to output one-half of VDDQIN
TT
IRQ and IRQSTAT are not cleared by hard reset or fault
on VTTR Pin 9. The VTTR voltage is used as the reference
for 1.ꢀA switching regulator 1 which is used as the DDR
termination supply. The LTC3676-1 EN_B1 pin and com-
mand register bit Buck1[7] enable both VTTR output and
switching regulator 1. The LTC3676-1 switching regula-
tor 1 settings are fixed to one-half frequency and forced
continuous operation.
shutdown. If V remains applied while the LTC3676 is in
IN
STANDBY or POR/HRST then IRQSTAT may be read on
the subsequent power up to determine if a fault or hard
reset occurred.
RSTO Status Pin
The LTC3676 RSTO status pin is pulled low when always-
on LDO1 is 8% below its programmed value or when the
LTC3676 is in the one second HRST timer state.
Figure 1 shows typical application connections for the
LTC3676-1 DDR termination reference and termination
supply.
Hard Reset
2
LDO4 has I C command register selectable output volt-
ages of 1.2V (default), 2.ꢀV, 2.8V and 3V and is enabled
A hard reset can be initiated by holding the ON pin low
or writing to the HRST command register. Bit six of the
CNTRL command register determines how long ON must
remain low to initiate the hard reset. A hard reset sets
2
only using the I C command register. Table 18 shows
the LDO4 command register controls for the LTC3676-1.
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Table 18. LDO4 Control Command Register Setting (LTC3676-1)
2
I C START and STOP Conditions
COMMAND
A bus master signals the beginning of communications
by transmitting a START condition. A START condition is
generated by transitioning SDA from HIGH to LOW while
SCL is HIGH. The master may transmit either the slave
write or the slave read address. Once data is written to the
LTC3676,themastermaytransmitaSTOPconditionwhich
commands the LTC3676 to act upon its new command
set. A STOP condition is sent by the master by transition-
ing SDA from LOW to HIGH while SCL is HIGH. The bus
REGISTER[BIT] VALUE SETTING
LDOB[0]
LDOB[1]
LDOB[2]
LDOB[4:3]
0* Do Not Keep Alive LDO4 in Standby
Keep Alive LDO4 in Standby
1
0* Enable LDO4 at Any Output Voltage
Enable LDO4 Only if Output Voltage Is <300mV
1
0* LDO4 Disabled
LDO4 Enable
1
00* 1.2V
01
10
11
2.ꢀV
2.8V
3.0V
2
is then free for communication with another I C device.
*denotes default power-on value.
2
I C Byte Format
2
I C OPERATION
Each byte sent to or received from the LTC3676 must
be 8 bits long followed by an extra clock cycle for the
acknowledge bit. The data should be sent to the LTC3676
most significant bit (MSB) first.
The LTC3676 communicates with a bus master using
the standard I C 2-wire interface. The timing diagram in
2
Figure 14 shows the relationship of the signals on the
bus. The two bus lines, SDA and SCL must be high when
the bus is not in use. External pull-up resistors or current
sources, such as the LTC1694 SMBus accelerator, are
required on SDA and SCL. The LTC3676 is both a slave
2
I C Acknowledge
The acknowledge signal is used for handshaking between
the master and the slave. When the LTC3676 is written
to, it acknowledges its write address and subsequent data
bytes. When it is read from, the LTC3676 acknowledges
itsreadaddressonly.Thebusmastershouldacknowledge
data returned from the LTC3676.
2
receiver and slave transmitter. The I C control signals,
SDA and SCL are scaled internally to the DV supply.
DD
DV must be connected to the same power supply as
DD
the bus pull-up resistors.
2
The I C port has an undervoltage lockout on the DV
AnacknowledgegeneratedbytheLTC3676letsthemaster
know that the latest byte of information was received.
The master generates the acknowledge related clock and
releases the SDA line during the acknowledge clock cycle.
The LTC3676 pulls down the SDA line during the write
acknowledge clock pulse so that it is a stable LOW during
the HIGH period of this clock pulse.
DD
2
pin. When DV is below approximately 1V, the I C
DD
serial port is cleared and the command registers are set
to default POR values.
2
The complete I C command register table is shown in
Table 20.
2
I C Bus Speed
At the end of a byte of data transferred from the LTC3676
during a READ operation, the LTC3676 releases the SDA
line to allow the master to acknowledge receipt of the
data. Failure of the master to acknowledge data from the
2
The I C port operates at speeds up to 400kHz. It has
built in timing delays to ensure correct operation when
2
addressed from an I C compliant master device. It also
2
LTC3676 has no effect on the operation of the I C port.
containsinputfiltersdesignedtosuppressglitchesshould
the bus become corrupted.
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SDA
t
t
t
SU, STA
BUF
SU, DAT
t
t
t
t
LOW
HD, STA
SU, STO
HD, DAT
3676 F14
SCL
t
t
HIGH
t
HD, STA
SP
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
t
r
t
f
Figure 14. LTC3676 I2C Serial Port Timing
2
TheLTC3676willkeepinterimwritestotheregisterswhen
a repeat START condition occurs. A repeat start may be
I C Slave Address
The LTC3676 responds to factory programmed read and
writeaddresses.Theleastsignificantbitoftheaddressbyte
is 0 when writing data and 1 when reading data. Table 19
shows read and write addresses for the LTC3676 options.
2
used to set up other devices on the I C bus prior to send-
ing a STOP condition. The LTC3676 will act on the data
written prior to the repeat start when a STOP condition
is detected.
Table 19. LTC3676 and LTC3676-1 I2C Read and Write
Addresses
LTC PART NUMBER
LTC3676
2
I C Read Operation
R/W
W
ADDRESS
Figure 16 shows the LTC3676 command register read
sequence. The bus master reads a byte of data from a
LTC3676 command or status register by first writing the
LTC3676 write address followed by the sub-address to
be read from. The LTC3676 acknowledges each of the
two bytes. Next, the bus master initiates a new START
condition and sends the LTC3676 read address. Follow-
ing the acknowledge of the read address by the LTC3676,
0111 1000, 0x78
0111 1001, 0x79
0111 1010, 0x7A
0111 1011, 0x7B
LTC3676
R
LTC3676-1
LTC3676-1
W
R
2
I C Write Operation
The LTC3676 has twenty-two command registers for
2
2
control input. They are accessed by the I C port via a
the LTC3676 pushes data onto the I C bus for the 8 clock
sub-addressed writing system.
cycles. The bus master then acknowledges the data on
its ninth clock.
A single write cycle of the LTC3676 consists of exactly
three bytes except when a clear interrupt or hard reset
command is written. The first byte is always the LTC3676
write address. The second byte represents the LTC3676
sub-address. The sub-address is a pointer which directs
the subsequent data byte within the LTC3676. The third
byte consists of the data to be written to the location
pointed to by the sub-address.
The last read sub-address that is written to the LTC3676
is stored. This allows repeated polling of a command or
statusregisterwithouttheneedtore-writeitssub-address.
Additionally, the last register written may be immedi-
ately read by issuing a START condition followed by read
address and clocking out the data.
As shown in Figure 1ꢀ, the LTC3676 supports multiple
sub-addressed write operations. Data pairs sent following
the chip write address are interpreted as sub-address and
data. Any number of sub-address and data pairs may be
sent. The data in the command registers is not acted on
by the LTC3676 until a STOP signal is issued.
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Table 20. LTC3676 Command Registers
REG NAME B[7]
B[6]
B[5]
B[4]
B[3]
B[2]
B[1]
B[0]
DEFAULT
0x01 BUCK1 Enable:
Mode:
Start-Up:
0 = Enable at
Any Output
Voltage
Phase Select: Clock Rate:
Keep Alive
Switch DV/DT 0000 0000
Control:
0 = Disabled if 00 = Pulse-Skipping
EN_B1 Low 01 = Burst
0 = Clock
Phase 1
0 = 2.2ꢀMHz Buck1:
1 = 1.12ꢀMHz 0 = Do Not
Keep Alive
0 = Slow
10 = Forced Continuous
1 = Fast
1 = Enabled
1 = Clock
Phase 2
1 = Enable
Only if Output
<300mV
1= Keep Alive in
Shutdown.
0x02 BUCK2 Enable:
Mode:
Start-Up:
0 = Enable at
Any Output
Voltage
Phase Select: Clock Rate:
Keep Alive
Switch DV/DT 0000 0000
Control:
0 = Disabled if 00 = Pulse-Skipping
EN_B2 Low 01 = Burst
0 = Clock
Phase 1
0 = 2.2ꢀMHz Buck2:
1 = 1.12ꢀMHz 0 = Do Not
Keep Alive
0 = Slow
10 = Forced Continuous
1 = Fast
1 = Enabled
1 = Clock
Phase 2
1 = Enable
Only if Output
<300mV
1 = Keep Alive
in Shutdown
0x03 BUCK3 Enable:
Mode:
Start-Up:
0 = Enable at
Any Output
Voltage
Phase Select: Clock Rate:
Keep Alive
Switch DV/DT 0000 0000
Control:
0 = Disabled if 00 = Pulse-Skipping
EN_B3 Low 01 = Burst
0 = Clock
Phase 1
0 = 2.2ꢀMHz Buck3:
1 = 1.12ꢀMHz 0 = Do Not
Keep Alive
0 = Slow
10 = Forced Continuous
1 = Fast
1 = Enabled
1 = Clock
Phase 2
1 = Enable
Only if Output
<300mV
1 = Keep Alive
in Shutdown
0x04 BUCK4 Enable:
Mode:
Start-Up:
0 = Enable at
Any Output
Voltage
Phase Select: Clock Rate:
Keep Alive
Switch DV/DT 0000 0000
Control:
0 = Disabled if 00 = Pulse-Skipping
EN_B4 Low 01 = Burst
0 = Clock
Phase 1
0 = 2.2ꢀMHz Buck4:
1 = 1.12ꢀMHz 0 = Do Not
Keep Alive
0 = Slow
10 = Forced Continuous
1 = Fast
1 = Enabled
1 = Clock
Phase 2
1 = Enable
Only if Output
<300mV
1 = Keep Alive
in Shutdown
0x0ꢀ LDOA
0x06 LDOB
0x07 SQD1
Reserved
Reserved
Reserved
Reserved
Enable LDO3: Start-Up LDO3: Keep Alive
Enable LDO2: Start-Up LDO2: Keep Alive
XX00 0000
XX00 0000
0000 0000
0 = Disabled if 0 = Enable at
LDO3:
0 = Disabled if 0 = Enable at
LDO2:
EN_L3 Low
Any Output
Voltage
0 = Do Not
Keep Alive
EN_L2 Low
Any Output
Voltage
0 = Do Not
Keep Alive
1 = Enabled
1 = Enabled
1 = Enable
Only if Output in Shutdown.
<300mV
1 = Keep Alive
1 = Enable
Only if Output in Shutdown
<300mV
1 = Keep Alive
Reserved
LTC3676-1 LDO4 Output
Voltage:
Enable LDO4: Start-Up LDO4: Keep Alive
0 = Disabled if 0 = Enable at
LDO4:
00 = 1.2V
EN_L4 Low
Any Output
Voltage
0 = Do Not
Keep Alive
01 = 2.ꢀV
1 = Enabled
10 = 2.8V
1 = Enable
1 = Keep Alive
11 = 3.0V
Only if Output in Shutdown
<300mV
Sequence Down Buck4:
00 = With WAKE
Sequence Down Buck3:
00 = With WAKE
Sequence Down Buck2:
00 = With WAKE
Sequence Down Buck1:
00 = With WAKE
01 = WAKE + 100ms
10 = WAKE + 200ms
11 = WAKE + 300ms
01 = WAKE + 100ms
10 = WAKE + 200ms
11 = WAKE + 300ms
01 = WAKE + 100ms
10 = WAKE + 200ms
11 = WAKE + 300ms
01 = WAKE + 100ms
10 = WAKE + 200ms
11 = WAKE + 300ms
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REG NAME B[7]
B[6]
B[5]
B[4]
B[3]
B[2]
B[1]
B[0]
DEFAULT
0x08 SQD2
Reserved
Reserved
Sequence Down LD04:
00 = With WAKE
Sequence Down LD03:
00 = With WAKE
Sequence Down LD02:
00 = With WAKE
XX00 0000
01 = WAKE + 100ms
10 = WAKE + 200ms
11 = WAKE + 300ms
01 = WAKE + 100ms
10 = WAKE + 200ms
11 = WAKE + 300ms
01 = WAKE + 100ms
10 = WAKE + 200ms
11 = WAKE + 300ms
0x09 CNTRL PWR_ON:
0 = Not
Pushbutton Software
UV Warning Threshold:
Over temperature Warning
Levels:
0000 0000
Hard Reset
Timer:
Control Mode: 000 = 2.7V
PWR_ON
0 = Pin or
Register
Control
001 = 2.8V
010 = 2.9V
011 = 3.0V
100 = 3.1V
101 = 3.2V
110 = 3.3V
111 = 3.4V
00 = 10°C Below
Overtemperature
0 = 10 sec
1 = ꢀ sec
1 = PWR_ON
01 = 20°C Below
Overtemperature
"ORed" with
PWR_ON PIN
1 = Inhibit Pin
Control
10 = 30°C Below
Overtemperature
11 = 40°C Below
Overtemperature
0x0A DVB1A Reserved
0x0B DVB1B Reserved
Reserved
Reserved
Buck1
Reference
Select:
0 =
Buck1 Feedback Reference Input (VA):
00000 = 412.ꢀmV
XX01 1001
XX01 1001
11001 = 72ꢀmV
11111 = 800mV
DVB1A[4-0] 12.ꢀmV Step Size
1 =
DVB1B[4-0]
PGOOD Mask: Buck1 Feedback Reference Input (VB):
0 = PGOOD
Low When
Slewing
00000 = 412.ꢀmV
11001 = 72ꢀmV
11111 = 800mV
12.ꢀmV Step Size
1 = PGOOD
Not Forced
Low When
Slewing
0x0C DVB2A Reserved
0x0D DVB2B Reserved
Reserved
Reserved
Buck2
Reference
Select:
0 =
Buck2 Feedback Reference Input (VA):
00000 = 412.ꢀmV
XX01 1001
XX01 1001
11001 = 72ꢀmV
11111 = 800mV
DVB2A[4-0] 12.ꢀmV Step Size
1 =
DVB2B[4-0]
PGOOD Mask: Buck2 Feedback Reference Input (VB):
0 = PGOOD
Low When
Slewing
00000 = 412.ꢀmV
11001 = 72ꢀmV
11111 = 800mV
12.ꢀmV Step Size
1 = PGOOD
Not Forced
Low When
Slewing
0x0E DVB3A Reserved
Reserved
Buck3
Reference
Select:
0 =
Buck3 Feedback Reference Input (VA):
00000 = 412.ꢀmV
XX01 1001
11001 = 72ꢀmV
11111 = 800mV
DVB3A[4-0] 12.ꢀmV Step Size
1 =
DVB3B[4-0]
3676ff
30
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
operaTion
REG NAME B[7]
B[6]
B[5]
B[4]
B[3]
B[2]
B[1]
B[0]
DEFAULT
0x0F DVB3B Reserved
Reserved
PGOOD Mask: Buck3 Feedback Reference Input (VB):
XX01 1001
0 = PGOOD
Low When
Slewing
00000 = 412.ꢀmV
11001 = 72ꢀmV
11111 = 800mV
12.ꢀmV Step Size
1 = PGOOD
Not Forced
Low When
Slewing
0x10 DVB4A Reserved
Reserved
Reserved
Buck4
Reference.
Select:
0 =
Buck4 Feedback Reference Input (VA):
00000 = 412.ꢀmV
XX01 1001
XX01 1001
11001 = 72ꢀmV
11111 = 800mV
DVB4A[4-0] 12.ꢀmV Step Size
1 =
DVB4B[4-0]
0x11 DVB4B Reserved
PGOOD Mask: Buck4 Feedback Reference Input (VB):
0 = PGOOD
Low When
Slewing
00000 = 412.ꢀmV
11001 = 72ꢀmV
11111 = 800mV
12.ꢀmV Step Size
1 = PGOOD
Not Forced
Low When
Slewing
0x12 MSKIRQ Reserved
Mask Over- Mask Over-
Mask
Mask
Mask PGOOD Reserved
Mask Push
Button Status
X000 00X0
temperature temperature Undervoltage Undervoltage Timeout
Shutdown
Warning
Shutdown
Warning
0x13 MSKPG Allow LDO 4 Allow LDO 3 Allow LDO 2 Reserved
PGOOD Fault PGOOD Fault PGOOD Fault
Allow Buck 4 Allow Buck 3 Allow Buck 2
PGOOD Fault PGOOD Fault PGOOD Fault
Allow Buck 1 1111 1111
PGOOD Fault
0x14 USER
0x1E HRST
0x1F CLIRQ
User Bit 7
User Bit 6
User Bit ꢀ
User Bit 4
User Bit 3
User Bit 2
User Bit 1
User Bit 0
0000 0000
Hard Reset Command. No Data.
Clear IRQ Command. No Data
Table 22. LTC3676 Status Registers
REG
NAME B[7]
B[6]
B[5]
B[4]
Undervoltage Undervoltage PGOOD
Shutdown Warning Timeout
B[3]
B[2]
B[1]
Hard Reset
B[0]
0x1ꢀ IRQSTAT Reserved
Over-
temperature
Shutdown
Over-
temperature
Warning
Pushbutton
Status (Real
Time)
0x16 PGSTATL LDO4 PGOOD LDO3 PGOOD LDO2 PGOOD LDO1 PGOOD Buck4 PGOOD Buck3 PGOOD Buck2 PGOOD Buck1 PGOOD
Hold 1ms Hold 1ms Hold 1ms Hold 1ms Hold 1ms Hold 1ms Hold 1ms Hold 1ms
0x17 PGSTATRT LDO4 PGOOD LDO3 PGOOD LDO2 PGOOD LDO1 PGOOD Buck4 PGOOD Buck3 PGOOD Buck2 PGOOD Buck1 PGOOD
Reserved Bits
The bits marked as reserved in command registers can-
not be written to and will return inconsistent data when
read. These bits must be considered invalid and masked
by software when reading.
3676ff
31
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
applicaTions inForMaTion
THERMAL CONSIDERATIONS AND BOARD LAYOUT
of the application load and the LDO load. This example
is with the LDO regulators at one third rated current and
the switching regulators at three quarters rated current.
Printed Circuit Board Power Dissipation
In order to ensure optimal performance and the ability
to deliver maximum output power to any regulator, it is
critical that the exposed ground pad on the backside of the
LTC3676 package be soldered to a ground plane on the
board.TheexposedpadistheonlyGNDconnectionforthe
Table 23. LTC3676 Power Loss Example
APPLICATION
LOAD (A)
TOTAL
EFF
V
IN
V
OUT
LOAD (A) (%) P (mW)
D
LDO1
LDO2
LDO3
LDO4
Buck1
Buck2
Buck3
Buck4
3.8
1.8
3.3
3.3
3.8
3.8
3.8
3.8
1.2
1.2
1.8
2.ꢀ
1.2
1.8
1.2ꢀ
3.3
0.01
0.1
0.010
0.100
0.100
0.100
1.87ꢀ
1.87ꢀ
1.12ꢀ
1.12ꢀ
–
–
26.00
60.00
2
LTC3676. Correctly soldered to a 2ꢀ00mm ground plane
0.1
–
1ꢀ0.00
80.00
on a double-sided 1oz copper board, the LTC3676 has a
0.1
–
thermalresistance( )ofapproximately34°C/W.Failure
JA
1.87ꢀ
1.77ꢀ
1.12ꢀ
0.92ꢀ
80
8ꢀ
80
90
4ꢀ0.00
ꢀ06.2ꢀ
281.2ꢀ
371.2ꢀ
192ꢀ
to make good thermal contact between the exposed pad
on the backside of the package and an adequately sized
ground plane will result in thermal resistances far greater
than 34°C/W. To ensure the junction temperature of the
LTC3676 die does not exceed the maximum rated limit
and to prevent overtemperature faults, the power output
of the LTC3676 must be managed by the application. The
totalpowerdissipationintheLTC3676isapproximatedby
summing the power dissipation in each of the switching
regulators and the LDO regulators. The power dissipation
in a switching regulator is estimated by:
Total Power =
Internal Junction Temperature at ꢀꢀ°C Ambient 120°C
Printed Circuit Board Layout
When laying out the printed circuit board, the following
checklist should be followed to ensure proper operation
of the LTC3676:
1. Connect the exposed pad of the package (Pin 41) di-
rectly to a large ground plane to minimize thermal and
electrical impedance.
100-Eff%
PD(SWx = VOUTx •IOUTx
•
W
( )
)
100
Where V
is the programmed output voltage I
is
OUTx
2. The switching regulator input supply traces to their
decoupling capacitors should be as short as possible.
Connect the GND side of the capacitors directly to the
ground plane of the board. The decoupling capacitors
provide the AC current to the internal power MOSFETs
and theirdrivers. It is importantto minimize inductance
from the capacitors to the LTC3676 pins.
OUTx
the load current and Eff is the % efficiency that can be
measured or looked up from the efficiency curves for the
programmed output voltage.
The power dissipated by an LDO regulator is estimated by:
P
= V
− V
• I
(W)
D(LDOx)
IN(LDOx)
LDOx LDOx
where V
is the programmed output voltage, V
IN(LDOx)
LDOx
3. Minimize the switching power traces connecting SW1,
SW2, SW3, and SW4 to the inductors to reduce radi-
ated EMI and parasitic coupling. Keep sensitive nodes
such as the feedback pins away from or shielded from
the large voltage swings on the switching nodes.
is the LDO supply voltage, and I
is the output load
LDOx
current. If one of the switching regulator outputs is used
as an LDO supply voltage, remember to include the LDO
supply current in the switching regulator load current for
calculating power loss.
4. Minimize the length of the connection between the
step-downswitchingregulatorinductorsandtheoutput
capacitors. Connect the GND side of the output capaci-
tors directly to the thermal ground plane of the board.
An example using the equations above with the param-
eters in Table 23 shows an application that is at a junction
temperature of 120°C at an ambient temperature of ꢀꢀ°C.
LDO2, LDO3, and LDO4 are powered by step-down Buck2
and Buck4. The total load on Buck2 and Buck4 is the sum
3676ff
32
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
Typical applicaTions
LTC3676 PMIC Configured to Support Freescale i.MX6 Processor
FREESCALE
i.MX6
22µF
22µF
22µF
35
22µF
V
IN
VSNVS_IN
3.3V TO 5V
36
16
15
ARM
0.9V TO 1.5V
AT 2.5A
PV
PV
PV
PV
IN4
IN1
IN2
IN3
1µH
(1.37V)
47µF
27
20
22
V
IN
SW3
VDDARM_IN
1µF
178k
200k
10pF
FB_B3
V
RTC
3V
28
26
SOC
0.9V TO 1.5V
AT 1.5A
LDO1
25mA
1µF
634k
200k
1.5µH
10pF
(1.37V)
47µF
40
24
VDDSOC_IN
VDDHIGH_IN
SW1
FB_L1
178k
200k
LTC3676
68k
FB_B1
33
37
WAKE
ARM
WAKE
EN_B1
EN_B2
EN_B3
EN_B4
EN_L2
EN_L3
EN_L4
1.5µH
10pF
I/O
3.3V
1.5A
(3.3V)
31
25
34
18
17
30
10
9
SW2
715k
200k
47µF
47µF
FB_B2
V
DDHIGH
I/O
DDR
1.5V AT 2.5A
1µH
11
I/O
SW4
VDD_DDR_IO
GND
68k 68k 68k
215k
200k
10pF
38
32
39
12
23
2
RSTO
IRQ
RSTO
IRQ
FB_B4
V
IN_L2
V
DDHIGH
2.97V
PGOOD
PGOOD
1µF
DDR
≤ 4 CHIPS
NO TERM
DV
DD
300mA
3
LDO2
4.7k 4.7k
619k
200k
1µF
14
13
19
21
29
SCL
SCA
SCL
1
5
FB_L2
SEQUENCE:
WAKE
SDA
V
IN_L3
ARM
SOC
I/O
VDDHIGH
LDO3
DDR
VSTB
VSTB
PWR_ON
ON
1µF
1µF
PWR_ON
LDO3
1.8V
300mA
4
7
LDO3
1µF
1µF
V
IN_L4
LDO4
3V
300mA
6
8
LDO4
634k
FB_L4
GND
41
200k
3676 TA02
3676ff
33
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
Typical applicaTions
LTC3676-1 PMIC Configured to Support Freescale i.MX6 Processor with DDR VTT and VTTR
FREESCALE
i.MX6
VSNVS_IN
VDDHIGH_IN
22µF
22µF
22µF
35
22µF
V
IN
V
DDHIGH
ARM
3V TO 5.5V
36
16
15
0.9V TO 1.5V
AT 2.5A
PV
PV
PV
PV
IN4
IN1
IN2
IN3
1µH
(1.37V)
47µF
27
20
22
V
IN
SW3
VDDARM_IN
VDDSOC_IN
VDD_DDR_IO
1µF
178k
200k
10pF
FB_B3
LDO1
3V
25mA
28
26
SOC
0.9V TO 1.5V
AT 1.5A
LDO1
1µF
634k
200k
1.5µH
10pF
(1.37V)
47µF
31
25
SW2
FB_L1
178k
200k
LTC3676-1
68k
FB_B2
33
37
34
18
17
30
10
WAKE
WAKE
EN_B1
EN_B2
EN_B3
EN_B4
EN_L2
EN_L3
DDR
1.5V AT 2.5A
1µH
11
23
SW4
215k
200k
47µF
10pF
FB_B4
V
DDHIGH
ARM
VTT
0.75V AT 1.5A
1µH
40
24
I/O
SW1
68k 68k 68k
215k
47µF
10pF
38
32
39
12
GND
RSTO
IRQ
RSTO
IRQ
FB_B1
PGOOD
PGOOD
DDR
8
9
2
DV
DD
VDDQIN
VTTR
8 CHIPS
WITH TERM
4.7k 4.7k
14
13
19
21
29
V
IN_L2
0.047µF
SCL
SCA
SCL
1µF
SDA
V
DDHIGH
3
VSTB
VSTB
PWR_ON
ON
LDO2
2.97V
300mA
PWR_ON
619k
200k
1µF
1
5
SEQUENCE:
WAKE
FB_L2
ARM
SOC
VDDHIGH
LDO3
DDR
VTT
V
IN_L3
1µF
1µF
LDO3
1.8V
300mA
4
7
LDO3
V
IN_L4
1µF
LDO4
3V
300mA
6
LDO4
GND
41
1µF
3676 TA03
3676ff
34
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
package DescripTion
Please refer to http://www.linear.com/product/LTC3676#packaging for the most recent package drawings.
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-ꢀ728 Rev Ø)
0.70 0.05
6.50 0.05
5.ꢀ0 0.05
4.42 0.05
4.50 0.05
(4 SIDES)
4.42 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 0.05
R = 0.ꢀꢀ5
TYP
6.00 0.ꢀ0
(4 SIDES)
R = 0.ꢀ0
TYP
39 40
0.40 0.ꢀ0
PIN ꢀ TOP MARK
(SEE NOTE 6)
ꢀ
2
PIN ꢀ NOTCH
R = 0.45 OR
0.35 × 45°
CHAMFER
4.42 0.ꢀ0
4.50 REF
(4-SIDES)
4.42 0.ꢀ0
(UJ40) QFN REV Ø 0406
0.200 REF
0.25 0.05
0.50 BSC
0.00 – 0.05
NOTE:
BOTTOM VIEW—EXPOSED PAD
ꢀ. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN ꢀ LOCATION ON THE TOP AND BOTTOM OF PACKAGE
3676ff
35
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
package DescripTion
Please refer to http://www.linear.com/product/LTC3676#packaging for the most recent package drawings.
LXE Package
48-Lead Plastic Exposed Pad LQFP (7mm × 7mm)
(Reference LTC DWG #05-08-1927 Rev A)
Exposed Pad Variation AA
7.15 – 7.25
5.50 REF
48
37
36
1
0.50 BSC
C0.30
5.50 REF
7.15 – 7.25
0.20 – 0.30
4.15 0.05
4.15 0.05
12
13
25
PACKAGE OUTLINE
24
1.30 MIN
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
9.00 BSC
7.00 BSC
4.15 0.10
48
37
37
48
SEE NOTE: 3
1
36
36
1
C0.30
9.00 BSC
7.00 BSC
4.15 0.10
A
A
25
12
12
25
C0.30 – 0.50
24
13
13
24
BOTTOM OF PACKAGE—EXPOSED PAD (SHADED AREA)
1.60
11° – 13°
1.35 – 1.45 MAX
R0.08 – 0.20
GAUGE PLANE
0.25
0° – 7°
LXE48 (AA) LQFP 0416 REV A
11° – 13°
1.00 REF
0.50
BSC
0.09 – 0.20
0.17 – 0.27
SIDE VIEW
0.05 – 0.15
0.45 – 0.75
SECTION A – A
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
3. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER
4. DRAWING IS NOT TO SCALE
2. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.25mm (10 MILS) BETWEEN THE LEADS AND ON ANY
SIDE OF EXPOSED PAD, MAX 0.50mm (20 MILS) AT CORNER OF EXPOSED
PAD, IF PRESENT
3676ff
36
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
12/13 Modified the Typical Application Circuit
Modified Start-Up Sequence Path
1
1
Changed Conditions on V Burst Mode Quiescent Current
3
IN
Removed Transient Response comment from V
Modified Command Registers table
Programming
16
OUT
28-30
Modified P equation in PCB Power Dissipation section Table 23
31
D
Changed R and C values in Typical Applications
09/14 Changed C values in application circuits
Corrected pin names in Conditions in Electrical Characteristics table
Corrected units on Current Limit graph
32, 33, 36
B
1, 32, 33, 36
3 to 5
8
Corrected units on LDO1 Dropout and LDO1 Load Response graphs
Corrected Operation Introduction section
9
14
24
25
28
30
Modified LTC3676-1 Operation section
2
Changed table reference in I C Operation section
Changed table number for Command Registers section
Clarified Command Registers table
C
D
09/14 Added LQFP Package (LXE)
1 to 3, 11,
12, 36
05/15 Modified Thermal Resistance of LXE Package
Modified Pin Description of EN_B1
Modified Figure 1 GND
2
12
15
25
36
2
Clarified LTC3676-1 Operation Section
Amended Package Drawing
E
F
04/17 Added thermal resistances ThetaJC
09/17 Modified Buck R
curves
9
DS(ON)
Modified LTC3676-1 Operation section
Added Reserved Bits section to Table 22
25
31
3676ff
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
37
LTC3676/LTC3676-1
Typical applicaTion
Sequenced Power for High Performance Processor and DDR Memory Using LTC3375 Parallelable Buck Converters
22µF
22µF
10µF
10µF
10µF
10µF
10µF
10µF
10µF
10µF
22µF
22µF
V
IN
5V
21.5k
PV
IN4
PWR_ON
PV
PV
PV
V
IN
V
V
V
V
V
V
V
V
V
IN8
ARM
1.35V
4A
IN3
IN2
IN1
IN1
IN2 IN3
IN4 IN5
IN6 IN7
V
TT
POWER GOOD
IN
0.75V
1.5A
SW1
SW2
SW3
SW4
FB1
SHNT
FROM V SUPPLY
2.2µH
V
RTC
3V
3.3V
1.5µH
10pF
LDO1
V
CC
SW1
25mA
100µF
1µF
634k
200k
1Ω
10µF
1.02M
576k
215k
47µF
47µF
47µF
47µF
174k
200k
FB_L1
FBV
CC
FB_B1
FB2
1.5µH
10pF
IO18
1.8V
1.5A
VIN_L2
IO33
RT
PB
CT
LTC3676-1
LTC3375
FB3
SW2
1µF
294k
200k
FB4
2.2µH
I033
3.3V
1A
2.8V
300mA
LDO2
FB_B2
SW5
0.01µF
1µF
576k
200k
22µF
715k
SOC
1.35V
2.5A
FB_L2
FB5
1µH
SYNC
EN2
EN3
EN4
EN7
EN8
SW3
200k
DRAM
1.5V
3A
174k
200k
10pF
SW6
SW7
SW8
FB6
IO33
VIN_L3
LDO3
2.2µH
FB_B3
1µF
V
DDHIGH
3V
2.5A
68µF
215k
200k
IO18ANALOG
1.8V
1µH
300mA
1µF
SW4
FB7
634k
200k
10pF
FB8
FB_B4
IO18
VIN_L4
ON
EN1
EN5
EN6
WDO
IRQ
RSTO
IRQ
1.2V
300mA
LDO4
1µF
RST
KILL
PGOOD
WAKE
DV
DD
EN_B1
EN_B2
EN_B3
EN_B4
EN_L3
EN_L2
ON
4.7k 4.7k
SDA
SCL
SDA
SCL
WDI
TEMP
VSTB
VDDQIN
VTTR
VTTR
750mV
10mA
GND
MICROPROCESSOR
CONTROL
GND
3676 TA04
relaTeD parTs
PART
NUMBER
DESCRIPTION
1.8V to USB, Multioutput DC/
COMMENTS
Seamless Transition Between Multiple Input Power Sources, V Range: 1.8V to 5.5V, Buck-Boost
LTC3101
IN
DC Converter with Low Loss USB Converter V
Range: 1.5V to 5.25V, 3.3V
at 800mA for V ≥ 3V, Dual 350mA Buck Regulators,
OUT
OUT IN
Power Controller
V
: 0.6V to V , 38μA Quiescent Current in Burst Mode Operation, 24-Lead 4mm 4mm 0.75mm
OUT IN
QFN Package
LTC3375
LTC3589/
8-Channel Programmable,
Parallelable 1A Buck DC/DCs
8-Channel Independent Step-Down DC/DCs. Master Slave Configurable for Up to 4A per Output Channel
with a Single Inductor, Die Temperature Monitor Output, 48-Lead 7mm 7mm QFN Package
2
8-Output Regulator with
Triple I C Adjustable High Efficiency Step-Down DC/DC Converters: 1.6A, 1A, 1A. High Efficiency 1.2A
2
LTC3589-1/ Sequencing and I C
LTC3589-2
Buck-Boost DC/DC Converter. Triple 250mA LDO Regulators. Pushbutton ON/OFF Control with System
2
Reset. Flexible Pin-Strap Sequencing Operation. I C and Independent Enable Control Pins, DVS and
Slew Rate Control, 40-Lead 6mm 6mm 0.75mm QFN Package
LTC3586/
Switching USB Power Manager
Complete Multifunction PMIC: Switching Power Manager, 1A Buck-Boost + 2 Bucks + Boost + LDO,
LTC3586-1 PMIC with Li-Ion/Polymer Charger 4mm 6mm QFN-38 Package, LTC3586-1 Version Has 4.1V V
.
FLOAT
3676ff
LT 0917 REV F • PRINTED IN USA
www.linear.com/LTC3676
38
© LINEAR TECHNOLOGY CORPORATION 2013
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