LTC3727IG-1#TRPBF_技术文档

LTC3727/LTC3727-1

High Efficiency, 2-Phase

Synchronous Step-Down Switching Regulators

U

FEATURES

DESCRIPTIO

The LTC^®3727/LTC3727-1 are high performance dual

step-down switching regulator controllers that drive all

N-channel synchronous power MOSFET stages. A con-

stant frequency current mode architecture allows phase-

lockable frequency of up to 550kHz. Power loss and noise

due to the ESR of the input capacitors are minimized by

operating the two controller output stages out of phase.

■

Wide Output Voltage Range: 0.8V ≤ V_OUT≤ 14V

Out-of-Phase Controllers Reduce Required Input

Capacitance and Power Supply Induced Noise

OPTI-LOOP^®Compensation Minimizes C_OUT

±1% Output Voltage Accuracy

■

Power Good Output Voltage Monitor

Phase-Lockable Fixed Frequency 250kHz to 550kHz

Latched Short-Circuit Shutdown (LTC3727 Only)

Dual N-Channel MOSFET Synchronous Drive

Wide V_INRange: 4V to 36V Operation

Very Low Dropout Operation: 99% Duty Cycle

Adjustable Soft-Start Current Ramping

Foldback Output Current Limiting

Output Overvoltage Protection

OPTI-LOOP compensation allows the transient response

tobeoptimizedoverawiderangeofoutputcapacitanceand

ESRvalues.Thereisa precision0.8Vreferenceandapower

good output indicator. A wide 4V to 30V (36V maximum)

input supply range encompasses all battery chemistries.

A RUN/SS pin for each controller provides soft-start, and

on the LTC3727GN, optional timed, short-circuit shut-

down. Current foldback limits MOSFET heat dissipation

during short-circuit conditions when overcurrent latchoff

isdisabled.Outputovervoltageprotectioncircuitrylatches

on the bottom MOSFET until V_OUTreturns to normal. The

FCB mode pin can select among Burst Mode, constant

frequencymodeandcontinuousinductorcurrentmodeor

regulate a secondary winding.

Low Shutdown I_Q: 20μA

Selectable Constant Frequency or Burst Mode^®

Operation

■

Small 28-Lead SSOP Package

LTC3727-1 Also Available in the 5mm × 5mm QFN

Package

U

APPLICATIO S

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Burst

Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation. All other

trademarks are the property of their respective owners. Protected by U.S. Patents, including

5481178, 5929620, 6177787, 6144194, 6100678, 5408150, 6580258, 6304066, 5705919.

■

Telecom Systems

■

Automotive Systems

■

Battery-Operated Digital Devices

U

TYPICAL APPLICATIO

V

IN

18V TO 28V

+

22μF

1μF

CERAMIC

50V

4.7μF

CERAMIC

V

IN

PGOOD INTV

CC

M1

M3

M4

TG1

TG2

0.1μF

BOOST1

SW1

BOOST2

SW2

15μH

8μH

0.1μF

LTC3727/

LTC3727-1

M2

BG1

BG2

PLLIN

PGND

+

SENSE1

SENSE2

1000pF

220pF

0.015Ω

–

SENSE2

V

SENSE1

V

12V

4A

OUT1

5V

5A

OUT2

V

OSENSE1

OSENSE2

105k

1%

280k

1%

I

TH1

TH2

+

56μF

220pF

15k

RUN/SS1

SGND

RUN/SS2

+

20k

1%

47μF

6V

SP

15V

SP

20k

1%

15k

0.1μF

M1, M2, M3, M4: FDS6680A

3727 F01

Figure 1. High Efficiency Dual 12V/5V Step-Down Converter

3727fc

1

LTC3727/LTC3727-1

W W

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ABSOLUTE AXI U RATI GS _{(Note 1)}

Input Supply Voltage (V_IN).........................36V to –0.3V

Top Side Driver Voltages

(BOOST1, BOOST2) ...................................42V to –0.3V

Switch Voltage (SW1, SW2) .........................36V to –5V

INTV_CC,EXTV_CC, (BOOST1-SW1),

I_TH1,I_TH2, V_OSENSE1, V_OSENSE2Voltages ...2.7V to –0.3V

Peak Output Current <10μs (TG1, TG2, BG1, BG2) ... 3A

INTV_CCPeak Output Current ................................ 50mA

Operating Temperature Range (Note 2) .. –40°C to 85°C

Junction Temperature (Note 3)............................. 125°C

Storage Temperature Range ................. –65°C to 125°C

Lead Temperature

(BOOST2-SW2) ........................................8.5V to –0.3V

RUN/SS1, RUN/SS2, PGOOD ..................... 7V to –0.3V

SENSE1⁺, SENSE2⁺, SENSE1^–,

(Soldering, 10 sec, G Package)............................. 300°C

Solder Reflow Temperature (UH Package) ........... 265°C

SENSE2^–Voltages.....................................14V to –0.3V

PLLIN, PLLFLTR, FCB Voltages ........... INTV_CCto –0.3V

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PACKAGE/ORDER I FOR ATIO

TOP VIEW

ORDER PART

TOP VIEW

NUMBER

1

2

PGOOD

TG1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RUN/SS1

+

SENSE1

LTC3727EG

LTC3727EG-1

LTC3727IG-1

LTC3727EUH-1

32 31 30 29 28 27 26 25

–

3

SW1

SENSE1

V

1

2

3

4

5

6

7

8

24 BOOST1

OSENSE1

4

BOOST1

V

OSENSE1

PLLFLTR

PLLIN

FCB

23

22

21

V

IN

5

V

IN

PLLFLTR

PLLIN

FCB

BG1

6

BG1

EXTV

CC

33

7

EXTV

CC

I

20 INTV

TH1

SGND

3.3V

CC

8

INTV

CC

I

PGND

TH1

19

18 BG2

BOOST2

9

PGND

BG2

SGND

OUT

UH PART

MARKING

10

11

12

13

14

I

TH2

17

3.3V

OUT

BOOST2

SW2

I

9 10 11 12 13 14 15 16

TH2

V

37271

OSENSE2

–

TG2

SENSE2

+

RUN/SS2

UH PACKAGE

32-LEAD (5mm × 5mm) PLASTIC QFN

G PACKAGE

28-LEAD PLASTIC SSOP

T_JMAX= 125°C, θ_JA= 34°C/W

EXPOSED PAD (PIN 33) IS SGND

(MUST BE SOLDERED TO PCB)

T_JMAX= 125°C, θ_JA= 95°C/W

Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF

Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The

●

denotes the specifications which apply over the full operating

= 5V unless otherwise noted.

temperature range, otherwise specifications are at T = 25°C. V = 15V, V

A

IN

RUN/SS1, 2

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loops

V

Regulated Feedback Voltage

Feedback Current

(Note 4); I

(Note 4)

Voltage = 1.2V

TH1, 2

●

0.792

0.800

–5

0.808

–50

V

nA

OSENSE1, 2

I

VOSENSE1, 2

V

Reference Voltage Line Regulation

V

= 3.6V to 30V (Note 4)

IN

0.002

0.02

%/V

REFLNREG

3727fc

2

LTC3727/LTC3727-1

ELECTRICAL CHARACTERISTICS

The

●

denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T = 25°C. V = 15V, V

= 5V unless otherwise noted.

A

IN

RUN/SS1, 2

SYMBOL

PARAMETER

CONDITIONS

(Note 4)

MIN

TYP

MAX

UNITS

V

Output Voltage Load Regulation

LOADREG

Measured in Servo Loop; ΔI Voltage = 1.2V to 0.7V

●

0.1

–0.1

0.5

–0.5

%

TH

Measured in Servo Loop; ΔI Voltage = 1.2V to 2.0V

TH

g

Transconductance Amplifier g

I = 1.2V; Sink/Source 5μA (Note 4)

TH1, 2

1.3

3

mmho

MHz

m1, 2

m

Transconductance Amplifier GBW

I

= 1.2V (Note 4)

TH1, 2

mGBW1, 2

I

Input DC Supply Current

Normal Mode

(Note 5)

IN

RUN/SS1, 2

Q

V

= 15V, EXTV Tied to V , V = 8.5V

670

20

μA

CC

OUT1 OUT1

Shutdown

= 0V

35

0.84

–0.05

7.3

V

Forced Continuous Threshold

Forced Continuous Pin Current

●

0.76

0.800

–0.18

6.8

V

μA

V

FCB

I

V

= 0.85V

–0.30

FCB

V

Burst Inhibit (Constant Frequency)

Threshold

Measured at FCB pin

BINHIBIT

UVLO

Undervoltage Lockout

V

Ramping Down

●

3.5

0.86

–60

99.4

1.2

1.5

4.1

2

4

V

IN

V

Feedback Overvoltage Lockout

Sense Pins Total Source Current

Maximum Duty Factor

Measured at V

0.84

–85

98

0.88

OVL

OSENSE1, 2

I

(Each Channel) V

In Dropout

–

– = V + + = 0V

SENSE1 , 2

μA

%

μA

V

SENSE

SENSE1 , 2

DF

MAX

I

Soft-Start Charge Current

V

= 1.9V

RUN/SS1, 2

0.5

RUN/SS1, 2

V

ON RUN/SS Pin ON Threshold

LT RUN/SS Pin Latchoff Arming Threshold

RUN/SS Discharge Current

V Rising

RUN/SS1, RUN/SS2

1.0

1.9

4.5

4

RUN/SS1, 2

SCL1, 2

V

Rising from 3V (LTC3727 Only)

V

RUN/SS1, RUN/SS2

I

Soft-Short Condition V

= 0.5V,

0.5

μA

OSENSE1, 2

V

= 4.5V (LTC 3727 Only)

RUN/SS1, 2

OSENSE1, 2

I

Shutdown Latch Disable Current

Maximum Current Sense Threshold

= 0.5V (LTC3727 Only)

1.6

5

μA

mV

SDLHO

V

= 0.7V,V

– – = 12V

●

105

135

165

SENSE(MAX)

SENSE1 , 2

TG Transition Time:

Rise Time

Fall Time

(Note 6)

TG1, 2 t

C

= 3300pF

50

90

ns

r

f

LOAD

= 3300pF

BG Transition Time:

Rise Time

Fall Time

(Note 6)

LOAD

BG1, 2 t

C

= 3300pF

40

90

80

ns

r

f

TG/BG t

Top Gate Off to Bottom Gate On Delay

Synchronous Switch-On Delay Time

C

= 3300pF Each Driver

90

ns

1D

LOAD

BG/TG t

Bottom Gate Off to Top Gate On Delay

Top Switch-On Delay Time

C

= 3300pF Each Driver

90

2D

LOAD

t

Minimum On-Time

Tested with a Square Wave (Note 7)

8.5V < V < 30V, V = 6V

180

ON(MIN)

INTV Linear Regulator

CC

INTVCC

V

Internal V Voltage

7.2

6.9

7.5

0.2

70

7.8

1.0

160

V

%

CC

IN

EXTVCC

INT

INTV Load Regulation

I

= 0mA to 20mA, V

= 6V

LDO

CC

EXTVCC

EXT

EXTV Voltage Drop

= 20mA, V

= 8.5V

mV

V

CC

EXTVCC

EXTV Switchover Voltage

= 20mA, EXTV Ramping Positive

●

7.3

0.3

EXTVCC

LDOHYS

CC

EXTV Hysteresis

V

CC

Oscillator and Phase-Locked Loop

f

Nominal Frequency

Lowest Frequency

Highest Frequency

V

= 1.2V

= 0V

350

220

460

380

255

530

430

290

580

kHz

NOM

LOW

HIGH

PLLFLTR

≥ 2.4V

3727fc

3

LTC3727/LTC3727-1

ELECTRICAL CHARACTERISTICS

The

●

denotes the specifications which apply over the full operating

= 5V unless otherwise noted.

temperature range, otherwise specifications are at T = 25°C. V = 15V, V

A

IN

RUN/SS1, 2

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

R

PLLIN Input Resistance

50

–15

15

kΩ

PLLIN

I

Phase Detector Output Current

Sinking Capability

PLLFLTR

f

< f

> f

μA

PLLIN

OSC

Sourcing Capability

OSC

3.3V Linear Regulator

V

3.3V Regulator Output Voltage

3.3V Regulator Load Regulation

3.3V Regulator Line Regulation

No Load

= 0mA to 10mA

●

3.25

3.35

0.5

3.45

2.5

V

3.3OUT

3.3IL

I

%

3.3

6V < V < 30V (LTC3727)

0.05

0.2

0.3

%

3.3VL

IN

6V < V < 30V (LTC3727-1)

IN

PGOOD Output

V

PGOOD Voltage Low

I

= 2mA

= 5V

0.1

0.3

V

PGL

PGOOD

I

PGOOD Leakage Current

PGOOD Trip Level, Either Controller

V

±1

μA

PGOOD

V

with Respect to Set Output Voltage

Ramping Negative

Ramping Positive

PG

OSENSE

V

–6

6

–7.5

7.5

–9.5

9.5

%

OSENSE

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

LTC3727EG/LTC3727EG-1/LTC3727IG-1: T = T + (P • 95 °C/W)

J A D

LTC3727EUH-1: T = T + (P • 34 °C/W)

J

A

D

Note 4: The LTC3727/LTC3727-1 are tested in a feedback loop that servos

to a specified voltage and measures the resultant V

V

ITH1, 2

OSENSE1, 2.

Note 2: The LTC3727E/LTC3727E-1 are guaranteed to meet performance

specifications from 0°C to 85°C. Specifications over the –40°C to 85°C

operating temperature range are assured by design, characterization and

correlation with statistical process controls. The LTC3727IG-1 is

guaranteed to meet performance specifications over the –40°C to 85°C

operating temperature range.

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications Information.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.

Note 7: The minimum on-time condition is specified for an inductor

peak-to-peak ripple current ≥40% of I

(see minimum on-time

considerations in the Applications Information section).

MAX

Note 3: T is calculated from the ambient temperature T and power

J

A

dissipation P according to the following formulas:

D

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Efficiency vs Output Current

and Mode (Figure 13)

Efficiency vs Output Current

(Figure 13)

Efficiency vs Input Voltage

(Figure 13)

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

100

90

80

70

60

50

V

= 5V

= 3A

Burst Mode

OPERATION

OUT

V

= 7V

IN

I

FORCED

CONTINUOUS

V

= 10V

IN

MODE

V

= 15V

IN

V

= 20V

IN

CONSTANT

FREQUENCY

(BURST DISABLE)

V

= 15V

= 8.5V

IN

OUT

V

OUT

= 5V

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

5

15

25

35

10

OUTPUT CURRENT (A)

INPUT VOLTAGE (V)

3727 G01

3727 G02

3727 G03

3727fc

4

LTC3727/LTC3727-1

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Supply Current vs Input Voltage

and Mode (Figure 13)

Internal 7.5V LDO Line Regulation

EXTV Voltage Drop

CC

1000

800

600

400

200

0

7.7

160

140

120

100

I

= 1mA

V

= 8.5V

LOAD

EXTVCC

7.6

7.5

7.4

7.3

7.2

7.1

7.0

6.9

BOTH

CONTROLLERS ON

80

60

40

20

0

SHUTDOWN

20

6.8

0

10

30

0

10

20

CURRENT (mA)

40

50

30

0

5

10

15

35

20

25

30

INPUT VOLTAGE (V)

3727 G04

3727 G05

3727 G06

Maximum Current Sense Threshold

vs Percent of Nominal Output

Voltage (Foldback)

Maximum Current Sense Threshold

vs V (Soft-Start)

Maximum Current Sense Threshold

vs Duty Factor

RUN/SS

= 1.6V

150

125

150

125

100

75

150

135

120

105

90

V

SENSE(CM)

100

75

60

50

25

0

45

30

15

50

0

20

40

60

80

100

0

1

2

3

4

5

6

0

20

40

60

80

100

V

(V)

DUTY FACTOR (%)

RUN/SS

PERCENT OF NOMINAL OUTPUT VOLTAGE (%)

3727 G07

3727 G09

3727 G08

Current Sense Threshold

vs I Voltage

Load Regulation

V

vs V

ITH

TH

RUN/SS

0.0

–0.1

–0.2

–0.3

–0.4

2.5

2.0

1.5

1.0

150

125

100

75

V

= 0.7V

FCB = 0V

OSENSE

V

= 15V

IN

FIGURE 1

50

25

0

–25

–50

0.5

0

0.5

1.0

2.0

1

3

0

2

3

4

5

6

0

2.5

0

2

4

5

1.5

(V)

1

V

(V)

V

LOAD CURRENT (A)

RUN/SS

ITH

3727 G10

3727 G11

3727 G12

3727fc

5

LTC3727/LTC3727-1

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TYPICAL PERFOR A CE CHARACTERISTICS

Dropout Voltage vs Output Current

(Figure 13)

RUN/SS Current vs Temperature

SENSE Pins Total Source Current

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

100

50

1.4

1.2

V

= 5V

OUT

0

–50

1.0

0.8

0.6

0.4

0.2

0

R

= 0.015Ω

SENSE

–100

–150

–200

–250

–300

–350

–400

= 0.010Ω

SENSE

3

0

10

5

COMMON MODE VOLTAGE (V)

15

0

1

2

4

5

–50 –25

0

25

125

50

75 100

V

TEMPERATURE (°C)

OUTPUT CURRENT (A)

SENSE

3727 G13

3727 G14

3727 G15

Soft-Start Up (Figure 12)

Load Step (Figure 12)

I_OUT

*

V_OUT

200mV/DIV

5A/DIV

V_OUT

200mV/DIV

V_OUT

5V/DIV

I_OUT

*

I_OUT

*

V_RUN/SS

5V/DIV

2A/DIV

V_IN= 20V

V_OUT= 12V

50ms/DIV

3727 G16

V_IN= 15V

V_OUT= 12V

50μs/DIV

3727 G17

V_IN= 15V

V_OUT= 12V

50μs/DIV

3727 G18

LOAD STEP = 0A TO 3A

Burst Mode OPERATION

LOAD STEP = 0A TO 3A

CONTINUOUS MODE

Input Source/Capacitor

Instantaneous Current (Figure 12)

Constant Frequency (Burst Inhibit)

Operation (Figure 12)

Burst Mode Operation (Figure 12)

I_IN

1A/DIV

V_OUT

20mV/DIV

V_OUT

20mV/DIV

V_SW1

20V/DIV

V_SW2

20V/DIV

I_OUT

*

I_OUT

*

0.5A/DIV

V_IN= 15V

1μs/DIV

3727 G19

V

_IN= 15V

V_OUT= 12V

_FCB= OPEN

I_OUT= 20mA

50μs/DIV

3727 G20

V

_IN= 15V

V_OUT= 12V

_FCB= 7.5V

I_OUT= 20mA

5μs/DIV

3727 G21

V_OUT1= 12V

V_OUT2= 5V

V

I_OUT1= I_OUT2= 2A

*I_OUT⇒ INDUCTOR CURRENT

3727fc

6

LTC3727/LTC3727-1

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Current Sense Pin Input Current

vs Temperature

EXTV Switch Resistance

Oscillator Frequency

vs Temperature

CC

vs Temperature

10

8

35

33

31

29

27

25

700

600

V

= 5V

OUT

V

= 5V

PLLFLTR

500

400

300

200

100

V

= 1.2V

= 0V

6

PLLFLTR

V

4

PLLFLTR

2

0

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75

100 125

TEMPERATURE (°C)

3727 G23

3727 G22

3727 G24

Undervoltage Lockout

vs Temperature

Shutdown Latch Thresholds

vs Temperature

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

3.50

3.45

3.40

3.35

LATCH ARMING

LATCHOFF

THRESHOLD

3.30

3.25

3.20

LTC3727 ONLY

0

50

100 125

–50 –25

0

25

125

–50 –25

0

25

75

50

75 100

TEMPERATURE (°C)

3727 G25

3727 G26

U

PI FU CTIO S ^{G Package/UH Package}

RUN/SS1, RUN/SS2 (Pins 1, 15/Pins 28, 13): Combina-

tion of Soft-Start, Run Control Inputs and Short-Circuit

DetectionTimers(LTC3727only).Acapacitortogroundat

eachofthesepinssetstheramptimetofulloutputcurrent.

Forcing either of these pins back below 1.0V causes the IC

to shut down the circuitry required for that particular

controller. Latchoff overcurrent protection is also invoked

via this pin as described in the Applications Information

section (LTC3727 only).

SENSE1⁺, SENSE2⁺(Pins 2, 14/Pins 30, 12): The (+)

Input to the Differential Current Comparators. The I_THpin

voltage and controlled offsets between the SENSE^–and

SENSE⁺pins in conjunction with R_SENSEset the current

trip threshold.

SENSE1^–, SENSE2^–(Pins 3, 13/Pins 31, 11): The (–)

Input to the Differential Current Comparators.

V_OSENSE1, V_OSENSE2(Pins 4, 12/Pins 1, 9): Receives the

remotely-sensedfeedbackvoltageforeachcontrollerfrom

an external resistive divider across the output.

3727fc

7

LTC3727/LTC3727-1

U

PI FU CTIO S

PLLFLTR (Pin 5/Pin 2): The phase-locked loop’s lowpass

filter is tied to this pin. Alternatively, this pin can be driven

with an AC or DC voltage source to vary the frequency of

the internal oscillator.

EXTV_CC(Pin 22/Pin 21): External Power Input to an

Internal Switch Connected to INTV_CC. This switch closes

and supplies V_CCpower, bypassing the internal low drop-

out regulator, whenever EXTV_CCis higher than 7.3V. See

EXTV_CCconnectioninApplicationssection. Donotexceed

8.5V on this pin.

PLLIN (Pin 6/Pin 3): External Synchronization Input to

Phase Detector. This pin is internally terminated to SGND

with 50kΩ. The phase-locked loop will force the rising top

gate signal of controller 1 to be synchronized with the

rising edge of the PLLIN signal.

BG1, BG2 (Pins 23, 19/Pins 22, 18): High Current Gate

Drives for Bottom (Synchronous) N-Channel MOSFETs.

Voltage swing at these pins is from ground to INTV_CC.

FCB(Pin7/Pin4):ForcedContinuousControl Input.This

input acts on both controllers and is normally used to

regulateasecondarywinding. Pullingthispinbelow0.8V

will force continuous synchronous operation. Do not

leave this pin floating.

V_IN(Pin 24/Pin 23): Main Supply Pin. A bypass capacitor

should be tied between this pin and the signal ground pin.

BOOST1,BOOST2(Pins25,18/Pins24,17):Bootstrapped

Supplies to the Top Side Floating Drivers. Capacitors are

connected between the boost and switch pins and Schot-

tky diodes are tied between the boost and INTV_CCpins.

Voltage swing at the boost pins is from INTV_CCto (V_IN+

INTV_CC).

I_{TH1, TH2}(Pins 8, 11/Pins 5, 8): Error Amplifier Outputs

I

and Switching Regulator Compensation Points. Each as-

sociatedchannels’currentcomparatortrippointincreases

with this control voltage.

SW1, SW2 (Pins 26, 17/Pins 25, 15): Switch Node

Connections to Inductors. Voltage swing at these pins is

from a Schottky diode (external) voltage drop below

ground to V_IN.

SGND (Pin 9/Pin 6): Small Signal Ground. Common

to both controllers; must be routed separately from

high current grounds to the common (–) terminals

of the C_OUTcapacitors.

TG1, TG2 (Pins 27, 16/Pins 26, 14): High Current Gate

DrivesforTopN-ChannelMOSFETs.Thesearetheoutputs

3.3V_OUT(Pin 10/Pin 7): Linear Regulator Output. Capable

of supplying 10mA DC with peak currents as high as

50mA.

of floating drivers with a voltage swing equal to INTV_CC

0.5V superimposed on the switch node voltage SW.

–

PGND(Pin20/Pin19):DriverPowerGround.Connectstothe

sources of bottom (synchronous) N-channel MOSFETs, an-

odes of the Schottky rectifiers and the (–) terminal(s) of C_IN.

PGOOD(Pin28/Pin27):Open-DrainLogicOutput.PGOOD

is pulled to ground when the voltage on either V_OSENSEpin

is not within ±7.5% of its set point.

INTV_CC(Pin 21/Pin 20): Output of the Internal 7.5V Linear

Low Dropout Regulator and the EXTV_CCSwitch. The driver

and control circuits are powered from this voltage source.

Mustbedecoupledtopowergroundwithaminimumof4.7μF

tantalum or other low ESR capacitor.

Exposed Pad (Pin 33, UH Package): Signal Ground. Must

be soldered to the PCB ground for electrical contact and

optimum thermal performance.

3727fc

8

LTC3727/LTC3727-1

U

W

FU CTIO AL DIAGRA

PLLIN

INTV

V

IN

CC

F

PHASE DET

IN

D

C

B

DUPLICATE FOR SECOND

CONTROLLER CHANNEL

50k

BOOST

TG

PLLFLTR

B

DROP

OUT

+

CLK1

CLK2

–

TOP

BOT

R

LP

C

IN

D

OSCILLATOR

1

DET

BOT

FCB

C

LP

SW

TOP ON

0.86V

S

Q

+

SWITCH

LOGIC

INTV

CC

R

V

OSENSE1

PGOOD

BG

–

+

0.74V

0.86V

C

OUT

PGND

B

+

–

0.55V

–

+

V

OUT

SHDN

R

SENSE

V

OSENSE2

–

+

INTV

CC

0.74V

BINH

I1

I2

V

1.5V

SEC

+

–

+

–

+

7V

–

+ +

–

+

0.18μA

FCB

–

SENSE

D

C

SEC

50k

R6

3mV

0.86V

4(V

–

)

+

–

FB

FCB

R5

SLOPE

COMP

25k

2.4V

3.3V

V

0.8V

OUT

OSENSE

R2

V

+

–

V

FB

REF

–

EA

+

0.80V

0.86V

R1

OV

V

IN

+

–

V

IN

C

+

–

7.3V

I

TH

7.5V

LDO

REG

1.2μA

EXTV

INTV

CC

SHDN

RST

RUN

SOFT

START

R

C

C2

SS

6V

4(V

)

FB

CC

7.5V

+

RUN/SS

INTERNAL

SUPPLY

SGND

C

3727 F02

Figure 2

U

OPERATIO

(Refer to Functional Diagram)

Main Control Loop

the voltage feedback signal, which is compared to the

internalreferencevoltagebytheEA. Whentheloadcurrent

increases, itcausesaslightdecreaseinV_OSENSErelativeto

the 0.8V reference, which in turn causes the I_THvoltage to

increase until the average inductor current matches the

new load current. After the top MOSFET has turned off, the

bottom MOSFET is turned on until either the inductor

currentstartstoreverse, asindicatedbycurrentcompara-

tor I₂, or the beginning of the next cycle.

The LTC3727/LTC3727-1 use a constant frequency, cur-

rent mode step-down architecture with the two controller

channels operating 180 degrees out of phase. During

normaloperation, eachtopMOSFETisturnedonwhenthe

clock for that channel sets the RS latch, and turned off

when the main current comparator, I₁, resets the RS latch.

The peak inductor current at which I₁resets the RS latch

is controlled by the voltage on the I_THpin, which is the

outputofeacherroramplifierEA.TheV_OSENSEpinreceives

3727fc

9

LTC3727/LTC3727-1

U

OPERATIO

(Refer to Functional Diagram)

The top MOSFET drivers are biased from floating boot-

strap capacitor C_B, which normally is recharged during

each off cycle through an external diode when the top

MOSFET turns off. As V_INdecreases to a voltage close to

V_OUT, the loop may enter dropout and attempt to turn on

the top MOSFET continuously. The dropout detector de-

tects this and forces the top MOSFET off for about 400ns

every tenth cycle to allow C_Bto recharge.

having the hysteretic comparator follow the error ampli-

fier gain block.

Frequency Synchronization

The phase-locked loop allows the internal oscillator to be

synchronized to an external source via the PLLIN pin. The

outputofthephasedetectoratthePLLFLTRpinisalsothe

DC frequency control input of the oscillator that operates

over a 250kHz to 550kHz range corresponding to a DC

voltage input from 0V to 2.4V. When locked, the PLL

aligns the turn on of the top MOSFET to the rising edge of

the synchronizing signal. When PLLIN is left open, the

PLLFLTR pin goes low, forcing the oscillator to its mini-

mum frequency.

The main control loop is shut down by pulling the RUN/SS

pin low. Releasing RUN/SS allows an internal 1.2μA

current source to charge soft-start capacitor C_SS. When

C_SSreaches1.5V,themaincontrolloopisenabledwiththe

I_THvoltageclampedatapproximately30%ofitsmaximum

value. As C_SScontinues to charge, the I_THpin voltage is

gradually released allowing normal, full-current opera-

tion. When both RUN/SS1 and RUN/SS2 are low, all

LTC3727/LTC3727-1 controller functions are shut down,

including the 7.5V and 3.3V regulators.

Continuous Current (PWM) Operation

Tying the FCB pin to ground will force continuous current

operation. This is the least efficient operating mode, but

may be desirable in certain applications. The output can

source or sink current in this mode. When sinking current

while in forced continuous operation, current will be

forced back into the main power supply potentially boost-

ing the input supply to dangerous voltage levels—

BEWARE!

Low Current Operation

The FCB pin is a multifunction pin providing two func-

tions:1)toprovideregulationforasecondarywindingby

temporarily forcing continuous PWM operation on

both controllers; and 2) to select between two modes of

low current operation. When the FCB pin voltage is below

0.8V, the controller forces continuous PWM current

mode operation. In this mode, the top and bottom

MOSFETsarealternatelyturnedontomaintaintheoutput

voltage independent of direction of inductor current.

When the FCB pin is below V_INTVCC– 2V but greater than

0.8V, the controller enters Burst Mode operation. Burst

Mode operation sets a minimum output current level

beforeinhibitingthetopswitchandturnsoffthesynchro-

nous MOSFET(s) when the inductor current goes nega-

tive. This combination of requirements will, at low cur-

rents, force the I_THpin below a voltage threshold that will

temporarily inhibit turn-on of both output MOSFETs until

the output voltage drops. There is 60mV of hysteresis in

the burst comparator B tied to the I_THpin. This hysteresis

produces output signals to the MOSFETs that turn them

on for several cycles, followed by a variable “sleep”

interval depending upon the load current. The resultant

output voltage ripple is held to a very small value by

INTV_CC/EXTV_CCPower

Power for the top and bottom MOSFET drivers and most

other internal circuitry is derived from the INTV_CCpin.

When the EXTV_CCpin is left open, an internal 7.5V low

dropoutlinearregulatorsuppliesINTV_CCpower.IfEXTV_CC

is taken above 7.3V, the 7.5V regulator is turned off and an

internalswitchisturnedonconnectingEXTV_CCtoINTV_CC.

This allows the INTV_CCpower to be derived from a high

efficiency external source such as the output of the regu-

lator itself or a secondary winding, as described in the

Applications Information section.

Output Overvoltage Protection

An overvoltage comparator, OV, guards against transient

overshoots (>7.5%) as well as other more serious condi-

tions that may overvoltage the output. In this case, the top

MOSFETisturnedoffandthebottomMOSFETisturnedon

until the overvoltage condition is cleared.

3727fc

10

LTC3727/LTC3727-1

U

OPERATIO

(Refer to Functional Diagram)

Power Good (PGOOD) Pin

THEORY AND BENEFITS OF 2-PHASE OPERATION

ThePGOODpinisconnectedtoanopendrainofaninternal

MOSFET.TheMOSFETturnsonandpullsthepinlowwhen

either output is not within ±7.5% of the nominal output

level as determined by the resistive feedback divider.

When both outputs meet the ±7.5% requirement, the

MOSFET is turned off within 10μs and the pin is allowed to

be pulled up by an external resistor to a source of up to 7V.

The LTC3727 dual high efficiency DC/DC controller brings

the considerable benefits of 2-phase operation to portable

applications. Notebook computers, PDAs, handheld ter-

minals and automotive electronics will all benefit from the

lower input filtering requirement, reduced electromag-

netic interference (EMI) and increased efficiency associ-

ated with 2-phase operation.

Why the need for 2-phase operation? Until recently, con-

stant-frequency dual switching regulators operated both

channels in phase (i.e., single-phase operation). This

means that both switches turned on at the same time,

causing current pulses of up to twice the amplitude of

those for one regulator to be drawn from the input capaci-

tor and battery. These large amplitude current pulses

increased the total RMS current flowing from the input

capacitor, requiring the use of more expensive input

capacitorsandincreasingbothEMIandlossesintheinput

capacitor and battery.

Foldback Current, Short-Circuit Detection

and Short-Circuit Latchoff (LTC3727 Only)

TheRUN/SScapacitorsareusedinitiallytolimittheinrush

current of each switching regulator. After the controller

has been started and been given adequate time to charge

up the output capacitors and provide full load current, the

RUN/SS capacitor is used in a short-circuit time-out

circuit. If the output voltage falls to less than 70% of its

nominal output voltage, the RUN/SS capacitor begins

discharging on the assumption that the output is in an

overcurrent and/or short-circuit condition. If the condi-

tion lasts for a long enough period as determined by the

size of the RUN/SS capacitor, the controller will be shut

down until the RUN/SS pin(s) voltage(s) are recycled.

This built-in latchoff can be overridden by providing a

>5μA pull-up at a compliance of 5V to the RUN/SS pin(s).

This current shortens the soft start period but also pre-

vents net discharge of the RUN/SS capacitor(s) during an

overcurrent and/or short-circuit condition. Foldback cur-

rent limiting is also activated when the output voltage falls

below 70% of its nominal level whether or not the short-

circuit latchoff circuit is enabled. Even if a short is present

and the short-circuit latchoff is not enabled, a safe, low

outputcurrentisprovidedduetointernalcurrentfoldback

and actual power wasted is low due to the efficient nature

of the current mode switching regulator.

With 2-phase operation, the two channels of the dual-

switching regulator are operated 180 degrees out of

phase. This effectively interleaves the current pulses

drawn by the switches, greatly reducing the overlap time

where they add together. The result is a significant reduc-

tion in total RMS input current, which in turn allows less

expensive input capacitors to be used, reduces shielding

requirements for EMI and improves real world operating

efficiency.

Figure 3 compares the input waveforms for a representa-

tive single-phase dual switching regulator to the new

LTC3727 2-phase dual switching regulator. An actual

measurement of the RMS input current under these con-

ditions shows that 2-phase operation dropped the input

current from 2.53A_RMSto 1.55A_RMS. While this is an

impressive reduction in itself, remember that the power

losses are proportional to I_RMS², meaning that the actual

power wasted is reduced by a factor of 2.66. The reduced

input ripple voltage also means less power is lost in the

PART NUMBER

LTC3727

FUNCTION

With Latchoff Function Available

Latchoff Always Disabled

LTC3727-1

3727fc

11

LTC3727/LTC3727-1

U

OPERATIO

(Refer to Functional Diagram)

5V SWITCH

20V/DIV

3.3V SWITCH

20V/DIV

INPUT CURRENT

5A/DIV

INPUT VOLTAGE

500mV/DIV

I_IN(MEAS)= 2.53A_RMS

I_IN(MEAS)= 1.55A_RMS

3727 F03a

3727 F03b

(b)

(a)

Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for

Dual Switching Regulators Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input

Ripple with the LTC3727 2-Phase Regulator Allows Less Expensive Input Capacitors,

Reduces Shielding Requirements for EMI and Improves Efficiency

inputpowerpath, whichcouldincludebatteries, switches,

require an oscillator derived “slope compensation” signal

to allow stable operation of each regulator at over 50%

duty cycle. This signal is relatively easy to derive in single-

phasedualswitchingregulators,butrequiredthedevelop-

ment of a new and proprietary technique to allow 2-phase

operation. In addition, isolation between the two channels

becomes more critical with 2-phase operation because

switch transitions in one channel could potentially disrupt

the operation of the other channel.

trace/connector resistances and protection circuitry. Im-

provements in both conducted and radiated EMI also

directly accrue as a result of the reduced RMS input

current and voltage.

Of course, the improvement afforded by 2-phase opera-

tion is a function of the dual switching regulator’s relative

duty cycles which, in turn, are dependent upon the input

voltage V_IN(Duty Cycle = V_OUT/V_IN). Figure 4 shows how

theRMSinputcurrentvariesforsingle-phaseand2-phase

operation for 3.3V and 5V regulators over a wide input

voltage range.

3.0

SINGLE PHASE

DUAL CONTROLLER

2.5

2.0

1.5

1.0

0.5

0

It can readily be seen that the advantages of 2-phase

operation are not just limited to a narrow operating range,

but in fact extend over a wide region. A good rule of thumb

for most applications is that 2-phase operation will reduce

theinputcapacitorrequirementtothatforjustonechannel

operating at maximum current and 50% duty cycle.

2-PHASE

DUAL CONTROLLER

V

= 5V/3A

O1

O2

A final question: If 2-phase operation offers such an

advantage over single-phase operation for dual switching

regulators, why hasn’t it been done before? The answer is

that, while simple in concept, it is hard to implement.

Constant-frequency current mode switching regulators

= 3.3V/3A

0

10

20

30

40

INPUT VOLTAGE (V)

3727 F04

Figure 4. RMS Input Current Comparison

3727fc

12

LTC3727/LTC3727-1

W U U

APPLICATIO S I FOR ATIO

Figure 1 on the first page is a basic LTC3727/LTC3727-1

applicationcircuit.Externalcomponentselectionisdriven

by the load requirement, and begins with the selection of

U

2.5

2.0

1.5

1.0

0.5

0

R

_SENSEandtheinductorvalue.Next,thepowerMOSFETs

and D1 are selected. Finally, C_INand C_OUTare selected.

The circuit shown in Figure 1 can be configured for

operation up to an input voltage of 28V (limited by the

external MOSFETs).

R_SENSESelection For Output Current

200 250 300 350 400 450 500 550

OPERATING FREQUENCY (kHz)

R_SENSEis chosen based on the required output current.

3727 F05

The LTC3727 current comparator has a maximum thresh-

old of 135mV/R_SENSEand an input common mode range

of SGND to 14V. The current comparator threshold sets

the peak of the inductor current, yielding a maximum

average output current I_MAXequal to the peak value less

half the peak-to-peak ripple current, ΔI_L.

Figure 5. PLLFLTR Pin Voltage vs Frequency

isincreasedthegatechargelosseswillbehigher,reducing

efficiency (see Efficiency Considerations). The maximum

switching frequency is approximately 550kHz.

Allowing a margin for variations in the LTC3727 and

external component values yields:

Inductor Value Calculation

90mV

I_MAX

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efficiency. A higher

frequency generally results in lower efficiency because of

MOSFET gate charge losses. In addition to this basic

trade-off, the effect of inductor value on ripple current and

low current operation must also be considered.

R_SENSE

=

When using the controller in very low dropout conditions,

the maximum output current level will be reduced due to

the internal compensation required to meet stability crite-

rion for buck regulators operating at greater than 50%

duty factor. A curve is provided to estimate this reducton

in peak output current level depending upon the operating

duty factor.

Theinductorvaluehasadirecteffectonripplecurrent.The

inductor ripple current ΔI_Ldecreases with higher induc-

tance or frequency and increases with higher V_IN:

Operating Frequency

The LTC3727 uses a constant frequency phase-lockable

architecture with the frequency determined by an internal

capacitor. This capacitor is charged by a fixed current plus

an additional current which is proportional to the voltage

applied to the PLLFLTR pin. Refer to Phase-Locked Loop

and Frequency Synchronization in the Applications Infor-

mation section for additional information.

1

⎛

⎝

V_OUT

V

IN

⎞

ΔI_L=

V_OUT1–

⎜

⎟

⎠

(f)(L)

Accepting larger values of ΔI_Lallows the use of low

inductances, but results in higher output voltage ripple

and greater core losses. A reasonable starting point for

settingripplecurrentisΔI_L=0.3(I_MAX). ThemaximumΔI_L

occurs at the maximum input voltage.

A graph for the voltage applied to the PLLFLTR pin vs

frequency is given in Figure 5. As the operating frequency

3727fc

13

LTC3727/LTC3727-1

W U U

U

APPLICATIO S I FOR ATIO

The inductor value also has secondary effects. The transi-

tion to Burst Mode operation begins when the average

inductor current required results in a peak current below

25% of the current limit determined by R_SENSE. Lower

inductor values (higher ΔI_L) will cause this to occur at

lower load currents, which can cause a dip in efficiency in

the upper range of low current operation. In Burst Mode

operation, lower inductance values will cause the burst

frequency to decrease.

The peak-to-peak drive levels are set by the INTV_CC

voltage.Thisvoltageistypically7.5Vduringstart-up(see

EXTV_CCPin Connection). Consequently, logic-level

threshold MOSFETs must be used in most applications.

The only exception is if low input voltage is expected

(V_IN< 5V); then, sub-logic level threshold MOSFETs

(V_GS(TH)< 3V) should be used. Pay close attention to the

BV_DSSspecification for the MOSFETs as well; most of the

logic level MOSFETs are limited to 30V or less.

SelectioncriteriaforthepowerMOSFETsincludethe“ON”

Inductor Core Selection

resistance R_DS(ON), reverse transfer capacitance C_RSS

,

Once the inductance value is determined, the type of

inductormustbeselected.Actualcorelossisindependent

of core size for a fixed inductor value, but it is very

dependent on inductance selected. As inductance in-

creases, core losses go down. Unfortunately, increased

inductance requires more turns of wire and therefore

copper (I²R) losses will increase.

input voltage and maximum output current. When the

LTC3727 is operating in continuous mode the duty cycles

for the top and bottom MOSFETs are given by:

V_OUT

V

IN

Main SwitchDuty Cycle =

V – V_OUT

IN

Synchronous SwitchDuty Cycle =

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so designers can concen-

trate on reducing I²R loss and preventing saturation.

Ferrite core material saturates “hard,” which means that

inductance collapses abruptly when the peak design cur-

rent is exceeded. This results in an abrupt increase in

inductor ripple current and consequent output voltage

ripple. Do not allow the core to saturate!

V

IN

The MOSFET power dissipations at maximum output

current are given by:

V_OUT

V

IN

2

P_MAIN

=

I

1+ δ R

+

(

_MAX) (

)

DS(ON)

2

k V

I

C

f

(

_IN) ( _MAX)( _RSS)( )

Different core materials and shapes will change the size/

current and price/current relationship of an inductor.

Toroid or shielded pot cores in ferrite or permalloy mate-

rials are small and don’t radiate much energy, but gener-

ally cost more than powdered iron core inductors with

similar characteristics. The choice of which style inductor

to use mainly depends on the price vs size requirements

and any radiated field/EMI requirements. New designs for

high current surface mount inductors are available from

numerous manufacturers, including Coiltronics, Vishay,

TDK,Pulse,Panasonic,Wuerth,Coilcraft,TokoandSumida.

V – V_OUT

2

IN

P_SYNC

=

I

1+ δ R

(

_MAX) (

)

DS(ON)

V

IN

where δ is the temperature dependency of R_DS(ON)and k

is a constant inversely related to the gate drive current.

BothMOSFETshaveI²RlosseswhilethetopsideN-channel

equation includes an additional term for transition losses,

which are highest at high input voltages. For V_IN< 20V the

high current efficiency generally improves with larger

MOSFETs, while for V_IN> 20V the transition losses rapidly

increasetothepointthattheuseofahigherR_DS(ON)device

with lower C_RSSactually provides higher efficiency. The

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during a

Power MOSFET and D1 Selection

Two external power MOSFETs must be selected for each

controller in the LTC3727: One N-channel MOSFET for the

top (main) switch, and one N-channel MOSFET for the

bottom (synchronous) switch.

3727fc

14

LTC3727/LTC3727-1

W U U

APPLICATIO S I FOR ATIO

U

short-circuit when the synchronous switch is on close to

the capacitor is important for capacitor power dissipation

as well as overall battery efficiency. All of the power (RMS

ripple current • ESR) not only heats up the capacitor but

wastes power from the battery.

100% of the period.

Theterm(1+δ)isgenerallygivenforaMOSFETintheform

of a normalized R_DS(ON)vs Temperature curve, but

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs. C_RSSis usually specified in the MOS-

FET characteristics. The constant k = 1.7 can be used to

estimate the contributions of the two terms in the main

switch dissipation equation.

Medium voltage (20V to 35V) ceramic, tantalum, OS-CON

and switcher-rated electrolytic capacitors can be used as

inputcapacitors,buteachhasdrawbacks:ceramicvoltage

coefficients are very high and may have audible piezoelec-

tric effects; tantalums need to be surge-rated; OS-CONs

suffer from higher inductance, larger case size and limited

surface-mount applicability; electrolytics’ higher ESR and

dryout possibility require several to be used. Multiphase

systems allow the lowest amount of capacitance overall.

As little as one 22μF or two to three 10μF ceramic capaci-

tors are an ideal choice in a 20W to 35W power supply due

to their extremely low ESR. Even though the capacitance

at 20V is substantially below their rating at zero-bias, very

low ESR loss makes ceramics an ideal candidate for

highest efficiency battery operated systems. Also con-

sider parallel ceramic and high quality electrolytic capaci-

tors as an effective means of achieving ESR and bulk

capacitance goals.

The Schottky diode D1 shown in Figure 2 conducts during

the dead-time between the conduction of the two power

MOSFETs. This prevents the body diode of the bottom

MOSFET from turning on, storing charge during the dead-

time and requiring a reverse recovery period that could

cost as much as 3% in efficiency at high V_IN. A 1A to 3A

Schottky is generally a good compromise for both regions

of operation due to the relatively small average current.

Larger diodes result in additional transition losses due to

their larger junction capacitance. Schottky diodes should

beplacedinparallelwiththesynchronousMOSFETswhen

operating in pulse-skip mode or in Burst Mode operation.

C_INand C_OUTSelection

Incontinuousmode, thesourcecurrentofthetopN-chan-

nel MOSFET is a square wave of duty cycle V_OUT/V_IN. To

preventlargevoltagetransients, alowESRinputcapacitor

sized for the maximum RMS current of one channel must

beused. ThemaximumRMScapacitorcurrentisgivenby:

The selection of C_INis simplified by the multiphase archi-

tecture and its impact on the worst-case RMS current

drawnthroughtheinputnetwork(battery/fuse/capacitor).

It can be shown that the worst case RMS current occurs

when only one controller is operating. The controller with

the highest (V_OUT)(I_OUT) product needs to be used in the

formula below to determine the maximum RMS current

requirement. Increasing the output current, drawn from

the other out-of-phase controller, will actually decrease

the input RMS ripple current from this maximum value

(see Figure 4). The out-of-phase technique typically re-

duces the input capacitor’s RMS ripple current by a factor

of 30% to 70% when compared to a single phase power

supply solution.

1/2

]

V

V − V

OUT

(

)

[

OUT IN

C_INRequiredI_RMS≅ I_MAX

V

IN

This formula has a maximum at V_IN= 2V_OUT, where

I_RMS= I_OUT/2. This simple worst case condition is com-

monlyusedfordesignbecauseevensignificantdeviations

donotoffermuchrelief.Notethatcapacitormanufacturer’s

ripple current ratings are often based on only 2000 hours

of life. This makes it advisable to further derate the

capacitor, or to choose a capacitor rated at a higher

temperaturethanrequired.Severalcapacitorsmayalsobe

paralleled to meet size or height requirements in the

design. Always consult the manufacturer if there is any

question.

The type of input capacitor, value and ESR rating have

efficiency effects that need to be considered in the selec-

tion process. The capacitance value chosen should be

sufficient to store adequate charge to keep high peak

battery currents down. 22μF to 47μF is usually sufficient

for a 25W output supply operating at 250kHz. The ESR of

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The benefit of the LTC3727 multiphase can be calculated

by using the equation above for the higher power control-

ler and then calculating the loss that would have resulted

if both controller channels switch on at the same time. The

total RMS power lost is lower when both controllers are

operatingduetotheinterleavingofcurrentpulsesthrough

theinputcapacitor’sESR. Thisiswhytheinputcapacitor’s

requirement calculated above for the worst-case control-

ler is adequate for the dual controller design. Remember

that input protection fuse resistance, battery resistance

and PC board trace resistance losses are also reduced due

to the reduced peak currents in a multiphase system. The

overall benefit of a multiphase design will only be fully

realized when the source impedance of the power supply/

battery is included in the efficiency testing. The drains of

thetwotopMOSFETSshouldbeplacedwithin1cmofeach

other and share a common C_IN(s). Separating the drains

and C_INmay produce undesirable voltage and current

resonances at V_IN.

discharging term but can be compensated for by using

capacitors of very low ESR to maintain the ripple voltage

at or below 50mV. The I_THpin OPTI-LOOP compensation

components can be optimized to provide stable, high

performance transient response regardless of the output

capacitors selected.

Manufacturers such as Nichicon, Nippon Chemi-Con and

Sanyo can be considered for high performance through-

hole capacitors. The OS-CON semiconductor dielectric

capacitor available from Sanyo has the lowest (ESR)(size)

product of any aluminum electrolytic at a somewhat

higher price. An additional ceramic capacitor in parallel

with OS-CON capacitors is recommended to reduce the

inductance effects.

In surface mount applications multiple capacitors may

need to be used in parallel to meet the ESR, RMS current

handling and load step requirements of the application.

Aluminum electrolytic, dry tantalum and special polymer

capacitors are available in surface mount packages. Spe-

cial polymer surface mount capacitors offer very low ESR

buthavelowerstoragecapacityperunitvolumethanother

capacitor types. These capacitors offer a very cost-effec-

tiveoutputcapacitorsolutionandareanidealchoicewhen

combined with a controller having high loop bandwidth.

Tantalum capacitors offer the highest capacitance density

and are often used as output capacitors for switching

regulators having controlled soft-start. Several excellent

surge-tested choices are the AVX TPS, AVX TPS Series III

or the KEMET T510 series of surface mount tantalums,

available in case heights ranging from 1.2mm to 4.1mm.

Aluminum electrolytic capacitors can be used in cost-

driven applications providing that consideration is given

to ripple current ratings, temperature and long term reli-

ability. A typical application will require several to many

aluminum electrolytic capacitors in parallel. A combina-

tion of the above mentioned capacitors will often result in

maximizingperformanceandminimizingoverallcost.Other

capacitor types include Nichicon PL series, NEC Neocap,

Cornell Dubilier ESRE and Sprague 595D series. Consult

manufacturers for other specific recommendations.

The selection of C_OUTis driven by the required effective

series resistance (ESR). Typically once the ESR require-

ment is satisfied the capacitance is adequate for filtering.

The output ripple (ΔV_OUT) is determined by:

⎛

⎝

1

⎞

ΔV_OUT≅ ΔI ESR +

⎜

⎟

⎠

L

8fC_OUT

Where f = operating frequency, C_OUT= output capaci-

tance, and ΔI_L= ripple current in the inductor. The output

ripple is highest at maximum input voltage since ΔI_L

increases with input voltage. With ΔI_L= 0.3I_OUT(MAX)the

output ripple will typically be less than 50mV at max V_IN

assuming:

C_OUTRecommended ESR < 2 R_SENSE

and C_OUT> 1/(8fR_SENSE

)

The first condition relates to the ripple current into the

ESR of the output capacitance while the second term

guarantees that the output capacitance does not signifi-

cantly discharge during the operating frequency period

due to ripple current. The choice of using smaller output

capacitance increases the ripple voltage due to the

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U

INTV_CCRegulator

EXTV_CCConnection

An internal P-channel low dropout regulator produces

7.5V at the INTV_CCpin from the V_INsupply pin. INTV_CC

powers the drivers and internal circuitry within the

LTC3727. The INTV_CCpin regulator can supply a peak

current of 50mA and must be bypassed to ground with a

minimumof4.7μFtantalum,10μFspecialpolymer,orlow

ESR type electrolytic capacitor. A 1μF ceramic capacitor

placed directly adjacent to the INTV_CCand PGND IC pins

is highly recommended. Good bypassing is necessary to

supplythehightransientcurrentsrequiredbythe MOSFET

gate drivers and to prevent interaction between channels.

The LTC3727 contains an internal P-channel MOSFET

switch connected between the EXTV_CCand INTV_CCpins.

When the voltage applied to EXTV_CCrises above 7.3V, the

internal regulator is turned off and the switch closes,

connecting the EXTV_CCpin to the INTV_CCpin thereby

supplying internal power. The switch remains closed as

longasthevoltageappliedtoEXTV_CCremainsabove7.0V.

This allows the MOSFET driver and control power to be

derived from the output during normal operation (7.2V <

V_OUT< 8.5V) and from the internal regulator when the

outputisoutofregulation(start-up, short-circuit). Ifmore

current is required through the EXTV_CCswitch than is

specified, an external Schottky diode can be added be-

tween the EXTV_CCand INTV_CCpins. Do not apply greater

than8.5VtotheEXTV_CCpinandensurethatEXTV_CC< V_IN.

Higher input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC3727 to be

exceeded. The system supply current is normally domi-

nated by the gate charge current. Additional external

loading of the INTV_CCand 3.3V linear regulators also

needs to be taken into account for the power dissipation

calculations. The total INTV_CCcurrent can be supplied by

either the 7.5V internal linear regulator or by the EXTV_CC

input pin. When the voltage applied to the EXTV_CCpin is

less than 7.3V, all of the INTV_CCcurrent is supplied by the

internal 7.5V linear regulator. Power dissipation for the IC

inthiscaseishighest:(V_IN)(I_INTVCC),andoverallefficiency

is lowered. The gate charge current is dependent on

operatingfrequencyasdiscussedintheEfficiencyConsid-

erations section. The junction temperature can be esti-

mated by using the equations given in Note 2 of the

Electrical Characteristics. For example, the LTC3727 V_IN

current is limited to less than 24mA from a 24V supply

when not using the EXTV_CCpin as follows:

Significant efficiency gains can be realized by powering

INTV_CCfrom the output, since the V_INcurrent resulting

from the driver and control currents will be scaled by a

factorof(DutyCycle)/(Efficiency).For7.5Vregulatorsthis

supply means connecting the EXTV_CCpin directly to V_OUT

.

However, for 3.3V and other lower voltage regulators,

additional circuitry is required to derive INTV_CCpower

from the output.

The following list summarizes the four possible connec-

tions for EXTV_CC:

1. EXTV_CCLeftOpen(orGrounded).ThiswillcauseINTV_CC

to be powered from the internal 7.5V regulator resulting in

an efficiency penalty of up to 10% at high input voltages.

2. EXTV_CCConnected directly to V_OUT. This is the normal

connection for a 7.5V regulator and provides the highest

efficiency.

T_J= 70°C + (24mA)(24V)(95°C/W) = 125°C

3. EXTV_CCConnected to an External supply. If an external

supplyisavailableinthe7.5Vto8.5Vrange,itmaybeused

to power EXTV_CCproviding it is compatible with the

MOSFET gate drive requirements.

UseoftheEXTV_CCinputpinreducesthejunctiontempera-

ture to:

T_J= 70°C + (24mA)(7.5V)(95°C/W) = 87°C

Dissipationshouldbecalculatedtoalsoincludeanyadded

current drawn from the internal 3.3V linear regulator. To

prevent maximum junction temperature from being ex-

ceeded, the input supply current must be checked operat-

ing in continuous mode at maximum V_IN.

4. EXTV_CCConnected to an Output-Derived Boost Net-

work. For3.3Vandotherlowvoltageregulators, efficiency

gains can still be realized by connecting EXTV_CCto an

output-derived voltage that has been boosted to greater

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Output Voltage

V

IN

OPTIONAL EXTV

CONNECTION

CC

+

The LTC3727 output voltages are each set by an external

feedback resistive divider carefully placed across the

output capacitor. The resultant feedback signal is

compared with the internal precision 0.800V voltage

reference by the error amplifier. The output voltage is

given by the equation:

7.5V < V

< 8.5V

SEC

C

IN

V

SEC

IN

+

N-CH

LTC3727

1μF

TG1

SW

R

SENSE

V

OUT

T1

1:N

EXTV

FCB

CC

R6

R5

R2

R1

⎛

⎝

⎞

⎟

⎠

C

BG1

OUT

V_OUT= 0.8V 1+

⎜

N-CH

SGND

PGND

where R1 and R2 are defined in Figure 2.

3727 F06

Figure 6. Secondary Output Loop & EXTV Connection

SENSE⁺/SENSE^–Pins

CC

The common mode input range of the current comparator

sense pins is from 0V to 14V. Continuous linear operation

is guaranteed throughout this range allowing output volt-

age setting from 0.8V to 14V. A differential NPN input

stage is biased with internal resistors from an internal

2.4V source as shown in the Functional Diagram. This

requires that current either be sourced or sunk from the

SENSE pins depending on the output voltage. If the output

voltage is below 2.4V current will flow out of both SENSE

pinstothemainoutput.Theoutputcanbeeasilypreloaded

by the V_OUTresistive divider to compensate for the current

comparator’s negative input bias current. The maximum

current flowing out of each pair of SENSE pins is:

than 7.5V. This can be done with the inductive boost

winding as shown in Figure 6.

Topside MOSFET Driver Supply (C_B, D_B)

External bootstrap capacitors C_Bconnected to the BOOST

pinssupplythegatedrivevoltagesforthetopsideMOSFETs.

Capacitor C_Bin the functional diagram is charged though

external diode D_Bfrom INTV_CCwhen the SW pin is low.

When one of the topside MOSFETs is to be turned on, the

driver places the C_Bvoltage across the gate-source of the

desiredMOSFET.ThisenhancestheMOSFETandturnson

the topside switch. The switch node voltage, SW, rises to

V_INand the BOOST pin follows. With the topside MOSFET

I_SENSE⁺+ I_SENSE^–= (2.4V – V_OUT)/24k

on, the boost voltage is above the input supply: V_BOOST

=

SinceV_OSENSEisservoedtothe0.8Vreferencevoltage, we

can choose R1 in Figure 2 to have a maximum value to

absorb this current.

V_IN+ V_INTVCC. The value of the boost capacitor C_Bneeds

to be 100 times that of the total input capacitance of the

topside MOSFET(s). The reverse breakdown of the exter-

nal Schottky diode must be greater than V_IN(MAX). When

adjusting the gate drive level, the final arbiter is the total

input current for the regulator. If a change is made and the

input current decreases, then the efficiency has improved.

If there is no change in input current, then there is no

change in efficiency.

⎛

⎜

0.8V

⎝ 2.4V – V_OUT

⎞

R1

= 24k

⎟

⎠

(MAX)

for V_OUT< 2.4V

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Regulating an output voltage of 1.8V, the maximum value

of R1 should be 32K. Note that for an output voltage above

2.4V, R1 has no maximum value necessary to absorb the

sense currents; however, R1 is still bounded by the

U

V

IN

INTV

CC

3.3V OR 5V

RUN/SS

R *

SS

R *

SS

D1

RUN/SS

C

SS

V

_OSENSEfeedback current.

C

SS

*OPTIONAL TO DEFEAT OVERCURRENT

LATCHOFF (NOT NEEDED WITH THE LTC3727-1)

Soft-Start/Run Function

3727 F07

(7a)

(7b)

The RUN/SS1 and RUN/SS2 pins are multipurpose pins

that provide a soft-start function and a means to shut

down the LTC3727. Soft-start reduces the input power

source’s surge currents by gradually increasing the

controller’s current limit (proportional to V_ITH). This pin

can also be used for power supply sequencing.

Figure 7. RUN/SS Pin Interfacing

The RUN/SS capacitor, C_SS, is used initially to turn on and

limit the inrush current. After the controller has been

started and been given adequate time to charge up the

outputcapacitorandprovidefullloadcurrent, theRUN/SS

capacitorisusedforashort-circuittimer. Iftheregulator’s

output voltage falls to less than 70% of its nominal value

after C_SSreaches 4.1V, C_SSbegins discharging on the

assumption that the output is in an overcurrent condition.

If the condition lasts for a long enough period as deter-

mined by the size of the C_SSand the specified discharge

current, the controller will be shut down until the RUN/SS

pin voltage is recycled. If the overload occurs during start-

up, the time can be approximated by:

An internal 1.2μA current source charges up the C_SS

capacitor_.When the voltage on RUN/SS1 (RUN/SS2)

reaches 1.5V, the particular controller is permitted to start

operating. As the voltage on RUN/SS increases from 1.5V

to 3.0V, the internal current limit is increased from 45mV/

R_SENSEto 135mV/R_SENSE. The output current limit ramps

up slowly, taking an additional 1.25s/μF to reach full

current. The output current thus ramps up slowly, reduc-

ing the starting surge current required from the input

power supply. If RUN/SS has been pulled all the way to

ground there is a delay before starting of approximately:

t_LO1≅ [C_SS(4.1 – 1.5 + 4.1 – 3.5)]/(1.2μA)

= 2.7 • 10⁶(C_SS)

1.5V

1.2μA

t_DELAY

=

C_SS= 1.25s / μF C

SS

(

)

If the overload occurs after start-up the voltage on C_SSwill

begin discharging from the zener clamp voltage:

3V − 1.5V

1.2μA

t_LO2≅ [C_SS(6 – 3.5)]/(1.2μA) = 2.1 • 10⁶(C_SS)

t_IRAMP

C_SS= 1.25s / μF C

SS

(

)

This built-in overcurrent latchoff can be overridden by

providing a pull-up resistor to the RUN/SS pin as shown

in Figure 7. This resistance shortens the soft-start period

and prevents the discharge of the RUN/SS capacitor

during an over current condition. Tying this pull-up resis-

tor to V_IN, as in Figure 7a, defeats overcurrent latchoff.

Diode-connecting this pull-up resistor to INTV_CC, as in

Figure 7b, eliminates any extra supply current during

controller shutdown while eliminating the INTV_CCloading

from preventing controller start-up. This pull-up resistor

is not needed in LTC3727-1 designs.

By pulling both RUN/SS pins below 1V, the LTC3727 is

put into low current shutdown (I_Q= 20μA). The RUN/SS

pins can be driven directly from logic as shown in Fig-

ure 7. Diode D1 in Figure 7 reduces the start delay but

allows C_SSto ramp up slowly providing the soft-start

function. EachRUN/SSpinhasaninternal6Vzenerclamp

(See Functional Diagram).

Fault Conditions: Overcurrent Latchoff (LTC3727 Only)

The RUN/SS pins also provide the ability to latch off the

controller(s) when an overcurrent condition is detected.

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Why should you defeat overcurrent latchoff? During the

prototyping stage of a design, there may be a problem

with noise pickup or poor layout causing the protection

circuit to latch off. Defeating this feature will easily allow

troubleshooting of the circuit and PC layout. The internal

short-circuit and foldback current limiting still remains

active, thereby protecting the power supply system from

failure. After the design is complete, a decision can be

made whether to enable the latchoff feature. If latchoff is

not required, the LTC3727-1 can be used.

The resulting short-circuit current is:

45mV

R_SENSE

1

2

I_SC

=

+ ΔI_L(SC)

Fault Conditions: Overvoltage Protection (Crowbar)

The overvoltage crowbar is designed to blow a system

input fuse when the output voltage of the regulator rises

much higher than nominal levels. The crowbar causes

huge currents to flow, that blow the fuse to protect against

a shorted top MOSFET if the short occurs while the

controller is operating.

The value of the soft-start capacitor C_SSmay need to be

scaled with output voltage, output capacitance and load

current characteristics. The minimum soft-start capaci-

tance is given by:

A comparator monitors the output for overvoltage condi-

tions. The comparator (OV) detects overvoltage faults

greater than 7.5% above the nominal output voltage.

When this condition is sensed, the top MOSFET is turned

off and the bottom MOSFET is turned on until the overvolt-

age condition is cleared. The output of this comparator is

only latched by the overvoltage condition itself and will

thereforeallowaswitchingregulatorsystemhavingapoor

PC layout to function while the design is being debugged.

The bottom MOSFET remains on continuously for as long

as the OV condition persists; if V_OUTreturns to a safe level,

normal operation automatically resumes. A shorted top

MOSFET will result in a high current condition which will

open the system fuse. The switching regulator will regu-

late properly with a leaky top MOSFET by altering the duty

cycle to accommodate the leakage.

C

_SS> (C_OUT)(V_OUT) (10^–4) (R_SENSE

)

The minimum recommended soft-start capacitor of

C_SS= 0.1μF will be sufficient for most applications.

Fault Conditions: Current Limit and Current Foldback

The LTC3727 current comparator has a maximum sense

voltage of 135mV resulting in a maximum MOSFET cur-

rent of 135mV/R_SENSE. The maximum value of current

limit generally occurs with the largest V_INat the highest

ambient temperature, conditions that cause the highest

power dissipation in the top MOSFET.

The LTC3727 includes current foldback to help further

limit load current when the output is shorted to ground.

The foldback circuit is active even when the overload

shutdown latch described above is overridden. If the

outputfallsbelow70%ofitsnominaloutputlevel,thenthe

maximum sense voltage is progressively lowered from

135mV to 45mV. Under short-circuit conditions with very

low duty cycles, the LTC3727 will begin cycle skipping in

order to limit the short-circuit current. In this situation the

bottom MOSFET will be dissipating most of the power but

less than in normal operation. The short-circuit ripple

current is determined by the minimum on-time t_ON(MIN)of

the LTC3727 (less than 200ns), the input voltage and

inductor value:

Phase-Locked Loop and Frequency Synchronization

The LTC3727 has a phase-locked loop comprised of an

internal voltage controlled oscillator and phase detector.

This allows the top MOSFET turn-on to be locked to the

rising edge of an external source. The frequency range of

the voltage controlled oscillator is ±50% around the

center frequency f_O. A voltage applied to the PLLFLTR pin

of 1.2V corresponds to a frequency of approximately

380kHz. The nominal operating frequency range of the

LTC3727 is 250kHz to 550kHz.

ΔI_L(SC)= t_ON(MIN)(V_IN/L)

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The phase detector used is an edge sensitive digital type

which provides zero degrees phase shift between the

external and internal oscillators. This type of phase detec-

tor will not lock up on input frequencies close to the

harmonics of the VCO center frequency. The PLL hold-in

range, Δf_H, is equal to the capture range, Δf_C:

Minimum On-Time Considerations

Minimum on-time t_ON(MIN)is the smallest time duration

thattheLTC3727iscapableofturningonthetopMOSFET.

It is determined by internal timing delays and the gate

chargerequiredtoturnonthetopMOSFET.Lowdutycycle

applications may approach this minimum on-time limit

and care should be taken to ensure that

Δf_H= Δf_C= ±0.5 f_O(250kHz-550kHz)

The output of the phase detector is a complementary pair

of current sources charging or discharging the external

filter network on the PLLFLTR pin.

V_OUT

V (f)

IN

t_ON(MIN)

<

Ifthedutycyclefallsbelowwhatcanbeaccommodatedby

the minimum on-time, the LTC3727 will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

If the external frequency (f_PLLIN) is greater than the oscil-

lator frequency f_0SC, current is sourced continuously,

pulling up the PLLFLTR pin. When the external frequency

is less than f_0SC, current is sunk continuously, pulling

down the PLLFLTR pin. If the external and internal fre-

quencies are the same but exhibit a phase difference, the

currentsourcesturnonforanamountoftimecorrespond-

ing to the phase difference. Thus the voltage on the

PLLFLTR pin is adjusted until the phase and frequency of

the external and internal oscillators are identical. At this

stable operating point the phase comparator output is

open and the filter capacitor C_LPholds the voltage. The

LTC3727 PLLIN pin must be driven from a low impedance

source such as a logic gate located close to the pin. When

using multiple LTC3727s for a phase-locked system, the

PLLFLTR pin of the master oscillator should be biased at

a voltage that will guarantee the slave oscillator(s) ability

to lock onto the master’s frequency. A DC voltage of 0.7V

to 1.7V applied to the master oscillator’s PLLFLTR pin is

recommended in order to meet this requirement. The

resultant operating frequency can range from 310kHz to

470kHz.

The minimum on-time for the LTC3727 is generally less

than200ns.However,asthepeaksensevoltagedecreases

the minimum on-time gradually increases up to about

300ns. This is of particular concern in forced continuous

applications with low ripple current at light loads. If the

duty cycle drops below the minimum on-time limit in this

situation, a significant amount of cycle skipping can occur

with correspondingly larger inductor current and output

voltage ripple.

FCB Pin Operation

The FCB pin can be used to regulate a secondary winding

or as a logic level input. Continuous operation is forced on

both controllers when the FCB pin drops below 0.8V.

During continuous mode, current flows continuously in

the transformer primary. The secondary winding(s) draw

current only when the bottom, synchronous switch is on.

When primary load currents are low and/or the V_IN/V_OUT

ratio is low, the synchronous switch may not be on for a

sufficient amount of time to transfer power from the

outputcapacitortothesecondaryload.Forcedcontinuous

operationwillsupportsecondarywindingsprovidingthere

is sufficient synchronous switch duty factor. Thus, the

FCB input pin removes the requirement that power must

The loop filter components (C_LP, R_LP) smooth out the

current pulses from the phase detector and provide a

stable input to the voltage controlled oscillator. The filter

components C_LPand R_LPdetermine how fast the loop

acquires lock. Typically R_LP=10kΩ and C_LPis 0.01μF to

0.1μF.

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be drawn from the inductor primary in order to extract

power from the auxiliary windings. With the loop in

continuous mode, the auxiliary outputs may nominally be

loaded without regard to the primary output load.

loading conditions. The open-loop DC gain of the control

loop is reduced depending upon the maximum load step

specifications. Voltage positioning can easily be added to

the LTC3727 by loading the I_THpin with a resistive divider

having a Thevenin equivalent voltage source equal to the

midpoint operating voltage range of the error amplifier, or

1.2V (see Figure 8).

The secondary output voltage V_SECis normally set as

shown in Figure 6 by the turns ratio N of the transformer:

V_SEC≅ (N + 1) V_OUT

The resistive load reduces the DC loop gain while main-

taining the linear control range of the error amplifier. The

maximum output voltage deviation can theoretically be

reduced to half or alternatively the amount of output

capacitance can be reduced for a particular application. A

complete explanation is included in Design Solutions 10

(see www.Linear.com).

However, if the controller goes into Burst Mode operation

and halts switching due to a light primary load current,

then V_SECwill droop. An external resistive divider from

V

_SECto the FCB pin sets a minimum voltage V_SEC(MIN):

R6

R5

⎛

⎝

⎞

⎟

⎠

V_SEC(MIN)≅ 0.8V 1+

⎜

INTV

CC

where R5 and R6 are shown in Figure 2.

R

T2

T1

I

TH

If V_SECdrops below this level, the FCB voltage forces

temporary continuous switching operation until V_SECis

again above its minimum.

LTC3727

R

C

3727 F08

In order to prevent erratic operation if no external connec-

tions are made to the FCB pin, the FCB pin has a 0.18μA

internal current source pulling the pin high. Include this

current when choosing resistor values R5 and R6.

Figure 8. Active Voltage Positioning Applied to the LTC3727

Efficiency Considerations

The following table summarizes the possible states avail-

able on the FCB pin:

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can be

expressed as:

Table 1

FCB PIN

CONDITION

0V to 0.75V

Forced Continuous Both Controllers

(Current Reversal Allowed—

Burst Inhibited)

%Efficiency = 100% – (L1 + L2 + L3 + ...)

0.85V < V < 6.8V

Minimum Peak Current Induces

Burst Mode Operation

FCB

whereL1, L2, etc. aretheindividuallossesasapercentage

of input power.

No Current Reversal Allowed

Feedback Resistors

>7.3V

Regulating a Secondary Winding

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC3727 circuits: 1) LTC3727 V_INcurrent (in-

cluding loading on the 3.3V internal regulator), 2) INTV_CC

regulator current, 3) I²R losses, 4) Topside MOSFET

transition losses.

Burst Mode Operation Disabled

Constant Frequency Mode Enabled

No Current Reversal Allowed No

Minimum Peak Current

Voltage Positioning

1. The V_INcurrent has two components: the first is the DC

supply current given in the Electrical Characteristics table,

Voltage positioning can be used to minimize peak-to-peak

output voltage excursions under worst-case transient

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which excludes MOSFET driver and control currents; the

second is the current drawn from the 3.3V linear regulator

output.V_INcurrenttypicallyresultsinasmall(<0.1%)loss.

4. Transition losses apply only to the topside MOSFET(s),

and become significant only when operating at high input

voltages (typically 15V or greater). Transition losses can

be estimated from:

2. INTV_CCcurrent is the sum of the MOSFET driver and

control currents. The MOSFET driver current results from

switching the gate capacitance of the power MOSFETs.

Each time a MOSFET gate is switched from low to high to

low again, a packet of charge dQ moves from INTV_CCto

ground. The resulting dQ/dt is a current out of INTV_CCthat

is typically much larger than the control circuit current. In

continuous mode, I_GATECHG=f(Q_T+ Q_B), where Q_Tand Q_B

are the gate charges of the topside and bottom side

MOSFETs.

2

Transition Loss = (1.7) V_INI_O(MAX)C_RSS

f

Other “hidden” losses such as copper trace and internal

battery resistances can account for an additional 5% to

10% efficiency degradation in portable systems. It is very

important to include these “system” level losses during

the design phase. The internal battery and fuse resistance

losses can be minimized by making sure that C_INhas

adequate charge storage and very low ESR at the switch-

ing frequency. A 25W supply will typically require a mini-

mum of 22μF to 47μF of capacitance having a maximum

of20mΩto50mΩofESR.TheLTC37272-phasearchitec-

ture typically halves this input capacitance requirement

over competing solutions. Other losses, including Schot-

tky diode conduction losses during dead-time and induc-

tor core losses, generally account for less than 2% total

additional loss.

SupplyingINTV_CCpowerthroughtheEXTV_CCswitchinput

from an output-derived source will scale the V_INcurrent

required for the driver and control circuits by a factor of

(Duty Cycle)/(Efficiency). For example, in a 20V to 5V

application, 10mA of INTV_CCcurrent results in approxi-

mately2.5mAofV_INcurrent. Thisreducesthemid-current

loss from 10% or more (if the driver was powered directly

from V_IN) to only a few percent.

Checking Transient Response

3. I²R losses are predicted from the DC resistances of the

fuse (if used), MOSFET, inductor, current sense resistor,

and input and output capacitor ESR. In continuous mode

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, V_OUTshifts by an

amount equal to ΔI_LOAD(ESR), where ESR is the effective

series resistance of C_OUT. ΔI_LOADalso begins to charge or

discharge C_OUTgenerating the feedback error signal that

forces the regulator to adapt to the current change and

return V_OUTto its steady-state value. During this recovery

time V_OUTcan be monitored for excessive overshoot or

ringing, which would indicate a stability problem. OPTI-

LOOP compensation allows the transient response to be

optimized over a wide range of output capacitance and

ESR values. The availability of the I_THpin not only allows

optimization of control loop behavior but also provides a

DC coupled and AC filtered closed loop response test

point. The DC step, rise time and settling at this test point

truly reflects the closed loop response. Assuming a pre-

dominantly second order system, phase margin and/or

damping factor can be estimated using the percentage of

the average output current flows through L and R_SENSE

,

but is “chopped” between the topside MOSFET and the

synchronous MOSFET. If the two MOSFETs have approxi-

mately the same R_DS(ON), then the resistance of one

MOSFET can simply be summed with the resistances of L,

R_SENSEand ESR to obtain I²R losses. For example, if each

R_DS(ON)= 30mΩ, R_L= 50mΩ, R_SENSE= 10mΩ and R_ESR

= 40mΩ (sum of both input and output capacitance

losses), then the total resistance is 130mΩ. This results in

losses ranging from 3% to 13% as the output current

increases from 1A to 5A for a 5V output, or a 4% to 20%

loss for a 3.3V output. Efficiency varies as the inverse

square of V_OUTfor the same external components and

output power level. The combined effects of increasingly

lower output voltages and higher currents required by

high performance digital systems is not doubling but

quadrupling the importance of loss terms in the switching

regulator system!

3727fc

23

LTC3727/LTC3727-1

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APPLICATIO S I FOR ATIO

overshoot seen at this pin. The bandwidth can also be

estimated by examining the rise time at the pin. The I_TH

external components shown in the Figure 1 circuit will

provide an adequate starting point for most applications.

approximately 25 • C_LOAD. Thus a 10μF capacitor would

require a 250μs rise time, limiting the charging current to

about 200mA.

Automotive Considerations: Plugging into the

Cigarette Lighter

The I_THseries R_C-C_Cfilter sets the dominant pole-zero

loop compensation. The values can be modified slightly

(from 0.5 to 2 times their suggested values) to optimize

transient response once the final PC layout is done and the

particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80% of

full-load current having a rise time of 1μs to 10μs will

produce output voltage and I_THpin waveforms that will

give a sense of the overall loop stability without breaking

the feedback loop. Placing a power MOSFET directly

across the output capacitor and driving the gate with an

appropriate signal generator is a practical way to produce

a realistic load step condition. The initial output voltage

step resulting from the step change in output current may

not be within the bandwidth of the feedback loop, so this

signal cannot be used to determine phase margin. This is

why it is better to look at the I_THpin signal which is in the

feedback loop and is the filtered and compensated control

loop response. The gain of the loop will be increased by

increasing R_Cand the bandwidth of the loop will be

increased by decreasing C_C. If R_Cis increased by the same

factor that C_Cis decreased, the zero frequency will be kept

the same, thereby keeping the phase shift the same in the

most critical frequency range of the feedback loop. The

outputvoltagesettlingbehaviorisrelatedtothestabilityof

the closed-loop system and will demonstrate the actual

overall supply performance.

As battery-powered devices go mobile, there is a natural

interest in plugging into the cigarette lighter in order to

conserve or even recharge battery packs during opera-

tion.Butbeforeyouconnect,beadvised:youareplugging

into the supply from Hell. The main power line in an

automobile is the source of a number of nasty potential

transients, including load-dump, reverse-battery, and

double-battery.

Load-dump is the result of a loose battery cable. When the

cablebreaksconnection,thefieldcollapseinthealternator

can cause a positive spike as high as 60V which takes

several hundred milliseconds to decay. Reverse-battery is

just what it says, while double-battery is a consequence of

tow-truck operators finding that a 24V jump start cranks

cold engines faster than 12V.

ThenetworkshowninFigure9isthemoststraightforward

approach to protect a DC/DC converter from the ravages

of an automotive power line. The series diode prevents

current from flowing during reverse-battery, while the

transient suppressor clamps the input voltage during

load-dump. Note that the transient suppressor should not

conduct during double-battery operation, but must still

clamptheinputvoltagebelowbreakdownoftheconverter.

Although the LTC3727 has a maximum input voltage of

36V, most applications will be limited to 30V by the

MOSFET BVDSS.

A second, more severe transient is caused by switching in

loads with large (>1μF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

with C_OUT, causing a rapid drop in V_OUT. No regulator can

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

50A I RATING

PK

V

IN

12V

LTC3727

TRANSIENT VOLTAGE

SUPPRESSOR

GENERAL INSTRUMENT

1.5KA24A

3727 F09

C

_LOADto C_OUTis greater than 1:50, the switch rise time

should be controlled so that the load rise time is limited to

Figure 9. Automotive Application Protection

3727fc

24

LTC3727/LTC3727-1

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APPLICATIO S I FOR ATIO

U

Design Example

Ashort-circuittogroundwillresultinafoldedbackcurrent

of:

As a design example for one channel, assume V_IN

=

24V(nominal), V_IN= 30V(max), V_OUT= 12V, I_MAX= 5A and

f = 250kHz.

⎛

⎝

⎞

45mV 1 200ns(30V)

I_SC

=

+

= 3.2A

⎜

⎟

⎠

0.015Ω

2

14μH

Theinductancevalueischosenfirstbasedona40%ripple

current assumption. The highest value of ripple current

occursatthemaximuminputvoltage. TiethePLLFLTRpin

to the SGND pin for 250kHz operation. The minimum

inductance for 40% ripple current is:

withatypicalvalueofR_DS(ON)andδ=(0.005/°C)(20)=0.1.

The resulting power dissipated in the bottom MOSFET is:

30V – 12V

30V

2

P_SYNC

=

3.2A 1.1 0.042Ω

(

) ( )(

)

V_OUT

(f)(L)⎝

⎛

⎜

V_OUT

V

IN

⎞

= 284mW

which is less than under full-load conditions.

ΔI_L=

1–

⎟

⎠

A14μHinductorwillresultin40%ripplecurrent. Thepeak

inductor current will be the maximum DC value plus one

half the ripple current, or 6A, for the 14μH value.

C_INis chosen for an RMS current rating of at least 3A at

temperature assuming only this channel is on. C_OUTis

chosen with an ESR of 0.02Ω for low output ripple. The

output ripple in continuous mode will be highest at the

maximum input voltage. The output voltage ripple due to

ESR is approximately:

The R_SENSEresistor value can be calculated by using the

maximum current sense voltage specification with some

accommodation for tolerances:

V_ORIPPLE= R_ESR(ΔI_L) = 0.02Ω(2A) = 40mV_P–P

90mV

6A

R_SENSE

≤

≈ 0.015Ω

PC Board Layout Checklist

Choosing 1% resistors; R1 = 20k and R2 = 280k yields an

output voltage of 12V.

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC3727. These items are also illustrated graphically in

the layout diagram of Figure 10; Figure 11 illustrates the

current waveforms present in the various branches of the

2-phase synchronous regulators operating in continuous

mode. Check the following in your layout:

The power dissipation on the top side MOSFET can be

easily estimated. Choosing a Siliconix Si4412DY results

in: R_DS(ON)= 0.042Ω, C_RSS= 100pF. At maximum input

voltage with T(estimated) = 50°C:

12V

30V

2

1. Are the top N-channel MOSFETs M1 and M3 located

within 1cm of each other with a common drain connection

at C_IN? Do not attempt to split the input decoupling for the

two channels as it can cause a large resonant loop.

P_MAIN

=

(

5 1+ (0.005)(50°C – 25°C)

( )

[

]

2

0.042Ω + 1.7 30V 5A 100pF 250kHz

) ( )( )( )

)

(

= 664mW

3727fc

25

LTC3727/LTC3727-1

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APPLICATIO S I FOR ATIO

2. Are the signal and power grounds kept separate? The

combined LTC3727 signal ground pin and the ground

return of C_INTVCCmust return to the combined C_OUT(–)

terminals. ThepathformedbythetopN-channelMOSFET,

Schottky diode and the C_INcapacitor should have short

leads and PC trace lengths. The output capacitor (–)

terminals should be connected as close as possible to the

(–) terminals of the input capacitor by placing the capaci-

tors next to each other and away from the Schottky loop

described above.

along the high current input feeds from the input

capacitor(s).

4. Are the SENSE ^–and SENSE⁺leads routed together

with minimum PC trace spacing? The filter capacitor

between SENSE⁺and SENSE^–should be as close as

possible to the IC. Ensure accurate current sensing with

Kelvin connections at the SENSE resistor.

5. Is the INTV_CCdecoupling capacitor connected close to

the IC, between the INTV_CCand the power ground pins?

This capacitor carries the MOSFET drivers current peaks.

An additional 1μF ceramic capacitor placed immediately

next to the INTV_CCand PGND pins can help improve noise

performance substantially.

3. Do the LTC3727 V_OSENSEpins resistive dividers con-

nect to the (+) terminals of C_OUT? The resistive divider

must be connected between the (+) terminal of C_OUTand

signal ground. The R2 and R4 connections should not be

R

PU

V

PULL-UP

(<7V)

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

PGOOD

RUN/SS1

PGOOD

TG1

L1

+

V

SENSE1

OUT1

R

SENSE

D1

3

–

SENSE1

SW1

R2

M1

M2

C

B1

R1

4

V

BOOST1

OSENSE1

5

PLLFLTR

PLLIN

FCB

V

IN

f

IN

6

C

OUT1

BG1

R

IN

7

C

IN

INTV

EXTV

CC

C

VIN

GND

LTC3727

8

I

INTV

TH1

V

IN

C

INTVCC

9

SGND

PGND

BG2

OUT2

D2

10

11

12

13

14

3.3V

OUT

I

BOOST2

SW2

TH2

C

B2

M3

M4

L2

V

OSENSE2

–

R

R3

R4

SENSE

V

SENSE2

TG2

OUT2

+

RUN/SS2

3727 F10

Figure 10. LTC3727 Recommended Printed Circuit Layout Diagram

3727fc

26

LTC3727/LTC3727-1

W U U

APPLICATIO S I FOR ATIO

U

SW1

L1

R

SENSE1

V

OUT1

+

D1

C

OUT1

R

L1

V

IN

R

IN

+

C

IN

SW2

L2

R

SENSE2

V

OUT2

+

D2

C

OUT2

R

L2

BOLD LINES INDICATE

HIGH SWITCHING

CURRENT. KEEP LINES

TO A MINIMUM LENGTH

3727 F11

Figure 11. Branch Current Waveforms

6. Keep the switching nodes (SW1, SW2), top gate nodes

(TG1, TG2), and boost nodes (BOOST1, BOOST2) away

from sensitive small-signal nodes, especially from the

oppositeschannel’svoltageandcurrentsensingfeedback

pins. All of these nodes have very large and fast moving

signals and therefore should be kept on the “output side”

of the LTC3727 and occupy minimum PC trace area.

decoupling capacitor, the bottom of the voltage feedback

resistive divider and the SGND pin of the IC.

PC Board Layout Debugging

Start with one controller on at a time. It is helpful to use

a DC-50MHz current probe to monitor the current in the

inductor while testing the circuit. Monitor the output

switching node (SW pin) to synchronize the oscilloscope

to the internal oscillator and probe the actual output

voltage as well. Check for proper performance over the

operating voltage and current range expected in the

7. Use a modified “star ground” technique: a low imped-

ance, large copper area central grounding point on the

same side of the PC board as the input and output

capacitors with tie-ins for the bottom of the INTV_CC

3727fc

27

LTC3727/LTC3727-1

U

W

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APPLICATIO S I FOR ATIO

application. The frequency of operation should be main-

tained over the input voltage range down to dropout and

until the output load drops below the low current opera-

tion threshold—typically 10% to 20% of the maximum

designed current level in Burst Mode operation.

Investigate whether any problems exist only at higher

output currents or only at higher input voltages. If prob-

lems coincide with high input voltages and low output

currents,lookforcapacitivecouplingbetweentheBOOST,

SW, TG, and possibly BG connections and the sensitive

voltage and current pins. The capacitor placed across the

current sensing pins needs to be placed immediately

adjacent to the pins of the IC. This capacitor helps to

minimize the effects of differential noise injection due to

high frequency capacitive coupling. If problems are en-

countered with high current output loading at lower input

voltages,lookforinductivecouplingbetweenC_IN,Schottky

and the top MOSFET components to the sensitive current

and voltage sensing traces. In addition, investigate com-

mon ground path voltage pickup between these compo-

nents and the SGND pin of the IC.

The duty cycle percentage should be maintained from

cycle to cycle in a well-designed, low noise PCB imple-

mentation. Variation in the duty cycle at a subharmonic

rate can suggest noise pickup at the current or voltage

sensing inputs or inadequate loop compensation. Over-

compensation of the loop can be used to tame a poor PC

layout if regulator bandwidth optimization is not required.

Only after each controller is checked for its individual

performance should both controllers be turned on at the

same time. A particularly difficult region of operation is

when one controller channel is nearing its current com-

parator trip point when the other channel is turning on its

topMOSFET. Thisoccursaround50%dutycycleoneither

channel due to the phasing of the internal clocks and may

cause minor duty cycle jitter.

An embarrassing problem, which can be missed in an

otherwise properly working switching regulator, results

when the current sensing leads are hooked up backwards.

Theoutputvoltageunderthisimproperhookupwillstillbe

maintained but the advantages of current mode control

will not be realized. Compensation of the voltage loop will

be much more sensitive to component selection. This

behavior can be investigated by temporarily shorting out

the current sensing resistor—don’t worry, the regulator

will still maintain control of the output voltage.

Short-circuit testing can be performed to verify proper

overcurrent latchoff, or 5μA can be provided to the RUN/

SS pin(s) by resistors from V_INto prevent the short-circuit

latchoff from occurring.

ReduceV_INfromitsnominalleveltoverifyoperationofthe

regulator in dropout. Check the operation of the

undervoltage lockout circuit by further lowering V_INwhile

monitoring the outputs to verify operation.

3727fc

28

LTC3727/LTC3727-1

U

TYPICAL APPLICATIO S

V

PULL-UP

(<7V)

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

L1

PGOOD

RUN/SS1

PGOOD

TG1

8μH

0.015Ω

V

0.1μF

OUT1

+

SENSE1

5V

5A; 6A PEAK

27pF

1000pF

105k

1%

3

–

SENSE1

SW1

20k

1%

M1A

M1B

0.1μF

D1

4

MBRM

V

BOOST1

OSENSE1

140T3

5

PLLFLTR

PLLIN

FCB

V

IN

0.01μF

C

OUT1

10k

1000pF

47μF

6

6.3V

f

SYNC

BG1

33pF

10Ω

22μF

50V

7

CMDSH-3

EXTV

INTV

CC

0.1μF

GND

LTC3727

8

I

TH1

1μF

10V

15k

4.7μF

220pF

9

SGND

PGND

BG2

C

100μF 16V

OUT2

V

33pF

IN

CMDSH-3

15V TO

28V

10

11

12

13

14

3.3V

OUT

D2

MBRM

140T3

I

BOOST2

SW2

TH2

15k

0.1μF

M2A

M2B

220pF

V

OSENSE2

–

20k

1%

V

12V

4A; 5A PEAK

OUT2

SENSE2

TG2

280k

1%

0.015Ω

1000pF

L2

15μH

+

27pF

RUN/SS2

0.1μF

3727 F12

C

: PANASONIC EEFCDOJ470R

: SANYO OS-CON 16SVP100M

V

: 15V TO 28V

SWITCHING FREQUENCY = 250kHz

MI, M2: FAIRCHILD FDS6680A

L1: 8μH SUMIDA CDEP134-8R0

L2: 15μH COILTRONICS UP4B-150

OUT1

OUT2

IN

: 5V, 5A/12V, 4A

OUT

Figure 12. LTC3727 12V/4A, 5V/5A Regulator with External Frequency Synchronization

3727fc

29

LTC3727/LTC3727-1

U

TYPICAL APPLICATIO S

V

PULL-UP

(<7V)

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

L1

PGOOD

RUN/SS1

PGOOD

TG1

8μH

0.015Ω

V

0.1μF

OUT1

2

+

SENSE1

5V

5A; 6A PEAK

27pF

1000pF

105k

1%

3

4

–

SENSE1

SW1

20k

1%

M1A

M1B

0.1μF

D1

MBRM

V

BOOST1

OSENSE1

140T3

5

PLLFLTR

PLLIN

FCB

V

IN

C

OUT1

47μF

6

6.3V

BG1

33pF

10Ω

22μF

50V

7

CMDSH-3

EXTV

CC

0.1μF

GND

LTC3727

8

I

INTV

TH1

1μF

10V

15k

4.7μF

220pF

9

SGND

PGND

BG2

C

OUT2

100μF 16V

33pF

V

CMDSH-3

IN

10

11

12

13

14

10V TO 15V

3.3V

OUT

D2

MBRM

140T3

I

BOOST2

SW2

TH2

15k

0.1μF

M2A

M2B

220pF

V

OSENSE2

–

20k

1%

V

OUT2

8.5V

SENSE2

TG2

192.5k

1%

3A; 4A PEAK

0.015Ω

1000pF

L2

8μH

+

27pF

RUN/SS2

0.1μF

3727 F13

C

: PANASONIC EEFCDOJ470R

OUT1

: SANYO OS-CON 16SVP100M

OUT2

V

: 10V TO 15V

SWITCHING FREQUENCY = 250kHz

MI, M2: FAIRCHILD FDS6680A

L1, L2: 8μH SUMIDA CDEP134-8R0

IN

: 5V, 5A/8.5V, 3A

OUT

Figure 13. LTC3727 8.5V/3A, 5V/5A Regulator

3727fc

30

LTC3727/LTC3727-1

U

PACKAGE DESCRIPTIO

G Package

28-Lead Plastic SSOP (5.3mm)

(Reference LTC DWG # 05-08-1640)

1.25 ±0.12

7.8 – 8.2

5.3 – 5.7

9.90 – 10.50*

(.390 – .413)

2.0

(.079)

MAX

5.00 – 5.60**

(.197 – .221)

0.42 ±0.03

0.65 BSC

28 27 26 25 24 23 22 21 20 19 18 17 16 15

RECOMMENDED SOLDER PAD LAYOUT

0° – 8°

7.40 – 8.20

(.291 – .323)

0.65

(.0256)

BSC

0.09 – 0.25

0.55 – 0.95

(.0035 – .010)

(.022 – .037)

0.05

0.22 – 0.38

(.009 – .015)

TYP

(.002)

NOTE:

MIN

1. CONTROLLING DIMENSION: MILLIMETERS

MILLIMETERS

2. DIMENSIONS ARE IN

(INCHES)

G28 SSOP 0204

5

7

8

1

2

3

4

6

9 10 11 12 13 14

3. DRAWING NOT TO SCALE

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED .152mm (.006") PER SIDE

**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE

UH Package

32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1693 Rev D)

0.70 ±0.05

NOTE:

1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE

M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

5.50 ±0.05

4.10 ±0.05

3. ALL DIMENSIONS ARE IN MILLIMETERS

3.45 ± 0.05

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

3.50 REF

(4 SIDES)

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

3.45 ± 0.05

PACKAGE OUTLINE

0.25 ± 0.05

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

BOTTOM VIEW—EXPOSED PAD

PIN 1 NOTCH R = 0.30 TYP

OR 0.35 × 45° CHAMFER

R = 0.05

TYP

0.00 – 0.05

R = 0.115

TYP

0.75 ± 0.05

5.00 ± 0.10

(4 SIDES)

31 32

0.40 ± 0.10

PIN 1

TOP MARK

(NOTE 6)

1

2

3.45 ± 0.10

3.50 REF

(4-SIDES)

3.45 ± 0.10

(UH32) QFN 0406 REV D

0.200 REF

0.25 ± 0.05

0.50 BSC

3727fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

31

LTC3727/LTC3727-1

RELATED PARTS

PART NUMBER

LTC1625/LTC1775

LTC1702

DESCRIPTION

COMMENTS

No R

^TMCurrent Mode Synchronous Step-Down Controllers

97% Efficiency, No Sense Resistor, 16-Pin SSOP

SENSE

2-Phase Dual Synchronous Step-Down Controller

550kHz, No Sense Resistor

Mobile Pentium^®III Processors, 550kHz,

LTC1703

with 5-Bit Mobile VID Control

V ≤ 7V

IN

LTC1708-PG

2-Phase, Dual Synchronous Controller with Mobile VID

3.5V ≤ V ≤ 36V, VID Sets V

, PGOOD

IN

OUT1

LT1709/

LT1709-8

High Efficiency, 2-Phase Synchronous Step-Down Switching Regulators

with 5-Bit VID

1.3V ≤ V

≤ 3.5V, Current Mode Ensures

OUT

Accurate Current Sharing, 3.5V ≤ V ≤ 36V

IN

LTC1735

LTC1736

High Efficiency Synchronous Step-Down Switching Regulator

Output Fault Protection, 16-Pin SSOP

High Efficiency Synchronous Controller with 5-Bit Mobile VID Control

Output Fault Protection, 24-Pin SSOP,

3.5V ≤ V ≤ 36V

IN

LTC1876

LTC1778

Triple Output DC/DC Synchronous Controller

Dual, 2-Phase Step-Down and Step-Up DC/DC

Converter, 2.6V ≤ V ≤ 36V, Fixed Frequency

IN

150kHz to 300kHz

No R

Wide Input Range Synchronous Step-Down Controller

Up to 97% Efficiency, 4V ≤ V ≤ 36V,

IN

SENSE

0.8V ≤ V

≤ (0.9)(V ), I

Up to 20A

OUT

IN OUT

LTC1929/

LTC1929-PG

2-Phase Synchronous Controllers

Up to 42A, Uses All Surface Mount Components,

No Heat Sinks, 3.5V ≤ V ≤ 36V

IN

LTC3727A-1

LTC3728

Dual, 2-Phase Synchronous Controller

Very Low Dropout; V

≤ 14V

OUT

2-Phase 550kHz, Dual Synchronous Step-Down Controller

QFN and SSOP Packages, High Frequency for

Smaller L and C

LTC3729

LTC3731

20A to 200A PolyPhase^®Synchronous Controllers

3-Phase, 600kHz Synchronous Step-Down Controller

Expandable from 2-Phase to 12-Phase, Uses All

Surface Mount Components, No Heat Sink

0.6V ≤ V

≤ 6V, 4.5V ≤ V ≤ 32V, I

≤ 60A,

OUT

IN

OUT

Integrated MOSFET Drivers

PolyPhase is a registered trademark of Linear Technology Corporation. No R

Pentium is a registered trademark of Intel Corporation.

is a trademark of Linear Technology Corporation.

SENSE

3727fc

LT 0507 REV C • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

32

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3727IG-1#TRPBF
厂家：	Linear
描述：	LTC3727-1 - High Efficiency, 2-Phase Synchronous Step-Down Switching Regulators; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C 开关光电二极管
文件：	总32页 (文件大小：354K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3727IG-1#TRPBF [Linear]

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