LTC3728EG#TR [Linear]
LTC3728 - Dual, 550kHz, 2-Phase Synchronous Step-Down Switching Regulator; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C;型号: | LTC3728EG#TR |
厂家: | Linear |
描述: | LTC3728 - Dual, 550kHz, 2-Phase Synchronous Step-Down Switching Regulator; Package: SSOP; Pins: 28; Temperature Range: -40°C to 85°C 开关 光电二极管 |
文件: | 总36页 (文件大小:1647K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC3728
Dual, 550kHz, 2-Phase
Synchronous Step-Down
Switching Regulator
DESCRIPTION
FEATURES
The LTC®3728 is a dual high performance step-down
switching regulator controller that drives all N-channel
synchronouspowerMOSFETstages.Aconstant-frequency
currentmodearchitectureallowsphase-lockablefrequency
of up to 550kHz. Power loss and noise due to the ESR of
the input capacitors are minimized by operating the two
controller output stages out of phase.
n
Dual, 180° Phased Controllers Reduce Required
Input Capacitance and Power Supply Induced Noise
OPTI-LOOP® Compensation Minimizes C
n
OUT
n
1ꢀ Output Voltage Accuracy
n
Power Good Output Voltage Indicator
n
Phase-Lockable Fixed Frequency 250kHz to 550kHz
n
Dual N-Channel MOSFET Synchronous Drive
n
Wide V Range: 3.5V to 36V Operation
IN
OPTI-LOOPcompensationallowsthetransientresponseto
be optimized over a wide range of output capacitance and
ESR values. The precision 0.8V reference and power good
outputindicatorarecompatiblewithfuturemicroprocessor
generations,andawide3.5Vto30V(36Vmaximum)input
supply range encompasses all battery chemistries.
n
n
n
n
n
n
n
n
n
Very Low Dropout Operation: 99% Duty Cycle
Adjustable Soft-Start Current Ramping
Foldback Output Current Limiting
Latched Short-Circuit Shutdown with Defeat Option
Output Overvoltage Protection
Remote Output Voltage Sense
A RUN/SS pin for each controller provides both soft-
start and optional timed, short-circuit shutdown. Current
foldback limits MOSFET dissipation during short-circuit
conditions when overcurrent latchoff is disabled. Output
overvoltage protection circuitry latches on the bottom
Low Shutdown I : 20μA
Q
5V and 3.3V Regulators
3 Selectable Operating Modes: Constant-Frequency,
Burst Mode® Operation and PWM
Available in 32-Pin 5mm × 5mm QFN and
28-Pin SSOP Packages
n
MOSFET until V
returns to normal. The FCB mode
OUT
pin can select among Burst Mode, constant-frequency
mode and continuous inductor current mode or regulate
asecondarywinding. TheLTC3728includesapowergood
output pin that indicates when both outputs are within
7.5% of their designed set point.
APPLICATIONS
n
Notebook and Palmtop Computers
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Telecom Systems
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Portable Instruments
n
Battery-Operated Digital Devices
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode and OPTI-LOOP are
registered trademarks of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents including 5481178, 5929620, 6177787,
6144194, 6100678, 5408150, 6580258, 5705919.
n
DC Power Distribution Systems
V
TYPICAL APPLICATION
IN
5.2V TO 28V
+
C
IN
4.7μF
1μF
22μF
D3
V
PGOOD INTV
D4
IN
CC
M1
M2
50V
TG1
TG2
L1
3.2μH
L2
3.2μH
BOOST1
SW1
BOOST2
SW2
C
, 0.1μF
B2
C
B1
, 0.1μF
LTC3728
BG1
BG2
f
IN
500kHz
PLLIN
PGND
+
+
SENSE1
SENSE2
R
R
SENSE2
SENSE1
1000pF
1000pF
0.01Ω
0.01Ω
–
–
SENSE1
V
I
SENSE2
V
V
3.3V
5A
V
OUT2
OUT1
5V
5A
OSENSE1
TH1
RUN/SS1 SGND RUN/SS2
OSENSE2
R2
105k
1%
R4
63.4k
1%
I
TH2
C
C
C
56μF
6V
C
47μF
6V
C1
220pF
C2
220pF
OUT
OUT1
+
+
R1
20k
1%
R3
20k
1%
R
C
C
C1
SS1
0.1μF
SS2
0.1μF
R
C2
15k
15k
SP
SP
M1, M2: FDS6982S
3728 F01
Figure 1. High Efficiency Dual 5V/3.3V Step-Down Converter
3728fg
1
LTC3728
(Note 1)
ABSOLUTE MAXIMUM RATINGS
I
I
, V
, V
Voltages ... 2.7V to –0.3V
Input Supply Voltage (V ).........................36V to –0.3V
TH1, TH2 OSENSE1 OSENSE2
Peak Output Current <10μs (TG1, TG2, BG1, BG2).....3A
IN
Topside Driver Voltages
INTV Peak Output Current ................................. 50mA
(BOOST1, BOOST2)............................... 42V to –0.3V
Switch Voltage (SW1, SW2) ......................... 36V to –5V
CC
Operating Temperature Range (Note 7).... –40°C to 85°C
Junction Temperature (Note 2) ............................. 125°C
Storage Temperature Range................... –65°C to 125°C
Lead Temperature (Soldering, 10 sec)
INTV EXTV , RUN/SS1, RUN/SS2,
CC,
CC
(BOOST1-SW1), (BOOST2-SW2), PGOOD ..... 7V to –0.3V
+
–
+
–
SENSE1 , SENSE2 , SENSE1 ,
(G Package Only) .................................................. 300°C
SENSE2 Voltages .........................(1.1)INTV to –0.3V
CC
CC
PLLIN, PLLFLTR, FCB Voltages ............ INTV to –0.3V
PIN CONFIGURATION
TOP VIEW
TOP VIEW
1
2
28 PGOOD
27 TG1
RUN/SS1
+
SENSE1
–
32 31 30 29 28 27 26 25
3
26 SW1
SENSE1
V
1
2
3
4
5
6
7
8
24 BOOST1
OSENSE1
4
25 BOOST1
V
OSENSE1
PLLFLTR
PLLIN
FCB
23
22
21
V
IN
5
24
V
IN
PLLFLTR
PLLIN
FCB
BG1
6
23 BG1
22 EXTV
21 INTV
EXTV
CC
7
CC
CC
33
I
20 INTV
TH1
SGND
3.3V
CC
8
I
TH1
PGND
19
9
20 PGND
SGND
18 BG2
OUT
10
11
12
13
14
19 BG2
3.3V
OUT
I
17 BOOST2
TH2
18 BOOST2
17 SW2
I
TH2
9
10 11 12 13 14 15 16
V
OSENSE2
–
16 TG2
SENSE2
SENSE2
+
15 RUN/SS2
G PACKAGE
28-LEAD PLASTIC SSOP
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
T
= 125°C, θ = 90°C/W - SINGLE LAYER BOARD
T
= 125°C, θ = 34°C/W
JMAX
JA
JMAX JA
EXPOSED PAD IS SGND (MUST BE SOLDERED TO PCB)
68º C/W - 4 LAYER
ORDER INFORMATION
LEAD FREE FINISH
LTC3728EG#PBF
LTC3728IG#PBF
LTC3728EUH#PBF
LTC3728IUH#PBF
LEAD BASED FINISH
LTC3728EG
TAPE AND REEL
LTC3728EG#TRPBF
LTC3728IG#TRPBF
LTC3728EUH#TRPBF
LTC3728IUH#TRPBF
TAPE AND REEL
LTC3728EG#TR
PART MARKING*
LTC3728EG
LTC3728IG
3728
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 85°C
28-Lead Plastic SSOP
28-Lead Plastic SSOP
–40°C to 85°C
–40°C to 85°C
32-Lead (5mm × 5mm) Plastic QFN
32-Lead (5mm × 5mm) Plastic QFN
PACKAGE DESCRIPTION
3728
–40°C to 85°C
PART MARKING*
LTC3728EG
LTC3728IG
3728
TEMPERATURE RANGE
–40°C to 85°C
28-Lead Plastic SSOP
LTC3728IG
LTC3728IG#TR
28-Lead Plastic SSOP
–40°C to 85°C
LTC3728EUH
LTC3728EUH#TR
LTC3728IUH#TR
–40°C to 85°C
32-Lead (5mm × 5mm) Plastic QFN
32-Lead (5mm × 5mm) Plastic QFN
LTC3728IUH
3728
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3728fg
2
LTC3728
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
Main Control Loops
l
V
Regulated Feedback Voltage
Feedback Current
(Note 3); I
(Note 3)
Voltage = 1.2V
TH1, 2
0.792
0.800 0.808
V
nA
OSENSE1, 2
I
–5
–50
OSENSE1, 2
V
V
Reference Voltage Line Regulation
Output Voltage Load Regulation
V
= 3.6V to 30V (Note 3)
IN
0.002
0.02
%/V
REFLNREG
LOADREG
(Note 3)
Measured in Servo Loop; ΔI Voltage = 1.2V to 0.7V
Measured in Servo Loop; ΔI Voltage = 1.2V to 2.0V
l
l
0.1
–0.1
0.5
–0.5
%
%
TH
TH
g
g
Transconductance Amplifier g
I
I
= 1.2V; Sink/Source 5μA (Note 3)
= 1.2V (Note 3)
1.3
3
mmho
m1, 2
m
TH1, 2
TH1, 2
Transconductance Amplifier GBW
MHzI
Q
mGBW1, 2
Input DC Supply Current
Normal Mode
(Note 4)
IN
RUN/SS1, 2
V
V
= 15V; EXTV Tied to V ; V = 5V
450
20
μA
μA
CC
OUT1 OUT1
Shutdown
= 0V
35
l
V
Forced Continuous Threshold
Forced Continuous Pin Current
0.76
0.800
–0.18
4.3
0.84
–0.1
4.8
V
μA
V
FCB
I
V
= 0.85V
–0.50
FCB
FCB
V
Burst Inhibit (Constant-Frequency)
Threshold
Measured at FCB Pin
BINHIBIT
l
l
UVLO
Undervoltage Lockout
Feedback Overvoltage Lockout
Sense Pins Total Source Current
Maximum Duty Factor
V
Ramping Down
3.5
0.86
–60
99.4
1.2
4
V
V
IN
V
Measured at V
0.84
–85
98
0.88
OVL
OSENSE1, 2
I
(Each Channel); V
In Dropout
–
– = V + + = 0V
SENSE1 , 2
μA
%
μA
V
SENSE
SENSE1 , 2
DF
MAX
I
Soft-Start Charge Current
V
V
V
= 1.9V
0.5
1.0
RUN/SS1, 2
RUN/SS1, 2
V
V
ON RUN/SS Pin ON Threshold
V Rising
RUN/SS1, RUN/SS2
1.5
1.9
4.5
RUN/SS1, 2
RUN/SS1, 2
LT
RUN/SS Pin Latchoff Arming
Threshold
V
Rising from 3V
3.8
V
RUN/SS1, RUN/SS2
I
I
RUN/SS Discharge Current
Soft-Short Condition V
RUN/SS1, 2
= 0.5V;
OSENSE1, 2
0.5
2
4
5
μA
μA
SCL1, 2
V
= 4.5V
Shutdown Latch Disable Current
Maximum Current Sense Threshold
V
= 0.5V
1.6
SDLHO
OSENSE1, 2
V
V
V
= 0.7V, V
= 0.7V, V
–
– = 5V
– = 5V
65
62
75
75
85
88
mV
mV
SENSE(MAX)
OSENSE1, 2
OSENSE1, 2
OSENSE1 , 2
OSENSE1 , 2
l
–
TG Transition Time:
Rise Time
Fall Time
(Note 5)
TG1, 2 t
TG1, 2 t
C
C
= 3300pF
50
50
90
90
ns
ns
r
f
LOAD
LOAD
= 3300pF
BG Transition Time:
Rise Time
Fall Time
(Note 5)
LOAD
LOAD
BG1, 2 t
BG1, 2 t
C
C
= 3300pF
= 3300pF
40
40
90
80
ns
ns
r
f
TG/BG t
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
1D
C
C
= 3300pF Each Driver
= 3300pF Each Driver
90
ns
LOAD
BG/TG t
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
2D
90
ns
ns
LOAD
t
Minimum On-Time
Tested with a Square Wave (Note 6)
100
ON(MIN)
INTV Linear Regulator
CC
V
V
V
Internal V Voltage
6V < V < 30V, V = 4V
EXTVCC
48
5.0
0.2
80
5.2
1.0
160
V
%
INTVCC
CC
IN
INT
LDO
INTV Load Regulation
I
I
= 0 to 20mA, V
= 4V
CC
CC
CC
EXTVCC
EXT
LDO
EXTV Voltage Drop
= 20mA, V
= 5V
mV
CC
EXTVCC
3728fg
3
LTC3728
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.
SYMBOL
PARAMETER
EXTV Switchover Voltage
CONDITIONS
= 20mA, EXTV Ramping Positive
MIN
TYP
4.7
0.2
MAX UNITS
l
V
I
4.5
V
V
EXTVCC
LDOHYS
CC
CC
CC
V
EXTV Hysteresis
CC
Oscillator and Phase-Locked Loop
f
f
f
Nominal Frequency
Lowest Frequency
Highest Frequency
PLLIN Input Resistance
V
V
V
= 1.2V
= 0V
360
230
480
400
260
550
50
440
290
590
kHz
kHz
kHz
kΩ
NOM
LOW
HIGH
PLLFLTR
PLLFLTR
PLLFLTR
≥ 2.4V
R
PLLIN
I
Phase Detector Output Current
Sinking Capability
PLLFLTR
f
f
< f
OSC
> f
OSC
–15
15
μA
μA
PLLIN
PLLIN
Sourcing Capability
3.3V Linear Regulator
l
V
V
V
3.3V Regulator Output Voltage
3.3V Regulator Load Regulation
3.3V Regulator Line Regulation
No Load
= 0 to 10mA
3.25
3.35
0.5
3.45
2
V
%
3.3OUT
3.3IL
I
3.3
6V < V < 30V
0.05
10
0.2
50
%
3.3VL
IN
RUN/SS1, 2
I
Leakage Current of 3.3V Regulator in
Shutdown
V
= 0V, V = 25V
μA
3.3LEAK
IN
PGOOD Output
V
PGOOD Voltage Low
I
= 2mA
PGOOD
0.1
0.3
1
V
PGL
I
PGOOD Leakage Current
PGOOD Trip Level, Either Controller
V
V
= 5V
μA
PGOOD
PGOOD
V
PG
with Respect to Set Output Voltage
OSENSE
OSENSE
OSENSE
V
V
Ramping Negative
Ramping Positive
–6
6
–7.5
7.5
–9.5
9.5
%
%
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 5: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 6: The IC minimum on-time is tested under an ideal condition
without external power FETs. It can be different when the IC is working in
an actual circuit. See Minimum On-Time Considerations in the Application
Information section.
Note 2: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formulas:
D
LTC3728: T = T + (P • 95 °C/W)
Note 3: The LTC3728 is tested in a feedback loop that servos V
specified voltage and measures the resultant V
Note 4: Dynamic supply current is higher due to the gate charge being
Note 7: The LTC3728E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3728I is guaranteed to meet
performance specifications over the full –40°C to 85°C operating
temperature range.
J
A
D
to a
ITH1, 2
OSENSE1, 2.
delivered at the switching frequency. See Applications Information.
3728fg
4
LTC3728
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Output Current and
Mode (Figure 13)
Efficiency vs Output Current
(Figure 13)
Efficiency vs Input Voltage
(Figure 13)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
100
90
80
70
60
50
Burst Mode
OPERATION
V
= 7V
IN
V
= 10V
IN
FORCED
CONTINUOUS
MODE (PWM)
V
= 15V
IN
V
IN
= 20V
CONSTANT
FREQUENCY
(BURST DISABLE)
V
V
= 15V
OUT
f = 250kHz
V
I
= 5V
= 3A
IN
OUT
OUT
V
= 5V
OUT
= 5V
f = 250kHz
f = 250kHz
0.1
1
0.01
0.1
1
5
15
25
35
0.001
0.01
10
0.001
10
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
INPUT VOLTAGE (V)
3728 G02
3728 G03
3728 G01
Supply Current vs Input Voltage
and Mode (Figure 13)
INTVCC and EXTVCC Switch
Voltage vs Temperature
EXTVCC Voltage Drop
1000
800
600
400
200
0
250
200
150
100
50
5.05
5.00
4.95
4.90
4.85
4.80
4.75
4.70
INTV VOLTAGE
CC
BOTH
CONTROLLERS ON
EXTV SWITCHOVER THRESHOLD
CC
SHUTDOWN
0
50
TEMPERATURE (°C)
100 125
0
5
10
INPUT VOLTAGE (V)
15
20
25
30
35
0
10
20
30
40
50
–50 –25
0
25
75
CURRENT (mA)
3728 G05
3728 G06
3728 G04
Maximum Current Sense
Threshold vs Percent of Nominal
Output Voltage (Foldback)
Maximum Current Sense
Threshold vs Duty Factor
Internal 5V LDO Line Regulation
5.1
5.0
75
50
25
0
80
70
60
50
40
30
20
10
0
I
= 1mA
LOAD
4.9
4.8
4.7
4.6
4.5
4.4
20
INPUT VOLTAGE (V)
30
35
0
5
10
15
25
0
20
40
60
80
100
50
0
25
75
100
DUTY FACTOR (%)
PERCENT ON NOMINAL OUTPUT VOLTAGE (%)
3728 G07
3728 G08
3728 G09
3728fg
5
LTC3728
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Current Sense Threshold
Maximum Current Sense Threshold
Current Sense Threshold
vs ITH Voltage
vs VRUN/SS (Soft-Start)
vs Sense Common Mode Voltage
90
80
80
60
40
20
80
76
72
68
64
60
V
= 1.6V
SENSE(CM)
70
60
50
40
30
20
10
0
–10
–20
–30
0
0
1
2
3
4
5
6
0
0.5
1
1.5
(V)
2
2.5
0
1
2
3
4
5
V
(V)
V
RUN/SS
COMMON MODE VOLTAGE (V)
ITH
3728 G10
3728 G12
3728 G11
Load Regulation
VITH vs VRUN/SS
SENSE Pins Total Source Current
2.5
2.0
1.5
1.0
0.0
–0.1
–0.2
–0.3
–0.4
100
50
V
= 0.7V
FCB = 0V
= 15V
OSENSE
V
IN
0
–50
–100
0.5
0
0
2
3
4
5
6
0
1
2
3
4
5
1
2
4
0
6
V
(V)
LOAD CURRENT (A)
RUN/SS
V
COMMON MODE VOLTAGE (V)
SENSE
3728 G14
3728 G13
3728 G15
Maximum Current Sense
Threshold vs Temperature
Dropout Voltage vs Output Current
(Figure 14)
RUN/SS Current vs Temperature
80
78
76
74
72
70
4
3
2
1
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
V
= 5V
OUT
R
= 0.015Ω
SENSE
R
= 0.010Ω
SENSE
0
0
–50 –25
0
25
50
75 100 125
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
OUTPUT CURRENT (A)
–50 –25
0
25
125
50
75 100
TEMPERATURE (°C)
TEMPERATURE (°C)
3728 G17
3728 G18
3728 G25
3728fg
6
LTC3728
TYPICAL PERFORMANCE CHARACTERISTICS
Soft-Start Up (Figure 13)
Load Step (Figure 13)
Load Step (Figure 13)
V
V
V
OUT
OUT
OUT
5V/DIV
200mV/DIV
200mV/DIV
V
RUN/SS
5V/DIV
I
I
L
L
2A/DIV
2A/DIV
I
L
2A/DIV
3728 G20
3728 G19
3728 G21
20μs/DIV
5ms/DIV
V
V
V
= 15V
= 5V
PLLFLTR
20μs/DIV
V
V
= 15V
= 5V
V
V
V
= 15V
= 5V
PLLFLTR
IN
OUT
IN
OUT
IN
OUT
= 0V
= 0V
LOAD STEP = 0A to 3A
Burst Mode OPERATION
LOAD STEP = 0A to 3A
CONTINUOUS OPERATION
Input Source/Capacitor
Instantaneous Current (Figure 13)
Constant-Frequency (Burst
Inhibit) Operation (Figure 13)
Burst Mode Operation (Figure 13)
I
IN
V
2A/DIV
OUT
V
OUT
20mV/DIV
V
20mV/DIV
IN
200mV/DIV
V
SW1
10V/DIV
V
SW2
I
I
10V/DIV
L
L
0.5A/DIV
0.5A/DIV
3728 G22
3728 G23
3728 G24
1μs/DIV
10μs/DIV
2μs/DIV
V
V
V
I
= 15V
= 5V
V
V
V
V
= 15V
= 5V
PLLFLTR
V
V
V
V
= 15V
= 5V
IN
OUT
IN
OUT
IN
OUT
= 0V
= 0V
= 0V
PLLFLTR
= I
PLLFLTR
= 2A
= OPEN
= 20mA
= 5V
FCB
OUT OUT3.3A
FCB
I
I
= 20mA
OUT
OUT
Current Sense Pin Input Current
vs Temperature
EXTVCC Switch Resistance
vs Temperature
Oscillator Frequency
vs Temperature
35
33
31
29
27
25
700
600
10
8
V
= 5V
OUT
V
= 5V
PLLFLTR
500
400
300
200
100
V
= 1.2V
= 0V
PLLFLTR
6
V
PLLFLTR
4
2
0
0
50
100 125
3728 G28
50
75 100 125
–50 –25
0
25
75
–50 –25
0
25
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3728 G26
3728 G27
3728fg
7
LTC3728
TYPICAL PERFORMANCE CHARACTERISTICS
Undervoltage Lockout
vs Temperature
Shutdown Latch Thresholds
vs Temperature
3.50
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
LATCH ARMING
3.45
3.40
3.35
LATCHOFF
THRESHOLD
3.30
3.25
3.20
0
50
TEMPERATURE (°C)
100 125
–50 –25
0
25
75
–50 –25
0
25
125
50
75 100
TEMPERATURE (°C)
3728 G29
3728 G30
G Package/UH Package
PIN FUNCTIONS
RUN/SS1,RUN/SS2(Pins1,15/Pins28,13):Combination
ofsoft-start, runcontrolinputsandshort-circuitdetection
timers. Acapacitortogroundateachofthesepinssetsthe
ramptimetofulloutputcurrent.Forcingeitherofthesepins
back below 1.0V causes the IC to shut down the circuitry
requiredforthatparticularcontroller. Latchoffovercurrent
protection is also invoked via this pin as described in the
Applications Information section.
with 50kΩ. The phase-locked loop will force the rising
top gate signal of controller 1 to be synchronized with
the rising edge of the PLLIN signal.
FCB (Pin 7/Pin 4): Forced Continuous Control Input.
This input acts on both controllers and is normally used
to regulate a secondary winding. Pulling this pin below
0.8V will force continuous synchronous operation.
I
I
(Pins 8, 11/Pins 5, 8): Error Amplifier Output
+
+
TH1, TH2
SENSE1 , SENSE2 (Pins 2, 14/Pins 30, 12): The (+)
and Switching Regulator Compensation Point. Each as-
sociatedchannels’currentcomparatortrippointincreases
with this control voltage.
Input to the Differential Current Comparators. The I pin
voltage and controlled offsets between the SENSE and
SENSE pins in conjunction with R
trip threshold.
TH
–
+
set the current
SENSE
SGND (Pin 9/Pin 6): Small Signal Ground common to
both controllers, must be routed separately from high
current grounds to the common (–) terminals of the
–
–
SENSE1 , SENSE2 (Pins 3, 13/Pins 31, 11): The (–)
Input to the Differential Current Comparators.
C
capacitors.
OUT
V
, V
(Pins 4, 12/Pins 1, 9): Receives the
OSENSE1 OSENSE2
3.3V
(Pin 10/Pin 7): Output of a linear regulator ca-
OUT
remotely-sensedfeedbackvoltageforeachcontrollerfrom
an external resistive divider across the output.
pable of supplying 10mA DC with peak currents as high
as 50mA.
PLLFLTR(Pin5/Pin2):ThePhase-LockedLoop’sLowpass
FilterisTiedtoThisPin.Alternatively,thispincanbedriven
with an AC or DC voltage source to vary the frequency of
the internal oscillator.
NC (Pins 10, 16, 29, 32 UH Package Only): No Connect.
PGND (Pin 20/Pin 19): Driver Power Ground. Connects to
thesourcesofbottom(synchronous)N-channelMOSFETs,
anodes of the Schottky rectifiers and the (–) terminal(s)
PLLIN (Pin 6/Pin 3): External Synchronization Input to
Phase Detector. This pin is internally terminated to SGND
of C .
IN
3728fg
8
LTC3728
PIN FUNCTIONS
INTV (Pin 21/Pin 20): Output of the Internal 5V Linear
are connected between the boost and switch pins and
CC
LowDropoutRegulatorandtheEXTV Switch. Thedriver
Schottky diodes are tied between the boost and INTV
CC
CC
and control circuits are powered from this voltage source.
Must be decoupled to power ground with a minimum of
4.7μF tantalum or other low ESR capacitor.
pins. Voltage swing at the boost pins is from INTV to
CC
(V + INTV ).
IN
CC
SW1, SW2 (Pins 26, 17/Pins 25, 15): Switch Node
Connections to Inductors. Voltage swing at these pins
is from a Schottky diode (external) voltage drop below
EXTV (Pin 22/Pin 21): External Power Input to an
CC
Internal Switch Connected to INTV . This switch closes
CC
and supplies V power, bypassing the internal low drop-
ground to V .
CC
IN
out regulator, whenever EXTV is higher than 4.7V. See
CC
TG1, TG2 (Pins 27, 16/Pins 26, 14): High Current Gate
Drives for Top N-Channel MOSFETs. These are the out-
puts of floating drivers with a voltage swing equal to
EXTV connection in Applications section. Do not exceed
CC
7V on this pin.
BG1, BG2 (Pins 23, 19/Pins 22, 18): High Current Gate
INTV – 0.5V superimposed on the switch node voltage
CC
Drives for Bottom (Synchronous) N-Channel MOSFETs.
SW.
Voltage swing at these pins is from ground to INTV .
CC
PGOOD(Pin28/Pin27):Open-DrainLogicOutput.PGOOD
V
(Pin 24/Pin 23): Main Supply Pin. A bypass capaci-
is pulled to ground when the voltage on either V
pin is not within 7.5% of its set point.
IN
OSENSE
tor should be tied between this pin and the signal ground
pin.
Exposed Pad (Pin 33) SGND: The Exposed Pad must be
soldered to PCB ground for electrical contact and rated
thermal performance.
BOOST1,BOOST2(Pins25,18/Pins24,17):Bootstrapped
Supplies to the Topside Floating Drivers. Capacitors
3728fg
9
LTC3728
FUNCTIONAL DIAGRAM
PLLIN
INTV
CC
V
IN
F
IN
PHASE DET
D
C
B
DUPLICATE FOR SECOND
CONTROLLER CHANNEL
50k
BOOST
TG
PLLFLTR
B
DROP
OUT
+
CLK1
CLK2
–
TOP
BOT
R
LP
C
C
IN
D
OSCILLATOR
1
DET
BOT
FCB
C
LP
SW
TOP ON
0.86V
S
Q
Q
+
SWITCH
LOGIC
INTV
CC
R
V
OSENSE1
PGOOD
BG
–
+
0.74V
0.86V
OUT
PGND
B
+
+
–
0.55V
–
+
V
OUT
SHDN
R
SENSE
V
OSENSE2
–
+
INTV
CC
0.74V
BINH
I1
I2
V
SEC
1.5V
+
–
+
–
+
4.5V
0.8V
–
+ +
–
+
+
0.18μA
FCB
–
SENSE
SENSE
D
C
SEC
SEC
30k
30k
R6
3mV
0.86V
4(V
–
)
+
–
FB
FCB
R5
SLOPE
COMP
45k
45k
2.4V
3.3V
V
OUT
OSENSE
R2
V
+
–
V
FB
REF
–
EA
+
0.80V
0.86V
R1
OV
V
IN
+
–
V
IN
C
C
+
–
4.7V
I
TH
5V
1.2μA
EXTV
INTV
LDO
REG
CC
SHDN
RST
4(V
FB
RUN
SOFT
START
R
C
C
C2
SS
6V
)
CC
5V
+
RUN/SS
INTERNAL
SUPPLY
SGND
C
3728 FD/F02
Figure 2
3728fg
10
LTC3728
OPERATION (Refer to Functional Diagram)
Main Control Loop
low currentoperation. When theFCBpin voltage is below
0.8V,thecontrollerforcescontinuousPWMcurrentmode
operation. In this mode, the top and bottom MOSFETs
are alternately turned on to maintain the output voltage
independent of direction of inductor current. When the
The LTC3728 uses a constant-frequency, current mode
step-down architecture with the two controller channels
operating180degreesoutofphase. Duringnormalopera-
tion, each top MOSFET is turned on when the clock for
that channel sets the RS latch, and turned off when the
main current comparator, I1, resets the RS latch. The peak
inductorcurrentatwhichI1resetstheRSlatchiscontrolled
FCB pin is below V
– 1V but greater than 0.8V,
INTVCC
the controller enters Burst Mode operation. Burst Mode
operation sets a minimum output current level before
inhibiting the top switch and turns off the synchronous
MOSFET(s)whentheinductorcurrentgoesnegative.This
combination of requirements will, at low currents, force
by the voltage on the I pin, which is the output of each
TH
error amplifier EA. The V
pin receives the voltage
OSENSE
feedback signal, which is compared to the internal refer-
the I pin below a voltage threshold that will temporarily
TH
ence voltage by the EA. When the load current increases,
inhibit turn-on of both output MOSFETs until the output
it causes a slight decrease in V
relative to the 0.8V
OSENSE
voltage drops. There is 60mV of hysteresis in the burst
reference, which in turn causes the I voltage to increase
TH
comparatorBtiedtotheI pin.Thishysteresisproduces
TH
until the average inductor current matches the new load
current. After the top MOSFET has turned off, the bottom
MOSFET is turned on until either the inductor current
starts to reverse, as indicated by current comparator I2,
or the beginning of the next cycle.
outputsignalstotheMOSFETsthatturnthemonforseveral
cycles, followed by a variable “sleep” interval depending
upontheloadcurrent. Theresultantoutputvoltageripple
is held to a very small value by having the hysteretic
comparator after the error amplifier gain block.
ThetopMOSFETdriversarebiasedfromfloatingbootstrap
capacitor C , which normally is recharged during each off
Frequency Synchronization
B
cycle through an external diode when the top MOSFET
The phase-locked loop allows the internal oscillator to
be synchronized to an external source via the PLLIN pin.
The output of the phase detector at the PLLFLTR pin is
also the DC frequency control input of the oscillator that
operates over a 250kHz to 550kHz range corresponding
to a DC voltage input from 0V to 2.4V. When locked, the
PLL aligns the turn on of the top MOSFET to the rising
edge of the synchronizing signal. When PLLIN is left
open, the PLLFLTR pin goes low, forcing the oscillator to
minimum frequency.
turns off. As V decreases to a voltage close to V , the
IN
OUT
loop may enter dropout and attempt to turn on the top
MOSFET continuously. The dropout detector detects this
andforcesthetopMOSFEToffforabout400nseverytenth
cycle to allow C to recharge.
B
The main control loop is shut down by pulling the RUN/
SS pin low. Releasing RUN/SS allows an internal 1.2μA
current source to charge soft-start capacitor C . When
SS
C
SS
reaches 1.5V, the main control loop is enabled with
the I voltage clamped at approximately 30% of its
TH
Constant-Frequency Operation
maximum value. As C continues to charge, the I
SS
TH
pin voltage is gradually released allowing normal, full-
current operation. When both RUN/SS1 and RUN/SS2
are low, all LTC3728 controller functions are shut down,
including the 5V and 3.3V regulators.
When the FCB pin is tied to INTV , Burst Mode opera-
CC
tion is disabled and the forced minimum output current
requirementisremoved.Thisprovidesconstant-frequency,
discontinuous (preventing reverse inductor current)
current operation over the widest possible output current
range.Thisconstant-frequencyoperationisnotasefficient
as Burst Mode operation, but does provide a lower noise,
constant-frequencyoperatingmodedowntoapproximately
1% of designed maximum output current.
Low Current Operation
The FCB pin is a multifunction pin providing two func-
tions: 1) to provide regulation for a secondary winding
by temporarily forcing continuous PWM operation on
both controllers; and 2) select between two modes of
3728fg
11
LTC3728
OPERATION (Refer to Functional Diagram)
Continuous Current (PWM) Operation
Foldback Current, Short-Circuit Detection
and Short-Circuit Latchoff
Tying the FCB pin to ground will force continuous current
operation. This is the least efficient operating mode, but
may be desirable in certain applications. The output can
source or sink current in this mode. When sinking current
whileinforcedcontinuousoperation,currentwillbeforced
back into the main power supply.
TheRUN/SScapacitorsareusedinitiallytolimittheinrush
current of each switching regulator. After the controller
has been started and been given adequate time to charge
up the output capacitors and provide full load current, the
RUN/SScapacitorisusedinashort-circuittime-outcircuit.
If the output voltage falls to less than 70% of its nominal
output voltage, the RUN/SS capacitor begins discharging
on the assumption that the output is in an overcurrent
and/or short-circuit condition. If the condition lasts for
a long enough period as determined by the size of the
RUN/SS capacitor, the controller will be shut down until
the RUN/SS pin(s) voltage(s) are recycled. This built-in
latchoff can be overridden by providing a >5μA pull-up
at a compliance of 5V to the RUN/SS pin(s). This current
shortens the soft start period but also prevents net dis-
charge of the RUN/SS capacitor(s) during an overcurrent
and/or short-circuit condition. Foldback current limiting
is also activated when the output voltage falls below
70% of its nominal level whether or not the short-circuit
latchoff circuit is enabled. Even if a short is present and
the short-circuit latchoff is not enabled, a safe, low output
current is provided due to internal current foldback and
actual power wasted is low due to the efficient nature of
the current mode switching regulator.
INTV /EXTV Power
CC
CC
Power for the top and bottom MOSFET drivers and most
otherinternalcircuitryisderivedfromtheINTV pin.When
CC
the EXTV pin is left open, an internal 5V low dropout
CC
linear regulator supplies INTV power. If EXTV is taken
CC
CC
above 4.7V, the 5V regulator is turned off and an internal
switch is turned on connecting EXTV to INTV . This al-
CC
CC
lowstheINTV powertobederivedfromahighefficiency
CC
external source such as the output of the regulator itself
or a secondary winding, as described in the Applications
Information section.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>7.5%) as well as other more serious condi-
tions that may overvoltage the output. In this case, the top
MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
THEORY AND BENEFITS OF 2-PHASE OPERATION
Power Good (PGOOD) Pin
The LTC1628 and the LTC3728 dual high efficiency DC/DC
controllers bring the considerable benefits of 2-phase op-
erationtoportableapplicationsforthefirsttime.Notebook
computers, PDAs, handheld terminals and automotive
electronics will all benefit from the lower input filter-
ing requirement, reduced electromagnetic interference
(EMI) and increased efficiency associated with 2-phase
operation.
ThePGOODpinisconnectedtoanopendrainofaninternal
MOSFET. TheMOSFETturnsonandpullsthepinlowwhen
either output is not within 7.5% of the nominal output
levelasdeterminedbytheresistivefeedbackdivider.When
both outputs meet the 7.5% requirement, the MOSFET is
turned off within 10μs and the pin is allowed to be pulled
up by an external resistor to a source of up to 7V.
3728fg
12
LTC3728
OPERATION (Refer to Functional Diagram)
5V SWITCH
20V/DIV
3.3V SWITCH
20V/DIV
INPUT CURRENT
5A/DIV
INPUT VOLTAGE
500mV/DIV
3728 F03a
3728 F03b
I
= 2.53A
(a)
I
= 1.55A
(b)
IN(MEAS)
RMS
IN(MEAS)
RMS
Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators
Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the LTC1628 2-Phase Regulator Allows
Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency
Why the need for 2-phase operation? Up until the 2-
phase family, constant-frequency dual switching regula-
tors operated both channels in phase (i.e., single-phase
operation). This means that both switches turned on at
the same time, causing current pulses of up to twice the
amplitude of those for one regulator to be drawn from the
input capacitor and battery. These large amplitude current
pulses increased the total RMS current flowing from the
input capacitor, requiring the use of more expensive input
capacitorsandincreasingbothEMIandlossesintheinput
capacitor and battery.
that 2-phase operation dropped the input current from
2.53A
to 1.55A
. While this is an impressive
RMS
RMS
reduction in itself, remember that the power losses are
2
proportionaltoI
,meaningthattheactualpowerwasted
RMS
is reduced by a factor of 2.66. The reduced input ripple
voltage also means less power is lost in the input power
path, which could include batteries, switches, trace/con-
nectorresistancesandprotectioncircuitry.Improvements
inbothconductedandradiatedEMIalsodirectlyaccrueas
a result of the reduced RMS input current and voltage.
Of course, the improvement afforded by 2-phase opera-
tion is a function of the dual switching regulator’s relative
duty cycles which, in turn, are dependent upon the input
With 2-phase operation, the two channels of the dual-
switchingregulatorareoperated180degreesoutofphase.
Thiseffectivelyinterleavesthecurrentpulsesdrawnbythe
switches,greatlyreducingtheoverlaptimewheretheyadd
together. The result is a significant reduction in total RMS
input current, which in turn allows less expensive input
capacitors to be used, reduces shielding requirements for
EMI and improves real world operating efficiency.
voltage V (Duty Cycle = V /V ). Figure 4 shows how
IN
OUT IN
theRMSinputcurrentvariesforsingle-phaseand2-phase
operation for 3.3V and 5V regulators over a wide input
voltage range.
Itcanreadilybeseenthattheadvantagesof2-phaseopera-
tion are not just limited to a narrow operating range, but
in fact extend over a wide region. A good rule of thumb
for most applications is that 2-phase operation will reduce
theinputcapacitorrequirementtothatforjustonechannel
operating at maximum current and 50% duty cycle.
Figure 3 compares the input waveforms for a representa-
tive single-phase dual switching regulator to the LTC1628
2-phase dual switching regulator. An actual measurement
of the RMS input current under these conditions shows
3728fg
13
LTC3728
OPERATION (Refer to Functional Diagram)
3.0
2.5
2.0
1.5
1.0
0.5
0
A final question: If 2-phase operation offers such an ad-
vantage over single-phase operation for dual switching
regulators, why hasn’t it been done before? The answer
is that, while simple in concept, it is hard to implement.
Constant-frequency current mode switching regulators
require an oscillator derived slope compensation signal
to allow stable operation of each regulator at over 50%
duty cycle. This signal is relatively easy to derive in
single-phase dual switching regulators, but required the
development of a new and proprietary technique to allow
2-phase operation. In addition, isolation between the two
channels becomes more critical with 2-phase operation
becauseswitchtransitionsinonechannelcouldpotentially
disrupt the operation of the other channel.
SINGLE PHASE
DUAL CONTROLLER
2-PHASE
DUAL CONTROLLER
V
V
= 5V/3A
O1
O2
= 3.3V/3A
0
10
20
30
40
INPUT VOLTAGE (V)
3728 F04
Figure 4. RMS Input Current Comparison
These 2-phase parts are proof that these hurdles have
been surmounted. They offer unique advantages for the
ever-expanding number of high efficiency power supplies
required in portable electronics.
3728fg
14
LTC3728
APPLICATIONS INFORMATION
2.5
2.0
1.5
1.0
0.5
0
Figure 1 on the first page is a basic LTC3728 application
circuit. External component selection is driven by the
loadrequirement,andbeginswiththeselectionofR
SENSE
and the inductor value. Next, the power MOSFETs and
D1 are selected. Finally, C and C are selected. The
IN
OUT
circuit shown in Figure 1 can be configured for operation
up to an input voltage of 28V (limited by the external
MOSFETs).
R
SENSE
Selection for Output Current
200 250 300 350 400 450 500 550
OPERATING FREQUENCY (kHz)
R
ischosenbasedontherequiredoutputcurrent.The
SENSE
3728 F05
LTC3728 current comparator has a maximum threshold
of 75mV/R
and an input common mode range of
SENSE
Figure 5. PPLFLTR Pin Voltage vs Frequency
SGND to 1.1(INTV ). The current comparator threshold
CC
sets the peak of the inductor current, yielding a maximum
and Frequency Synchronization in the Applications Infor-
mation section for additional information.
average output current I
half the peak-to-peak ripple current, ΔI .
equal to the peak value less
MAX
L
A graph for the voltage applied to the PLLFLTR pin vs
frequency is given in Figure 5. As the operating frequency
isincreasedthegatechargelosseswillbehigher, reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 550kHz.
AllowingamarginforvariationsintheLTC3728andexternal
component values yields:
50mV
IMAX
RSENSE
=
Inductor Value Calculation
BecauseofpossiblePCBnoiseinthecurrentsensingloop,
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because
of MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.
the AC current sensing ripple of ΔV = ΔI • R
also needs to be checked in the design to get good sig-
nal-to-noise ratio. In general, for a reasonable good PCB
SENSE
SENSE
layout, a 15mV ΔV
voltage is recommended as a
SENSE
conservative number to start with.
When using the controller in very low dropout conditions,
themaximumoutputcurrentlevelwillbereducedduetothe
internal compensation required to meet stability criterion
for buck regulators operating at greater than 50% duty
factor. A curve is provided to estimate this reduction in
peak output current level depending upon the operating
duty factor.
The inductor value has a direct effect on ripple current.
The inductor ripple current ΔI decreases with higher
L
inductance or frequency and increases with higher V :
IN
ꢁ
ꢃ
ꢂ
OUT ꢄ
V
1
ꢀIL =
VOUT 1–
Operating Frequency
ꢆ
(f)(L)
V
IN
ꢅ
The LTC3728 uses a constant-frequency, phase-lockable
architecture with the frequency determined by an internal
capacitor. This capacitor is charged by a fixed current plus
an additional current which is proportional to the voltage
applied to the PLLFLTR pin. Refer to Phase-Locked Loop
Accepting larger values of ΔI allows the use of low
L
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ΔI =0.3(I
) or higher for good
L
MAX
3728fg
15
LTC3728
APPLICATIONS INFORMATION
load transient response and sufficient ripple current sig-
Power MOSFET and D1 Selection
nal in the current loop. The maximum ΔI occurs at the
L
Two external power MOSFETs must be selected for each
controller in the LTC3728: One N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for
the bottom (synchronous) switch.
maximum input voltage.
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
The peak-to-peak drive levels are set by the INTV
CC
25% of the current limit determined by R
. Lower
SENSE
voltage. This voltage is typically 5V during start-up
inductor values (higher ΔI ) will cause this to occur at
L
(see EXTV Pin Connection). Consequently, logic-level
CC
lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected
(V <5V);then,sublogiclevelthresholdMOSFETs(V
IN
GS(TH)
< 3V) should be used. Pay close attention to the BV
DSS
specification for the MOSFETs as well; most of the logic
Inductor Core Selection
level MOSFETs are limited to 30V or less.
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
affordthecorelossfoundinlowcostpowderedironcores,
forcing the use of more expensive ferrite, molypermalloy,
orKoolMμ® cores. Actualcorelossisindependentofcore
size for a fixed inductor value, but it is very dependent
on inductance selected. As inductance increases, core
losses go down. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Selection criteria for the power MOSFETs include the
on-resistanceR
,reverse-transfercapacitanceC
,
DS(ON)
RSS
input voltage and maximum output current. When the
LTC3728 is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:
VOUT
Main Switch Duty Cycle =
V
IN
V – VOUT
IN
Synchronous SwitchDuty Cycle=
V
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates hard, which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
IN
The MOSFET power dissipations at maximum output
current are given by:
VOUT
2
)
I
PMAIN
=
I
1+ ꢀ R
+
(
)
(
)
MAX
DS(ON)
V
IN
2
k V
I
C
f
( )
)
(
IN ) ( MAX
(
RSS
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive
than ferrite. A reasonable compromise from the same
manufacturer is Kool Mμ. Toroids are very space efficient,
especiallywhenyoucanuseseverallayersofwire.Because
they generally lack a bobbin, mounting is more difficult.
However, designs for surface mount are available that do
not increase the height significantly.
V – VOUT
2
IN
PSYNC
=
1+ ꢀ R
DS(ON)
(
)
(
)
MAX
V
IN
where δ is the temperature dependency of R
and k
DS(ON)
is a constant inversely related to the gate drive current.
2
BothMOSFETshaveI RlosseswhilethetopsideN-channel
equation includes an additional term for transition losses,
3728fg
16
LTC3728
APPLICATIONS INFORMATION
which are highest at high input voltages. For V < 20V
requirement. Increasing the output current, drawn from
theotherout-of-phasecontroller,willactuallydecreasethe
input RMS ripple current from this maximum value (see
Figure 4). The out-of-phase technique typically reduces
the input capacitor’s RMS ripple current by a factor of
30% to 70% when compared to a single phase power
supply solution.
IN
the high current efficiency generally improves with larger
MOSFETs, while for V > 20V the transition losses rapidly
IN
increasetothepointthattheuseofahigherR
device
DS(ON)
with lower C
actually provides higher efficiency. The
RSS
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100% of the period.
The type of input capacitor, value and ESR rating have
efficiency effects that need to be considered in the selec-
tion process. The capacitance value chosen should be
sufficient to store adequate charge to keep high peak
battery currents down. 20μF to 40μF is usually sufficient
for a 25W output supply operating at 200kHz. The ESR of
the capacitor is important for capacitor power dissipation
as well as overall battery efficiency. All of the power (RMS
ripple current • ESR) not only heats up the capacitor but
wastes power from the battery.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R
vs Temperature curve, but
DS(ON)
δ = 0.005/°C can be used as an approximation for low
voltageMOSFETs.C isusuallyspecifiedintheMOSFET
RSS
characteristics. The constant k = 1.7 can be used to esti-
mate the contributions of the two terms in the main switch
dissipation equation.
The Schottky diode D1 shown in Figure 1 conducts dur-
ing the dead time between the conduction of the two
power MOSFETs. This prevents the body diode of the
bottom MOSFET from turning on, storing charge during
the dead time and requiring a reverse recovery period
Medium voltage (20V to 35V) ceramic, tantalum, OS-CON
and switcher-rated electrolytic capacitors can be used
as input capacitors, but each has drawbacks: ceramic
voltage coefficients are very high and may have audible
piezoelectric effects; tantalums need to be surge-rated;
OS-CONs suffer from higher inductance, larger case size
and limited surface-mount applicability; electrolytics’
higher ESR and dryout possibility require several to be
used. Multiphase systems allow the lowest amount of
capacitance overall. As little as one 22μF or two to three
10μF ceramic capacitors are an ideal choice in a 20W to
35W power supply due to their extremely low ESR. Even
though the capacitance at 20V is substantially below their
rating at zero-bias, very low ESR loss makes ceramics
an ideal candidate for highest efficiency battery operated
systems. Also consider parallel ceramic and high quality
electrolytic capacitors as an effective means of achieving
ESR and bulk capacitance goals.
that could cost as much as 3% in efficiency at high V .
IN
A 1A to 3A Schottky is generally a good compromise for
both regions of operation due to the relatively small aver-
age current. Larger diodes result in additional transition
losses due to their larger junction capacitance. Schottky
diodes should be placed in parallel with the synchronous
MOSFETs when operating in pulse-skip mode or in Burst
Mode operation.
C and C
Selection
IN
OUT
The selection of C is simplified by the multiphase ar-
IN
chitecture and its impact on the worst-case RMS current
drawnthroughtheinputnetwork(battery/fuse/capacitor).
It can be shown that the worst case RMS current occurs
when only one controller is operating. The controller with
Incontinuousmode,thesourcecurrentofthetopN-channel
the highest (V )(I ) product needs to be used in the
MOSFETisasquarewaveofdutycycleV /V .Toprevent
OUT OUT
OUT IN
formula below to determine the maximum RMS current
largevoltagetransients,alowESRinputcapacitorsizedfor
3728fg
17
LTC3728
APPLICATIONS INFORMATION
the maximum RMS current of one channel must be used.
The maximum RMS capacitor current is given by:
The output ripple (ΔV ) is determined by:
OUT
ꢂ
ꢅ
1
8fC
ꢀVOUT ꢁ ꢀIL ESR+
ꢄ
ꢇ
ꢄ1/2
ꢅ
ꢃ
OUT ꢆ
ꢂ
VOUT V ꢁ V
(
)
IN
OUT
ꢃ
CIN RequiredIRMS ꢀIMAX
Wheref=operatingfrequency, C
=outputcapacitance,
V
OUT
IN
and ΔI = ripple current in the inductor. The output ripple is
L
This formula has a maximum at V = 2V , where
highestatmaximuminputvoltagesinceΔI increaseswith
IN
OUT
L
I
= I /2. This simple worst case condition is com-
input voltage. With ΔI = 0.3I
the output ripple
RMS
OUT
L
OUT(MAX)
monlyusedfordesignbecauseevensignificantdeviations
donotoffermuchrelief.Notethatcapacitormanufacturer’s
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the capaci-
tor, or to choose a capacitor rated at a higher temperature
than required. Several capacitors may also be paralleled
to meet size or height requirements in the design. Always
consult the manufacturer if there is any question.
will typically be less than 50mV at max V assuming:
IN
C
OUT
Recommended ESR < 2 R
SENSE
and C
> 1/(8fR
)
SENSE
OUT
ThefirstconditionrelatestotheripplecurrentintotheESR
oftheoutputcapacitancewhilethesecondtermguarantees
thattheoutputcapacitancedoesnotsignificantlydischarge
duringtheoperatingfrequencyperiodduetoripplecurrent.
The choice of using smaller output capacitance increases
the ripple voltage due to the discharging term but can be
compensated for by using capacitors of very low ESR to
maintain the ripple voltage at or below 50mV. The ITH pin
OPTI-LOOP compensation components can be optimized
to provide stable, high performance transient response
regardless of the output capacitors selected.
ThebenefitoftheLTC3728multiphasecanbecalculatedby
using the equation above for the higher power controller
and then calculating the loss that would have resulted if
both controller channels switch on at the same time. The
total RMS power lost is lower when both controllers are
operatingduetotheinterleavingofcurrentpulsesthrough
the input capacitor’s ESR. This is why the input capacitor’s
requirementcalculatedabovefortheworst-casecontroller
is adequate for the dual controller design. Remember that
inputprotectionfuseresistance,batteryresistanceandPC
board trace resistance losses are also reduced due to the
reduced peak currentsina multiphase system. The overall
benefit of a multiphase design will only be fully realized
when the source impedance of the power supply/battery
is included in the efficiency testing. The drains of the
two top MOSFETs should be placed within 1cm of each
Manufacturers such as Nichicon, United Chemicon and
Sanyo can be considered for high performance through-
hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON capacitors is recommended to reduce the
inductance effects.
other and share a common C (s). Separating the drains
IN
In surface mount applications multiple capacitors may
need to be used in parallel to meet the ESR, RMS current
handling and load step requirements of the application.
Aluminum electrolytic, dry tantalum and special polymer
capacitorsareavailableinsurfacemountpackages.Special
polymer surface mount capacitors offer very low ESR but
and C may produce undesirable voltage and current
IN
resonances at V .
IN
The selection of C
is driven by the required effective
OUT
series resistance (ESR). Typically, once the ESR require-
ment is satisfied the capacitance is adequate for filtering.
3728fg
18
LTC3728
APPLICATIONS INFORMATION
have lower storage capacity per unit volume than other
capacitor types. These capacitors offer a very cost-effec-
tiveoutputcapacitorsolutionandareanidealchoicewhen
combined with a controller having high loop bandwidth.
Tantalum capacitors offer the highest capacitance density
and are often used as output capacitors for switching
regulators having controlled soft-start. Several excellent
surge-tested choices are the AVX TPS, AVX TPSV or the
KEMET T510 series of surface mount tantalums, available
in case heights ranging from 2mm to 4mm. Aluminum
electrolytic capacitors can be used in cost-driven ap-
plications providing that consideration is given to ripple
current ratings, temperature and long term reliability. A
typical application will require several to many aluminum
electrolytic capacitors in parallel. A combination of the
aforementioned capacitors will often result in maximizing
performance and minimizing overall cost. Other capacitor
types include Nichicon PL series, NEC Neocap, Cornell
Dubilier ESRE and Sprague 595D series. Consult manu-
facturers for other specific recommendations.
input pin. When the voltage applied to the EXTV pin is
CC
less than 4.7V, all of the INTV current is supplied by
CC
the internal 5V linear regulator. Power dissipation for the
IC in this case is highest: (V )(I
), and overall ef-
IN INTVCC
ficiency is lowered. The gate charge current is dependent
on operating frequency, as discussed in the Efficiency
Considerations section. The junction temperature can be
estimated by using the equations given in Note 2 of the
Electrical Characteristics. For example, the LTC3728 V
IN
current is limited to less than 24mA from a 24V supply
when not using the EXTV pin, as follows:
CC
T = 70°C + (24mA)(24V)(95°C/W) = 125°C
J
Use of the EXTV input pin reduces the junction tem-
CC
perature to:
T = 70°C + (24mA)(5V)(95°C/W) = 81°C
J
Dissipationshouldbecalculatedtoalsoincludeanyadded
current drawn from the internal 3.3V linear regulator.
To prevent maximum junction temperature from being
exceeded, the input supply current must be checked op-
INTV Regulator
erating in continuous mode at maximum V .
CC
IN
An internal P-channel low dropout regulator produces 5V
at the INTVCC pin from the VIN supply pin. INTVCC pow-
ers the drivers and internal circuitry within the LTC3728.
The INTVCC pin regulator can supply a peak current of
50mA and must be bypassed to ground with a minimum
of 4.7ꢀF tantalum, 10μF special polymer, or low ESR type
electrolytic capacitor. A 1μF ceramic capacitor placed di-
rectly adjacent to the INTVCC and PGND IC pins is highly
recommended. Good bypassing is necessary to supply
the high transient currents required by the MOSFET gate
drivers and to prevent interaction between channels.
EXTV Connection
CC
The LTC3728 contains an internal P-channel MOSFET
switch connected between the EXTV and INTV pins.
When the voltage applied to EXTV rises above 4.7V,
CC
CC
CC
the internal regulator is turned off and the switch closes,
connecting the EXTV pin to the INTV pin thereby
CC
CC
supplying internal power. The switch remains closed as
long as the voltage applied to EXTV remains above 4.5V.
CC
This allows the MOSFET driver and control power to be
derived from the output during normal operation (4.7V
< V
< 7V) and from the internal regulator when the
OUT
Higher input voltage applications in which large MOS-
FETs are being driven at high frequencies may cause the
maximum junction temperature rating for the LTC3728
to be exceeded. The system supply current is normally
dominated by the gate charge current. Additional external
outputisoutofregulation(start-up, short-circuit). Ifmore
current is required through the EXTV switch than is
CC
specified,anexternalSchottkydiodecanbeaddedbetween
the EXTV and INTV pins. Do not apply greater than 7V
CC
CC
to the EXTV pin and ensure that EXTV < V .
CC
CC
IN
loading of the INTV and 3.3V linear regulators also
CC
Significant efficiency gains can be realized by powering
INTV from the output, since the V current resulting
needs to be taken into account for the power dissipation
calculations. The total INTV current can be supplied by
CC
IN
CC
from the driver and control currents will be scaled by a
either the 5V internal linear regulator or by the EXTV
CC
3728fg
19
LTC3728
APPLICATIONS INFORMATION
factor of (Duty Cycle)/(Efficiency). For 5V regulators this
Topside MOSFET Driver Supply (C , D )
B B
supply means connecting the EXTV pin directly to V
.
CC
OUT
External bootstrap capacitors C connected to the BOOST
B
However, for 3.3V and other lower voltage regulators,
pins supply the gate drive voltages for the topside MOS-
additional circuitry is required to derive INTV power
CC
FETs. Capacitor C in the Functional Diagram is charged
B
from the output.
though external diode D from INTV when the SW pin
B
CC
The following list summarizes the four possible connec-
is low. When one of the topside MOSFETs is to be turned
tions for EXTV
on, thedriverplacestheC voltageacrossthegate-source
CC:
B
of the desired MOSFET. This enhances the MOSFET and
turns on the topside switch. The switch node voltage, SW,
1. EXTV Left Open (or Grounded). This will cause INTV
CC
CC
to be powered from the internal 5V regulator resulting in
rises to V and the BOOST pin follows. With the topside
IN
an efficiency penalty of up to 10% at high input voltages.
MOSFET on, the boost voltage is above the input supply:
2. EXTV Connected Directly to V . This is the normal
CC
OUT
V
= V + V
. The value of the boost capacitor
BOOST
IN
INTVCC
connection for a 5V regulator and provides the highest
C needstobe100timesthatofthetotalinputcapacitance
B
efficiency.
of the topside MOSFET(s). The reverse breakdown of the
external Schottky diode must be greater than V
.
3. EXTV Connected to an External Supply. If an external
IN(MAX)
CC
When adjusting the gate drive level, the final arbiter is the
total input current for the regulator. If a change is made
and the input current decreases, then the efficiency has
improved. If there is no change in input current, then there
is no change in efficiency.
supply is available in the 5V to 7V range, it may be used
to power EXTV providing it is compatible with the
CC
MOSFET gate drive requirements.
4. EXTV ConnectedtoanOutput-DerivedBoostNetwork.
CC
For 3.3V and other low voltage regulators, efficiency
gains can still be realized by connecting EXTV to an
CC
Output Voltage
output-derivedvoltagethathasbeenboostedtogreater
than 4.7V. This can be done with either the inductive
boost winding as shown in Figure 6a or the capacitive
charge pump shown in Figure 6b. The charge pump
has the advantage of simple magnetics.
The LTC3728 output voltages are each set by an exter-
nal feedback resistive divider carefully placed across
the output capacitor. The resultant feedback signal is
compared with the internal precision 0.800V voltage
+
V
V
IN
IN
1MF
OPTIONAL EXTV
CONNECTION
CC
+
+
5V < V
< 7V
SEC
C
C
IN
IN
0.22MF
BAT85
BAT85
BAT85
V
V
V
SEC
IN
IN
+
+
LTC3728
CC
LTC3728
CC
1MF
VN2222LL
TG1
SW
TG1
SW
R
R
SENSE
SENSE
N-CH
N-CH
N-CH
N-CH
V
OUT
V
OUT
L1
T1
1:N
EXTV
EXTV
FCB
R6
R5
+
C
C
BG1
OUT
BG1
OUT
SGND
PGND
PGND
3728 F06b
3728 F06a
Figure 6a. Secondary Output Loop and EXTVCC Connection
Figure 6b. Capacitive Charge Pump for EXTVCC
3728fg
20
LTC3728
APPLICATIONS INFORMATION
referencebytheerroramplifier.Theoutputvoltageisgiven
by the equation:
Soft-Start/Run Function
The RUN/SS1 and RUN/SS2 pins are multipurpose pins
thatprovideasoft-startfunctionandameanstoshutdown
the LTC3728. Soft-start reduces the input power source’s
surge currents by gradually increasing the controller’s
current limit (proportional to V ). This pin can also be
used for power supply sequencing.
R2
R1
ꢀ
ꢁ
ꢃ
ꢄ
VOUT = 0.8V 1+
ꢂ
ꢅ
ITH
where R1 and R2 are defined in Figure 2.
+
–
An internal 1.2μA current source charges up the C
SS
SENSE /SENSE PINS
capacitor. When the voltage on RUN/SS1 (RUN/SS2)
reaches 1.5V, the particular controller is permitted to start
operating. As the voltage on RUN/SS increases from 1.5V
to 3.0V, the internal current limit is increased from 25mV/
The common mode input range of the current comparator
sense pins is from 0V to (1.1)INTV . Continuous linear
CC
operation is guaranteed throughout this range allowing
output voltage setting from 0.8V to 7.7V, depending upon
R
to 75mV/R
. The output current limit ramps
SENSE
SENSE
the voltage applied to EXTV . A differential NPN input
CC
up slowly, taking an additional 1.25s/ꢀF to reach full cur-
rent. The output current thus ramps up slowly, reducing
the starting surge current required from the input power
supply. If RUN/SS has been pulled all the way to ground
there is a delay before starting of approximately:
stageisbiasedwithinternalresistorsfromaninternal2.4V
source, as shown in the Functional Diagram. This requires
that current either be sourced or sunk from the SENSE
pinsdependingontheoutputvoltage. Iftheoutputvoltage
is below 2.4V, current will flow out of both SENSE pins to
the main output. The output can be easily preloaded by
1.5V
1.2μA
tDELAY
=
CSS = 1.25s / μF C
SS
(
)
the V
resistive divider to compensate for the current
OUT
comparator’s negative input bias current. The maximum
current flowing out of each pair of SENSE pins is:
3V ꢀ1.5V
1.2μA
tIRAMP
=
CSS = 1.25s / μF C
SS
(
)
+
–
I
+ I
= (2.4V – V )/24k
SENSE OUT
SENSE
Since V
is servoed to the 0.8V reference voltage,
BypullingbothRUN/SSpinsbelow1V, theLTC3728isput
into low current shutdown (IQ = 20μA). The RUN/SS pins
can be driven directly from logic, as shown in Figure 7.
Diode D1 in Figure 7 reduces the start delay but allows
CSS to ramp up slowly providing the soft-start function.
Each RUN/SS pin has an internal 6V Zener clamp (see
the Functional Diagram).
OSENSE
we can choose R1 in Figure 2 to have a maximum value
to absorb this current.
ꢀ
ꢃ
0.8V
2.4V – V
R1(MAX) = 24k
ꢂ
ꢅ
ꢁ
OUT ꢄ
for V
< 2.4V
OUT
Regulating an output voltage of 1.8V, the maximum value
of R1 should be 32k. Note that for an output voltage above
2.4V, R1 has no maximum value necessary to absorb the
sensecurrents;however,R1isstillboundedbytheV
feedback current.
OSENSE
3728fg
21
LTC3728
APPLICATIONS INFORMATION
Fault Conditions: Overcurrent Latchoff
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. After the design is complete, a decision can be
made whether to enable the latchoff feature.
The RUN/SS pins also provide the ability to latch off the
controller(s)whenanovercurrentconditionisdetected.The
RUN/SS capacitor, C , is used initially to turn on and limit
SS
theinrushcurrent.Afterthecontrollerhasbeenstartedand
given adequate time to charge up the output capacitor and
provide full load current, the RUN/SS capacitor is used for
a short-circuit timer. If the regulator’s output voltage falls
The value of the soft-start capacitor C may need to be
SS
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capaci-
tance is given by:
to less than 70% of its nominal value after C reaches
SS
4.1V, C begins discharging on the assumption that the
–4
SS
C
SS
> (C
)(V ) (10 ) (R
)
SENSE
OUT
OUT
output is in an overcurrent condition. If the condition lasts
The minimum recommended soft-start capacitor of
= 0.1μF will be sufficient for most applications.
for a long enough period, as determined by the size of the
C
SS
C
and the specified discharge current, the controller will
SS
be shut down until the RUN/SS pin voltage is recycled.
If the overload occurs during start-up, the time can be
approximated by:
Fault Conditions: Current Limit and Current Foldback
The LTC3728 current comparator has a maximum sense
voltage of 75mV, resulting in a maximum MOSFET cur-
t
≈ [C (4.1 – 1.5 + 4.1 – 3.5)]/(1.2μA)
LO1
SS
6
rent of 75mV/R
. The maximum value of current
SENSE
= 2.7 • 10 (C )
SS
limit generally occurs with the largest V at the highest
IN
If the overload occurs after start-up, the voltage on C
will begin discharging from the Zener clamp voltage:
SS
ambient temperature—conditions that cause the highest
power dissipation in the top MOSFET.
6
t
≈ [C (6 – 3.5)]/(1.2μA) = 2.1 • 10 (C )
LO2
SS
SS
The LTC3728 includes current foldback to help further
limit load current when the output is shorted to ground.
The foldback circuit is active even when the overload
shutdown latch previously described is overridden. If the
output falls below 70% of its nominal output level, then
themaximumsensevoltageisprogressivelyloweredfrom
75mV to 25mV. Under short-circuit conditions with very
low duty cycles, the LTC3728 will begin cycle skipping in
order to limit the short-circuit current. In this situation,
the bottom MOSFET will be dissipating most of the power
but less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time tON(MIN)
of the LTC3728 (less than 200ns), the input voltage and
inductor value:
This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor to the RUN/SS pin, as shown
in Figure 7. This resistance shortens the soft-start period
andpreventsthedischargeoftheRUN/SScapacitorduring
an over current condition. Tying this pull-up resistor to
VIN (as in Figure 7) defeats overcurrent latchoff.
Why should you defeat overcurrent latchoff? During the
prototyping stage of a design there may be a problem
with noise pickup or poor layout, causing the protection
circuit to latch off. Defeating this feature will easily allow
V
IN
3.3V OR 5V
RUN/SS
R
*
SS
D1
ΔI
= t (V /L)
ON(MIN) IN
L(SC)
C
SS
The resulting short-circuit current is:
25mV
RSENSE
1
2
ISC
=
+ ꢀIL(SC)
*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF
3728 F07
Figure 7. RUN/SS Pin Interfacing
3728fg
22
LTC3728
APPLICATIONS INFORMATION
Fault Conditions: Overvoltage Protection (Crowbar)
the external and internal oscillators. This type of phase
detector will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes
huge currents to flow that blow the fuse to protect against
a shorted top MOSFET, if the short occurs while the con-
troller is operating.
range, Δf , is equal to the capture range, Δf
H
C:
Δf = Δf = 0.5 f (250kHz-550kHz)
H
C
O
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLFLTR pin.
A comparator monitors the output for overvoltage con-
ditions. The comparator (OV) detects overvoltage faults
greaterthan7.5%abovethenominaloutputvoltage.When
this condition is sensed, the top MOSFET is turned off
and the bottom MOSFET is turned on until the overvolt-
age condition is cleared. The output of this comparator
is only latched by the overvoltage condition itself and
will, therefore, allow a switching regulator system hav-
ing a poor PC layout to function while the design is being
debugged. The bottom MOSFET remains on continuously
If the external frequency (f
) is greater than the oscil-
PLLIN
lator frequency, f , current is sourced continuously,
OSC
pullingupthePLLFLTRpin.Whentheexternalfrequencyis
less than f , current is sunk continuously, pulling down
OSC
the PLLFLTR pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sourcesturnonforanamountoftimecorrespondingtothe
phase difference. Thus, the voltage on the PLLFLTR pin is
adjusted until the phase and frequency of the external and
internal oscillators are identical. At this stable operating
point, the phase comparator output is open and the filter
for as long as the OV condition persists. If V
returns
OUT
to a safe level, normal operation automatically resumes. A
shorted top MOSFET will result in a high current condition
which will open the system fuse. The switching regulator
will regulate properly with a leaky top MOSFET by altering
the duty cycle to accommodate the leakage.
capacitor C holds the voltage. The LTC3728 PLLIN pin
LP
must be driven from a low impedance source such as a
logic gate located close to the pin. When using multiple
LTC3728’s (or LTC3729’s, as shown in Figure 14) for a
phase-locked system, the PLLFLTR pin of the master
oscillator should be biased at a voltage that will guarantee
the slave oscillator(s) ability to lock onto the master’s
frequency. A DC voltage of 0.7V to 1.7V applied to the
master oscillator’s PLLFLTR pin is recommended in order
tomeetthisrequirement.Theresultantoperatingfrequency
can range from 300kHz to 470kHz.
Phase-Locked Loop and Frequency Synchronization
The LTC3728 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range
of the voltage controlled oscillator is 50% around the
center frequency, f . A voltage applied to the PLLFLTR
O
The loop filter components (C , R ) smooth out the
LP
LP
pin of 1.2V corresponds to a frequency of approximately
400kHz. The nominal operating frequency range of the
LTC3728 is 250kHz to 550kHz.
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components, C and R , determine how fast the loop
LP
LP
The phase detector used is an edge-sensitive digital
type which provides zero degrees phase shift between
acquires lock. Typically, R =10kΩ, and C is 0.01μF
LP
LP
to 0.1μF.
3728fg
23
LTC3728
APPLICATIONS INFORMATION
Minimum On-Time Considerations
from the auxiliary windings. With the loop in continuous
mode, the auxiliary outputs may nominally be loaded
without regard to the primary output load.
Minimum on-time, t , is the smallest time duration
ON(MIN)
that the LTC3728 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that:
The secondary output voltage, V , is normally set (as
SEC
shown in Figure 6a) by the turns ratio N of the trans-
former:
V
SEC
≅ (N + 1) V
OUT
VOUT
However, if the controller goes into Burst Mode operation
andhaltsswitchingduetoalightprimaryloadcurrent,then
tON(MIN)
<
V (f)
IN
V
will droop. An external resistive divider from V to
SEC
SEC
If the duty cycle falls below what can be accommodated
by the minimum on-time, the LTC3728 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
the FCB pin sets a minimum voltage V
:
SEC(MIN)
R6
R5
ꢁ
ꢂ
ꢄ
ꢅ
VSEC(MIN) ꢀ0.8V 1+
ꢃ
ꢆ
The typical tested minimum on-time of the LTC3728 is
100ns under an ideal condition without switching noise.
However, the minimum on-time can be affected by PCB
switching noise in the voltage and current loops. With
reasonably good PCB layout, minimum 30% inductor
current ripple and about 15mV sensing ripple voltage,
200ns minimum on-time is a conservative number to
start with.
where R5 and R6 are shown in Figure 2.
If V drops below this level, the FCB voltage forces
SEC
temporary continuous switching operation until V
is
SEC
again above its minimum.
In order to prevent erratic operation if no external connec-
tions are made to the FCB pin, the FCB pin has a 0.18ꢀA
internal current source pulling the pin high. Include this
current when choosing resistor values R5 and R6.
FCB Pin Operation
Table 1 summarizes the possible states available on the
FCB pin:
The FCB pin can be used to regulate a secondary winding
or as a logic-level input. Continuous operation is forced
on both controllers when the FCB pin drops below 0.8V.
During continuous mode, current flows continuously in
the transformer primary. The secondary winding(s) draw
current only when the bottom, synchronous switch is on.
Table 1
FCB Pin
Condition
0V to 0.75V
Forced Continuous Both Controllers
(Current Reversal Allowed—Burst
Inhibited)
When primary load currents are low and/or the V /V
IN OUT
0.85V < V < 4.0V
Minimum Peak Current Induces
Burst Mode Operation
No Current Reversal Allowed
FCB
ratio is low, the synchronous switch may not be on for a
sufficientamountoftimetotransferpowerfromtheoutput
capacitortothesecondaryload.Forcedcontinuousopera-
tion will support secondary windings providing there is
sufficient synchronous switch duty factor. Thus, the FCB
input pin removes the requirement that power must be
drawn from the inductor primary in order to extract power
Feedback Resistors
>4.8V
Regulating a Secondary Winding
Burst Mode Operation Disabled
Constant-Frequency Mode Enabled
No Current Reversal Allowed
No Minimum Peak Current
3728fg
24
LTC3728
APPLICATIONS INFORMATION
Voltage Positioning
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most
Voltage positioning can be used to minimize peak-to-peak
output voltage excursions under worst-case transient
loading conditions. The open-loop DC gain of the control
loop is reduced depending upon the maximum load step
specifications. Voltage positioning can easily be added to
of the losses in LTC3728 circuits: 1) LTC3728 V cur-
IN
rent (including loading on the 3.3V internal regulator),
2
2) INTV regulator current, 3) I R losses, 4) Topside
CC
MOSFET transition losses.
the LTC3728 by loading the I pin with a resistive divider
1. The V current has two components: the first is the
TH
IN
having a Thevenin equivalent voltage source equal to the
midpoint operating voltage range of the error amplifier, or
1.2V (see Figure 8).
DCsupplycurrentgivenintheElectricalCharacteristics
table, which excludes MOSFET driver and control cur-
rents; the second is the current drawn from the 3.3V
linear regulator output. V current typically results in
IN
The resistive load reduces the DC loop gain while main-
taining the linear control range of the error amplifier. The
maximum output voltage deviation can theoretically be
reduced to half, or alternatively, the amount of output
capacitance can be reduced for a particular application.
A complete explanation is included in Design Solutions
10 (see www.linear.com).
a small (<0.1%) loss.
2. INTV current is the sum of the MOSFET driver and
CC
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ
moves from INTV to ground. The resulting dQ/dt is
CC
a current out of INTV that is typically much larger
INTV
CC
CC
than the control circuit current. In continuous mode,
R
T2
I
= f(Q Q ), where Q and Q are the gate
GATECHG
T B T B
I
TH
LTC3728
charges of the topside and bottom side MOSFETs.
R
R
T1
C
C
C
Supplying INTV power through the EXTV switch
CC
CC
input from an output-derived source will scale the V
3728 F08
IN
current required for the driver and control circuits by
Figure 8. Active Voltage Positioning
Applied to the LTC3728
a factor of (Duty Cycle)/(Efficiency). For example, in a
20V to 5V application, 10mA of INTV current results
CC
in approximately 2.5mA of V current. This reduces
IN
the mid-current loss from 10% or more (if the driver
Efficiency Considerations
was powered directly from V ) to only a few percent.
IN
2
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
3. I R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resis-
tor, and input and output capacitor ESR. In continuous
mode, the average output current flows through L and
R
, but is “chopped” between the topside MOSFET
SENSE
and the synchronous MOSFET. If the two MOSFETs
have approximately the same R
tance of one MOSFET can simply be summed with the
resistances of L, R
For example, if each R
, then the resis-
DS(ON)
%Efficiency = 100% – (L1 + L2 + L3 + ...)
2
where L1, L2, etc. are the individual losses as a percent-
age of input power.
and ESR to obtain I R losses.
SENSE
= 30mΩ, R = 50mΩ,
DS(ON)
L
3728fg
25
LTC3728
APPLICATIONS INFORMATION
R
SENSE
= 10mΩ and R
= 40mΩ (sum of both input
this recovery time, V
can be monitored for excessive
OUT
ESR
andoutputcapacitancelosses),thenthetotalresistance
is 130mΩ. This results in losses ranging from 3% to
13% as the output current increases from 1A to 5A for
a 5V output, or a 4% to 20% loss for a 3.3V output.
overshoot or ringing, which would indicate a stability
problem. OPTI-LOOP compensation allows the transient
response to be optimized over a wide range of output
capacitance and ESR values. The availability of the I pin
TH
Efficiency varies as the inverse square of V
for the
not only allows optimization of control loop behavior but
also provides a DC-coupled and AC-filtered closed loop
response test point. The DC step, rise time and settling
at this test point truly reflects the closed loop response.
Assuming a predominantly second order system, phase
margin and/or damping factor can be estimated using the
percentage of overshoot seen at this pin. The bandwidth
can also be estimated by examining the rise time at the
OUT
sameexternalcomponentsandoutputpowerlevel. The
combined effects of increasingly lower output voltages
andhighercurrentsrequiredbyhighperformancedigital
systemsisnotdoublingbutquadruplingtheimportance
of loss terms in the switching regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
pin. The I external components shown in the Figure 1
TH
circuit will provide an adequate starting point for most
applications.
2
Transition Loss = (1.7) V
I
C
f
IN O(MAX) RSS
The I series R -C filter sets the dominant pole-zero
TH
C
C
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these system level losses during the
design phase. The internal battery and fuse resistance
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1μs to 10μs will
losses can be minimized by ensuring C has adequate
IN
chargestorageandverylowESRattheswitchingfrequency.
A 25W supply will typically require a minimum of 20μF
to 40μF of capacitance having a maximum of 20mΩ to
50mΩofESR. TheLTC37282-phasearchitecturetypically
halvesthisinputcapacitancerequirementovercompeting
solutions. Other losses, including Schottky conduction
lossesduringdeadtimeandinductorcorelosses,generally
account for less than 2% total additional loss.
produce output voltage and I pin waveforms that will
TH
give a sense of the overall loop stability without break-
ing the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
is why it is better to look at the I pin signal, which is
TH
in the feedback loop and is the filtered and compensated
load current. When a load step occurs, V
shifts by
control loop response. The gain of the loop will be in-
OUT
an amount equal to ΔI
(ESR), where ESR is the ef-
creased by increasing R and the bandwidth of the loop
LOAD
C
fective series resistance of C . ΔI
also begins to
will be increased by decreasing C . If R is increased by
OUT
LOAD
C
C
charge or discharge C , generating the feedback error
the same factor that C is decreased, the zero frequency
OUT
C
signal that forces the regulator to adapt to the current
will be kept the same, thereby keeping the phase shift the
change and return V
to its steady-state value. During
same in the most critical frequency range of the feedback
OUT
3728fg
26
LTC3728
APPLICATIONS INFORMATION
loop. The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
ging into the supply from hell. The main power line in an
automobile is the source of a number of nasty potential
transients, including load-dump, reverse-battery and
double-battery.
A second, more severe transient is caused by switching
in loads with large (>1μF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
Load-dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alterna-
tor can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse-battery is
just what it says, while double-battery is a consequence of
tow truck operators finding that a 24V jump start cranks
cold engines faster than 12V.
with C , causing a rapid drop in V . No regulator can
OUT
OUT
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
LOAD
to C
is greater than 1:50, the switch rise time
OUT
should be controlled so that the load rise time is limited to
approximately 25 • C . Thus, a 10μF capacitor would
The network shown in Figure 9 is the most straight for-
ward approach to protect a DC/DC converter from the
ravages of an automotive power line. The series diode
prevents current from flowing during reverse-battery,
while the transient suppressor clamps the input voltage
during load-dump. Note that the transient suppressor
should not conduct during double-battery operation, but
must still clamp the input voltage below breakdown of the
converter. Although the LTC3728 has a maximum input
voltage of 36V, most applications will be limited to 30V
by the MOSFET BVDSS.
LOAD
require a 250μs rise time, limiting the charging current
to about 200mA.
Automotive Considerations: Plugging into the
Cigarette Lighter
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during opera-
tion. But before you connect, be advised: you are plug-
50A I RATING
PK
V
IN
12V
LTC3728
TRANSIENT VOLTAGE
SUPPRESSOR
GENERAL INSTRUMENT
1.5KA24A
3728 F09
Figure 9. Automotive Application Protection
3728fg
27
LTC3728
APPLICATIONS INFORMATION
Design Example
Choosing 1% resistors; R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.
As a design example for one channel, assume V = 12V
IN
(nominal), V = 22V(max), V
= 1.8V, I
= 5A, and
The power dissipation on the topside MOSFET can be
easily estimated. Choosing a Siliconix Si4412DY results
IN
OUT
MAX
f = 300kHz.
in R
= 0.042Ω, C
= 100pF. At maximum input
DS(ON)
RSS
Theinductancevalueischosenfirstbasedona30%ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the PLLFLTR
voltage with T(estimated) = 50°C:
1.8V
22V
2
PMAIN
=
5
1+(0.005)(50°C – 25°C)
( )
[
]
pin to a resistive divider using the INTV pin generating
CC
1V for 300kHz operation. The minimum inductance for
2
0.042ꢀ +1.7 22V 5A 100pF 300kHz
(
)
(
) ( )(
)(
30% ripple current is:
= 220mW
ꢁ
OUT ꢄ
V
VOUT
(f)(L)
ꢀIL =
1–
ꢃ
ꢆ
A short-circuit to ground will result in a folded back cur-
rent of:
V
ꢂ
ꢅ
IN
A 4.7μH inductor will produce 23% ripple current and a
3.3μH will result in 33%. The peak inductor current will
be the maximum DC value plus one-half the ripple cur-
rent, or 5.84A, for the 3.3μH value. Increasing the ripple
current will also help ensure that the minimum on-time
of 100ns is not violated. The minimum on-time occurs at
ꢁ
ꢃ
ꢄ
25mV 1 200ns(22V)
ISC
=
+
= 3.2A
ꢆ
0.01ꢀ 2ꢂ 3.3μH
ꢅ
with a typical value of R
0.1. TheresultingpowerdissipatedinthebottomMOSFET
and δ = (0.005/°C)(20) =
DS(ON)
is:
maximum V :
IN
22V –1.8V
22V
2
VOUT
IN(MAX)f 22V(300kHz)
1.8V
PSYNC
=
3.2A 1.1 0.042ꢀ
) ( )(
(
)
tON(MIN)
=
=
= 273ns
V
= 434mW
which is less than under full-load conditions.
C is chosen for an RMS current rating of at least 3A at
The R
resistor value can be calculated by using the
maximum current sense voltage specification with some
accommodation for tolerances:
SENSE
IN
temperature assuming only this channel is on. C
is
OUT
60mV
5.84A
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
R
SENSE ꢀ
ꢁ0.01ꢂ
Since the output voltage is below 2.4V the output resis-
tive divider will need to be sized to not only set the output
voltage but also to absorb the SENSE pins specified input
current.
V
= R (ΔI ) = 0.02Ω(1.67A) = 33mV
ESR L P–P
ORIPPLE
ꢀ
ꢃ
0.8V
2.4V – V
R1(MAX) = 24k
= 24K
ꢂ
ꢅ
ꢁ
OUT ꢄ
0.8V
2.4V –1.8V
ꢀ
ꢃ
ꢅ
= 32k
ꢂ
ꢁ
ꢄ
3728fg
28
LTC3728
APPLICATIONS INFORMATION
PC Board Layout Checklist
2. Are the signal and power grounds kept separate? The
combined LTC3728 signal ground pin and the ground
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3728. These items are also illustrated graphically
in the layout diagram of Figure 10. Figure 11 illustrates
the current waveforms present in the various branches
of the 2-phase synchronous regulators operating in the
continuous mode. Check the following in your layout:
return of C
must return to the combined C
INTVCC
OUT
(–) terminals. The path formed by the top N-channel
MOSFET, Schottky diode and the C capacitor should
IN
have short leads and PC trace lengths. The output
capacitor (–) terminals should be connected as close
as possible to the (–) terminals of the input capacitor
by placing the capacitors next to each other and away
from the Schottky loop described above.
1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connec-
3. DotheLTC3728V
pinsresistivedividersconnect
OSENSE
tion at C ? Do not attempt to split the input decoupling
IN
to the (+) terminals of C ? The resistive divider must
OUT
for the two channels as it can cause a large resonant
be connected between the (+) terminal of C
and
OUT
loop.
R
PU
V
PULL-UP
(<7V)
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PGOOD
RUN/SS1
PGOOD
TG1
L1
R
SENSE
D1
+
V
SENSE1
OUT1
3
–
SENSE1
SW1
R2
M1
M2
C
B1
R1
4
V
BOOST1
OSENSE1
5
PLLFLTR
PLLIN
FCB
V
IN
f
IN
6
C
C
OUT1
BG1
R
IN
7
C
IN
INTV
EXTV
CC
CC
CC
C
VIN
GND
LTC3728
8
I
INTV
TH1
V
IN
C
INTVCC
9
SGND
PGND
BG2
OUT2
D2
10
11
12
13
14
3.3V
3.3V
OUT
I
BOOST2
SW2
TH2
C
B2
M3
M4
L2
V
OSENSE2
–
R
R3
R4
SENSE
V
OUT2
SENSE2
TG2
+
SENSE2
RUN/SS2
3728 F10
Figure 10. LTC3728 Recommended Printed Circuit Layout Diagram
3728fg
29
LTC3728
APPLICATIONS INFORMATION
SW1
D1
L1
R
SENSE1
V
OUT1
+
C
R
L1
OUT1
V
IN
R
IN
+
C
IN
SW2
L2
R
SENSE2
V
OUT2
+
D2
C
R
L2
OUT2
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH.
3728 F11
Figure 11. Branch Current Waveforms
signal ground. The R2 and R4 connections should not
be along the high current input feeds from the input
capacitor(s).
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1,TG2),andboostnodes(BOOST1,BOOST2)away
from sensitive small-signal nodes, especially from
the opposites channel’s voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and therefore should be kept on
the output side of the LTC3728 and occupy minimum
PC trace area.
–
+
4. Are the SENSE and SENSE leads routed together
with minimum PC trace spacing? The filter capacitor
+
–
between SENSE and SENSE should be as close as
possible to the IC. Ensure accurate current sensing
with Kelvin connections at the SENSE resistor.
7. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
5. Is the INTV decoupling capacitor connected close
CC
to the IC, between the INTV and the power ground
CC
pins?ThiscapacitorcarriestheMOSFETdriverscurrent
capacitors with tie-ins for the bottom of the INTV
CC
peaks. An additional 1μF ceramic capacitor placed im-
decouplingcapacitor,thebottomofthevoltagefeedback
resistive divider and the SGND pin of the IC.
3728fg
mediately next to the INTV and PGND pins can help
CC
improve noise performance substantially.
30
LTC3728
APPLICATIONS INFORMATION
PC Board Layout Debugging
Reduce V from its nominal level to verify operation
IN
of the regulator in dropout. Check the operation of the
Start with one controller on at a time. It is helpful to use
a DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output volt-
age. Check for proper performance over the operating
voltage and current range expected in the application. The
frequencyofoperationshouldbemaintainedovertheinput
voltage range down to dropout and until the output load
dropsbelowthelowcurrentoperationthreshold—typically
10% to 20% of the maximum designed current level in
Burst Mode operation.
undervoltage lockout circuit by further lowering V while
IN
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
Thedutycyclepercentageshouldbemaintainedfromcycle
tocycleinawelldesigned, lownoisePCBimplementation.
Variation in the duty cycle at a subharmonic rate can sug-
gest noise pickup at the current or voltage sensing inputs
or inadequate loop compensation. Overcompensation of
the loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required. Only after each
controller is checked for their individual performance
should both controllers be turned on at the same time.
A particularly difficult region of operation is when one
controller channel is nearing its current comparator trip
pointwhentheotherchannelisturningonitstopMOSFET.
This occurs around 50% duty cycle on either channel due
to the phasing of the internal clocks and may cause minor
duty cycle jitter.
for inductive coupling between C , Schottky and the top
IN
MOSFET components to the sensitive current and voltage
sensing traces. In addition, investigate common ground
path voltage pickup between these components and the
SGND pin of the IC.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still
be maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
Short-circuit testing can be performed to verify proper
overcurrentlatchoff,or5μAcanbeprovidedtotheRUN/SS
pin(s) by resistors from V to prevent the short-circuit
IN
latchoff from occurring.
3728fg
31
LTC3728
TYPICAL APPLICATIONS
59k
1M
100k
MBRS1100T3
V
+
PULL-UP
33MF
25V
(<7V)
T1, 1:1.8
10MH
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PGOOD
TG1
PGOOD
RUN/SS1
0.0157
V
0.1MF
OUT1
2
+
5V
SENSE1
3A; 4A PEAK
180pF
1000pF
3
4
8
–
SW1
SENSE1
105k, 1%
5
20k
1%
M1
M2
0.1MF
D1
MBRM
140T3
LT1121
ON/OFF
BOOST1
V
OSENSE1
3
2
1
220k
V
5
OUT3
V
IN
PLLFLTR
PLLIN
FCB
12V
120mA
6
150MF, 6.3V
PANASONIC SP
BG1
+
33pF
1MF
25V
107
22MF
50V
100k
7
CMDSH-3TR
EXTV
CC
0.1MF
GND
LTC3728
8
INTV
CC
I
TH1
1MF
10V
15k
4.7MF
1000pF
1000pF
9
180MF, 4V
PGND
BG2
SGND
PANASONIC SP
V
33pF
IN
CMDSH-3TR
7V TO
28V
10
11
12
13
14
3.3V
3.3V
OUT
D2
MBRM
140T3
BOOST2
SW2
I
TH2
15k
0.1MF
M3
M4
V
OSENSE2
–
20k
1%
V
OUT2
3.3V
5A; 6A PEAK
TG2
SENSE2
63.4k
1%
0.017
1000pF
L1
6.3MH
+
RUN/SS2
SENSE2
180pF
0.1MF
3728 F12
V
V
: 7V TO 28V
IN
: 5V, 3A/3.3V, 5A/12V, 120mA
OUT
SWITCHING FREQUENCY = 250kHz
MI, M2, M3, M4: NDS8410A
L1: SUMIDA CEP123-6R3MC
T1: 10MH 1:1.8 — DALE LPE6562-A262 GAPPED E-CORE OR BH ELECTRONICS #501-0657 GAPPED TOROID
Figure 12. LTC3728 High Efficiency Low Noise 5V/3A, 3.3V/5A, 12V/120mA Regulator
3728fg
32
LTC3728
TYPICAL APPLICATIONS
V
PULL-UP
(<7V)
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
L1
PGOOD
RUN/SS1
PGOOD
TG1
8MH
0.0157
V
0.1MF
OUT1
2
+
SENSE1
5V
3A; 4A PEAK
27pF
1000pF
105k
1%
3
4
–
SENSE1
SW1
20k
1%
0.1MF
V
BOOST1
OSENSE1
5
M1
PLLFLTR
PLLIN
FCB
V
0.01MF
IN
10k
1000pF
47MF
6.3V
6
f
SYNC
BG1
33pF
107
22MF
50V
7
CMDSH-3TR
EXTV
INTV
CC
CC
0.1MF
GND
LTC3728
8
I
TH1
1MF
10V
15k
4.7MF
220pF
9
SGND
PGND
BG2
56MF, 4V
V
33pF
IN
CMDSH-3TR
5.2V TO
28V
10
11
12
13
14
3.3V
3.3V
OUT
I
BOOST2
SW2
TH2
15k
0.1MF
220pF
V
OSENSE2
–
20k
1%
M2
V
OUT2
3.3V
SENSE2
SENSE2
TG2
0.0157
63.4k
1%
3A; 4A PEAK
1000pF
L2
8MH
+
27pF
RUN/SS2
0.1MF
: 5.2V TO 28V
3728 F13
V
V
SWITCHING FREQUENCY = 250kHz TO 550kHz
MI, M2: FDS6982S
L1, L2: 8MH SUMIDA CEP1238R0MC
OUTPUT CAPACITORS: PANASONIC SP SERIES
IN
: 5V, 4A/3.3V, 4A
OUT
Figure 13. LTC3728 5V/4A, 3.3V/4A Regulator with External Frequency Synchronization
3728fg
33
LTC3728
PACKAGE DESCRIPTION
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
9.90 – 10.50*
(.390 – .413)
28 27 26 25 24 23 22 21 20 19 18
16 15
17
1.25 ±0.12
7.8 – 8.2
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 ±0.03
0.65 BSC
5
7
8
1
2
3
4
6
9 10 11 12 13 14
RECOMMENDED SOLDER PAD LAYOUT
2.0
(.079)
MAX
5.00 – 5.60**
(.197 – .221)
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.25
0.55 – 0.95
(.0035 – .010)
(.022 – .037)
0.05
0.22 – 0.38
(.009 – .015)
TYP
(.002)
NOTE:
MIN
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
G28 SSOP 0204
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
3728fg
34
LTC3728
PACKAGE DESCRIPTION
UH32 Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.45 ± 0.05
3.50 REF
(4 SIDES)
3.45 ± 0.05
PACKAGE OUTLINE
0.25 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
R = 0.05
TYP
0.00 – 0.05
R = 0.115
TYP
0.75 ± 0.05
5.00 ± 0.10
(4 SIDES)
31 32
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.45 ± 0.10
3.50 REF
(4-SIDES)
3.45 ± 0.10
(UH32) QFN 0406 REV D
0.200 REF
0.25 ± 0.05
0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3728fg
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC3728
TYPICAL APPLICATION
I
IN
12V
IN
C
IN
I
1
I
IN
*
0°
BUCK: 2.5V/15A
BUCK: 2.5V/15A
OPEN
PHASMD TG1
180°
I
1
2
3
4
2.5V /30A
O
TG2
U1
LTC3729
I
I
90°
2
3
I
CLKOUT
I
I
1.5V /15A
O
90°
BUCK: 1.5V/15A
BUCK: 1.8V/15A
TG1
270°
1.8V /15A
O
TG2
LTC3728
U2
*INPUT RIPPLE CURRENT CANCELLATION
INCREASES THE RIPPLE FREQUENCY AND
REDUCES THE RMS INPUT RIPPLE CURRENT
THUS, SAVING INPUT CAPACITORS
I
90°
4
PLLIN
3728 F14
Figure 14. Multioutput PolyPhase Application
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
High Efficiency 5V to 3.3V Conversion at Up to 15A
LTC1350
High Power Step-Down Synchronous DC/DC
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LTC1628/LTC1628-PG/ 2-Phase, Dual Output Synchronous Step-Down
Reduces C and C , Power Good Output Signal, Synchronizable,
IN
OUT
OUT
LTC1628-SYNC
DC/DC Controller
3.5V ≤ V ≤ 36V, I
Up to 20A, 0.8V ≤ V
≤ 5V
IN
OUT
LTC1629/
LTC1629-PG
20A to 200A PolyPhase® Synchronous Controllers Expandable from 2-Phase to 12-Phase, Uses All Surface Mount
Components, No Heat Sink, V Up to 36V
IN
LTC1702
550kHz, No Sense Resistor
No R
™
2-Phase Dual Synchronous
SENSE
Step-Down Controller
LTC1703
No R
2-Phase Dual Synchronous Step-Down Mobile Pentium III Processors, 550kHz, V ≤ 7V
SENSE IN
Controller with 5-Bit Mobile VID Control
LTC1708-PG
LT1709/LT1709-8
LTC1735
2-Phase, Dual Synchronous Controller with
Mobile VID
3.5V ≤ V ≤ 36V, VID Sets V
, PGOOD
IN
OUT1
High Efficiency, 2-Phase Synchronous Step-Down 1.3V ≤ V
Switching Regulators with 5-Bit VID
≤ 3.5V, Current Mode Ensures Accurate Current Sharing,
OUT
IN
3.5V ≤ V ≤ 36V
High Efficiency Synchronous Step-Down
Switching Regulator
Output Fault Protection, 16-Pin SSOP
LTC1736
High Efficiency Synchronous Controller with
5-Bit Mobile VID Control
Output Fault Protection, 24-Pin SSOP, 3.5V ≤ V ≤ 36V
IN
LTC1778
No R
Current Mode Synchronous
Up to 97% Efficiency, 4V ≤ V ≤ 36V, 0.8V ≤ V
≤ (0.9)(V ),
OUT IN
SENSE
IN
Step-Down Controller
I
Up to 20A
OUT
LTC1929/LTC1929-PG 2-Phase Synchronous Controllers
Up to 42A, Uses All Surface Mount Components, No Heat Sinks,
3.5V ≤ V ≤ 36V
IN
LTC3711
LTC3729
No R
Current Mode Synchronous Step-Down Up to 97% Efficiency, Ideal for Pentium III Processors, 0.925V ≤ V
≤ 2V,
SENSE
OUT
Controller with Digital 5-Bit Interface
4V ≤ V ≤ 36V, I
Up to 20A
OUT
IN
20A to 200A, 550kHz PolyPhase Synchronous
Controller
Expandable from 2-Phase to 12-Phase, Uses All Surface Mount
Components, V Up to 36V
IN
PolyPhase is a registered trademark of Linear Technology Corporation. No R
is a trademark of Linear Technology Corporation.
SENSE
3728fg
LT 0909 REV G • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
●
●
© LINEAR TECHNOLOGY CORPORATION 2006
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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