LTC3728EUH_技术文档

LTC3728

Dual, 550kHz, 2-Phase

Synchronous Step-Down Switching Regulator

U

FEATURES

DESCRIPTIO

The LTC^®3728 is a dual high performance step-down

switching regulator controller that drives all N-channel

synchronous power MOSFET stages. A constant fre-

quency current mode architecture allows phase-lockable

frequency of up to 550kHz. Power loss and noise due to

theESRoftheinputcapacitorsareminimizedbyoperating

the two controller output stages out of phase.

■

Dual, 180° Phased Controllers Reduce Required

Input Capacitance and Power Supply Induced Noise

OPTI-LOOP^®Compensation Minimizes C_OUT

±1% Output Voltage Accuracy

Power Good Output Voltage Indicator

Phase-Lockable Fixed Frequency 250kHz to 550kHz

Dual N-Channel MOSFET Synchronous Drive

Wide V_INRange: 3.5V to 36V Operation

Very Low Dropout Operation: 99% Duty Cycle

Adjustable Soft-Start Current Ramping

Foldback Output Current Limiting

■

OPTI-LOOP compensation allows the transient response

tobeoptimizedoverawiderangeofoutputcapacitanceand

ESRvalues. Theprecision0.8Vreferenceandpowergood

output indicator are compatible with future microproces-

sor generations, and a wide 3.5V to 30V (36V maximum)

input supply range encompasses all battery chemistries.

Latched Short-Circuit Shutdown with Defeat Option

Output Overvoltage Protection

Remote Output Voltage Sense

A RUN/SS pin for each controller provides both soft-start

and optional timed, short-circuit shutdown. Current

foldback limits MOSFET dissipation during short-circuit

conditions when overcurrent latchoff is disabled. Output

overvoltage protection circuitry latches on the bottom

MOSFET until V_OUTreturns to normal. The FCB mode pin

can select among Burst Mode, constant frequency mode

and continuous inductor current mode or regulate a

secondary winding. The LTC3728 includes a power good

output pin that indicates when both outputs are within

7.5% of their designed set point.

Low Shutdown I_Q: 20µA

5V and 3.3V Regulators

3 Selectable Operating Modes: Constant Frequency,

Burst Mode^®Operation and PWM

■

Available in 32-Pin 5mm × 5mm QFN and

28-Pin SSOP Packages

U

APPLICATIO S

■

Notebook and Palmtop Computers

■

Telecom Systems

■

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 5481178, 5929620, 6177787, 6144194, 6100678,

5408150, 6580258, 6304066, 5705919.

Portable Instruments

■

Battery-Operated Digital Devices

■

DC Power Distribution Systems

U

V

IN

5.2V TO 28V

+

C

IN

TYPICAL APPLICATIO

4.7µF

22µF

1µF

D3

D4

50V

V

PGOOD INTV

IN

CC

M2

M1

TG1

TG2

L1

3.2µH

L2

3.2µH

BOOST1

SW1

BOOST2

SW2

C

, 0.1µF

B1

C

, 0.1µF

B2

LTC3728

BG1

BG2

f

IN

500kHz

PLLIN

PGND

+

SENSE1

SENSE2

R

SENSE2

SENSE1

1000pF

0.01Ω

–

SENSE1

V

SENSE2

V

3.3V

5A

OSENSE1

TH1

OSENSE2

V

OUT2

OUT1

5V

5A

R2

R4

63.4k

1%

I

TH2

105k

1%

C

C2

C1

220pF

C

47µF

6V

C

56µF

6V

RUN/SS1

SGND

RUN/SS2

OUT1

OUT

220pF

R

C2

+

R1

20k

1%

R3

20k

1%

R

C1

C

SS1

0.1µF

SS2

0.1µF

15k

SP

M1, M2: FDS6982S

3728 F01

Figure 1. High Efficiency Dual 5V/3.3V Step-Down Converter

3728fb

1

LTC3728

W W U W

ABSOLUTE AXI U RATI GS

(Note 1)

PLLIN, PLLFLTR, FCB, Voltage ............ INTV_CCto –0.3V

_TH1,I_TH2, V_OSENSE1, V_OSENSE2Voltages ...2.7V to –0.3V

Input Supply Voltage (V_IN).........................36V to –0.3V

Top Side Driver Voltages

I

Peak Output Current <10µs (TG1, TG2, BG1, BG2) ... 3A

INTV_CCPeak Output Current ................................ 50mA

Operating Temperature Range (Note 7) ... –40°C to 85°C

Junction Temperature (Note 2)............................. 125°C

Storage Temperature Range ................. –65°C to 125°C

Lead Temperature (Soldering, 10 sec)

(BOOST1, BOOST2) ...................................42V to –0.3V

Switch Voltage (SW1, SW2) .........................36V to –5V

INTV_CC,EXTV_CC, RUN/SS1, RUN/SS2, (BOOST1-SW1),

(BOOST2-SW2), PGOOD .............................7V to –0.3V

SENSE1⁺, SENSE2⁺, SENSE1^–,

SENSE2^–Voltages........................ (1.1)INTV_CCto –0.3V

(G Package Only) .................................................. 300°C

U W

U

PACKAGE/ORDER I FOR ATIO

TOP VIEW

ORDER PART

1

2

PGOOD

TG1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RUN/SS1

NUMBER

+

SENSE1

LTC3728EG

LTC3728EUH

–

32 31 30 29 28 27 26 25

3

SW1

SENSE1

V

1

2

3

4

5

6

7

8

24 BOOST1

OSENSE1

4

BOOST1

V

OSENSE1

PLLFLTR

PLLIN

FCB

23

22

21

V

IN

5

V

IN

PLLFLTR

PLLIN

FCB

BG1

6

BG1

EXTV

CC

7

EXTV

CC

33

I

20 INTV

TH1

CC

8

INTV

CC

I

TH1

SGND

3.3V

PGND

19

9

PGND

BG2

SGND

18 BG2

UH PART

MARKING

OUT

10

11

12

13

14

3.3V

OUT

I

17 BOOST2

TH2

BOOST2

SW2

I

TH2

9

10 11 12 13 14 15 16

V

OSENSE2

–

3728

TG2

SENSE2

+

RUN/SS2

UH PACKAGE

32-LEAD (5mm × 5mm) PLASTIC QFN

_JMAX= 125°C, θ_JA= 34°C/W

EXPOSED PAD IS SGND (MUST BE SOLDERED TO PCB)

G PACKAGE

28-LEAD PLASTIC SSOP

T

T_JMAX= 125°C, θ_JA= 95°C/W

Order Options Tape and Reel: Add #TR

Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS

The

●

denotes the specifications which apply over the full operating

= 5V unless otherwise noted.

temperature range, otherwise specifications are at T = 25°C. V = 15V, V

A

IN

RUN/SS1, 2

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loops

V

Regulated Feedback Voltage

Feedback Current

(Note 3); I

(Note 3)

Voltage = 1.2V

TH1, 2

●

0.792

0.800

–5

0.808

–50

V

nA

OSENSE1, 2

I

VOSENSE1, 2

V

Reference Voltage Line Regulation

Output Voltage Load Regulation

V

= 3.6V to 30V (Note 3)

IN

0.002

0.02

%/V

REFLNREG

LOADREG

(Note 3)

Measured in Servo Loop; ∆I Voltage = 1.2V to 0.7V

Measured in Servo Loop; ∆I Voltage = 1.2V to 2.0V

●

0.1

–0.1

0.5

–0.5

%

TH

3728fb

2

LTC3728

ELECTRICAL CHARACTERISTICS

The

●

denotes the specifications which apply over the full operating

= 5V unless otherwise noted.

temperature range, otherwise specifications are at T = 25°C. V = 15V, V

A

IN

RUN/SS1, 2

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

g

Transconductance Amplifier g

I

= 1.2V; Sink/Source 5uA; (Note 3)

= 1.2V; (Note 3)

1.3

3

mmho

m1, 2

m

TH1, 2

g

Transconductance Amplifier GBW

MHzI

Q

mGBW1, 2

Input DC Supply Current

Normal Mode

(Note 4)

IN

RUN/SS1, 2

V

= 15V; EXTV Tied to V ; V = 5V

450

20

µA

CC

OUT1 OUT1

Shutdown

= 0V

35

V

Forced Continuous Threshold

Forced Continuous Pin Current

●

0.76

0.800

–0.18

4.3

0.84

–0.1

4.8

V

µA

V

FCB

I

V

= 0.85V

–0.50

FCB

V

Burst Inhibit (Constant Frequency)

Threshold

Measured at FCB pin

BINHIBIT

UVLO

Undervoltage Lockout

V

Ramping Down

●

3.5

0.86

–60

99.4

1.2

1.5

3.8

2

4

V

IN

V

Feedback Overvoltage Lockout

Sense Pins Total Source Current

Maximum Duty Factor

Measured at V

0.84

–85

98

0.88

OVL

OSENSE1, 2

I

(Each Channel); V

In Dropout

–

– = V + + = 0V

SENSE1 , 2

µA

%

µA

V

SENSE

SENSE1 , 2

DF

MAX

I

Soft-Start Charge Current

V

= 1.9V

RUN/SS1, 2

0.5

RUN/SS1, 2

V

ON RUN/SS Pin ON Threshold

LT RUN/SS Pin Latchoff Arming Threshold

RUN/SS Discharge Current

V Rising

RUN/SS1, RUN/SS2

1.0

1.9

4.5

4

RUN/SS1, 2

SCL1, 2

V

Rising from 3V

V

RUN/SS1, RUN/SS2

I

Soft Short Condition V

V

= 0.5V;

0.5

µA

OSENSE1, 2

= 4.5V

RUN/SS1, 2

I

Shutdown Latch Disable Current

Maximum Current Sense Threshold

V

= 0.5V

1.6

5

µA

mV

SDLHO

OSENSE1, 2

V

= 0.7V,V

–

SENSE1 , 2

–

= 5V

65

62

75

85

88

SENSE(MAX)

OSENSE1, 2

–

●

TG Transition Time:

Rise Time

Fall Time

(Note 5)

TG1, 2 t

C

= 3300pF

50

90

ns

r

f

LOAD

= 3300pF

BG Transition Time:

Rise Time

Fall Time

(Note 5)

LOAD

BG1, 2 t

C

= 3300pF

40

90

80

ns

r

f

TG/BG t

Top Gate Off to Bottom Gate On Delay

Synchronous Switch-On Delay Time

1D

C

= 3300pF Each Driver

90

ns

LOAD

BG/TG t

Bottom Gate Off to Top Gate On Delay

Top Switch-On Delay Time

2D

90

ns

t

Minimum On-Time

Tested with a Square Wave (Note 6)

100

ON(MIN)

INTV Linear Regulator

CC

V

Internal V Voltage

6V < V < 30V, V = 4V

4.8

4.5

5.0

0.2

80

5.2

1.0

V

%

INTVCC

CC

IN

EXTVCC

INT

INTV Load Regulation

I

= 0 to 20mA, V

= 4V

LDO

CC

EXTVCC

EXT

EXTV Voltage Drop

= 20mA, V

= 5V

160

mV

V

CC

EXTVCC

EXTV Switchover Voltage

= 20mA, EXTV Ramping Positive

●

4.7

0.2

EXTVCC

LDOHYS

CC

EXTV Hysteresis

V

CC

Oscillator and Phase-Locked Loop

f

Nominal Frequency

Lowest Frequency

Highest Frequency

PLLIN Input Resistance

V

= 1.2V

= 0V

360

230

480

400

260

550

50

440

290

590

kHz

kΩ

NOM

LOW

HIGH

PLLFLTR

≥ 2.4V

R

PLLIN

I

Phase Detector Output Current

Sinking Capability

Sourcing Capability

PLLFLTR

f

< f

OSC

> f

OSC

–15

15

µA

PLLIN

3728fb

3

LTC3728

ELECTRICAL CHARACTERISTICS

The

●

denotes the specifications which apply over the full operating

= 5V unless otherwise noted.

temperature range, otherwise specifications are at T = 25°C. V = 15V, V

A

IN

RUN/SS1, 2

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

3.3V Linear Regulator

V

3.3V Regulator Output Voltage

3.3V Regulator Load Regulation

3.3V Regulator Line Regulation

No Load

●

3.25

3.35

0.5

3.45

2

V

%

3.3OUT

3.3IL

I

= 0 to 10mA

3.3

6V < V < 30V

0.05

0.2

3.3VL

IN

PGOOD Output

V

PGOOD Voltage Low

I

= 2mA

= 5V

0.1

0.3

V

PGL

PGOOD

I

PGOOD Leakage Current

PGOOD Trip Level, Either Controller

V

±1

µA

PGOOD

V

with Respect to Set Output Voltage

Ramping Negative

Ramping Positive

PG

OSENSE

V

–6

6

–7.5

7.5

–9.5

9.5

%

OSENSE

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliabilty and lifetime.

delivered at the switching frequency. See Applications Information.

Note 5: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.

Note 6: The minimum on-time condition is specified for an inductor

Note 2: T is calculated from the ambient temperature T and power

J

A

peak-to-peak ripple current ≥40% of I

(see minimum on-time

considerations in the Applications Information section).

MAX

dissipation P according to the following formulas:

D

LTC3728: T = T + (P • 95 °C/W)

Note 3: The LTC3728 is tested in a feedback loop that servos V

specified voltage and measures the resultant V

Note 4: Dynamic supply current is higher due to the gate charge being

J

A

D

Note 7: The LTC3728E is guaranteed to meet performance specifications

from 0°C to 70°C. Specifications over the –40°C to 85°C operating

temperature range are assured by design, characterization and correlation

with statistical process controls.

to a

ITH1, 2

OSENSE1, 2.

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Efficiency vs Output Current

and Mode (Figure 13)

Efficiency vs Output Current

(Figure 13)

Efficiency vs Input Voltage

(Figure 13)

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

100

90

80

70

60

50

Burst Mode

OPERATION

V

= 7V

IN

V

= 10V

IN

= 15V

FORCED

CONTINUOUS

MODE (PWM)

V

IN

V

= 20V

IN

CONSTANT

FREQUENCY

(BURST DISABLE)

V

= 5V

= 3A

V

= 15V

= 5V

OUT

IN

OUT

V

= 5V

OUT

f = 250kHz

I

V

f = 250kHz

0.1

1

5

35

0.001

0.01

15

25

10

0.001

0.01

0.1

1

10

OUTPUT CURRENT (A)

INPUT VOLTAGE (V)

OUTPUT CURRENT (A)

3728 G02

3728 G03

3728 G01

3728fb

4

LTC3728

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Supply Current vs Input Voltage

and Mode (Figure 13)

INTV and EXTV Switch

CC CC

Voltage vs Temperature

EXTV Voltage Drop

CC

1000

800

600

400

200

0

250

200

150

100

50

5.05

5.00

4.95

4.90

4.85

4.80

4.75

4.70

INTV VOLTAGE

CC

BOTH

CONTROLLERS ON

EXTV SWITCHOVER THRESHOLD

CC

SHUTDOWN

10 15

INPUT VOLTAGE (V)

0

10

20

30

40

50

TEMPERATURE (°C)

100 125

0

5

20

25

30

35

–50 –25

0

25

75

CURRENT (mA)

3728 G05

3728 G04

3728 G06

Maximum Current Sense Threshold

vs Percent of Nominal Output

Voltage (Foldback)

Maximum Current Sense Threshold

vs Duty Factor

Internal 5V LDO Line Regulation

75

50

25

0

5.1

5.0

80

70

60

50

40

30

20

10

0

I

= 1mA

LOAD

4.9

4.8

4.7

4.6

4.5

4.4

0

20

40

60

80

100

50

20

INPUT VOLTAGE (V)

30

35

0

25

75

100

0

5

10

15

25

DUTY FACTOR (%)

PERCENT ON NOMINAL OUTPUT VOLTAGE (%)

3728 G08

3728 G09

3728 G07

Maximum Current Sense Threshold

vs V (Soft-Start)

Maximum Current Sense Threshold

vs Sense Common Mode Voltage

Current Sense Threshold

vs I Voltage

RUN/SS

TH

90

80

76

72

68

64

60

80

60

40

20

V

= 1.6V

SENSE(CM)

70

60

50

40

30

20

10

0

–10

–20

–30

0

1

2

3

4

5

6

0

1

2

3

4

5

0

0.5

1

1.5

(V)

2

2.5

V

(V)

COMMON MODE VOLTAGE (V)

V

ITH

RUN/SS

3728 G10

3728 G11

3728 G12

3728fb

5

LTC3728

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Load Regulation

V

ITH

vs V

SENSE Pins Total Source Current

RUN/SS

0.0

–0.1

–0.2

–0.3

–0.4

2.5

2.0

1.5

1.0

100

50

V

= 0.7V

FCB = 0V

= 15V

OSENSE

V

IN

0

–50

–100

0.5

0

2

3

4

5

6

2

4

0

1

2

3

4

5

1

0

6

V

(V)

LOAD CURRENT (A)

V

COMMON MODE VOLTAGE (V)

RUN/SS

SENSE

3728 G14

3728 G13

3728 G15

Maximum Current Sense

Threshold vs Temperature

Dropout Voltage vs Output Current

(Figure 14)

RUN/SS Current vs Temperature

80

78

76

74

72

70

4

3

2

1

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

V

OUT

= 5V

R

SENSE

= 0.015Ω

R

SENSE

= 0.010Ω

0

50

75 100 125

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

OUTPUT CURRENT (A)

–50 –25

0

25

–50 –25

0

25

125

50

75 100

TEMPERATURE (°C)

3728 G18

3728 G17

3728 G25

Soft-Start Up (Figure 13)

Load Step (Figure 13)

V_OUT

5V/DIV

V_OUT

200mV/DIV

V_OUT

200mV/DIV

V_RUN/SS

5V/DIV

I_L

2A/DIV

I_L

2A/DIV

V

_IN= 15V

5ms/DIV

3728 G19

V

_IN= 15V

V_OUT= 5V

_PLLFLTR= 0V

20µs/DIV

3728 G20

V_IN= 15V

V_OUT= 5V

V_PLLFLTR= 0V

20µs/DIV

3728 G21

V_OUT= 5V

V

LOAD STEP = 0A TO 3A

Burst Mode OPERATION

LOAD STEP = 0A TO 3A

CONTINUOUS MODE

3728fb

6

LTC3728

U W

TYPICAL PERFOR A CE CHARACTERISTICS

Input Source/Capacitor

Instantaneous Current (Figure 13)

Constant Frequency (Burst Inhibit)

Operation (Figure 13)

Burst Mode Operation (Figure 13)

I_IN

V_OUT

20mV/DIV

2A/DIV

V_OUT

20mV/DIV

V_IN

200mV/DIV

V_SW1

10V/DIV

V_SW2

10V/DIV

I_L

0.5A/DIV

V

_IN= 15V

1µs/DIV

3728 G22

V_IN= 15V

10µs/DIV

3728 G23

V_IN= 15V

2µs/DIV

3728 G24

V_OUT= 5V

V_PLLFLTR= 0V

I_OUT5= I_OUT3.3= 2A

V

_FCB= OPEN

V_FCB= 5V

I_OUT= 20mA

Current Sense Pin Input Current

vs Temperature

EXTV Switch Resistance

Oscillator Frequency

vs Temperature

CC

vs Temperature

35

33

31

29

27

25

10

8

700

600

V

OUT

= 5V

V

= 5V

PLLFLTR

500

400

300

200

100

V

= 1.2V

= 0V

6

PLLFLTR

V

4

PLLFLTR

2

0

–50 –25

0

25

50

75 100 125

–50 –25

0

25

50

75 100 125

50

100 125

–50 –25

0

25

75

TEMPERATURE (°C)

3728 G26

3728 G27

3728 G28

Undervoltage Lockout

vs Temperature

Shutdown Latch Thresholds

vs Temperature

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

3.50

3.45

3.40

3.35

LATCH ARMING

LATCHOFF

THRESHOLD

3.30

3.25

3.20

0

50

TEMPERATURE (°C)

100 125

–50 –25

0

25

125

–50 –25

0

25

75

50

75 100

TEMPERATURE (°C)

3728 G29

3728 G30

3728fb

7

LTC3728

U

PI FU CTIO S

G Package/UH Package

RUN/SS1, RUN/SS2 (Pins 1, 15/Pins 28, 13): Combina- NC (Pins 10, 16, 29, 32 UH Package Only): No Connect.

tionofsoft-start, runcontrolinputsandshort-circuitdetec-

PGND(Pin20/Pin19):DriverPowerGround.Connectstothe

tion timers. A capacitor to ground at each of these pins sets

sources of bottom (synchronous) N-channel MOSFETs, an-

the ramp time to full output current. Forcing either of these

odes of the Schottky rectifiers and the (–) terminal(s) of C_IN.

pins back below 1.0V causes the IC to shut down the

INTV_CC(Pin 21/Pin 20): Output of the Internal 5V Linear Low

Dropout Regulator and the EXTV_CCSwitch. The driver and

control circuits are powered from this voltage source. Must

be decoupled to power ground with a minimum of 4.7µF

tantalum or other low ESR capacitor.

circuitry required for that particular controller. Latchoff

overcurrent protection is also invoked via this pin as de-

scribed in the Applications Information section.

SENSE1⁺, SENSE2⁺(Pins 2, 14/Pins 30, 12):The (+) Input

to the Differential Current Comparators. The I_thpin voltage

and controlled offsets between the SENSE^–and SENSE⁺

pins in conjunction with R_SENSEset the current trip thresh-

old.

EXTV_CC(Pin 22/Pin 21): External Power Input to an

Internal Switch Connected to INTV_CC. This switch closes

and supplies V_CCpower, bypassing the internallow drop-

out regulator, whenever EXTV_CCis higher than 4.7V. See

EXTV_CCconnectioninApplicationssection. Donotexceed

7V on this pin.

SENSE1^–, SENSE2^–(Pins 3, 13/Pins 31, 11):The (–) Input

to the Differential Current Comparators.

V

_OSENSE1, V_OSENSE2(Pins 4, 12/Pins 1, 9): Receives the

BG1, BG2 (Pins 23, 19/Pins 22, 18): High Current Gate

Drives for Bottom (Synchronous) N-Channel MOSFETs.

Voltage swing at these pins is from ground to INTV_CC.

remotely-sensed feedback voltage for each controller from

an external resistive divider across the output.

PLLFLTR (Pin 5/Pin 2): The Phase-Locked Loop’s Low-

pass Filter is Tied to This Pin. Alternatively, this pin can be

driven with an AC or DC voltage source to vary the fre-

quency of the internal oscillator.

V_IN(Pin 24/Pin 23): Main Supply Pin. A bypass capacitor

should be tied between this pin and the signal ground pin.

BOOST1,BOOST2(Pins25,18/Pins24,17):Bootstrapped

Supplies to the Top Side Floating Drivers. Capacitors are

connected between the boost and switch pins and Schot-

tky diodes are tied between the boost and INTV_CCpins.

Voltage swing at the boost pins is from INTV_CCto (V_IN+

INTV_CC).

PLLIN(Pin6/Pin3):ExternalSynchronizationInputtoPhase

Detector. This pin is internally terminated to SGND with

50kΩ. The phase-locked loop will force the rising top gate

signal of controller 1 to be synchronized with the rising

edge of the PLLIN signal.

SW1, SW2 (Pins 26, 17/Pins 25, 15): Switch Node

Connections to Inductors. Voltage swing at these pins is

from a Schottky diode (external) voltage drop below

ground to V_IN.

FCB (Pin 7/Pin 4): Forced Continuous Control Input. This

input acts on both controllers and is normally used to

regulate a secondary winding. Pulling this pin below 0.8V

will force continuous synchronous operation.

TG1, TG2 (Pins 27, 16/Pins 26, 14): High Current Gate

DrivesforTopN-ChannelMOSFETs.Thesearetheoutputs

I_{TH1, TH2}(Pins 8, 11/Pins 5, 8): Error Amplifier Output and

I

Switching Regulator Compensation Point. Each associated

channels’ current comparator trip point increases with this

control voltage.

of floating drivers with a voltage swing equal to INTV_CC

0.5V superimposed on the switch node voltage SW.

–

PGOOD(Pin28/Pin27):Open-DrainLogicOutput.PGOOD

is pulled to ground when the voltage on either V_OSENSEpin

is not within ±7.5% of its set point.

SGND (Pin 9/Pin 6): Small Signal Ground common to

both controllers, must be routed separately from high

current grounds to the common (–) terminals of the

C_OUTcapacitors.

Exposed Pad (Pin 33) SGND: The exposed pad must be

soldered to PCB ground for elecrical contact and rated

thermal performance.

3.3V_OUT(Pin10/Pin7):Outputofalinearregulatorcapable

of supplying 10mA DC with peak currents as high as 50mA.

3728fb

8

LTC3728

U

W

FU CTIO AL DIAGRA

PLLIN

INTV

CC

V

IN

F

IN

PHASE DET

D

C

B

DUPLICATE FOR SECOND

CONTROLLER CHANNEL

50k

BOOST

TG

PLLFLTR

B

DROP

OUT

+

CLK1

CLK2

–

TOP

BOT

R

LP

C

IN

D

OSCILLATOR

1

DET

BOT

FCB

C

LP

SW

TOP ON

0.86V

S

Q

+

SWITCH

LOGIC

INTV

CC

R

V

OSENSE1

PGOOD

BG

–

+

0.74V

0.86V

C

OUT

PGND

B

+

–

0.55V

–

+

V

OUT

SHDN

R

SENSE

V

OSENSE2

–

+

INTV

CC

0.74V

BINH

I1

I2

V

SEC

1.5V

+

–

+

–

+

4.5V

0.8V

–

+ +

–

+

0.18µA

FCB

–

SENSE

D

SEC

C

SEC

30k

R6

3mV

0.86V

4(V

–

)

FB

+

–

FCB

R5

SLOPE

COMP

45k

2.4V

3.3V

OUT

V

OSENSE

R2

V

FB

+

–

V

REF

–

EA

+

0.80V

0.86V

R1

OV

V

IN

+

–

V

IN

C

+

–

4.7V

I

TH

5V

1.2µA

EXTV

INTV

LDO

REG

CC

SHDN

RST

RUN

SOFT

START

R

C

C2

6V

4(V

)

CC

FB

5V

+

RUN/SS

INTERNAL

SUPPLY

SGND

C

SS

3728 FD/F02

Figure 2

U

OPERATIO

(Refer to Functional Diagram)

Main Control Loop

inductor current at which I₁resets the RS latch is con-

trolled by the voltage on the I_THpin, which is the output of

each error amplifier EA. The V_OSENSEpin receives the

voltage feedback signal, which is compared to the internal

reference voltage by the EA. When the load current in-

creases, it causes a slight decrease in V_OSENSErelative to

the 0.8V reference, which in turn causes the I_THvoltage to

The LTC3728 uses a constant frequency, current mode

step-down architecture with the two controller channels

operating180degreesoutofphase. Duringnormalopera-

tion, eachtopMOSFETisturnedonwhentheclockforthat

channel sets the RS latch, and turned off when the main

current comparator, I₁, resets the RS latch. The peak

3728fb

9

LTC3728

U

OPERATIO

(Refer to Functional Diagram)

increase until the average inductor current matches the

new load current. After the top MOSFET has turned off, the

bottom MOSFET is turned on until either the inductor

currentstartstoreverse, asindicatedbycurrentcompara-

tor I₂, or the beginning of the next cycle.

temporarily inhibit turn-on of both output MOSFETs until

the output voltage drops. There is 60mV of hysteresis in

the burst comparator B tied to the I_THpin. This hysteresis

produces output signals to the MOSFETs that turn them

on for several cycles, followed by a variable “sleep”

interval depending upon the load current. The resultant

output voltage ripple is held to a very small value by

having the hysteretic comparator after the error amplifier

gain block.

The top MOSFET drivers are biased from floating boot-

strap capacitor C_B, which normally is recharged during

each off cycle through an external diode when the top

MOSFET turns off. As V_INdecreases to a voltage close to

V_OUT, the loop may enter dropout and attempt to turn on

the top MOSFET continuously. The dropout detector de-

tects this and forces the top MOSFET off for about 400ns

every tenth cycle to allow C_Bto recharge.

Frequency Synchronization

The phase-locked loop allows the internal oscillator to be

synchronized to an external source via the PLLIN pin. The

output of the phase detector at the PLLFLTR pin is also the

DC frequency control input of the oscillator that operates

over a 250kHz to 550kHz range corresponding to a DC

voltageinputfrom0Vto2.4V.Whenlocked,thePLLaligns

the turn on of the top MOSFET to the rising edge of the

synchronizingsignal.WhenPLLINisleftopen,thePLLFLTR

pingoeslow,forcingtheoscillatortominimumfrequency.

The main control loop is shut down by pulling the RUN/SS

pin low. Releasing RUN/SS allows an internal 1.2µA

current source to charge soft-start capacitor C_SS. When

C_SSreaches1.5V,themaincontrolloopisenabledwiththe

I_THvoltageclampedatapproximately30%ofitsmaximum

value. As C_SScontinues to charge, the I_THpin voltage is

gradually released allowing normal, full-current opera-

tion. When both RUN/SS1 and RUN/SS2 are low, all

LTC3728 controller functions are shut down,

including the 5V and 3.3V regulators.

Constant Frequency Operation

When the FCB pin is tied to INTV_CC, Burst Mode operation

is disabled and the forced minimum output current

requirementisremoved.Thisprovidesconstantfrequency,

discontinuous (preventing reverse inductor current)

current operation over the widest possible output current

range.Thisconstantfrequencyoperationisnotasefficient

as Burst Mode operation, but does provide a lower noise,

constant frequency operating mode down to approxi-

mately 1% of designed maximum output current.

Low Current Operation

The FCB pin is a multifunction pin providing two func-

tions:1)toprovideregulationforasecondarywindingby

temporarily forcing continuous PWM operation on

bothcontrollers;and2)selectbetweentwomodesoflow

current operation. When the FCB pin voltage is below

0.8V, the controller forces continuous PWM current

mode operation. In this mode, the top and bottom

MOSFETsarealternatelyturnedontomaintaintheoutput

voltage independent of direction of inductor current.

When the FCB pin is below V_INTVCC– 1V but greater than

0.8V, the controller enters Burst Mode operation. Burst

Mode operation sets a minimum output current level

beforeinhibitingthetopswitchandturnsoffthesynchro-

nous MOSFET(s) when the inductor current goes nega-

tive. This combination of requirements will, at low cur-

rents, force the I_THpin below a voltage threshold that will

Continuous Current (PWM) Operation

Tying the FCB pin to ground will force continuous current

operation. This is the least efficient operating mode, but

may be desirable in certain applications. The output can

source or sink current in this mode. When sinking current

while in forced continuous operation, current will be

forced back into the main power supply.

3728fb

10

LTC3728

U

OPERATIO

(Refer to Functional Diagram)

INTV_CC/EXTV_CCPower

This built-in latchoff can be overridden by providing a

>5µA pull-up at a compliance of 5V to the RUN/SS pin(s).

This current shortens the soft start period but also pre-

vents net discharge of the RUN/SS capacitor(s) during an

overcurrent and/or short-circuit condition. Foldback cur-

rent limiting is also activated when the output voltage falls

below 70% of its nominal level whether or not the short-

circuit latchoff circuit is enabled. Even if a short is present

and the short-circuit latchoff is not enabled, a safe, low

outputcurrentisprovidedduetointernalcurrentfoldback

and actual power wasted is low due to the efficient nature

of the current mode switching regulator.

Power for the top and bottom MOSFET drivers and most

other internal circuitry is derived from the INTV_CCpin.

When the EXTV_CCpin is left open, an internal 5V low

dropoutlinearregulatorsuppliesINTV_CCpower.IfEXTV_CC

is taken above 4.7V, the 5V regulator is turned off and an

internalswitchisturnedonconnectingEXTV_CCtoINTV_CC.

This allows the INTV_CCpower to be derived from a high

efficiency external source such as the output of the regu-

lator itself or a secondary winding, as described in the

Applications Information section.

Output Overvoltage Protection

THEORY AND BENEFITS OF 2-PHASE OPERATION

An overvoltage comparator, OV, guards against transient

overshoots (>7.5%) as well as other more serious condi-

tions that may overvoltage the output. In this case, the top

MOSFETisturnedoffandthebottomMOSFETisturnedon

until the overvoltage condition is cleared.

TheLTC1628andtheLTC3728dualhighefficiencyDC/DC

controllers bring the considerable benefits of 2-phase

operation to portable applications for the first time. Note-

book computers, PDAs, handheld terminals and automo-

tiveelectronicswillallbenefitfromthelowerinputfiltering

requirement, reduced electromagnetic interference (EMI)

and increased efficiency associated with 2-phase opera-

tion.

Power Good (PGOOD) Pin

ThePGOODpinisconnectedtoanopendrainofaninternal

MOSFET.TheMOSFETturnsonandpullsthepinlowwhen

either output is not within ±7.5% of the nominal output

level as determined by the resistive feedback divider.

When both outputs meet the ±7.5% requirement, the

MOSFET is turned off within 10µs and the pin is allowed to

be pulled up by an external resistor to a source of up to 7V.

Why the need for 2-phase operation? Up until the 2-phase

family, constant-frequency dual switching regulators op-

erated both channels in phase (i.e., single-phase opera-

tion). Thismeansthatbothswitchesturnedonatthesame

time, causing current pulses of up to twice the amplitude

of those for one regulator to be drawn from the input

capacitorandbattery.Theselargeamplitudecurrentpulses

increased the total RMS current flowing from the input

capacitor, requiring the use of more expensive input

capacitorsandincreasingbothEMIandlossesintheinput

capacitor and battery.

Foldback Current, Short-Circuit Detection

and Short-Circuit Latchoff

TheRUN/SScapacitorsareusedinitiallytolimittheinrush

current of each switching regulator. After the controller

has been started and been given adequate time to charge

up the output capacitors and provide full load current, the

RUN/SS capacitor is used in a short-circuit time-out

circuit. If the output voltage falls to less than 70% of its

nominal output voltage, the RUN/SS capacitor begins

discharging on the assumption that the output is in an

overcurrent and/or short-circuit condition. If the condi-

tion lasts for a long enough period as determined by the

size of the RUN/SS capacitor, the controller will be shut

down until the RUN/SS pin(s) voltage(s) are recycled.

With 2-phase operation, the two channels of the dual-

switching regulator are operated 180 degrees out of

phase. This effectively interleaves the current pulses

drawn by the switches, greatly reducing the overlap time

where they add together. The result is a significant reduc-

tion in total RMS input current, which in turn allows less

expensive input capacitors to be used, reduces shielding

requirements for EMI and improves real world operating

efficiency.

3728fb

11

LTC3728

U

OPERATIO

(Refer to Functional Diagram)

5V SWITCH

20V/DIV

3.3V SWITCH

20V/DIV

INPUT CURRENT

5A/DIV

INPUT VOLTAGE

500mV/DIV

I_IN(MEAS)= 2.53A_RMS

I_IN(MEAS)= 1.55A_RMS

DC236 F03a

DC236 F03b

(a)

(b)

Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators

Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the LTC1628 2-Phase Regulator Allows

Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency

Figure 3 compares the input waveforms for a representa-

tive single-phase dual switching regulator to the LTC1628

2-phase dual switching regulator. An actual measurement

of the RMS input current under these conditions shows

that 2-phase operation dropped the input current from

2.53A_RMSto 1.55A_RMS. While this is an impressive reduc-

tion in itself, remember that the power losses are propor-

tional to I_RMS², meaning that the actual power wasted is

reduced by a factor of 2.66. The reduced input ripple

voltage also means less power is lost in the input power

path, which could include batteries, switches, trace/con-

nectorresistancesandprotectioncircuitry.Improvements

inbothconductedandradiatedEMIalsodirectlyaccrueas

a result of the reduced RMS input current and voltage.

regulators, why hasn’t it been done before? The answer is

that, while simple in concept, it is hard to implement.

Constant-frequency current mode switching regulators

require an oscillator derived “slope compensation” signal

to allow stable operation of each regulator at over 50%

duty cycle. This signal is relatively easy to derive in single-

phasedualswitchingregulators,butrequiredthedevelop-

ment of a new and proprietary technique to allow 2-phase

operation. In addition, isolation between the two channels

becomes more critical with 2-phase operation because

switch transitions in one channel could potentially disrupt

the operation of the other channel.

These 2-phase parts are proof that these hurdles have

been surmounted. They offer unique advantages for the

ever-expanding number of high efficiency power supplies

required in portable electronics.

Of course, the improvement afforded by 2-phase opera-

tion is a function of the dual switching regulator’s relative

duty cycles which, in turn, are dependent upon the input

voltage V_IN(Duty Cycle = V_OUT/V_IN). Figure 4 shows how

theRMSinputcurrentvariesforsingle-phaseand2-phase

operation for 3.3V and 5V regulators over a wide input

voltage range.

3.0

SINGLE PHASE

DUAL CONTROLLER

2.5

2.0

1.5

It can readily be seen that the advantages of 2-phase

operation are not just limited to a narrow operating range,

but in fact extend over a wide region. A good rule of thumb

for most applications is that 2-phase operation will reduce

theinputcapacitorrequirementtothatforjustonechannel

operating at maximum current and 50% duty cycle.

2-PHASE

DUAL CONTROLLER

1.0

0.5

V

= 5V/3A

O1

O2

= 3.3V/3A

0

10

20

INPUT VOLTAGE (V)

30

40

3728 F04

A final question: If 2-phase operation offers such an

advantage over single-phase operation for dual switching

Figure 4. RMS Input Current Comparison

3728fb

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LTC3728

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APPLICATIO S I FOR ATIO

U

2.5

Figure 1 on the first page is a basic LTC3728 application

circuit. External component selection is driven by the

loadrequirement,andbeginswiththeselectionofR_SENSE

andtheinductorvalue. Next, thepowerMOSFETsandD1

are selected. Finally, C_INand C_OUTare selected. The

circuit shown in Figure 1 can be configured for operation

up to an input voltage of 28V (limited by the external

MOSFETs).

2.0

1.5

1.0

0.5

0

R_SENSESelection For Output Current

200 250 300 350 400 450 500 550

OPERATING FREQUENCY (kHz)

R_SENSEis chosen based on the required output current.

3728 F05

The LTC3728 current comparator has a maximum thresh-

old of 75mV/R_SENSEand an input common mode range of

SGND to 1.1(INTV_CC). The current comparator threshold

sets the peak of the inductor current, yielding a maximum

average output current I_MAXequal to the peak value less

half the peak-to-peak ripple current, ∆I_L.

Figure 5. PLLFLTR Pin Voltage vs Frequency

isincreasedthegatechargelosseswillbehigher,reducing

efficiency (see Efficiency Considerations). The maximum

switching frequency is approximately 550kHz.

Allowing a margin for variations in the LTC3728 and

external component values yields:

Inductor Value Calculation

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efficiency. A higher

frequency generally results in lower efficiency because of

MOSFET gate charge losses. In addition to this basic

trade-off, the effect of inductor value on ripple current and

low current operation must also be considered.

50mV

I_MAX

R_SENSE

=

When using the controller in very low dropout conditions,

the maximum output current level will be reduced due to

the internal compensation required to meet stability crite-

rion for buck regulators operating at greater than 50%

duty factor. A curve is provided to estimate this reducton

in peak output current level depending upon the operating

duty factor.

Theinductorvaluehasadirecteffectonripplecurrent.The

inductor ripple current ∆I_Ldecreases with higher induc-

tance or frequency and increases with higher V_IN:

Operating Frequency

The LTC3728 uses a constant frequency phase-lockable

architecture with the frequency determined by an internal

capacitor. This capacitor is charged by a fixed current plus

an additional current which is proportional to the voltage

applied to the PLLFLTR pin. Refer to Phase-Locked Loop

and Frequency Synchronization in the Applications Infor-

mation section for additional information.

⎛

⎞

1

(f)(L)

V_OUT

V

IN

∆I_L=

V_OUT1–

⎜

⎟

⎝

⎠

Accepting larger values of ∆I_Lallows the use of low

inductances, but results in higher output voltage ripple

and greater core losses. A reasonable starting point for

setting ripple current is ∆I_L=0.3(I_MAX). The maximum ∆I_L

occurs at the maximum input voltage.

A graph for the voltage applied to the PLLFLTR pin vs

frequency is given in Figure 5. As the operating frequency

3728fb

13

LTC3728

W U U

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APPLICATIO S I FOR ATIO

The inductor value also has secondary effects. The transi-

tion to Burst Mode operation begins when the average

inductor current required results in a peak current below

25% of the current limit determined by R_SENSE. Lower

inductor values (higher ∆I_L) will cause this to occur at

lower load currents, which can cause a dip in efficiency in

the upper range of low current operation. In Burst Mode

operation, lower inductance values will cause the burst

frequency to decrease.

The peak-to-peak drive levels are set by the INTV_CC

voltage. This voltage is typically 5V during start-up (see

EXTV_CCPin Connection). Consequently, logic-level

threshold MOSFETs must be used in most applications.

The only exception is if low input voltage is expected

(V_IN< 5V); then, sub-logic level threshold MOSFETs

(V_GS(TH)< 3V) should be used. Pay close attention to the

BV_DSSspecification for the MOSFETs as well; most of the

logic level MOSFETs are limited to 30V or less.

SelectioncriteriaforthepowerMOSFETsincludethe“ON”

Inductor Core Selection

resistance R_DS(ON), reverse transfer capacitance C_RSS

,

Once the value for L is known, the type of inductor must

be selected. High efficiency converters generally cannot

afford the core loss found in low cost powdered iron

cores, forcing the use of more expensive ferrite,

molypermalloy, or Kool Mµ^®cores. Actual core loss is

independent of core size for a fixed inductor value, but it

is very dependent on inductance selected. As inductance

increases, core losses go down. Unfortunately, increased

inductance requires more turns of wire and therefore

copper losses will increase.

input voltage and maximum output current. When the

LTC3728 is operating in continuous mode the duty cycles

for the top and bottom MOSFETs are given by:

V_OUT

V

IN

Main SwitchDuty Cycle =

V – V_OUT

IN

Synchronous SwitchDuty Cycle =

V

IN

The MOSFET power dissipations at maximum output

current are given by:

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

2

V_OUT

P_MAIN

=

I_MAX1+ δ R_DS(ON)

+

(

) (

)

V

IN

2

k V

I_MAXC_RSS

f

(

^IN) (

)(

)( )

2

Molypermalloy (from Magnetics, Inc.) is a very good, low

losscorematerialfortoroids,butitismoreexpensivethan

ferrite. A reasonable compromise from the same manu-

facturer is Kool Mµ. Toroids are very space efficient,

especially when you can use several layers of wire. Be-

cause they generally lack a bobbin, mounting is more

difficult. However, designsforsurfacemountareavailable

that do not increase the height significantly.

V – V_OUT

IN

P

SYNC

=

I_MAX1+ δ R_DS(ON)

(

) (

)

V

IN

where δ is the temperature dependency of R_DS(ON)and k

is a constant inversely related to the gate drive current.

BothMOSFETshaveI²RlosseswhilethetopsideN-channel

equation includes an additional term for transition losses,

which are highest at high input voltages. For V_IN< 20V the

high current efficiency generally improves with larger

MOSFETs, while for V_IN> 20V the transition losses rapidly

increasetothepointthattheuseofahigherR_DS(ON)device

with lower C_RSSactually provides higher efficiency. The

Power MOSFET and D1 Selection

Two external power MOSFETs must be selected for each

controller in the LTC3728: One N-channel MOSFET for the

top (main) switch, and one N-channel MOSFET for the

bottom (synchronous) switch.

Kool Mµ is a registered trademark of Magnetics, Inc.

3728fb

14

LTC3728

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APPLICATIO S I FOR ATIO

U

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during a

short-circuit when the synchronous switch is on close to

100% of the period.

battery currents down. 20µF to 40µF is usually sufficient

for a 25W output supply operating at 200kHz. The ESR of

the capacitor is important for capacitor power dissipation

as well as overall battery efficiency. All of the power (RMS

ripple current • ESR) not only heats up the capacitor but

wastes power from the battery.

Theterm(1+δ)isgenerallygivenforaMOSFETintheform

of a normalized R_DS(ON)vs Temperature curve, but

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs. C_RSSis usually specified in the MOS-

FET characteristics. The constant k = 1.7 can be used to

estimate the contributions of the two terms in the main

switch dissipation equation.

Medium voltage (20V to 35V) ceramic, tantalum, OS-CON

and switcher-rated electrolytic capacitors can be used as

inputcapacitors,buteachhasdrawbacks:ceramicvoltage

coefficients are very high and may have audible piezoelec-

tric effects; tantalums need to be surge-rated; OS-CONs

suffer from higher inductance, larger case size and limited

surface-mount applicability; electrolytics’ higher ESR and

dryout possibility require several to be used. Multiphase

systems allow the lowest amount of capacitance overall.

As little as one 22µF or two to three 10µF ceramic capaci-

tors are an ideal choice in a 20W to 35W power supply due

to their extremely low ESR. Even though the capacitance

at 20V is substantially below their rating at zero-bias, very

low ESR loss makes ceramics an ideal candidate for

highest efficiency battery operated systems. Also con-

sider parallel ceramic and high quality electrolytic capaci-

tors as an effective means of achieving ESR and bulk

capacitance goals.

The Schottky diode D1 shown in Figure 1 conducts during

the dead-time between the conduction of the two power

MOSFETs. This prevents the body diode of the bottom

MOSFET from turning on, storing charge during the dead-

time and requiring a reverse recovery period that could

cost as much as 3% in efficiency at high V_IN. A 1A to 3A

Schottky is generally a good compromise for both regions

of operation due to the relatively small average current.

Larger diodes result in additional transition losses due to

their larger junction capacitance. Schottky diodes should

beplacedinparallelwiththesynchronousMOSFETswhen

operating in pulse-skip mode or in Burst Mode operation.

Incontinuousmode, thesourcecurrentofthetopN-chan-

nel MOSFET is a square wave of duty cycle V_OUT/V_IN. To

preventlargevoltagetransients, alowESRinputcapacitor

sized for the maximum RMS current of one channel must

beused. ThemaximumRMScapacitorcurrentisgivenby:

C_INand C_OUTSelection

The selection of C_INis simplified by the multiphase archi-

tecture and its impact on the worst-case RMS current

drawnthroughtheinputnetwork(battery/fuse/capacitor).

It can be shown that the worst case RMS current occurs

when only one controller is operating. The controller with

the highest (V_OUT)(I_OUT) product needs to be used in the

formula below to determine the maximum RMS current

requirement. Increasing the output current, drawn from

the other out-of-phase controller, will actually decrease

the input RMS ripple current from this maximum value

(see Figure 4). The out-of-phase technique typically re-

duces the input capacitor’s RMS ripple current by a factor

of 30% to 70% when compared to a single phase power

supply solution.

1/2

]

V

V − V

OUT

(

)

[

OUT IN

C_INRequiredI_RMS≈I_MAX

V

IN

This formula has a maximum at V_IN= 2V_OUT, where

_RMS= I_OUT/2. This simple worst case condition is com-

I

monlyusedfordesignbecauseevensignificantdeviations

donotoffermuchrelief.Notethatcapacitormanufacturer’s

ripple current ratings are often based on only 2000 hours

of life. This makes it advisable to further derate the

capacitor, or to choose a capacitor rated at a higher

temperaturethanrequired.Severalcapacitorsmayalsobe

paralleled to meet size or height requirements in the

design. Always consult the manufacturer if there is any

The type of input capacitor, value and ESR rating have

efficiency effects that need to be considered in the selec-

tion process. The capacitance value chosen should be

sufficient to store adequate charge to keep high peak

question.

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The benefit of the LTC3728 multiphase can be calculated

by using the equation above for the higher power control-

ler and then calculating the loss that would have resulted

if both controller channels switch on at the same time. The

total RMS power lost is lower when both controllers are

operatingduetotheinterleavingofcurrentpulsesthrough

theinputcapacitor’sESR. Thisiswhytheinputcapacitor’s

requirement calculated above for the worst-case control-

ler is adequate for the dual controller design. Remember

that input protection fuse resistance, battery resistance

and PC board trace resistance losses are also reduced due

to the reduced peak currents in a multiphase system. The

overall benefit of a multiphase design will only be fully

realized when the source impedance of the power supply/

battery is included in the efficiency testing. The drains of

thetwotopMOSFETSshouldbeplacedwithin1cmofeach

other and share a common C_IN(s). Separating the drains

and C_INmay produce undesirable voltage and current

resonances at V_IN.

capacitance increases the ripple voltage due to the dis-

charging term but can be compensated for by using

capacitors of very low ESR to maintain the ripple voltage

at or below 50mV. The I_THpin OPTI-LOOP compensation

components can be optimized to provide stable, high

performance transient response regardless of the output

capacitors selected.

Manufacturers such as Nichicon, United Chemicon and

Sanyo can be considered for high performance through-

hole capacitors. The OS-CON semiconductor dielectric

capacitor available from Sanyo has the lowest (ESR)(size)

product of any aluminum electrolytic at a somewhat

higher price. An additional ceramic capacitor in parallel

with OS-CON capacitors is recommended to reduce the

inductance effects.

In surface mount applications multiple capacitors may

need to be used in parallel to meet the ESR, RMS current

handling and load step requirements of the application.

Aluminum electrolytic, dry tantalum and special polymer

capacitors are available in surface mount packages. Spe-

cial polymer surface mount capacitors offer very low ESR

buthavelowerstoragecapacityperunitvolumethanother

capacitor types. These capacitors offer a very cost-effec-

tiveoutputcapacitorsolutionandareanidealchoicewhen

combined with a controller having high loop bandwidth.

Tantalum capacitors offer the highest capacitance density

and are often used as output capacitors for switching

regulators having controlled soft-start. Several excellent

surge-tested choices are the AVX TPS, AVX TPSV or the

KEMET T510 series of surface mount tantalums, available

in case heights ranging from 2mm to 4mm. Aluminum

electrolytic capacitors can be used in cost-driven applica-

tionsprovidingthatconsiderationisgiventoripplecurrent

ratings, temperature and long term reliability. A typical

application will require several to many aluminum electro-

lytic capacitors in parallel. A combination of the above

mentioned capacitors will often result in maximizing per-

formance and minimizing overall cost. Other capacitor

types include Nichicon PL series, NEC Neocap, Cornell

Dubilier ESRE and Sprague 595D series. Consult manu-

facturers for other specific recommendations.

The selection of C_OUTis driven by the required effective

series resistance (ESR). Typically once the ESR require-

ment is satisfied the capacitance is adequate for filtering.

The output ripple (∆V_OUT) is determined by:

⎛

⎞

1

∆V_OUT≈ ∆I_LESR +

⎜

⎟

8fC_OUT

⎝

⎠

Wheref=operatingfrequency,C_OUT=outputcapacitance,

and ∆I_L= ripple current in the inductor. The output ripple

is highest at maximum input voltage since ∆I_Lincreases

with input voltage. With ∆I_L= 0.3I_OUT(MAX)the output

ripple will typically be less than 50mV at max V_INassum-

ing:

C_OUTRecommended ESR < 2 R_SENSE

and C_OUT> 1/(8fR_SENSE

)

The first condition relates to the ripple current into the

ESR of the output capacitance while the second term

guarantees that the output capacitance does not signifi-

cantly discharge during the operating frequency period

due to ripple current. The choice of using smaller output

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U

INTV_CCRegulator

EXTV_CCConnection

An internal P-channel low dropout regulator produces 5V

at the INTV_CCpin from the V_INsupply pin. INTV_CCpowers

the drivers and internal circuitry within the LTC3728. The

INTV_CCpin regulator can supply a peak current of 50mA

and must be bypassed to ground with a minimum of

4.7µF tantalum, 10µF special polymer, or low ESR type

electrolytic capacitor. A 1µF ceramic capacitor placed

directlyadjacenttotheINTV_CCandPGNDICpinsishighly

recommended. Good bypassing is necessary to supply

the high transient currents required by the MOSFET gate

drivers and to prevent interaction between channels.

The LTC3728 contains an internal P-channel MOSFET

switch connected between the EXTV_CCand INTV_CCpins.

When the voltage applied to EXTV_CCrises above 4.7V, the

internal regulator is turned off and the switch closes,

connecting the EXTV_CCpin to the INTV_CCpin thereby

supplying internal power. The switch remains closed as

longasthevoltageappliedtoEXTV_CCremainsabove4.5V.

This allows the MOSFET driver and control power to be

derived from the output during normal operation (4.7V <

V

_OUT<7V)andfromtheinternalregulatorwhentheoutput

is out of regulation (start-up, short-circuit). If more

current is required through the EXTV_CCswitch than is

specified, an external Schottky diode can be added be-

tween the EXTV_CCand INTV_CCpins. Do not apply greater

than 7V to the EXTV_CCpin and ensure that EXTV_CC< V_IN.

Higher input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC3728 to be

exceeded. The system supply current is normally domi-

nated by the gate charge current. Additional external

loading of the INTV_CCand 3.3V linear regulators also

needs to be taken into account for the power dissipation

calculations. The total INTV_CCcurrent can be supplied by

either the 5V internal linear regulator or by the EXTV_CC

input pin. When the voltage applied to the EXTV_CCpin is

less than 4.7V, all of the INTV_CCcurrent is supplied by the

internal 5V linear regulator. Power dissipation for the IC in

this case is highest: (V_IN)(I_INTVCC), and overall efficiency

is lowered. The gate charge current is dependent on

operatingfrequencyasdiscussedintheEfficiencyConsid-

erations section. The junction temperature can be esti-

mated by using the equations given in Note 2 of the

Electrical Characteristics. For example, the LTC3728 V_IN

current is limited to less than 24mA from a 24V supply

when not using the EXTV_CCpin as follows:

Significant efficiency gains can be realized by powering

INTV_CCfrom the output, since the V_INcurrent resulting

from the driver and control currents will be scaled by a

factor of (Duty Cycle)/(Efficiency). For 5V regulators this

supply means connecting the EXTV_CCpin directly to V_OUT

.

However, for 3.3V and other lower voltage regulators,

additional circuitry is required to derive INTV_CCpower

from the output.

The following list summarizes the four possible connec-

tions for EXTV_CC:

1. EXTV_CCLeftOpen(orGrounded).ThiswillcauseINTV_CC

to be powered from the internal 5V regulator resulting in

an efficiency penalty of up to 10% at high input voltages.

2. EXTV_CCConnected directly to V_OUT. This is the normal

connection for a 5V regulator and provides the highest

efficiency.

T_J= 70°C + (24mA)(24V)(95°C/W) = 125°C

3. EXTV_CCConnected to an External supply. If an external

supply is available in the 5V to 7V range, it may be used to

powerEXTV_CCprovidingitiscompatiblewiththeMOSFET

gate drive requirements.

UseoftheEXTV_CCinputpinreducesthejunctiontempera-

ture to:

T_J= 70°C + (24mA)(5V)(95°C/W) = 81°C

Dissipationshouldbecalculatedtoalsoincludeanyadded

current drawn from the internal 3.3V linear regulator. To

prevent maximum junction temperature from being

exceeded, the input supply current must be checked

operating in continuous mode at maximum V_IN.

4. EXTV_CCConnected to an Output-Derived Boost Net-

work. For3.3Vandotherlowvoltageregulators, efficiency

gains can still be realized by connecting EXTV_CCto an

output-derived voltage that has been boosted to greater

than 4.7V. This can be done with either the inductive boost

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winding as shown in Figure 6a or the capacitive charge

pump shown in Figure 6b. The charge pump has the

advantage of simple magnetics.

compared with the internal precision 0.800V voltage

reference by the error amplifier. The output voltage is

given by the equation:

Topside MOSFET Driver Supply (C_B, D_B)

⎛

⎞

R2

R1

V_OUT= 0.8V 1+

⎜

⎟

External bootstrap capacitors C_Bconnected to the BOOST

pinssupplythegatedrivevoltagesforthetopsideMOSFETs.

Capacitor C_Bin the functional diagram is charged though

external diode D_Bfrom INTV_CCwhen the SW pin is low.

When one of the topside MOSFETs is to be turned on, the

driver places the C_Bvoltage across the gate-source of the

desiredMOSFET.ThisenhancestheMOSFETandturnson

the topside switch. The switch node voltage, SW, rises to

V_INand the BOOST pin follows. With the topside MOSFET

⎝

⎠

where R1 and R2 are defined in Figure 2.

SENSE⁺/SENSE^–Pins

The common mode input range of the current comparator

sense pins is from 0V to (1.1)INTV_CC. Continuous linear

operation is guaranteed throughout this range allowing

output voltage setting from 0.8V to 7.7V, depending upon

the voltage applied to EXTV_CC. A differential NPN input

stage is biased with internal resistors from an internal

2.4V source as shown in the Functional Diagram. This

requires that current either be sourced or sunk from the

SENSE pins depending on the output voltage. If the output

voltage is below 2.4V current will flow out of both SENSE

pinstothemainoutput.Theoutputcanbeeasilypreloaded

by the V_OUTresistive divider to compensate for the current

comparator’s negative input bias current. The maximum

current flowing out of each pair of SENSE pins is:

on, the boost voltage is above the input supply: V_BOOST

=

V_IN+ V_INTVCC. The value of the boost capacitor C_Bneeds

to be 100 times that of the total input capacitance of the

topside MOSFET(s). The reverse breakdown of the exter-

nal Schottky diode must be greater than V_IN(MAX). When

adjusting the gate drive level, the final arbiter is the total

input current for the regulator. If a change is made and the

input current decreases, then the efficiency has improved.

If there is no change in input current, then there is no

change in efficiency.

I_SENSE⁺+ I_SENSE^–= (2.4V – V_OUT)/24k

Output Voltage

The LTC3728 output voltages are each set by an external

feedback resistive divider carefully placed across

the output capacitor. The resultant feedback signal is

SinceV_OSENSEisservoedtothe0.8Vreferencevoltage, we

can choose R1 in Figure 2 to have a maximum value to

absorb this current.

+

V

IN

1µF

OPTIONAL EXTV

CONNECTION

CC

+

5V < V

< 7V

SEC

C

IN

0.22µF

BAT85

V

SEC

IN

+

LTC3728

CC

LTC3728

1µF

VN2222LL

TG1

SW

TG1

SW

R

SENSE

N-CH

V

OUT

L1

T1

1:N

EXTV

FCB

CC

R6

R5

+

C

BG1

OUT

BG1

OUT

SGND

PGND

3728 F06b

3728 F06a

Figure 6b. Capacitive Charge Pump for EXTV

Figure 6a. Secondary Output Loop & EXTV Connection

CC

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U

V

IN

INTV

CC

R

⎛

⎞

⎟

0.8V

3.3V OR 5V

RUN/SS

*

R1

= 24k

R

*

SS

(MAX)

SS

⎜

D1

2.4V – V

⎝

⎠

OUT

RUN/SS

C

SS

for V_OUT< 2.4V

C

SS

Regulating an output voltage of 1.8V, the maximum value

of R1 should be 32K. Note that for an output voltage above

2.4V, R1 has no maximum value necessary to absorb the

sense currents; however, R1 is still bounded by the

*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF

(a)

3728 F07

(b)

Figure 7. RUN/SS Pin Interfacing

V

_OSENSEfeedback current.

Soft-Start/Run Function

Fault Conditions: Overcurrent Latchoff

The RUN/SS1 and RUN/SS2 pins are multipurpose pins

that provide a soft-start function and a means to shut

down the LTC3728. Soft-start reduces the input power

source’s surge currents by gradually increasing the

controller’s current limit (proportional to V_ITH). This pin

can also be used for power supply sequencing.

The RUN/SS pins also provide the ability to latch off the

controller(s) when an overcurrent condition is detected.

The RUN/SS capacitor, C_SS, is used initially to turn on and

limit the inrush current. After the controller has been

started and been given adequate time to charge up the

outputcapacitorandprovidefullloadcurrent, theRUN/SS

capacitorisusedforashort-circuittimer. Iftheregulator’s

output voltage falls to less than 70% of its nominal value

after C_SSreaches 4.1V, C_SSbegins discharging on the

assumption that the output is in an overcurrent condition.

If the condition lasts for a long enough period as deter-

mined by the size of the C_SSand the specified discharge

current, the controller will be shut down until the RUN/SS

pin voltage is recycled. If the overload occurs during start-

up, the time can be approximated by:

An internal 1.2µA current source charges up the C_SS

capacitor_.When the voltage on RUN/SS1 (RUN/SS2)

reaches 1.5V, the particular controller is permitted to start

operating. As the voltage on RUN/SS increases from 1.5V

to 3.0V, the internal current limit is increased from 25mV/

R_SENSEto 75mV/R_SENSE. The output current limit ramps

up slowly, taking an additional 1.25s/µF to reach full

current. The output current thus ramps up slowly, reduc-

ing the starting surge current required from the input

power supply. If RUN/SS has been pulled all the way to

ground there is a delay before starting of approximately:

t_LO1≈ [C_SS(4.1 – 1.5 + 4.1 – 3.5)]/(1.2µA)

= 2.7 • 10⁶(C_SS)

If the overload occurs after start-up the voltage on C_SSwill

begin discharging from the zener clamp voltage:

1.5V

1.2µA

t_DELAY

=

C_SS= 1.25s /µF C_SS

(

)

t_LO2≈ [C_SS(6 – 3.5)]/(1.2µA) = 2.1 • 10⁶(C_SS)

3V − 1.5V

1.2µA

This built-in overcurrent latchoff can be overridden by

providing a pull-up resistor to the RUN/SS pin as shown

in Figure 7. This resistance shortens the soft-start period

and prevents the discharge of the RUN/SS capacitor

during an over current condition. Tying this pull-up resis-

tor to V_INas in Figure 7a, defeats overcurrent latchoff.

Diode-connecting this pull-up resistor to INTV_CC, as in

Figure 7b, eliminates any extra supply current during

controller shutdown while eliminating the INTV_CCloading

from preventing controller start-up.

t

C_SS= 1.25s /µF C_SS

IRAMP

(

)

By pulling both RUN/SS pins below 1V, the LTC3728 is

put into low current shutdown (I_Q= 20µA). The RUN/SS

pins can be driven directly from logic as shown in Figure

7. Diode D1 in Figure 7 reduces the start delay but allows

C_SSto ramp up slowly providing the soft-start function.

Each RUN/SS pin has an internal 6V zener clamp (See

Functional Diagram).

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Why should you defeat overcurrent latchoff? During the

prototyping stage of a design, there may be a problem

with noise pickup or poor layout causing the protection

circuit to latch off. Defeating this feature will easily allow

troubleshooting of the circuit and PC layout. The internal

short-circuit and foldback current limiting still remains

active, thereby protecting the power supply system from

failure. After the design is complete, a decision can be

made whether to enable the latchoff feature.

The resulting short-circuit current is:

25mV

R_SENSE

1

2

I_SC

=

+ ∆I_L(SC)

Fault Conditions: Overvoltage Protection (Crowbar)

The overvoltage crowbar is designed to blow a system

input fuse when the output voltage of the regulator rises

much higher than nominal levels. The crowbar causes

huge currents to flow, that blow the fuse to protect against

a shorted top MOSFET if the short occurs while the

controller is operating.

The value of the soft-start capacitor C_SSmay need to be

scaled with output voltage, output capacitance and load

current characteristics. The minimum soft-start capaci-

tance is given by:

A comparator monitors the output for overvoltage condi-

tions. The comparator (OV) detects overvoltage faults

greater than 7.5% above the nominal output voltage.

When this condition is sensed, the top MOSFET is turned

off and the bottom MOSFET is turned on until the overvolt-

age condition is cleared. The output of this comparator is

only latched by the overvoltage condition itself and will

thereforeallowaswitchingregulatorsystemhavingapoor

PC layout to function while the design is being debugged.

The bottom MOSFET remains on continuously for as long

as the OV condition persists; if V_OUTreturns to a safe level,

normal operation automatically resumes. A shorted top

MOSFET will result in a high current condition which will

open the system fuse. The switching regulator will regu-

late properly with a leaky top MOSFET by altering the duty

cycle to accommodate the leakage.

C

_SS> (C_OUT)(V_OUT) (10^–4) (R_SENSE

)

The minimum recommended soft-start capacitor of

C_SS= 0.1µF will be sufficient for most applications.

Fault Conditions: Current Limit and Current Foldback

The LTC3728 current comparator has a maximum sense

voltage of 75mV resulting in a maximum MOSFET current

of 75mV/R_SENSE. The maximum value of current limit

generally occurs with the largest V_INat the highest ambi-

ent temperature, conditions that cause the highest power

dissipation in the top MOSFET.

The LTC3728 includes current foldback to help further

limit load current when the output is shorted to ground.

The foldback circuit is active even when the overload

shutdown latch described above is overridden. If the

outputfallsbelow70%ofitsnominaloutputlevel,thenthe

maximum sense voltage is progressively lowered from

75mV to 25mV. Under short-circuit conditions with very

low duty cycles, the LTC3728 will begin cycle skipping in

order to limit the short-circuit current. In this situation the

bottom MOSFET will be dissipating most of the power but

less than in normal operation. The short-circuit ripple

current is determined by the minimum on-time t_ON(MIN)of

the LTC3728 (less than 200ns), the input voltage and

inductor value:

Phase-Locked Loop and Frequency Synchronization

The LTC3728 has a phase-locked loop comprised of an

internal voltage controlled oscillator and phase detector.

This allows the top MOSFET turn-on to be locked to the

rising edge of an external source. The frequency range of

the voltage controlled oscillator is ±50% around the

center frequency f_O. A voltage applied to the PLLFLTR pin

of 1.2V corresponds to a frequency of approximately

400kHz. The nominal operating frequency range of the

LTC3728 is 250kHz to 550kHz.

∆I_L(SC)= t_ON(MIN)(V_IN/L)

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The phase detector used is an edge sensitive digital type

which provides zero degrees phase shift between the

external and internal oscillators. This type of phase detec-

tor will not lock up on input frequencies close to the

harmonics of the VCO center frequency. The PLL hold-in

range, ∆f_H, is equal to the capture range, ∆f_C:

Minimum On-Time Considerations

Minimum on-time t_ON(MIN)is the smallest time duration

thattheLTC3728iscapableofturningonthetopMOSFET.

It is determined by internal timing delays and the gate

chargerequiredtoturnonthetopMOSFET.Lowdutycycle

applications may approach this minimum on-time limit

and care should be taken to ensure that

∆f_H= ∆f_C= ±0.5 f_O(250kHz-550kHz)

The output of the phase detector is a complementary pair

of current sources charging or discharging the external

filter network on the PLLFLTR pin.

V_OUT

V (f)

IN

t_ON(MIN)

<

If the external frequency (f_PLLIN) is greater than the oscil-

lator frequency f_0SC, current is sourced continuously,

pulling up the PLLFLTR pin. When the external frequency

is less than f_0SC, current is sunk continuously, pulling

down the PLLFLTR pin. If the external and internal fre-

quencies are the same but exhibit a phase difference, the

currentsourcesturnonforanamountoftimecorrespond-

ing to the phase difference. Thus the voltage on the

PLLFLTR pin is adjusted until the phase and frequency of

the external and internal oscillators are identical. At this

stable operating point the phase comparator output is

open and the filter capacitor C_LPholds the voltage. The

LTC3728 PLLIN pin must be driven from a low impedance

source such as a logic gate located close to the pin. When

using multiple LTC3728’s (or LTC3729’s, as shown in

Figure 14) for a phase-locked system, the PLLFLTR pin of

the master oscillator should be biased at a voltage that will

guarantee the slave oscillator(s) ability to lock onto the

master’s frequency. A DC voltage of 0.7V to 1.7V applied

to the master oscillator’s PLLFLTR pin is recommended in

order to meet this requirement. The resultant operating

frequency can range from 300kHz to 470kHz.

Ifthedutycyclefallsbelowwhatcanbeaccommodatedby

the minimum on-time, the LTC3728 will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

The minimum on-time for the LTC3728 is approximately

100ns. However, as the peak sense voltage decreases the

minimum on-time gradually increases up to about 150ns.

This is of particular concern in forced continuous applica-

tions with low ripple current at light loads. If the duty cycle

drops below the minimum on-time limit in this situation,

a significant amount of cycle skipping can occur with

correspondingly larger current and voltage ripple.

FCB Pin Operation

The FCB pin can be used to regulate a secondary winding

or as a logic level input. Continuous operation is forced on

both controllers when the FCB pin drops below 0.8V.

During continuous mode, current flows continuously in

the transformer primary. The secondary winding(s) draw

current only when the bottom, synchronous switch is on.

When primary load currents are low and/or the V_IN/V_OUT

ratio is low, the synchronous switch may not be on for a

sufficient amount of time to transfer power from the

outputcapacitortothesecondaryload.Forcedcontinuous

operationwillsupportsecondarywindingsprovidingthere

is sufficient synchronous switch duty factor. Thus, the

FCB input pin removes the requirement that power must

be drawn from the inductor primary in order to extract

The loop filter components (C_LP, R_LP) smooth out the

current pulses from the phase detector and provide a

stable input to the voltage controlled oscillator. The filter

components C_LPand R_LPdetermine how fast the loop

acquires lock. Typically R_LP=10kΩ and C_LPis 0.01µF to

0.1µF.

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power from the auxiliary windings. With the loop in

continuous mode, the auxiliary outputs may nominally be

loaded without regard to the primary output load.

loop is reduced depending upon the maximum load step

specifications. Voltage positioning can easily be added to

the LTC3728 by loading the I_THpin with a resistive divider

having a Thevenin equivalent voltage source equal to the

midpoint operating voltage range of the error amplifier, or

1.2V (see Figure 8).

The secondary output voltage V_SECis normally set as

shown in Figure 6a by the turns ratio N of the transformer:

V_SEC≅ (N + 1) V_OUT

The resistive load reduces the DC loop gain while main-

taining the linear control range of the error amplifier. The

maximum output voltage deviation can theoretically be

reduced to half or alternatively the amount of output

capacitance can be reduced for a particular application. A

complete explanation is included in Design Solutions 10.

(See www.linear-tech.com)

However, if the controller goes into Burst Mode operation

and halts switching due to a light primary load current,

then V_SECwill droop. An external resistive divider from

V_SECto the FCB pin sets a minimum voltage V_SEC(MIN)

:

⎛

⎞

R6

R5

V_SEC(MIN)≈ 0.8V 1+

⎜

⎟

⎝

⎠

INTV

CC

where R5 and R6 are shown in Figure 2.

R

T2

T1

I

If V_SECdrops below this level, the FCB voltage forces

temporary continuous switching operation until V_SECis

again above its minimum.

TH

LTC3728

R

C

3728 F08

In order to prevent erratic operation if no external connec-

tions are made to the FCB pin, the FCB pin has a 0.18µA

internal current source pulling the pin high. Include this

current when choosing resistor values R5 and R6.

Figure 8. Active Voltage Positioning

Applied to the LTC3728

Efficiency Considerations

The following table summarizes the possible states avail-

able on the FCB pin:

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can be

expressed as:

Table 1

FCB Pin

Condition

0V to 0.75V

Forced Continuous Both Controllers

(Current Reversal Allowed—

Burst Inhibited)

0.85V < V < 4.0V

Minimum Peak Current Induces

Burst Mode Operation

FCB

%Efficiency = 100% – (L1 + L2 + L3 + ...)

No Current Reversal Allowed

whereL1, L2, etc. aretheindividuallossesasapercentage

of input power.

Feedback Resistors

>4.8V

Regulating a Secondary Winding

Burst Mode Operation Disabled

Constant Frequency Mode Enabled

No Current Reversal Allowed

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC3728 circuits: 1) LTC3728 V_INcurrent (in-

cluding loading on the 3.3V internal regulator), 2) INTV_CC

regulator current, 3) I²R losses, 4) Topside MOSFET

transition losses.

No Minimum Peak Current

Voltage Positioning

Voltage positioning can be used to minimize peak-to-peak

output voltage excursions under worst-case transient

loading conditions. The open-loop DC gain of the control

1. The V_INcurrent has two components: the first is the DC

supply current given in the Electrical Characteristics table,

3728fb

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APPLICATIO S I FOR ATIO

U

which excludes MOSFET driver and control currents; the

second is the current drawn from the 3.3V linear regulator

output.V_INcurrenttypicallyresultsinasmall(<0.1%)loss.

4. Transition losses apply only to the topside MOSFET(s),

and become significant only when operating at high input

voltages (typically 15V or greater). Transition losses can

be estimated from:

2. INTV_CCcurrent is the sum of the MOSFET driver and

control currents. The MOSFET driver current results from

switching the gate capacitance of the power MOSFETs.

Each time a MOSFET gate is switched from low to high to

low again, a packet of charge dQ moves from INTV_CCto

ground. The resulting dQ/dt is a current out of INTV_CCthat

is typically much larger than the control circuit current. In

continuous mode, I_GATECHG=f(Q_T+Q_B), where Q_Tand Q_B

are the gate charges of the topside and bottom side

MOSFETs.

2

Transition Loss = (1.7) V_INI_O(MAX)C_RSS

f

Other “hidden” losses such as copper trace and internal

battery resistances can account for an additional 5% to

10% efficiency degradation in portable systems. It is very

important to include these “system” level losses during

the design phase. The internal battery and fuse resistance

losses can be minimized by making sure that C_INhas

adequate charge storage and very low ESR at the switch-

ing frequency. A 25W supply will typically require a mini-

mum of 20µF to 40µF of capacitance having a maximum

of20mΩto50mΩofESR.TheLTC37282-phasearchitec-

ture typically halves this input capacitance requirement

overcompetingsolutions.OtherlossesincludingSchottky

conduction losses during dead-time and inductor core

losses generally account for less than 2% total additional

loss.

SupplyingINTV_CCpowerthroughtheEXTV_CCswitchinput

from an output-derived source will scale the V_INcurrent

required for the driver and control circuits by a factor of

(Duty Cycle)/(Efficiency). For example, in a 20V to 5V

application, 10mA of INTV_CCcurrent results in approxi-

mately2.5mAofV_INcurrent. Thisreducesthemid-current

loss from 10% or more (if the driver was powered directly

from V_IN) to only a few percent.

Checking Transient Response

3. I²R losses are predicted from the DC resistances of the

fuse (if used), MOSFET, inductor, current sense resistor,

and input and output capacitor ESR. In continuous mode

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, V_OUTshifts by an

amount equal to ∆I_LOAD(ESR), where ESR is the effective

series resistance of C_OUT. ∆I_LOADalso begins to charge or

discharge C_OUTgenerating the feedback error signal that

forces the regulator to adapt to the current change and

return V_OUTto its steady-state value. During this recovery

time V_OUTcan be monitored for excessive overshoot or

ringing, which would indicate a stability problem. OPTI-

LOOP compensation allows the transient response to be

optimized over a wide range of output capacitance and

ESR values. The availability of the I_THpin not only allows

optimization of control loop behavior but also provides a

DC coupled and AC filtered closed loop response test

point. The DC step, rise time and settling at this test point

truly reflects the closed loop response. Assuming a pre-

dominantly second order system, phase margin and/or

damping factor can be estimated using the percentage of

the average output current flows through L and R_SENSE

,

but is “chopped” between the topside MOSFET and the

synchronous MOSFET. If the two MOSFETs have approxi-

mately the same R_DS(ON), then the resistance of one

MOSFET can simply be summed with the resistances of L,

R_SENSEand ESR to obtain I²R losses. For example, if each

R_DS(ON)= 30mΩ, R_L= 50mΩ, R_SENSE= 10mΩ and R_ESR

= 40mΩ (sum of both input and output capacitance

losses), then the total resistance is 130mΩ. This results in

losses ranging from 3% to 13% as the output current

increases from 1A to 5A for a 5V output, or a 4% to 20%

loss for a 3.3V output. Efficiency varies as the inverse

square of V_OUTfor the same external components and

output power level. The combined effects of increasingly

lower output voltages and higher currents required by

high performance digital systems is not doubling but

quadrupling the importance of loss terms in the switching

regulator system!

3728fb

23

LTC3728

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APPLICATIO S I FOR ATIO

overshoot seen at this pin. The bandwidth can also be

estimated by examining the rise time at the pin. The I_TH

external components shown in the Figure 1 circuit will

provide an adequate starting point for most applications.

approximately 25 • C_LOAD. Thus a 10µF capacitor would

require a 250µs rise time, limiting the charging current to

about 200mA.

Automotive Considerations: Plugging into the

Cigarette Lighter

The I_THseries R_C-C_Cfilter sets the dominant pole-zero

loop compensation. The values can be modified slightly

(from 0.5 to 2 times their suggested values) to optimize

transient response once the final PC layout is done and the

particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80% of

full-load current having a rise time of 1µs to 10µs will

produce output voltage and I_THpin waveforms that will

give a sense of the overall loop stability without breaking

the feedback loop. Placing a power MOSFET directly

across the output capacitor and driving the gate with an

appropriate signal generator is a practical way to produce

a realistic load step condition. The initial output voltage

step resulting from the step change in output current may

not be within the bandwidth of the feedback loop, so this

signal cannot be used to determine phase margin. This is

why it is better to look at the I_THpin signal which is in the

feedback loop and is the filtered and compensated control

loop response. The gain of the loop will be increased by

increasing R_Cand the bandwidth of the loop will be

increased by decreasing C_C. If R_Cis increased by the same

factor that C_Cis decreased, the zero frequency will be kept

the same, thereby keeping the phase shift the same in the

most critical frequency range of the feedback loop. The

outputvoltagesettlingbehaviorisrelatedtothestabilityof

the closed-loop system and will demonstrate the actual

overall supply performance.

As battery-powered devices go mobile, there is a natural

interest in plugging into the cigarette lighter in order to

conserveorevenrechargebatterypacksduringoperation.

But before you connect, be advised: you are plugging into

thesupplyfromhell. Themainpowerlineinanautomobile

is the source of a number of nasty potential transients,

including load-dump, reverse-battery, and double-bat-

tery.

Load-dump is the result of a loose battery cable. When the

cablebreaksconnection,thefieldcollapseinthealternator

can cause a positive spike as high as 60V which takes

several hundred milliseconds to decay. Reverse-battery is

just what it says, while double-battery is a consequence of

tow-truck operators finding that a 24V jump start cranks

cold engines faster than 12V.

ThenetworkshowninFigure9isthemoststraightforward

approach to protect a DC/DC converter from the ravages

of an automotive power line. The series diode prevents

current from flowing during reverse-battery, while the

transient suppressor clamps the input voltage during

load-dump. Note that the transient suppressor should not

conduct during double-battery operation, but must still

clamptheinputvoltagebelowbreakdownoftheconverter.

Although the LTC3728 has a maximum input voltage of

36V, most applications will be limited to 30V by the

MOSFET BVDSS.

A second, more severe transient is caused by switching in

loads with large (>1µF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

with C_OUT, causing a rapid drop in V_OUT. No regulator can

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

C_LOADto C_OUTis greater than1:50, the switch rise time

should be controlled so that the load rise time is limited to

50A I RATING

PK

V

IN

12V

LTC3728

TRANSIENT VOLTAGE

SUPPRESSOR

GENERAL INSTRUMENT

1.5KA24A

3728 F09

Figure 9. Automotive Application Protection

3728fb

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LTC3728

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APPLICATIO S I FOR ATIO

U

Design Example

Choosing 1% resistors; R1 = 25.5k and R2 = 32.4k yields

an output voltage of 1.816V.

As a design example for one channel, assume V_IN

=

12V(nominal), V_IN= 22V(max), V_OUT= 1.8V, I_MAX= 5A,

and f = 300kHz.

The power dissipation on the top side MOSFET can be

easily estimated. Choosing a Siliconix Si4412DY results

in; R_DS(ON)= 0.042Ω, C_RSS= 100pF. At maximum input

voltage with T(estimated) = 50°C:

Theinductancevalueischosenfirstbasedona30%ripple

current assumption. The highest value of ripple current

occursatthemaximuminputvoltage. TiethePLLFLTRpin

to a resistive divider using the INTV_CCpin generating 1V

for 300kHz operation. The minimum inductance for 30%

ripple current is:

1.8V

22V

P_MAIN

=

(

5 ²1+ (0.005)(50°C – 25°C)

( )

[

]

2

0.042Ω + 1.7 22V 5A 100pF 300kHz

)

(

) ( )( )(

)

= 220mW

⎛

⎞

V_OUT

(f)(L)

V_OUT

V

IN

∆I_L=

1–

⎜

⎟

Ashort-circuittogroundwillresultinafoldedbackcurrent

of:

⎝

⎠

A 4.7µH inductor will produce 23% ripple current and a

3.3µH will result in 33%. The peak inductor current will be

the maximum DC value plus one half the ripple current, or

5.84A, for the 3.3µH value. Increasing the ripple current

will also help ensure that the minimum on-time of 100ns

is not violated. The minimum on-time occurs at maximum

V_IN:

⎛

⎞

25mV 1 200ns(22V)

I_SC

=

+

= 3.2A

⎜

⎟

0.01Ω

2

3.3µH

⎝

⎠

with a typical value of R_DS(ON)and δ = (0.005/°C)(20) =

0.1. TheresultingpowerdissipatedinthebottomMOSFET

is:

2

22V – 1.8V

22V

= 434mW

V_OUT

1.8V

P

SYNC

=

3.2A 1.1 0.042Ω

(

) ( )(

)

t_ON(MIN)

=

= 273ns

V

_IN(MAX)f 22V(300kHz)

The R_SENSEresistor value can be calculated by using the

maximum current sense voltage specification with some

accommodation for tolerances:

which is less than under full-load conditions.

C_INis chosen for an RMS current rating of at least 3A at

temperature assuming only this channel is on. C_OUTis

chosen with an ESR of 0.02Ω for low output ripple. The

output ripple in continuous mode will be highest at the

maximum input voltage. The output voltage ripple due to

ESR is approximately:

60mV

5.84A

R_SENSE

≤

≈ 0.01Ω

Since the output voltage is below 2.4V the output resistive

divider will need to be sized to not only set the output

voltage but also to absorb the SENSE pins specified input

current.

V

_ORIPPLE= R_ESR(∆I_L) = 0.02Ω(1.67A) = 33mV_P–P

⎛

⎞

0.8V

R1

= 24k

(MAX)

⎜

⎟

2.4V – V

⎝

⎠

OUT

⎛

⎞

0.8V

2.4V – 1.8V

= 24K

= 32k

⎜

⎟

⎝

⎠

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LTC3728

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APPLICATIO S I FOR ATIO

PC Board Layout Checklist

2. Are the signal and power grounds kept separate? The

combined LTC3728 signal ground pin and the ground

return of C_INTVCCmust return to the combined C_OUT(–)

terminals. ThepathformedbythetopN-channelMOSFET,

Schottky diode and the C_INcapacitor should have short

leads and PC trace lengths. The output capacitor (–)

terminals should be connected as close as possible to the

(–) terminals of the input capacitor by placing the capaci-

tors next to each other and away from the Schottky loop

described above.

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC3728. These items are also illustrated graphically in

the layout diagram of Figure 10. The Figure 11 illustrates

the current waveforms present in the various branches of

the 2-phase synchronous regulators operating in the

continuous mode. Check the following in your layout:

1. Are the top N-channel MOSFETs M1 and M3 located

within 1cm of each other with a common drain connection

at C_IN? Do not attempt to split the input decoupling for the

two channels as it can cause a large resonant loop.

3. Do the LTC3728 V_OSENSEpins resistive dividers con-

nect to the (+) terminals of C_OUT? The resistive divider

must be connected between the (+) terminal of C_OUTand

R

PU

V

PULL-UP

(<7V)

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

PGOOD

RUN/SS1

PGOOD

TG1

L1

R

SENSE

D1

+

V

SENSE1

OUT1

3

–

SENSE1

SW1

R2

M1

M2

C

B1

R1

4

V

BOOST1

OSENSE1

5

PLLFLTR

PLLIN

FCB

V

IN

f

IN

6

C

OUT1

BG1

R

IN

7

C

IN

INTV

EXTV

CC

C

VIN

GND

LTC3728

8

I

INTV

TH1

CC

V

IN

C

INTVCC

9

SGND

PGND

BG2

OUT2

D2

10

11

12

13

14

3.3V

OUT

I

BOOST2

SW2

TH2

C

B2

M3

M4

L2

V

OSENSE2

–

R

R3

R4

SENSE

V

OUT2

SENSE2

TG2

+

RUN/SS2

3728 F10

Figure 10. LTC3728 Recommended Printed Circuit Layout Diagram

3728fb

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LTC3728

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APPLICATIO S I FOR ATIO

U

SW1

L1

R

SENSE1

V

OUT1

+

D1

C

OUT1

R

L1

V

IN

R

IN

+

C

IN

SW2

L2

R

SENSE2

V

OUT2

+

D2

C

OUT2

R

L2

BOLD LINES INDICATE

HIGH, SWITCHING

CURRENT LINES.

KEEP LINES TO A

MINIMUM LENGTH.

3728 F11

Figure 11. Branch Current Waveforms

signal ground. The R2 and R4 connections should not be

along the high current input feeds from the input

capacitor(s).

An additional 1µF ceramic capacitor placed immediately

next to the INTV_CCand PGND pins can help improve noise

performance substantially.

4. Are the SENSE ^–and SENSE⁺leads routed together

with minimum PC trace spacing? The filter capacitor

between SENSE⁺and SENSE^–should be as close as

possible to the IC. Ensure accurate current sensing with

Kelvin connections at the SENSE resistor.

6. Keep the switching nodes (SW1, SW2), top gate nodes

(TG1, TG2), and boost nodes (BOOST1, BOOST2) away

from sensitive small-signal nodes, especially from the

oppositeschannel’svoltageandcurrentsensingfeedback

pins. All of these nodes have very large and fast moving

signals and therefore should be kept on the “output side”

of the LTC3728 and occupy minimum PC trace area.

5. Is the INTV_CCdecoupling capacitor connected close to

the IC, between the INTV_CCand the power ground pins?

This capacitor carries the MOSFET drivers current peaks.

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LTC3728

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APPLICATIO S I FOR ATIO

7. Use a modified “star ground” technique: a low imped-

ance, large copper area central grounding point on the

same side of the PC board as the input and output

capacitors with tie-ins for the bottom of the INTV_CC

decoupling capacitor, the bottom of the voltage feedback

resistive divider and the SGND pin of the IC.

Short-circuit testing can be performed to verify proper

overcurrent latchoff, or 5µA can be provided to the RUN/

SS pin(s) by resistors from V_INto prevent the short-circuit

latchoff from occurring.

ReduceV_INfromitsnominalleveltoverifyoperationofthe

regulator in dropout. Check the operation of the under-

voltage lockout circuit by further lowering V_INwhile moni-

toring the outputs to verify operation.

PC Board Layout Debugging

Start with one controller on at a time. It is helpful to use a

DC-50MHz current probe to monitor the current in the

inductor while testing the circuit. Monitor the output

switching node (SW pin) to synchronize the oscilloscope

to the internal oscillator and probe the actual output

voltage as well. Check for proper performance over the

operating voltage and current range expected in the appli-

cation. The frequency of operation should be maintained

over the input voltage range down to dropout and until the

output load drops below the low current operation thresh-

old—typically 10% to 20% of the maximum designed

current level in Burst Mode operation.

Investigate whether any problems exist only at higher

output currents or only at higher input voltages. If prob-

lems coincide with high input voltages and low output

currents,lookforcapacitivecouplingbetweentheBOOST,

SW, TG, and possibly BG connections and the sensitive

voltage and current pins. The capacitor placed across the

current sensing pins needs to be placed immediately

adjacent to the pins of the IC. This capacitor helps to

minimize the effects of differential noise injection due to

high frequency capacitive coupling. If problems are en-

countered with high current output loading at lower input

voltages,lookforinductivecouplingbetweenC_IN,Schottky

and the top MOSFET components to the sensitive current

and voltage sensing traces. In addition, investigate com-

mon ground path voltage pickup between these compo-

nents and the SGND pin of the IC.

The duty cycle percentage should be maintained from

cycle to cycle in a well-designed, low noise PCB imple-

mentation. Variation in the duty cycle at a subharmonic

rate can suggest noise pickup at the current or voltage

sensing inputs or inadequate loop compensation. Over-

compensation of the loop can be used to tame a poor PC

layout if regulator bandwidth optimization is not required.

Only after each controller is checked for their individual

performance should both controllers be turned on at the

same time. A particularly difficult region of operation is

when one controller channel is nearing its current com-

parator trip point when the other channel is turning on its

topMOSFET. Thisoccursaround50%dutycycleoneither

channel due to the phasing of the internal clocks and may

cause minor duty cycle jitter.

An embarrassing problem, which can be missed in an

otherwise properly working switching regulator, results

when the current sensing leads are hooked up backwards.

Theoutputvoltageunderthisimproperhookupwillstillbe

maintained but the advantages of current mode control

will not be realized. Compensation of the voltage loop will

be much more sensitive to component selection. This

behavior can be investigated by temporarily shorting out

the current sensing resistor—don’t worry, the regulator

will still maintain control of the output voltage.

3728fb

28

LTC3728

U

TYPICAL APPLICATIO S

59k

1M

100k

MBRS1100T3

V

+

PULL-UP

33µF

25V

(<7V)

T1, 1:1.8

10µH

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

PGOOD

TG1

PGOOD

RUN/SS1

0.015Ω

V

0.1µF

OUT1

5V

+

SENSE1

3A; 4A PEAK

180pF

1000pF

3

8

LT1121

–

SW1

SENSE1

105k, 1%

5

20k

1%

M1

M2

0.1µF

D1

MBRM

140T3

ON/OFF

4

BOOST1

V

OSENSE1

3

2

1

220k

V

5

OUT3

V

IN

PLLFLTR

PLLIN

FCB

12V

120mA

6

150µF, 6.3V

PANASONIC SP

BG1

+

33pF

1µF

25V

10Ω

22µF

50V

100k

7

CMDSH-3TR

EXTV

CC

0.1µF

GND

LTC3728

8

INTV

CC

I

TH1

1µF

10V

15k

4.7µF

1000pF

9

180µF, 4V

PANASONIC SP

PGND

BG2

SGND

V

33pF

IN

7V TO

28V

CMDSH-3TR

10

11

12

13

14

3.3V

OUT

D2

MBRM

140T3

BOOST2

SW2

I

TH2

15k

0.1µF

M3

M4

V

OSENSE2

20k

1%

V

OUT2

3.3V

5A; 6A PEAK

–

TG2

SENSE2

63.4k

1%

0.01Ω

1000pF

L1

6.3µH

+

RUN/SS2

180pF

0.1µF

3728 F12

V

: 7V TO 28V

IN

: 5V, 3A/3.3V, 5A/12V, 120mA

OUT

SWITCHING FREQUENCY = 250kHz

MI, M2, M3, M4: NDS8410A

L1: SUMIDA CEP123-6R3MC

T1: 10µH 1:1.8 — DALE LPE6562-A262 GAPPED E-CORE OR BH ELECTRONICS #501-0657 GAPPED TOROID

Figure 12. LTC3728 High Efficiency Low Noise 5V/3A, 3.3V/5A, 12V/120mA Regulator

3728fb

29

LTC3728

U

TYPICAL APPLICATIO S

V

PULL-UP

(<7V)

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

L1

PGOOD

RUN/SS1

PGOOD

TG1

8µH

0.015Ω

V

0.1µF

OUT1

2

3

+

–

SENSE1

5V

3A; 4A PEAK

27pF

1000pF

105k

1%

SW1

20k

1%

0.1µF

4

V

BOOST1

OSENSE1

5

M1

PLLFLTR

PLLIN

FCB

V

IN

0.01µF

10k

1000pF

47µF

6.3V

6

f

SYNC

BG1

33pF

10Ω

22µF

50V

7

CMDSH-3TR

EXTV

INTV

CC

0.1µF

GND

LTC3728

8

I

TH1

1µF

10V

15k

4.7µF

220pF

9

SGND

PGND

BG2

56µF, 4V

V

33pF

IN

CMDSH-3TR

5.2V TO

28V

10

11

12

13

14

3.3V

OUT

I

BOOST2

SW2

TH2

15k

0.1µF

220pF

V

OSENSE2

20k

1%

M2

V

OUT2

–

3.3V

SENSE2

TG2

0.015Ω

63.4k

1%

3A; 4A PEAK

1000pF

L2

8µH

+

27pF

RUN/SS2

0.1µF

: 5.2V TO 28V

3728 F13

V

SWITCHING FREQUENCY = 250kHz TO 550kHz

MI, M2: FDS6982S

L1, L2: 8µH SUMIDA CEP1238R0MC

OUTPUT CAPACITORS: PANASONIC SP SERIES

IN

: 5V, 4A/3.3V, 4A

OUT

Figure 13. LTC3728 5V/4A, 3.3V/4A Regulator with External Frequency Synchronization

3728fb

30

LTC3728

U

PACKAGE DESCRIPTIO (For purposes of clarity, drawings are not to scale)

G Package

28-Lead Plastic SSOP (0.209)

(LTC DWG # 05-08-1640)

10.07 – 10.33*

(0.397 – 0.407)

5.20 – 5.38**

(0.205 – 0.212)

1.73 – 1.99

(0.068 – 0.078)

28 27 26 25 24 23 22 21 20 19 18

16 15

17

0° – 8°

7.65 – 7.90

(0.301 – 0.311)

0.65

(0.0256)

BSC

0.13 – 0.22

0.55 – 0.95

(0.005 – 0.009)

(0.022 – 0.037)

0.05 – 0.21

(0.002 – 0.008)

0.25 – 0.38

(0.010 – 0.015)

NOTE: DIMENSIONS ARE IN MILLIMETERS

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.152mm (0.006") PER SIDE

**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE

G28 SSOP 1098

5

7

8

1

2

3

4

6

9

10 11 12 13 14

UH32 Package

32-Lead Plastic QFN (5mm × 5mm)

(Reference LTC DWG # 05-08-1693)

0.57 ±0.05

5.35 ±0.05

4.20 ±0.05

3.45 ±0.05

(4 SIDES)

PACKAGE OUTLINE

0.23 ± 0.05

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

BOTTOM VIEW—EXPOSED PAD

R = 0.115

TYP

0.75 ± 0.05

0.40 ± 0.10

5.00 ± 0.10

(4 SIDES)

31 32

0.00 – 0.05

PIN 1

TOP MARK

1

2

3.45 ± 0.10

(4-SIDES)

(UH) QFN 0102

0.200 REF

0.23 ± 0.05

0.50 BSC

NOTE:

1. DRAWING PROPOSED TO INCLUDE JEDEC PACKAGE OUTLINE

M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

3728fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.

31

LTC3728

U

TYPICAL APPLICATIO

I

IN

12V

IN

C

IN

I

1

I

*

IN

0°

BUCK: 2.5V/15A

OPEN

PHASMD TG1

180°

I

1

2

3

4

2.5V /30A

O

TG2

U1

LTC3729

I

90°

2

3

I

CLKOUT

I

1.5V /15A

O

90°

BUCK: 1.5V/15A

BUCK: 1.8V/15A

TG1

270°

1.8V /15A

O

TG2

LTC3728

U2

*INPUT RIPPLE CURRENT CANCELLATION

INCREASES THE RIPPLE FREQUENCY AND

REDUCES THE RMS INPUT RIPPLE CURRENT

THUS, SAVING INPUT CAPACITORS

I

90°

4

PLLIN

3728 F14

Figure 14. Multioutput PolyPhase Application

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COMMENTS

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Mobile Pentium^®III Processors, 550kHz,

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3.5V ≤ V ≤ 36V, VID Sets V

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OUT

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IN

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High Efficiency Synchronous Step-Down

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Output Fault Protection, 16-Pin SSOP

High Efficiency Synchronous Controller with 5-Bit Mobile Output Fault Protection, 24-Pin SSOP,

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IN

No R Current Mode Synchronous Step-Down

Up to 97% Efficiency, 4V ≤ V ≤ 36V, 0.8V ≤ V

≤ (0.9)(V ),

OUT IN

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I

up to 20A

OUT

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2-Phase Synchronous Controllers

Up to 42A, Uses All Surface Mount Components,

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IN

LTC3711

No R

Current Mode Synchronous Step-Down

Up to 97% Efficiency, Ideal for Pentium III Processors,

0.925V ≤ V ≤ 2V, 4V ≤ V ≤ 36V, I up to 20A

SENSE

Controller with Digital 5-Bit Interface

20A to 200A, 550kHz PolyPhase Synchronous Controller Expandable from 2-Phase to 12-Phase, Uses all Surface Mount

Components, V up to 36V

OUT

IN

OUT

LTC3729

IN

No R

and PolyPhase are trademarks of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation.

SENSE

3728fb

LT 0406 REV B • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

32

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3728EUH
厂家：	Linear
描述：	Dual, 550kHz, 2-Phase Synchronous Step-Down Switching Regulator 双通道， 550kHz的，两相同步降压型开关稳压器稳压器开关
文件：	总32页 (文件大小：672K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3728EUH [Linear]

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