LTC3736EUF-1#TRPBF [Linear]
LTC3736-1 - Dual 2-Phase, No RSENSE Synchronous Controller with Spread Spectrum; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C;
| 型号： | LTC3736EUF-1#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC3736-1 - Dual 2-Phase, No RSENSE Synchronous Controller with Spread Spectrum; Package: QFN; Pins: 24; Temperature Range: -40°C to 85°C 稳压器 开关式稳压器或控制器 电源电路 开关式控制器 |
| 文件： | 总28页 (文件大小：525K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3736-1
TM
Dual 2-Phase, No RSENSE
,
Synchronous Controller with
Spread Spectrum
U
FEATURES
DESCRIPTIO
The LTC®3736-1 is a 2-phase dual synchronous step-
down switching regulator controller with tracking that
drives external complementary power MOSFETs using
few external components. The constant frequency current
mode architecture with MOSFET VDS sensing eliminates
the need for sense resistors and improves efficiency.
Power loss and noise due to the ESR of the input capaci-
tance are minimized by operating the two controllers out
of phase.
■
Spread Spectrum Operation
■
Tracking Function
■
No Current Sense Resistors Required
■
Out-of-Phase Controllers Reduce Required
Input Capacitance
■
Wide VIN Range: 2.75V to 9.8V
■
Current Mode Operation
■
0.6V ±1.5% Voltage Reference
■
Low Dropout Operation: 100% Duty Cycle
■
Pulse Skipping Operation at Light Loads
A unique spread spectrum architecture randomly varies
the LTC3736-1’s switching frequency from 450kHz to
580kHz, significantly reducing the peak radiated and con-
ducted noise on both the input and output supplies,
making it easier to comply with electromagnetic interfer-
ence (EMI) standards.
■
Internal Soft-Start Circuitry
■
Power Good Output Voltage Monitor
■
Output Overvoltage Protection
■
Micropower Shutdown: IQ = 9µA
■
Tiny Low Profile (4mm × 4mm) QFN and Narrow
SSOP Packages
Pulse skipping operation provides high efficiency at light
loads.100%dutycyclecapabilityprovideslowdropoutop-
eration, extending operating time in battery-powered sys-
tems. The high switching frequencies allow for the use of
small surface mount inductors and capacitors.
U
APPLICATIO S
■
One or Two Lithium-Ion Powered Devices
■
Notebook and Palmtop Computers, PDAs
■
Portable Instruments
The LTC3736-1 is available in the low profile (0.75mm)
24-pin thermally enhanced (4mm × 4mm) QFN package
and 24-lead narrow SSOP packages.
■
Distributed DC Power Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
No RSENSE is a trademark of Linear Technology Corporation.
Protected by U.S. Patents including 5481178, 5929620, 6144194, 6580258, 6304066,
6611131, 6498466.
U
TYPICAL APPLICATIO
Output Voltage Frequency
Low Noise, 2-Phase, Dual Synchronous DC/DC Step-Down Converter
Spectrum
V
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
IN
FIGURE 13 CIRCUIT
SPREAD SPECTRUM
DISABLED
2.75V TO 9.8V
V
= 2.5V
= 30Hz
10µF
×2
OUT
BW
V
+
IN
R
+
SENSE1 SENSE2
SPREAD SPECTRUM
ENABLED
TG1
TG2
2.2µH
2.2µH
SW1
SW2
LTC3736-1
BG1
BG2
PGND
PGND
118k
187k
V
OUT1
2.5V
V
OUT2
1.8V
V
FB1
V
FB2
I
I
TH1
TH2
+
+
220pF
15k
220pF
59k
SGND
47µF
47µF
410k
450k
490k
530k
570k
610k
15k
59k
FREQUENCY (Hz)
37361 TA01b
37361 TA01a
37361f
1
LTC3736-1
W W
U W
ABSOLUTE AXI U RATI GS (Note 1)
Input Supply Voltage (VIN) ........................ –0.3V to 10V
TG1, TG2, BG1, BG2 Peak Output Current (<10µs) ..... 1A
Operating Temperature Range (Note 2) ... –40°C to 85°C
Storage Temperature Range .................. –65°C to 125°C
Junction Temperature (Note 3) ............................ 125°C
Lead Temperature (Soldering, 10 sec)
FREQ, RUN/SS, SSDIS,
TRACK, SENSE1+, SENSE2+,
IPRG1, IPRG2 Voltages................. –0.3V to (VIN + 0.3V)
V
FB1, VFB2, ITH1, ITH2 Voltages .................. –0.3V to 2.4V
SW1, SW2 Voltages ............ –2V to VIN + 1V or 10V Max
PGOOD ..................................................... –0.3V to 10V
(LTC3736EGN-1) .................................................. 300°C
U W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
NUMBER
ORDER PART
TOP VIEW
NUMBER
+
1
2
SENSE1
PGND
BG1
24
23
22
21
20
19
18
17
16
15
14
13
SW1
IPRG1
LTC3736EUF-1
LTC3736EGN-1
24 23 22 21 20 19
3
V
FB1
TH1
I
1
2
3
4
5
6
18 SSDIS
TH1
4
SSDIS
TG1
I
IPRG2
FREQ
SGND
TG1
17
16
5
IPRG2
FREQ
SGND
PGND
25
6
PGND
TG2
15 TG2
7
V
IN
14 RUN/SS
13 BG2
8
RUN/SS
BG2
V
IN
TRACK
UF PART MARKING
3736-1
9
TRACK
7
8
9 10 11 12
10
11
12
PGND
SENSE2
SW2
V
FB2
TH2
+
I
PGOOD
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
GN PACKAGE
24-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 37°C/W
EXPOSED PAD (PIN 25) IS PGND
MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 130°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loops
Input DC Supply Current
Normal Mode
Shutdown
(Note 4)
500
9
3
850
20
10
µA
µA
µA
RUN/SS = 0V
UVLO
V
IN
< UVLO Threshold
Undervoltage Lockout Threshold
V
IN
V
IN
Falling
Rising
●
●
1.95
2.15
2.25
2.45
2.55
2.75
V
V
Shutdown Threshold at RUN/SS
Start-Up Current Source
0.45
0.5
0.65
0.7
0.85
1
V
RUN/SS = 0V
µA
Regulated Feedback Voltage
0°C to 85°C (Note 5)
–40°C to 85°C
0.591
0.588
0.6
0.6
0.609
0.612
V
V
●
Output Voltage Line Regulation
2.75V < V < 9.8V (Note 5)
0.05
0.2
mV/V
IN
37361f
2
LTC3736-1
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Output Voltage Load Regulation
I
I
= 0.9V (Note 5)
= 1.7V
0.12
–0.12
0.5
–0.5
%
%
TH
TH
V
Input Current
(Note 5)
10
10
50
50
nA
nA
V
FB1,2
TRACK Input Current
TRACK = 0.6V
Measured at V
Overvoltage Protect Threshold
Overvoltage Protect Hysteresis
Top Gate (TG) Drive 1, 2 Rise Time
Top Gate (TG) Drive 1, 2 Fall Time
Bottom Gate (BG) Drive 1, 2 Rise Time
Bottom Gate (BG) Drive 1, 2 Fall Time
0.66
0.68
20
0.7
FB
mV
ns
ns
ns
ns
C = 3000pF
L
40
C = 3000pF
L
40
C = 3000pF
L
50
C = 3000pF
L
40
Maximum Current Sense Voltage
IPRG = Floating (Note 6)
IPRG = 0V
●
●
●
110
70
185
125
85
204
140
100
223
mV
mV
mV
+
(SENSE – SW)(∆V
)
SENSE(MAX)
IPRG = V
IN
Soft-Start Time
Time for V to Ramp from 0.05V to 0.55V
0.667
0.833
1
ms
FB1
Spread Spectrum Oscillator
Oscillator Frequency
Spread Spectrum Disabled (SSDIS = V )
IN
V
FREQ
V
FREQ
V
FREQ
= Floating
= 0V
●
●
●
480
260
650
550
300
750
600
340
825
kHz
kHz
kHz
= V
IN
Spread Spectrum Frequency Range
SSDIS = GND
Minimum Switching Frequency
Maximum Switching Frequency
450
580
kHz
kHz
PGOOD Output
PGOOD Voltage Low
PGOOD Trip Level
I
Sinking 1mA
125
mV
PGOOD
V
with Respect to Set Output Voltage
FB
V
FB
V
FB
V
FB
V
FB
< 0.6V, Ramping Positive
< 0.6V, Ramping Negative
> 0.6V, Ramping Negative
> 0.6V, Ramping Positive
–13
–16
7
–10.0
–13.3
10.0
–7
–10
13
%
%
%
%
10
13.3
16
Note 4: Dynamic supply current is higher due to gate charge being
Note 1: Absolute Maximum Ratings are those values beyond which the life
delivered at the switching frequency.
of a device may be impaired.
Note 5: The LTC3736-1 is tested in a feedback loop that servos I to a
Note 2: The LTC3736E-1 is guaranteed to meet specified performance
from 0°C to 70°C. Specifications over the –40°C to 85°C operating range
are assured by design, characterization and correlation with statistical
process controls.
TH
specified voltage and measures the resultant V voltage.
FB
Note 6: Peak current sense voltage is reduced dependent on duty cycle to
a percentage of value as shown in Figure 2.
Note 3: T is calculated from the ambient temperature T and power
J
A
dissipation P according to the following formula:
D
T = T + (P • θ °C/W)
J
A
D
JA
37361f
3
LTC3736-1
TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise noted.
U W
Efficiency and Power Lost vs
Load Current
Load Step
Load Step
(Spread Spectrum Enabled)
(Spread Spectrum Disabled)
10
1
100
95
90
85
80
75
70
65
60
55
50
FIGURE 13 CIRCUIT
V
IN
= 5V
V
V
OUT
OUT
AC-COUPLED
100mV/DIV
AC-COUPLED
100mV/DIV
0.1
I
I
L
L
2A/DIV
2A/DIV
0.01
0.001
V
V
I
= 3.3V
100µs/DIV
37361 G02
V
V
I
= 3.3V
100µs/DIV
37361 G03
IN
OUT
IN
OUT
= 1.8V
= 300mA TO 3A
= 1.8V
= 300mA TO 3A
V
V
= 2.5V
= 1.8V
OUT
OUT
LOAD
LOAD
SSDIS = GND
SSDIS = V
IN
1
10
100
1000
10000
FIGURE 15 CIRCUIT
FIGURE 15 CIRCUIT
LOAD CURRENT (mA)
37361 G01
Tracking Start-Up with Internal
Soft-Start (CSS = 0µF)
Input Voltage Noise
(Spread Spectrum Disabled)
Input Voltage Noise
(Spread Spectrum Enabled)
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–10
FIGURE 13 CIRCUIT
FIGURE 13 CIRCUIT
V
OUT1
V
V
= 5V
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
V
V
= 5V
IN
IN
2.5V
= 2.5V
= 30Hz
= 2.5V
= 30Hz
OUT
OUT
V
1.8V
R
R
OUT2
BW
BW
SSDIS = GND
SSDIS = V
IN
500mV/
DIV
V
= 5V
LOAD1
200µs/DIV
= 1Ω
37361 G06
IN
R
= R
LOAD2
SSDIS = GND
FIGURE 15 CIRCUIT
410k
450k
490k
530k
570k
610k
410k
450k
490k
530k
570k
610k
FREQUENCY (Hz)
FREQUENCY (Hz)
37361 G05
37361 G04
Tracking Start-Up with External
Soft-Start (CSS = 0.15µF)
Oscillator Frequency
vs Input Voltage
Output Voltage Ripple
5
4
SSDIS = V
IN
V
OUT1
OUT2
SSDIS = V
IN
2.5V
CONSTANT
550kHz
3
V
1.8V
OPERATION
2
500mV/
DIV
50mV/DIV
AC-COUPLED
1
0
SSDIS = GND
SPREAD
SPECTRUM
–1
–2
–3
–4
–5
V
= 5V
40ms/DIV
37361 G07
1µs/DIV
FIGURE 15 CIRCUIT
ENVELOPE OF 100 SAMPLES
37361 G20
IN
R
= R
IN
= 1Ω
LOAD1
SSDIS = V
FIGURE 15 CIRCUIT
LOAD2
2
6
8
9
3
4
5
7
10
INPUT VOLTAGE (V)
37361 G08
37361f
4
LTC3736-1
TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise noted.
U W
Maximum Current Sense Voltage
vs ITH Pin Voltage
Efficiency and Power Lost vs
Load Current
Efficiency vs Load Current
10
1
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
100
80
60
40
20
0
FIGURE 13 CIRCUIT
FIGURE 13 CIRCUIT
V
= 2.5V
V
V
= 2.5V
OUT
OUT
= 5V
IN
0.1
0.01
0.001
V
V
V
V
= 5V
IN
IN
IN
IN
= 3.3V
= 4.2V
= 7.2V
SPREAD SPECTRUM
CONSTANT 550kHz
–20
0.5
1
1.5
VOLTAGE (V)
2
1
10
100
1000
10000
1
10
100
1000
10000
I
TH
LOAD CURRENT (mA)
LOAD CURRENT (mA)
37361 G10
37361 G19
37361 G09
Regulated Feedback Voltage
vs Temperature
Shutdown (RUN) Threshold
vs Temperature
RUN/SS Pull-Up Current
vs Temperature
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.609
0.607
0.605
0.603
0.601
0.599
0.597
0.595
0.593
0.591
40 60
–60 –40 –20
TEMPERATURE (°C)
–60
20
TEMPERATURE (°C)
60 80
0
20
80 100
20 40
–60 –40 –20
TEMPERATURE (°C)
–40 –20
0
40
100
0
60 80 100
37361 G12
37361 G13
37361 G11
Maximum Current Sense Threshold
vs Temperature
Oscillator Frequency
vs Temperature
Undervoltage Lockout Threshold
vs Temperature
10
8
135
130
125
120
2.50
2.45
2.40
2.35
2.30
2.25
2.20
2.15
2.10
I
= FLOAT
SSDIS = V
IN
PRG
V
RISING
IN
6
4
2
0
V
FALLING
IN
–2
–4
–6
–8
–10
115
–60 –40 –20
0
20 40 60 80 100
–60
20
TEMPERATURE (°C)
60 80
–40 –20
0
40
100
20 40
–60 –40 –20
0
60 80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
37361 G14
37361 G15
37361 G16
37361f
5
LTC3736-1
TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise noted.
U W
Shutdown Quiescent Current
vs Input Voltage
RUN/SS Start-Up Current
vs Input Voltage
20
18
16
14
12
10
8
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
RUN/SS = 0V
RUN/SS = 0V
6
4
2
0
2
6
8
9
3
4
5
7
10
6
7
2
3
4
5
8
9
10
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
37361 G17
37361 G18
U
U
U
PI FU CTIO S
(UF/GN Package)
ITH1/ITH2 (Pins 1, 8/Pins 4, 11): Current Threshold and
Error Amplifier Compensation Point. Nominal operating
range on these pins is from 0.7V to 2V. The voltage on
these pins determines the threshold of the main current
comparator.
R = 10Ω, C = 1µF) is suggested to minimize noise pickup,
especially in high load current applications.
TRACK (Pin 6/Pin 9): Tracking Input for Second Control-
ler. Allows the start-up of VOUT2 to “track” that of VOUT1
according to a ratio established by a resistor divider on
VOUT1 connected to the TRACK pin. For one-to-one track-
ing of VOUT1 and VOUT2 during start-up, a resistor divider
with a ratio equal to those connected to VFB2 from VOUT2
FREQ (Pin 3/Pin 6): Frequency Filter and Adjust Pin. Nor-
mally,whenspreadspectrumoperationisenabled(SSDIS
= GND), a capacitor (1nF to 4.7nF) is connected from this
pin to SGND or VIN to filter and smooth the changes in fre-
quency of the LTC3736-1’s internal oscillator.
should be used to connect to TRACK from VOUT1
.
PGOOD(Pin 9/Pin 12): Power Good Output Voltage Moni-
tor Open-Drain Logic Output. This pin is pulled to ground
when the voltage on either feedback pin (VFB1, VFB2) is not
within ±13.3% of its nominal set point.
Whenspreadspectrumoperationisdisabled(SSDIS=VIN),
thispinservesasafrequencyadjustpin.Inthismode,tying
this pin to GND selects 300kHz operation; tying this pin to
VIN selects 750kHz operation; floating this pin selects
550kHz operation.
PGND(Pins12,16,20,25/Pins15,19,23):PowerGround.
These pins serve as the ground connection for the gate
drivers and the negative input to the reverse current com-
parators.TheExposedPad(UFpackage)mustbesoldered
to PCB ground.
When spread spectrum operation is enabled (SSDIS =
GND),anexternalvoltagebetweenapproximately0.7Vand
1.5V may be applied to this pin to adjust (in an analog
manner) the LTC3736-1’s frequency.
RUN/SS (Pin 14/Pin 17): Run Control Input and Optional
ExternalSoft-StartInput.Forcingthispinbelow0.65Vshuts
down the chip (both channels). Driving this pin to VIN or
releasing this pin enables the chip, using the chip’s inter-
nalsoft-start.Anexternalsoft-startcanbeprogrammedby
connecting a capacitor between this pin and ground.
SGND(Pin4/Pin7):Small-SignalGround. Thispinserves
as the ground connection for most internal circuits.
VIN (Pin 5/Pin 8): Chip Signal Power Supply. This pin
powerstheentirechipexceptforthegatedrivers.Externally
filtering this pin with a lowpass RC network (e.g.,
37361f
6
LTC3736-1
U
U
U
PI FU CTIO S
(UF/GN Package)
TG1/TG2(Pins17,15/Pins20,18):Top(PMOS)GateDrive
Output.ThesepinsdrivethegatesoftheexternalP-channel
MOSFETs. ThesepinshaveanoutputswingfromPGNDto
SENSE+.
SW1/SW2(Pins22,10/Pins1,13):SwitchNodeConnec-
tiontoInductor. Alsothenegativeinputtodifferentialpeak
current comparator and an input to the reverse current
comparator. Normally connected to the drain of the exter-
nalP-channelMOSFETs,thedrainoftheexternalN-channel
MOSFET and the inductor.
SSDIS(Pin18/Pin21):SpreadSpectrumDisableInput.Tie
thispintoVIN todisablespreadspectrumoperation.Inthis
mode, the LTC3736-1 operates at a constant frequency
determined by the voltage on the FREQ pin. Tie this pin to
GND to enable spread spectrum operation.
IPRG1/IPRG2 (Pins 23, 2/Pins 2, 5): Three-State Pins to
SelectMaximumPeakSenseVoltageThreshold.Thesepins
select the maximum allowed voltage drop between the
SENSE+ and SW pins (i.e., the maximum allowed drop
across the external P-channel MOSFET) for each channel.
Tie to VIN, GND or float to select 204mV, 85mV or 125mV
respectively.
BG1/BG2(Pins19,13/Pins22,16):Bottom(NMOS)Gate
Drive Output. These pins drive the gates of the external N-
channel MOSFETs. These pins have an output swing from
PGND to SENSE+.
SENSE1+/SENSE2+ (Pins 21, 11/Pins 24, 14): Positive
Input to Differential Current Comparator. Also powers the
gate drivers. Normally connected to the source of the ex-
ternal P-channel MOSFET.
VFB1/VFB2(Pins24,7/Pins3,10):FeedbackPins.Receives
theremotelysensedfeedbackvoltageforitscontrollerfrom
an external resistor divider across the output.
Exposed Pad (Pin 25/NA): The exposed pad (UF Package)
must be soldered to the PCB ground.
U
U
W
FU CTIO AL DIAGRA
(Common Circuitry)
R
VIN
V
IN
(TO CONTROLLER 1, 2)
V
IN
C
VIN
UNDERVOLTAGE
LOCKOUT
VOLTAGE
REFERENCE
0.6V
REF
V
0.7µA
SHDN
RUN/SS
t
= 1ms
+
–
SEC
EXTSS
INTSS
SSDIS
FREQ
CLK1
CLK2
SPREAD
SPECTRUM
OSCILLATOR
SLOPE1
SLOPE2
SLOPE
COMP
–
V
FB1
UV1
UV2
PGOOD
OV1
SHDN
+
0.54V
IPRG1
IPRG2
MAXIMUM
IPROG1
37361 FD
+
–
OV2
SENSE VOLTAGE
SELECT
IPROG2
V
FB2
37361f
7
LTC3736-1
U
U
W
FU CTIO AL DIAGRA (Controller 1)
V
IN
+
SENSE1
TG1
C
IN
RS1
CLK1
S
R
Q
MP1
SWITCHING
LOGIC
PGND
SW1
BG1
ANTISHOOT
THROUGH
L1
AND
OV1
SC1
BLANKING
CIRCUIT
V
OUT1
+
SENSE1
C
OUT1
MN1
PGND
SKIP1
IREV1
SLOPE1
–
+
SW1
ICMP
+
SENSE1
IPROG1
SHDN
–
R1B
R1A
V
FB1
+
–
EAMP
+
EXTSS
INTSS
0.6V
I
TH1
–
+
R
SKIP1
ITH1
0.12V
+
–
C
ITH1
SC1
SCP
V
FB1
0.15V
V
PGND
–
+
–
+
FB1
OV1
OVP
IREV1
RICMP
0.68V
SW1
37361 CONT1
IPROG1
37361f
8
LTC3736-1
U
U
W
FU CTIO AL DIAGRA (Controller 2)
V
IN
+
SENSE2
TG2
RS2
CLK2
S
R
Q
MP2
SWITCHING
LOGIC
PGND
SW2
BG2
ANTISHOOT
THROUGH
L2
AND
OV2
SC2
BLANKING
CIRCUIT
V
OUT2
+
SENSE2
C
OUT2
MN2
PGND
SKIP2
IREV2
SLOPE2
–
+
SW2
ICMP
+
SENSE2
SHDN
–
+
R2B
R2A
V
FB2
+
–
EAMP
V
OUT1
R
TRACKB
TRACKA
TRACK
0.6V
R
I
TH2
–
+
R
ITH2
SKIP2
0.12V
+
–
C
ITH2
SC2
0.15V
SCP
V
FB2
TRACK
V
PGND
SW2
–
+
–
+
FB2
OV2
OVP
IREV2
0.68V
37361 CONT2
IPROG2
37361f
9
LTC3736-1
U
(Refer to Functional Diagram)
OPERATIO
Main Control Loop
charged by the internal 0.7µA current source), the EAMP
regulates the VFB1 proportionally linearly from 0V to 0.6V.
The LTC3736-1 uses a current mode architecture with the
two controllers operating 180 degrees out of phase.
Duringnormaloperation,thetopexternalP-channelpower
MOSFET is turned on when the clock for that channel sets
the RS latch, and turned off when the current comparator
(ICMP) resets the latch. The peak inductor current at which
The start-up of VOUT2 is controlled by the voltage on the
TRACK pin. When the voltage on the TRACK pin is less
than the 0.6V internal reference, the LTC3736-1 regulates
the VFB2 voltage to the TRACK pin instead of the 0.6V
reference. Typically, a resistor divider on VOUT1 is con-
nected to the TRACK pin to allow the start-up of VOUT2 to
“track”thatofVOUT1.Forone-to-onetrackingduringstart-
up, the resistor divider would have the same ratio as the
ICMP resets the RS latch is determined by the voltage on
the ITH pin, which is driven by the output of the error
amplifier (EAMP). The VFB pin receives the output voltage
feedback signal from an external resistor divider. This
feedback signal is compared to the internal 0.6V reference
voltage by the EAMP. When the load current increases, it
causes a slight decrease in VFB relative to the 0.6V refer-
ence, which in turn causes the ITH voltage to increase until
the average inductor current matches the new load cur-
rent. While the top P-channel MOSFET is off, the bottom
N-channel MOSFET is turned on until either the inductor
current starts to reverse, as indicated by the current
reversal comparator, IRCMP, or the beginning of the next
cycle.
divider on VOUT2 that is connected to VFB2
.
Light Load Operation
The LTC3736-1 operates in PWM pulse skipping mode at
lightloads. Inthismode, thecurrentcomparatorICMP may
remain tripped for several cycles and force the external P-
channelMOSFETtostayoffforthesamenumberofcycles.
Theinductorcurrentisnotallowedtoreverse(discontinu-
ous operation). This mode exhibits low output ripple as
well as low audio noise and reduced RF interference, while
providing high light load efficiency.
Shutdown, Soft-Start and Tracking Start-Up
(RUN/SS and TRACK Pins)
Spread Spectrum Operation
Switching regulators can be particularily troublesome in
applications where electromagnetic interference (EMI) is
a concern. Switching regulators operate on a cycle-by-
cycle basis to transfer power to an output. In most cases,
the frequency of operation is either fixed or is a constant
based on the output load. This method of conversion
creates large components of noise at the frequency of
operation (fundamental) and multiples of the operating
frequency (harmonics). Figures 1a and 1b depict the
output noise spectrum of a conventional buck switching
converter(1/2ofLTC3736-1withspreadspectrumopera-
tion disabled) with VIN = 5V, VOUT = 2.5V and IOUT = 2A.
The LTC3736-1 is shut down by pulling the RUN/SS pin
low. In shutdown, all controller functions are disabled and
thechipdrawsonly9µA.TheTGoutputsareheldhigh(off)
and the BG outputs low (off) in shutdown. Releasing
RUN/SS allows an internal 0.7µA current source to charge
up the RUN/SS pin. When the RUN/SS pin reaches 0.65V,
the LTC3736-1’s two controllers are enabled.
The start-up of VOUT1 is controlled by the LTC3736-1’s
internal soft-start. During soft-start, the error amplifier
EAMP compares the feedback signal VFB1 to the internal
soft-startramp(insteadofthe0.6Vreference),whichrises
linearly from 0V to 0.6V in about 1ms. This allows the
output voltage to rise smoothly from 0V to its final value,
while maintaining control of the inductor current.
Unlike conventional buck converters, the LTC3736-1’s
internal oscillator is designed to produce a clock pulse
whose frequency is randomly varied between 450kHz and
580kHz. This has the benefit of spreading the switching
noiseoverarangeoffrequencies,thussignificantlyreduc-
ing the peak noise. Figures 1c and 1d show the output
noise spectrum of the LTC3736-1 (with spread spectrum
The 1ms soft-start time can be increased by connecting
the optional external soft-start capacitor CSS between the
RUN/SS and SGND pins. As the RUN/SS pin continues to
rise linearly from approximately 0.65V to 1.3V (being
37361f
10
LTC3736-1
U
(Refer to Functional Diagram)
OPERATIO
operation enabled) with VIN = 5V, VOUT = 2.5V and IOUT
=
Output Overvoltage Protection
1A. Note the significant reduction in peak output noise
(>20dBm).
As a further protection, the overvoltage comparator (OV)
guardsagainsttransientovershoots,aswellasothermore
serious conditions that may overvoltage the output. When
the feedback voltage on the VFB pin has risen 13.33%
above the reference voltage of 0.6V, the external P-chan-
nel MOSFET is turned off and the N-channel MOSFET is
turned on until the overvoltage is cleared.
Short-Circuit Protection
When an output is shorted to ground (VFB < 0.12V), the
switching frequency of that controller is reduced to 1/5 of
the normal operating frequency. The other controller is
unaffected and maintains normal operation.
Frequency Selection (FREQ Pin)
(Spread Spectrum Operation Disabled)
Theshort-circuitthresholdonVFB2 isbasedonthesmaller
of 0.12V and a fraction of the voltage on the TRACK pin.
This also allows VOUT2 to start up and track VOUT1 more
easily. Note that if VOUT1 is truly short-circuited
(VOUT1 = VFB1 = 0V), then the LTC3736-1 will try to
regulate VOUT2 to 0V if a resistor divider on VOUT1 is
connected to the TRACK pin.
TheswitchingfrequencyoftheLTC3736-1canbeselected
using the FREQ pin when spread spectrum operation is
disabled (SSDIS = VIN).
–10
–10
R
BW
= 30Hz
R
BW
= 3kHz
–20
–30
–20
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–100
–110
410k
450k
490k
530k
570k
610k
0
6M
12M
18M
24M
30M
FREQUENCY (Hz)
FREQUENCY (Hz)
37361 F01b
37361 F01a
Figure 1b. Zoom-In of Fundamental Frequency of Conventional
Buck Switching Converter
Figure 1a. Output Noise Spectrum of Conventional Buck
Switching Converter (LTC3736-1 with Spread Spectrum
Disabled) Showing Fundamental and Harmonic Frequencies
–10
–10
R
BW
= 3kHz
R
BW
= 30Hz
–20
–30
–20
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–100
–110
0
6M
12M
18M
24M
30M
410k
450k
490k
530k
570k
610k
FREQUENCY (Hz)
FREQUENCY (Hz)
37361 F01c
37361 F01d
Figure 1c. Output Noise Spectrum of the LTC3736-1 Spread
Spectrum Buck Switching Converter. Note the Reduction in
Fundamental and Harmonic Peak Spectral Amplitude
Compared to Figure 1a.
Figure 1d. Zoom-In of Fundamental Frequency of the
LTC3736-1 Spread Spectrum Switching Converter. Note the
>20dB Reduction in Peak Amplitude and Spreading of the
Frequency Spectrum (Between Approximately 450kHz and
580kHz) Compared to Figure 1b.
37361f
11
LTC3736-1
U
(Refer to Functional Diagram)
OPERATIO
maximum sense voltage allowed across the external
P-channel MOSFET is 125mV, 85mV or 204mV for the
three respective states of the IPRG pin. The peak sense
voltages for the two controllers can be independently
selected by the IPRG1 and IPRG2 pins.
The FREQ pin can be floated, tied to VIN or tied to SGND to
select 550kHz, 750kHz or 300kHz respectively.
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency operation
increasesefficiencybyreducingMOSFETswitchinglosses,
butrequireslargerinductanceand/orcapacitancetomain-
tain low output ripple voltage.
However, once the controller’s duty cycle exceeds 20%,
slope compensation begins and effectively reduces the
peak sense voltage by a scale factor given by the curve in
Figure 2.
Dropout Operation
When the input supply voltage (VIN) decreases towards
the output voltage, the rate of change of the inductor
current while the external P-channel MOSFET is on (ON
cycle)decreases.ThisreductionmeansthattheP-channel
MOSFET will remain on for more than one oscillator cycle
if the inductor current has not ramped up to the threshold
set by the EAMP on the ITH pin. Further reduction in the
input supply voltage will eventually cause the P-channel
MOSFET to be turned on 100%; i.e., DC. The output
voltage will then be determined by the input voltage minus
the voltage drop across the P-channel MOSFET and the
inductor.
110
100
90
80
70
60
50
40
30
20
10
0
0
10 20 30 40 50 60 70 80 90 100
DUTY CYCLE (%)
37361 F02
Undervoltage Lockout
Figure 2. Maximum Peak Current vs Duty Cycle
To prevent operation of the external MOSFETs below safe
inputvoltagelevels,anundervoltagelockoutisincorporated
in the LTC3736-1. When the input supply voltage (VIN)
dropsbelow2.3V,theexternalP-andN-channelMOSFETs
and all internal circuitry are turned off except for the und-
ervoltage block, which draws only a few microamperes.
Thepeakinductorcurrentisdeterminedbythepeaksense
voltage and the on-resistance of the external P-channel
MOSFET:
∆VSENSE(MAX)
IPK
=
RDS(ON)
Peak Current Sense Voltage Selection and Slope
Compensation (IPRG1 and IPRG2 Pins)
Power Good (PGOOD) Pin
When a controller is operating below 20% duty cycle, the
peak current sense voltage (between the SENSE+ and SW
pins) allowed across the external P-channel MOSFET is
determined by:
A window comparator monitors both feedback voltages
and the open-drain PGOOD output pin is pulled low when
either or both feedback voltages are not within ±10% of
the 0.6V reference voltage. PGOOD is low when the
LTC3736-1 is shut down or in undervoltage lockout.
A V – 0.7V
(
)
ITH
∆VSENSE(MAX)
=
2-Phase Operation
10
Why the need for 2-phase operation? Until recently, con-
stant frequency dual switching regulators operated both
controllers in phase (i.e., single phase operation). This
means that both topside MOSFETs (P-channel) are turned
37361f
where A is a constant determined by the state of the IPRG
pins. Floating the IPRG pin selects A = 1; tying IPRG to VIN
selects A = 5/3; tying IPRG to SGND selects A = 2/3. The
maximum value of VITH is typically about 1.98V, so the
12
LTC3736-1
U
(Refer to Functional Diagram)
OPERATIO
on at the same time, causing current pulses of up to twice
the amplitude of those from a single regulator to be drawn
from the input capacitor. These large amplitude pulses
increase the total RMS current flowing in the input capaci-
tor, requiring the use of larger and more expensive input
capacitors, and increase both EMI and power losses in the
input capacitor and input power supply.
operation would reduce the RMS input capacitor current
from 1.79ARMS to 0.91ARMS. While this is an impressive
reduction by itself, remember that power losses are pro-
portional to IRMS2, meaning that actual power wasted is
reduced by a factor of 3.86.
The reduced input ripple current also means that less
power is lost in the input power path, which could include
batteries, switches, trace/connector resistances, and pro-
tection circuitry. Improvements in both conducted and
radiated EMI also directly accrue as a result of the reduced
RMS input current and voltage. Significant cost and board
footprint savings are also realized by being able to use
smaller, less expensive, lower RMS current-rated input
capacitors.
With 2-phase operation, the two controllers of the
LTC3736-1 are operated 180 degrees out of phase. This
effectively interleaves the current pulses coming from the
topsideMOSFETswitches,greatlyreducingthetimewhere
they overlap and add together. The result is a significant
reductioninthetotalRMScurrent,whichinturnallowsthe
use of smaller, less expensive input capacitors, reduces
shielding requirements for EMI and improves real world
operating efficiency.
Of course, the improvement afforded by 2-phase opera-
tion is a function of the relative duty cycles of the two
controllers, which in turn are dependent upon the input
supply voltage. Figure 4 depicts how the RMS input
current varies for single phase and 2-phase dual control-
lers with 2.5V and 1.8V outputs over a wide input voltage
range.
Figure 3 shows qualitatively example waveforms for a
single phase dual controller versus a 2-phase LTC3736-1
system. In this case, 2.5V and 1.8V outputs, each drawing
a load current of 2A, are derived from a 7V (e.g., a 2-cell
Li-Ion battery) input supply. In this example, 2-phase
It can be readily seen that the advantages of 2-phase
operation are not limited to a narrow operating range, but
in fact extend over a wide region. A good rule of thumb for
mostapplicationsisthat2-phaseoperationwillreducethe
input capacitor requirement to that for just one channel
operating at maximum current and 50% duty cycle.
Single Phase
Dual Controller
2-Phase
Dual Controller
SW1 (V)
SW2 (V)
2.0
1.8
SINGLE PHASE
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
DUAL CONTROLLER
I
L1
2-PHASE
DUAL CONTROLLER
I
L2
V
V
= 2.5V/2A
= 1.8V/2A
OUT1
OUT2
I
IN
2
6
8
9
3
4
5
7
10
INPUT VOLTAGE (V)
37361 F03
37361 F04
Figure 4. RMS Input Current Comparison
Figure 3. Example Waveforms for a Single Phase
Dual Controller vs the 2-Phase LTC3736-1
37361f
13
LTC3736-1
W U U
U
APPLICATIO S I FOR ATIO
The typical LTC3736-1 application circuit is shown in
Figure 13. External component selection for each of the
LTC3736-1’s controllers is driven by the load requirement
and begins with the selection of the inductor (L) and the
power MOSFETs (MP and MN).
A reasonable starting point is setting ripple current IRIPPLE
to be 40% of IOUT(MAX). Rearranging the above equation
yields:
∆VSENSE(MAX)
5
6
RDS(ON)(MAX)
=
•
IOUT(MAX)
Power MOSFET Selection
for Duty Cycle < 20%.
Each of the LTC3736-1’s two controllers requires two
external power MOSFETs: a P-channel MOSFET for the
topside (main) switch and an N-channel MOSFET for the
bottom (synchronous) switch. Important parameters for
However, for operation above 20% duty cycle, slope
compensation has to be taken into consideration to select
the appropriate value of RDS(ON) to provide the required
amount of load current:
the power MOSFETs are the breakdown voltage VBR(DSS)
,
threshold voltage VGS(TH), on-resistance RDS(ON), reverse
transfer capacitance CRSS, turn-off delay tD(OFF) and the
total gate charge QG.
∆VSENSE(MAX)
IOUT(MAX)
5
6
R
DS(ON)(MAX) = • SF •
Thegatedrivevoltageistheinputsupplyvoltage.Sincethe
LTC3736-1 is designed for operation down to low input
voltages, a sublogic level MOSFET (RDS(ON) guaranteed at
VGS = 2.5V) is required for applications that work close to
this voltage. When these MOSFETs are used, make sure
that the input supply to the LTC3736-1 is less than the
absolute maximum MOSFET VGS rating, which is
typically 8V.
whereSFisascalefactorwhosevalueisobtainedfromthe
curve in Figure 1.
These must be further derated to take into account the
significant variation in on-resistance with temperature.
Thefollowingequationisagoodguidefordeterminingthe
required RDS(ON)MAX at 25°C (manufacturer’s specifica-
tion), allowing some margin for variations in the
LTC3736-1 and external component values:
The P-channel MOSFET’s on-resistance is chosen based
on the required load current. The maximum average
output load current IOUT(MAX) is equal to the peak inductor
∆VSENSE(MAX)
IOUT(MAX) • ρT
5
6
R
DS(ON)(MAX) = • 0.9 • SF •
current minus half the peak-to-peak ripple current IRIPPLE
.
The ρT is a normalizing term accounting for the tempera-
ture variation in on-resistance, which is typically about
0.4%/°C, as shown in Figure 5. Junction to case tempera-
ture TJC is about 10°C in most applications. For a maxi-
mum ambient temperature of 70°C, using ρ80°C ~ 1.3 in
the above equation is a reasonable choice.
The LTC3736-1’s current comparator monitors the drain-
to-source voltage VDS of the P-channel MOSFET, which is
sensed between the SENSE+ and SW pins. The peak
inductor current is limited by the current threshold, set by
the voltage on the ITH pin of the current comparator. The
voltage on the ITH pin is internally clamped, which limits
the maximum current sense threshold ∆VSENSE(MAX) to
approximately 125mV when IPRG is floating (85mV when
IPRG is tied low; 204mV when IPRG is tied high).
The power dissipated in the top and bottom MOSFETs
strongly depends on their respective duty cycles and load
current. When the LTC3736-1 is operating in continuous
mode, the duty cycles for the MOSFETs are:
The output current that the LTC3736-1 can provide is
given by:
VOUT
V
IN
TopP−ChannelDuty Cycle =
∆VSENSE(MAX)
IRIPPLE
IOUT(MAX)
=
–
RDS(ON)
2
V – VOUT
IN
BottomN−ChannelDuty Cycle =
V
IN
37361f
14
LTC3736-1
W U U
APPLICATIO S I FOR ATIO
U
less than 25nC to 30nC (at 4.5VGS) and a turn-off delay
(tD(OFF)) of less than approximately 140ns. However, due
to differences in test and specification methods of various
MOSFET manufacturers, and in the variations in QG and
tD(OFF)withgatedrive(VIN)voltage,theP-channelMOSFET
ultimately should be evaluated in the actual LTC3736-1
application circuit to ensure proper operation.
2.0
1.5
1.0
0.5
0
Shoot-through between the P-channel and N-channel
MOSFETs can most easily be spotted by monitoring the
input supply current. As the input supply voltage in-
creases,iftheinputsupplycurrentincreasesdramatically,
then the likely cause is shoot-through. Note that some
MOSFETsthatdonotworkwellathighinputvoltages(e.g.,
VIN > 5V) may work fine at lower voltages (e.g., 3.3V).
Table 1 shows a selection of P-channel MOSFETs from
different manufacturers that are known to work well in
LTC3736-1 applications.
50
100
–50
150
0
JUNCTION TEMPERATURE (°C)
37361 F05
Figure 5. RDS(ON) vs Temperature
The MOSFET power dissipations at maximum output
current are:
Selecting the N-channel MOSFET is typically easier, since
for a given RDS(ON), the gate charge and turn-on and turn-
off delays are much smaller than for a P-channel MOSFET.
VOUT
2
PTOP
=
=
•IOUT(MAX)2 •ρT •RDS(ON) + 2•V
IN
V
IN
•IOUT(MAX) •CRSS • fOSC
V – VOUT
Table 1. Selected P-Channel MOSFETs Suitable for LTC3736-1
Applications
P
BOT
•IOUT(MAX)2 •ρT •RDS(ON)
IN
PART
NUMBER
V
IN
MANUFACTURER
TYPE
PACKAGE
Si7540DP
Siliconix
Complementary
P/N
PowerPak
SO-8
Both MOSFETs have I2R losses and the PTOP equation
includesanadditionaltermfortransitionlosses,whichare
largest at high input voltages. The bottom MOSFET losses
are greatest at high input voltage or during a short circuit
when the bottom duty cycle is nearly 100%.
Si9801DY
FDW2520C
FDW2521C
Siliconix
Fairchild
Fairchild
Complementary
P/N
SO-8
Complementary
P/N
TSSOP-8
TSSOP-8
Complementary
P/N
The LTC3736-1 utilizes a nonoverlapping, antishoot-
through gate drive control scheme to ensure that the P-
and N-channel MOSFETs are not turned on at the same
time. To function properly, the control scheme requires
that the MOSFETs used are intended for DC/DC switching
applications. Many power MOSFETs, particularly P-chan-
nel MOSFETs, are intended to be used as static switches
and therefore are slow to turn on or off.
Si3447BDV
Si9803DY
FDC602P
Siliconix
Siliconix
Fairchild
Fairchild
Fairchild
Fairchild
Fairchild
Hitachi
Single P
Single P
Single P
Single P
Single P
Dual P
TSOP-6
SO-8
TSOP-6
TSOP-6
TSOP-6
TSSOP-8
SO-8
FDC606P
FDC638P
FDW2502P
FDS6875
Dual P
Reasonable starting criteria for selecting the P-channel
MOSFET are that it must typically have a gate charge (QG)
HAT1054R
NTMD6P02R2-D
Dual P
SO-8
On Semi
Dual P
SO-8
37361f
15
LTC3736-1
W U U
U
APPLICATIO S I FOR ATIO
Inductor Value Calculation
Operating Frequency
Given the desired input and output voltages, the inductor
value and operating frequency fOSC directly determine the
inductor’s peak-to-peak ripple current:
When spread spectrum operation is enabled (SSDIS =
GND), the frequency of the LTC3736-1 is randomly varied
overtherangeoffrequenciesbetween450kHzand580kHz.
Inthiscase,acapacitor(1nFto4.7nF)shouldbeconnected
betweentheFREQpinandSGND(orVIN)tosmoothoutthe
changes in frequency. This not only provides a smoother
frequency spectrum but also ensures that the switching
regulator remains stable by preventing abrupt changes
in frequency. A value of 2200pF is suitable in most
applications.
VOUT
V
IN
⎛
V
–
VOUT
⎞
IN
IRIPPLE
=
⎜
⎟
⎝ fOSC •L ⎠
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
Whenthespreadspectrumoperationisdisabled(SSDIS =
VIN), the LTC3736-1’s frequency may be selected from
amongthreediscrete,constantfrequenciesusingtheFREQ
pin. Floating the FREQ pin selects 550kHz operation; tying
this pin to VIN selects 750kHz, while tying this pin to GND
selects 300kHz. Table 2 summarizes the different states in
which the FREQ pin can be used.
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). Note that the largest ripple
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
Table 2
FREQ PIN
0V
V – VOUT VOUT
IN
SSDIS PIN
FREQUENCY
L ≥
•
V
300kHz
fOSC •IRIPPLE
V
IN
IN
Floating
V
V
550kHz
750kHz
IN
IN
V
Inductor Core Selection
IN
Capacitor to GND
GND
Spread Spectrum (450kHz to 580kHz)
Once the inductance value is determined, the type of
inductor must be selected. High efficiency converters
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of ferrite, molyper-
malloy or Kool Mµ® cores. Actual core loss is independent
of core size for a fixed inductor value, but it is very
dependent on inductance selected. As inductance in-
creases, core losses go down. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses will increase.
or V
IN
Notethatwhenspreadspectrumoperationisdisabled, the
LTC3736-1operateslikethestandard,constantfrequency
LTC3736, except that at light loads, the LTC3736-1 oper-
ates in pulse skipping mode. This mode is not available on
the LTC3736 unless the device is synchronized to an ex-
ternalclocksignalusingitsphase-lockedloop(PLL).Thus,
ifanLTC3736withpulseskippingfunctionisneeded, then
theLTC3736-1withspreadspectrumdisabledistheappro-
priate solution. Table 3 summarizes the key differences in
the available features on the LTC3736 and LTC3736-1.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design cur-
rent is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
Table 3
AVAILABLE FEATURES/OPTIONS
Selectable Constant Frequency
Spread Spectrum
LTC3736
LTC3736-1
Yes
Yes
No
Yes
Synchronizable (PLL)
Burst Mode®
Yes
No
Yes
Yes
No
Burst Mode is a registered trademark of Linear Technology Corporation.
Kool Mµ is a registered trademark of Magnetics, Inc.
Forced Continuous Mode
Pulse Skipping Mode
No
When Synchronized
Yes
37361f
16
LTC3736-1
W U U
APPLICATIO S I FOR ATIO
U
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
usedfordesignbecauseevensignificantdeviationsdonot
offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may be
paralleled to meet size or height requirements in the
design. Due to the high operating frequency of the
LTC3736-1, ceramic capacitors can also be used for CIN.
Always consult the manufacturer if there is any question.
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive
than ferrite. A reasonable compromise from the same
manufacturerisKoolMµ. Toroidsareveryspaceefficient,
especially when you can use several layers of wire.
Because they lack a bobbin, mounting is more difficult.
However, designs for surface mount are available which
do not increase the height significantly.
Schottky Diode Selection (Optional)
The Schottky diodes D1 and D2 in Figure 15 conduct
current during the dead time between the conduction of
the power MOSFETs . This prevents the body diode of the
bottom N-channel MOSFET from turning on and storing
charge during the dead time, which could cost as much as
1% in efficiency. A 1A Schottky diode is generally a good
size for most LTC3736-1 applications, since it conducts a
relatively small average current. Larger diodes result in
additional transition losses due to their larger junction
capacitance. This diode may be omitted if the efficiency
loss can be tolerated.
The benefit of the LTC3736-1 2-phase operation can be
calculatedbyusingtheequationaboveforthehigherpower
controller and then calculating the loss that would have
resulted if both controller channels switched on at the
same time. The total RMS power lost is lower when both
controllers are operating due to the reduced overlap of
currentpulsesrequiredthroughtheinputcapacitor’sESR.
This is why the input capacitor’s requirement calculated
above for the worst-case controller is adequate for the
dual controller design. Also, the input protection fuse re-
sistance,batteryresistance,andPCboardtraceresistance
losses are also reduced due to the reduced peak currents
in a 2-phase system. The overall benefit of a multiphase
design will only be fully realized when the source imped-
ance of the power supply/battery is included in the effi-
ciency testing. The sources of the P-channel MOSFETs
should be placed within 1cm of each other and share a
common CIN(s). Separating the sources and CIN may pro-
duce undesirable voltage and current resonances at VIN.
CIN and COUT Selection
The selection of CIN is simplified by the 2-phase architec-
ture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can
be shown that the worst-case capacitor RMS current
occurs when only one controller is operating. The control-
ler with the highest (VOUT)(IOUT) product needs to be used
in the formula below to determine the maximum RMS
capacitor current requirement. Increasing the output cur-
rent drawn from the other controller will actually decrease
the input RMS ripple current from its maximum value. The
out-of-phase technique typically reduces the input
capacitor’s RMS ripple current by a factor of 30% to 70%
when compared to a single phase power supply solution.
A small (0.1µF to 1µF) bypass capacitor between the chip
VIN pin and ground, placed close to the LTC3736-1, is also
suggested. A 10Ω resistor placed between CIN (C1) and
the VIN pin provides further isolation between the two
channels.
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle (VOUT)/(VIN). To
preventlargevoltagetransients, alowESRcapacitorsized
for the maximum RMS current of one channel must be
used. The maximum RMS capacitor current is given by:
The selection of COUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement is
satisfied, the capacitance is adequate for filtering. The
output ripple (∆VOUT) is approximated by:
⎛
1
⎞
1/2
]
IMAX
V
IN
∆VOUT ≈IRIPPLE ESR +
⎜
⎟
CIN RequiredIRMS
≈
V
OUT)(
V – V
IN OUT
(
[
)
⎝
8fCOUT
⎠
37361f
17
LTC3736-1
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APPLICATIO S I FOR ATIO
where f is the operating frequency, COUT is the output
capacitance and IRIPPLE is the ripple current in the induc-
tor. The output ripple is highest at maximum input voltage
since IRIPPLE increases with input voltage.
allows CSS to ramp up slowly providing the soft-start
function. This diode (and capacitor) can be deleted if the
external soft-start is not needed.
During soft-start, the start-up of VOUT1 is controlled by
slowlyrampingthepositivereferencetotheerroramplifier
from 0V to 0.6V, allowing VOUT1 to rise smoothly from 0V
toitsfinalvalue. Thedefaultinternalsoft-starttimeis1ms.
This can be increased by placing a capacitor between the
RUN/SSpinandSGND. Inthiscase, thesoft-starttimewill
be approximately:
Setting Output Voltage
TheLTC3736-1outputvoltagesareeachsetbyanexternal
feedback resistor divider carefully placed across the out-
put, as shown in Figure 6. The regulated output voltage is
determined by:
600mV
0.7µA
⎛
RB ⎞
RA ⎠
t
SS1 = CSS •
VOUT = 0.6V • 1+
⎜
⎟
⎝
It is recommended that CSS have a value of at least twice
that of the frequency filtering capacitor connected to the
FREQ pin when spread sprectrum operation is enabled
(see Operation Frequency section).
To improve the frequency response, a feed-forward ca-
pacitor, CFF, may be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line. When spread spectrum operation
is enabled, it is recommended that RA and RB be large-
valued, preferably on the order of hundreds of kilohms.
Tracking
The start-up of VOUT2 is controlled by the voltage on the
TRACK pin. Normally this pin is used to allow the start-up
of VOUT2 to track that of VOUT1 as shown qualitatively in
Figures 8a and 8b. When the voltage on the TRACK pin is
less than the internal 0.6V reference, the LTC3736-1
regulates the VFB2 voltage to the TRACK pin voltage
instead of 0.6V. The start-up of VOUT2 may ratiometrically
track that of VOUT1, according to a ratio set by a resistor
divider (Figure 8c):
Run/Soft Start Function
The RUN/SS pin is a dual purpose pin that provides the
optional external soft-start function and a means to shut
down the LTC3736-1.
Pulling the RUN/SS pin below 0.65V puts the LTC3736-1
into a low quiescent current shutdown mode (IQ = 9µA). If
RUN/SS has been pulled all the way to ground, there will
be a delay before the LTC3736-1 comes out of shutdown
and is given by:
VOUT1
VOUT2 RTRACKA
R2A
R
TRACKA +RTRACKB
R2B +R2A
=
•
CSS
0.7µA
tDELAY = 0.65V •
= 0.93s/µF •CSS
For coincident tracking (VOUT1 = VOUT2 during start-up),
R2A/R2B = RTRACKA/RTRACKB
This pin can be driven directly from logic as shown in
Figure 6. Diode D1 in Figure 7 reduces the start delay but
V
OUT
3.3V OR 5V
RUN/SS
RUN/SS
R
B
C
FF
D1
1/2 LTC3736-1
V
FB
C
SS
R
A
C
SS
37361 F07
37361 F06
Figure 6. Setting Output Voltage
Figure 7. RUN/SS Pin Interfacing
37361f
18
LTC3736-1
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APPLICATIO S I FOR ATIO
V
OUT2 when using the TRACK pin. If no tracking function
is desired, then the TRACK pin may be tied to VIN. How-
ever, in this situation there would be no (internal nor
The ramp time for VOUT2 to rise from 0V to its final value
is:
RTRACKA
R1A
R1A +R1B
TRACKA +RTRACKB
t
SS2 = tSS1
•
•
external) soft-start on VOUT2
.
R
When using tracking with spread spectrum operation
enabled, the tracking resistors RTRACKA and RTRACKB
should have value at least 10 times smaller than corre-
sponding feedback resistors R2A and R2B.
For coincident tracking,
VOUT2F
t
SS2 = tSS1 •
VOUT1F
Fault Condition: Short Circuit and Current Limit
where VOUT1F and VOUT2F are the final, regulated values of
VOUT1 and VOUT2. VOUT1 should always be greater than
To prevent excessive heating of the bottom MOSFET,
foldback current limiting can be added to reduce the
current in proportion to the severity of the fault.
V
OUT1
V
OUT2
Foldback current limiting is implemented by adding di-
odes DFB1 and DFB2 between the output and the ITH pin as
shown in Figure 9. In a hard short (VOUT = 0V), the current
will be reduced to approximately 50% of the maximum
output current.
LTC3736-1
R1B
R2B
V
V
FB2
FB1
R1A
R2A
R
R
TRACKB
TRACK
37361 F08a
TRACKA
Low Supply Operation
Figure 8a. Using the TRACK Pin
Although the LTC3736-1 can function down to below
2.4V, themaximumallowableoutputcurrentisreducedas
VIN decreases below 3V. Figure 10 shows the amount of
V
OUT1
V
OUT
1/2 LTC3736-1
R2
R1
D
D
+
FB1
I
TH
V
FB
V
OUT2
FB2
37361 F09
TIME
Figure 9. Foldback Current Limiting
(8b) Coincident Tracking
105
V
REF
V
V
100
OUT1
OUT2
95
90
MAXIMUM
SENSE VOLTAGE
85
80
75
37361 F08b,c
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
INPUT VOLTAGE (V)
TIME
(8c) Ratiometric Tracking
37361 F10
Figure 10. Line Regulation of VREF and
Maximum Sense Voltage for Low Input Supply
Figures 8b and 8c. Two Different Modes of Output
Voltage Tracking
37361f
19
LTC3736-1
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APPLICATIO S I FOR ATIO
2) MOSFETgatechargecurrentresultsfromswitchingthe
gate capacitance of the power MOSFETs. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from SENSE+ to ground.
The resulting dQ/dt is a current out of SENSE+, which is
typically much larger than the DC supply current. In
continuous mode, IGATECHG = f • QP.
3) I2R losses are calculated from the DC resistances of the
MOSFETs and inductor. In continuous mode, the aver-
age output current flows through L but is “chopped”
between the top P-channel MOSFET and the bottom
N-channel MOSFET. The MOSFET RDS(ON)s multiplied
by duty cycle can be summed with the resistance of L
to obtain I2R losses.
changeasthesupplyisreduceddownto2.4V. Alsoshown
is the effect on VREF
.
Minimum On-Time Considerations
Minimumon-time,tON(MIN),isthesmallestamountoftime
in which the LTC3736-1 is capable of turning the top
P-channel MOSFET on and then off. It is determined by
internal timing delays and the gate charge required to turn
on the top MOSFET. Low duty cycle and high frequency
applications may approach the minimum on-time limit
and care should be taken to ensure that:
VOUT
OSC • V
tON(MIN)
<
f
IN
If the duty cycle falls below what can be accommodated
bytheminimumon-time,theLTC3736-1willbegintoskip
cycles. The output voltage will continue to be regulated,
but the ripple current and ripple voltage will increase. The
minimum on-time for the LTC3736-1 is typically about
4) Transition losses apply to the top external P-channel
MOSFET and increase with higher operating frequen-
cies and input voltages. Transition losses can be esti-
mated from:
Transition Loss = 2 (VIN)2IO(MAX) RSS
(f)
C
250ns. However, as the peak sense voltage (IL(PEAK)
•
RDS(ON)) decreases, the minimum on-time gradually in-
creases up to about 300ns.
Other losses, including CIN and COUT ESR dissipative
lossesandinductorcorelosses,generallyaccountforless
than 2% total additional loss.
Efficiency Considerations
Checking Transient Response
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting efficiency and which change would produce the
most improvement. Efficiency can be expressed as:
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to (∆ILOAD)(ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or dis-
chargeCOUT, whichgeneratesafeedbackerrorsignal. The
regulator loop then returns VOUT to its steady-state value.
Duringthisrecoverytime,VOUT canbemonitoredforover-
shoot or ringing. OPTI-LOOP compensation allows the
transient response to be optimized over a wide range of
output capacitance and ESR values.
Efficiency = 100% – (L1 + L2 + L3 + …)
whereL1, L2, etc. aretheindividuallossesasapercentage
of input power.
Although all dissipative elements in the circuit produce
losses, five main sources usually account for most of the
losses in LTC3736-1 circuits: 1) LTC3736-1 DC bias
current, 2) MOSFET gate charge current, 3) I2R losses,
and 4) transition losses.
The ITH series RC-CC filter (see Functional Diagram) sets
the dominant pole-zero loop compensation. The ITH exter-
nal components shown in the Typical Application on the
front page of this data sheet will provide an adequate
starting point for most applications. The values can be
1) The VIN (pin) current is the DC supply current, given in
the electrical characteristics, excluding MOSFET driver
currents. VIN current results in a small loss that in-
creases with VIN.
37361f
20
LTC3736-1
W U U
APPLICATIO S I FOR ATIO
U
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(CLOAD).
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
modified slightly (from 0.2 to 5 times their suggested
values) to optimize transient response once the final PC
layout is done and the particular output capacitor type and
value have been determined. The output capacitors need
to be decided upon because the various types and values
determine the loop feedback factor gain and phase. An
output current pulse of 20% to 100% of full load current
having a rise time of 1µs to 10µs will produce output
voltage and ITH pin waveforms that will give a sense of the
overall loop stability. The gain of the loop will be increased
by increasing RC, and the bandwidth of the loop will be
increased by decreasing CC. The output voltage settling
behavior is related to the stability of the closed-loop
system and will demonstrate the actual overall supply
performance. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3736-1. These items are illustrated in the layout dia-
gram of Figure 11. Figure 12 depicts the current wave-
forms present in the various branches of the 2-phase dual
regulator.
1) The power loop (input capacitor, MOSFETs, inductor,
output capacitor) of each channel should be as small as
possible and isolated as much as possible from the power
loop of the other channel. Ideally, the drains of the P- and
N-channel FETs should be connected close to one another
with an input capacitor placed across the FET sources
(from the P-channel source to the N-channel source) right
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
dischargedbypasscapacitorsareeffectivelyputinparallel
with COUT, causing a rapid drop in VOUT. No regulator can
+
C
OUT1
V
OUT1
L1
LTC3736EGN-1
1
24
23
22
21
20
19
18
17
16
15
14
13
+
SENSE1
SW1
2
3
PGND
BG1
IPRG1
MN1
VIN1
MP1
V
FB1
TH1
C
4
SSDIS
TG1
I
5
IPRG2
FREQ
SGND
C
VIN
6
PGND
TG2
V
IN
7
C
8
VIN2
RUN/SS
BG2
V
IN
9
MN2
MP2
TRACK
10
11
12
PGND
V
FB2
TH2
+
SENSE2
I
SW2
PGOOD
L2
+
V
OUT2
C
OUT2
37361 F11
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 11. LTC3736-1 Layout Diagram
37361f
21
LTC3736-1
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APPLICATIO S I FOR ATIO
attheFETs.Itisbettertohavetwoseparate,smallervalued
input capacitors (e.g., two 10µF—one for each channel)
than it is to have a single larger valued capacitor (e.g.,
22µF) that the channels share with a common connection.
The PGND pins on the LTC3736-1 IC should be shorted
together and connected to the common power ground
connection (away from the switching currents).
3) Put the feedback resistors close to the VFB pins. The
trace connecting the top feedback resistor (RB) to the
outputcapacitorshouldbeaKelvintrace.TheITHcompen-
sation components should also be very close to the
LTC3736-1.
4) The current sense traces (SENSE+ and SW) should be
Kelvin connections right at the P-channel MOSFET source
and drain.
2) The signal and power grounds should be kept separate.
The signal ground consists of the feedback resistor divid-
ers, ITH compensation networks and the SGND pin.
The power grounds consist of the (–) terminal of the input
and output capacitors and the source of the N-channel
MOSFET. Eachchannelshouldhaveitsownpowerground
for its power loop (as described in (1) above). The power
grounds for the two channels should connect together at
a common point. It is most important to keep the ground
paths with high switching currents away from each other.
5) Keep the switch nodes (SW1, SW2) and the gate driver
nodes (TG1, TG2, BG1, BG2) away from the small-signal
components, especially the opposite channels feedback
resistors, ITH compensation components and the current
sense pins (SENSE+ and SW).
MP1
L1
V
OUT1
+
C
OUT1
R
L1
MN1
V
IN
R
IN
+
C
IN
MP2
L2
V
OUT2
+
C
OUT2
R
L2
MN2
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH
37361 F12
Figure 12. Branch Current Waveforms
37361f
22
LTC3736-1
U
TYPICAL APPLICATIO S
R
R
FB1B
562k
FB1A
178k
C
ITH1A
L1
100pF
1.5µH
V
2.5V
5A
MP1
OUT1
22
23
24
1
2
3
21
20
19
18
17
16
+
SW1
IPRG1
SENSE1
C
ITH1
PGND
BG1
SSDIS
TG1
R
ITH1
15k
220pF
MN1
V
FB1
+
Si7540DP
C
OUT1
I
TH1
2200pF
150µF
IPRG2
FREQ
PGND
4
15
V
5V
C
IN
SGND
TG2
R
VIN
10Ω
5
14
V
IN
RUN/SS
IN
10µF
×2
LTC3736EUF-1
13
12
11
MN2
Si7540DP
C
BG2
OUT2
9
7
8
6
C
ITH2
220pF
+
150µF
PGND
PGOOD
V
1.8V
5A
C
OUT2
VIN
+
V
FB2
SENSE2
1µF
MP2
I
L2
1.5µH
TH2
10
R
15k
ITH2
TRACK
PGND
25
SW2
C
10nF
SS
C
ITH2B
100pF
R
R
FB2B
909k
FB2A
R
R
TRACKB
1.18k
TRACKA
590Ω
453k
37361 F13
L1, L2: VISHAY IHLP-2525CZ-01
, C : SANYO 4TPB150MC
C
OUT1 OUT2
Figure 13. 2-Phase, Spread Spectrum, Dual Output Synchronous DC/DC Converter
37361f
23
LTC3736-1
TYPICAL APPLICATIO S
U
68pF
R
R
FB1B
187k
FB1A
59k
C
ITH1A
L1
1.5µH
47pF
V
2.5V
2A
MP1
OUT1
22
23
24
1
2
3
21
20
19
18
17
16
+
SW1
IPRG1
SENSE1
C
ITH1
PGND
BG1
SSDIS
TG1
PGND
TG2
R
ITH1
22k
470pF
MN1
Si7540DP
V
FB1
C
OUT1
I
TH1
100µF
2200pF
IPRG2
FREQ
SGND
4
15
V
IN
3.3V
R
VIN
10Ω
5
14
V
IN
RUN/SS
C
IN
LTC3736EUF-1
22µF
C
13
12
11
MN2
Si7540DP
OUT2
BG2
100µF
9
7
8
6
C
ITH2
PGND
PGOOD
V
1.8V
2A
C
OUT2
470pF
VIN
+
V
I
SENSE2
1µF
FB2
MP2
L2
1.5µH
TH2
10
R
ITH2
TRACK
PGND
SW2
22k
C
SS
25
C
ITH2A
10nF
47pF
R
R
FB2B
118k
FB2A
R
R
TRACKA
590Ω
TRACKB
1.18k
59k
37361 F14
L1, L2: VISHAY IHLP-2525CZ-01
, C : MURATA GRM32EROJ107M
C
OUT1 OUT2
100pF
Figure 14. 2-Phase, Spread Spectrum, Dual Output Synchronous DC/DC Converter with Ceramic Output Capacitors
Efficiency vs Load Current
Load Step
Load Step
100
90
80
70
60
50
40
30
20
10
0
V
V
OUT
OUT
AC-COUPLED
100mV/DIV
AC-COUPLED
50mV/DIV
I
I
L
L
1A/DIV
1A/DIV
100µs/DIV
= 100mA TO 1A
37361 F14c
100µs/DIV
= 100mA TO 1A
37361 F14d
V
V
= 2.5V
= 1.8V
OUT
OUT
V
I
= 1.8V
V
I
= 2.5V
OUT
LOAD
OUT
LOAD
1
10
100
1000
10000
LOAD CURRENT (mA)
37361 F14b
37361f
24
LTC3736-1
U
TYPICAL APPLICATIO S
C
FF1
100pF
R
R
FB1A
FB1B
187k
59k
SSDIS
MP1
L1
C
ITH1
1.5µH
V
2.5V
3A
OUT1
R
ITH1
15k
SW1
1
220pF
24
23
22
21
20
19
18
+
SW1
IPRG1
SENSE1
2
3
4
5
6
7
PGND
BG1
SSDIS
TG1
PGND
TG2
MN1
Si7540DP
D1
V
FB1
+
C
OUT1
I
TH1
150µF
2200pF
IPRG2
FREQ
SGND
V
IN
3.3V
R
10Ω
LTC3736EGN-1
IN
VIN
5
17
V
RUN/SS
C
IN
22µF
16
15
14
MN2
D2
C
BG2
OUT2
12
10
11
9
C
Si7540DP
ITH2
+
150µF
PGND
PGOOD
V
1.8V
4A
C
OUT2
220pF
VIN
+
V
SENSE2
1µF
FB2
MP2
SW2
I
L2
1.5µH
TH2
TRACK
13
R
ITH2
15k
SW2
R
R
R
FB2A
FB2B R
TRACKA
590Ω
TRACKB
1.18k
59k
118k
37361 F15
C
, C
OUT1 OUT2
: SANYO 4TPB150MC
L1, L2: VISHAY IHLP-2525CZ-01
C
FF1
100pF
4.7nF
D1, D2: OPTIONAL SCHOTTKY DIODE
Figure 15. 2-Phase, Fixed 550kHz or Spread Spectrum, Dual Output Synchronous DC/DC Converter
37361f
25
LTC3736-1
U
PACKAGE DESCRIPTIO
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
0.70 ±0.05
4.50 ± 0.05
3.10 ± 0.05
2.45 ± 0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
0.23 TYP
(4 SIDES)
R = 0.115
TYP
0.75 ± 0.05
4.00 ± 0.10
(4 SIDES)
23 24
PIN 1
TOP MARK
(NOTE 6)
0.38 ± 0.10
1
2
2.45 ± 0.10
(4-SIDES)
(UF24) QFN 1103
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
37361f
26
LTC3736-1
U
PACKAGE DESCRIPTIO
GN Package
24-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.337 – .344*
(8.560 – 8.738)
.033
(0.838)
REF
24 23 22 21 20 19 18 17 16 15 14 13
.045 ±.005
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.254 MIN
.150 – .165
1
2
3
4
5
6
7
8
9 10 11 12
.0165 ±.0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
.015 ± .004
(0.38 ± 0.10)
.0532 – .0688
(1.35 – 1.75)
× 45°
.004 – .0098
(0.102 – 0.249)
.0075 – .0098
(0.19 – 0.25)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.008 – .012
.0250
(0.635)
BSC
GN24 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
37361f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
27
LTC3736-1
U
TYPICAL APPLICATIO
2-Phase, Spread Spectrum Dual Output, Synchronous DC/DC Converter
R
R
FB1B
187k
FB1A
59k
C
ITH1A
L1
100pF
1.5µH
V
2.5V
2A
MP1
OUT1
22
23
24
1
2
3
21
20
19
18
17
16
+
SW1
IPRG1
SENSE1
C
ITH1
PGND
BG1
SSDIS
TG1
R
ITH1
15k
220pF
V
MN1
MN2
FB1
+
C
OUT1
I
TH1
2200pF
150µF
IPRG2
FREQ
PGND
4
V
5V
C
15
IN
SGND
TG2
R
10Ω
VIN
5
14
V
RUN/SS
IN
IN
10µF
×2
LTC3736EUF-1
13
12
11
C
BG2
OUT2
9
7
8
6
C
ITH2
220pF
+
150µF
PGND
PGOOD
V
1.8V
2A
C
VIN
1µF
OUT2
+
V
SENSE2
FB2
MP2
I
L2
1.5µH
TH2
TRACK
PGND
10
R
ITH2
15k
SW2
C
SS
25
C
ITH2B
100pF
10nF
R
FB2A
59k
R
FB2B
118k
R
R
TRACKA
590Ω
TRACKB
1.18k
37361 TA02
MP1, MP2: FDC638P
MN1, MN2: FDC637N
L1, L2: VISHAY IHLP-2525CZ-01
, C : SANYO 4TPB150MC
C
OUT1 OUT2
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PART NUMBER
DESCRIPTION
COMMENTS
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IN
SD
TSSOP-20E Package
LTC3701
LTC3708
2-Phase, Low Input Voltage Dual Step-Down DC/DC Controller
2.5V ≤ V ≤ 9.8V, 550kHz, PGOOD, PLL, 16-Lead SSOP
IN
Fast 2-Phase, No R
Output Tracking
Buck Controller with
Constant On-Time Dual Controller, V Up to 36V, Very Low
SENSE
IN
Duty Cycle Operation, 5mm × 5mm QFN Package
LTC3728/LTC3728L Dual, 550kHz, 2-Phase, Synchronous Step-Down
Switching Regulator
Constant Frequency, V to 36V, 5V and 3.3V LDOs,
IN
5mm × 5mm QFN or 28-Lead SSOP
LTC3736
Dual, 2-Phase, No R
Tracking
, Synchronous Controller with Output
SENSE
V : 2.75V to 9.8V, I
Up to 5A, 4mm × 4mm QFN Package
IN
OUT
LTC3737
LTC6902
Dual, 2-Phase, No R
Controller with Output Tracking
V : 2.75V to 9.8V, I
IN
Up to 5A, 4mm × 4mm QFN Package
SENSE
OUT
Multiphase Oscillator with Spread Spectrum Frequency
Modulation
Resistor Programs Nominal Frequency and Spreading;
2-, 3-, or 4-Phase Outputs; 10-Pin MSOP Package
No RSENSE is a trademark of Linear Technology Corporation.
37361f
LT/TP 0804 1K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
28
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
©LINEAR TECHNOLOGY CORPORATION 2004
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