LTC3773EG-TRPBF [Linear]
Triple Output Synchronous 3-Phase DC/DC Controller with Up/Down Tracking; 三路输出有向上/向下跟踪同步3相DC / DC控制器型号: | LTC3773EG-TRPBF |
厂家: | Linear |
描述: | Triple Output Synchronous 3-Phase DC/DC Controller with Up/Down Tracking |
文件: | 总32页 (文件大小:467K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC3773
Triple Output Synchronous
3-Phase DC/DC Controller with
Up/Down Tracking
FEATURES
DESCRIPTION
TheLTC®3773isahighperformance,3-phase,tripleoutput
synchronous step-down switching regulator controller
with output voltage power up/down tracking capability.
The controller allows for sequential, coincident or ratio-
metric tracking.
■
Current Mode Controller with Onboard
MOSFET Drivers
■
Programmable Power Up/Down Tracking
■
Wide V Range: 3.3V to 36V (V = 5V)
IN
CC
■
■
■
1ꢀ 0.6V V Accuracy Over Temperature
FB
Power Good Output Voltage Monitor
Phase-Lockable or Adjustable Frequency:
160kHz to 700kHz
This 3-phase controller drives its output stages with 120°
phaseseparationatfrequenciesofupto700kHzperphase
minimizingtheRMSinputcurrent.Lightloadefficiencycan
be maximized by using selectable Burst Modeoperation.
The 0.6V precision reference supports output voltages
from 0.6V to 5V.
OPTI-LOOP® Compensation Minimizes C
■
■
■
OUT
Current Foldback and Overvoltage Protection
Selectable Continuous, Discontinuous or
Burst Mode® Operation at Light Load
Programmable Phase Operation
Available in 5mm x 7mm QFN and 36-Lead
SSOP Packages
■
■
Faultprotectionfeaturesincludeoutputovervoltage, input
undervoltage lockout plus current foldback under short-
circuit or overload conditions.
, LT, LTC, LTM, Burst Mode and OPTI-LOOP are registered trademarks of
Linear Technology Corporation. All other trademarks are the property of their respective
owners. Protected by U.S. Patents including 5408150, 5481178, 5705919, 5929620,
6144194, 6177787, 6304066, 6498466, 6580258, 6611131.
APPLICATIONS
■
Servers, Telecom, Industrial Power Supplies
■
General Purpose Multiple Rail DC/DC
■
FPGA and DSP Requirements
TYPICAL APPLICATION
High Efficiency, 3-Phase, Triple Synchronous DC/DC Step-Down Controller
V
CC
4.5V TO 6V
10k
0.1μF
10μF
SW1, 2, 3
PGOOD
V
IN
4.5V TO 22V
PGOOD
V
BOOST1, 2, 3
V
DR
CC
V
TG2
SW2
BG2
OUT2
C
IN
1.5μH
0.003Ω
1.8V/15A
SDB1, 2, 3
POWER UP/SHUTDOWN
+
TRACK1, 2, 3
C
OUT2
20k
0.01μF
LTC3773
+
–
SENSE2
SENSE2
V
FB2
V
IN
V
TG1
SW1
BG1
OUT1
2.5V/15A
V
IN
10k
2.2μH
0.003Ω
V
TG3
SW3
BG3
OUT3
1.2μH
0.003Ω
1.2V/15A
C
OUT1
C
OUT3
+
–
PGND
SENSE1
SENSE1
+
–
SENSE3
SENSE3
V
FB1
31.6k
I
TH1, 2, 3
10k
V
FB3
PLLFLTR
SGND
20k
20k
3773 F01
3773fb
1
LTC3773
ABSOLUTE MAXIMUM RATINGS (Note 1)
Extended Commercial Operating
Topside Driver Voltage (BOOSTn) ..............42V to –0.3V
Switch Voltage (SWn)...................................36V to –1V
Boosted Driver Voltage (BOOSTn – SWn)....7V to –0.3V
Temperature Range (Note 2)................–40°C to 85°C
Junction Temperature (Note 2) ............................. 125°C
Storage Temperature Range...................–65°C to 125°C
Lead Temperature (Soldering, 10 sec)
G Package......................................................... 300°C
Peak Body Temperature UHF Package................... 240°C
Supply Voltages (V , V )..........................7V to –0.3V
CC DR
PGOOD, PHASEMD, PLLFLTR, PLLIN/FC, SDBn,
TRACKn, V n...............................(V + 0.3V) to –0.3V
FB
CC
+
–
SENSE n, SENSE n ........................ (1.1 • V ) to –0.3V
CC
I
Voltage...............................................2.7V to –0.3V
THn
PIN CONFIGURATIONS
TOP VIEW
TOP VIEW
+
SENSE1
SENSE1
1
2
36 PHASEMD
35 PGOOD
34 BOOST1
33 TG1
–
SDB
3
38 37 36 35 34 33 32
TRACK1
4
TRACK1
1
2
3
4
5
6
7
8
9
31 BOOST1
30 TG1
V
5
32 SW1
FB1
TH1
V
I
FB1
I
6
31 SW2
SW1
SW2
29
28
TH1
SGND
7
30 TG2
SGND
I
I
8
29 BOOST2
28 BOOST3
27 TG3
TH2
TH3
I
I
27 TG2
TH2
TH3
9
BOOST2
26
V
V
10
11
FB2
39
V
V
25 BOOST3
26 SW3
FB2
FB3
TRACK2 12
TRACK3 13
25 BG1
24
TG3
FB3
24 BG2
TRACK2
23 SW3
22 BG1
21 BG2
–
SENSE2 14
23
V
DR
TRACK3 10
+
SENSE2 15
22 PGND
–
SENSE2 11
–
SENSE3 16
21 BG3
+
20
SENSE2 12
V
DR
SENSE3+ 17
20 PLLIN/FC
19 PLLFLTR
13 14 15 16 17 18 19
V
18
CC
G PACKAGE
36-LEAD PLASTIC SSOP
UHF PACKAGE
T
= 125°C, θ = 95°C/W
JA
JMAX
38-LEAD (5mm × 7mm) PLASTIC QFN
EXPOSED PAD IS PGND (PIN 39),
MUST BE SOLDERED TO PCB
T
= 125°C, θ = 34°C/W
JA
JMAX
ORDERING INFORMATION
LEAD FREE FINISH
LTC3773EG#PBF
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 85°C
LTC3773EG#TRPBF
LTC3773EUHF#TRPBF
36-Lead Plastic SSOP
LTC3773EUHF#PBF
3773E
38-Lead (5mm x 7mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3773fb
2
LTC3773
ELECTRICAL CHARACTERISTICS (Note 3) The ● denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. VCC = VDR = VBOOST = VSDB = 5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Main Control Loop
V
Feedback Voltage
V
= 1.2V, 0°C ≤ T ≤ 85°C (Note 4)
ITH
0.594
0.591
0.600
0.600
0.606
0.609
V
V
FB
●
●
I
Feedback Pin Input Current
0 ≤ V ≤ 1V
–15
–100
nA
VFB
FB
–
V
Maximum Current Sense Threshold
V
= 0.55V, V
= 1V, V = 2.5V
SENSE
65
60
75
75
85
90
mV
mV
SENSEMAX
FB
TRACK
V
Feedback Voltage Load Regulation
Measured in Servo Loop (Note 4)
ITH
ITH
FBLOADREG
Δ
Δ
Voltage = 1.2V to 0.7V
Voltage = 1.2V to 2V
0.15
–0.2
0.5
–0.5
ꢀ
ꢀ
●
●
V
Feedback Voltage Line Regulation
V
V
V
V
V
= 4.5V to 6V
0.01
2.7
3
ꢀ/V
mmho
MHz
FBLNREG
CC
●
●
g
Transconductance Amplifier g
= 1.2V, Sink/Source 25μA (Note 4)
= 1.2V (Note 5)
2.3
3.2
m
m
ITH
ITH
ITH
f
Transconductance Amplifier GBW
Transconductance Amplifier DC Gain
u
A
V
= 0.8V to 1.6V
50
56
dB
ERR
V
Undervoltage Reset
Ramping Positive
3.7
4.1
0.16
4.4
6
V
V
UVR
CC
CC
Undervoltage Hysteresis
●
V
CC
V
V
Supply Voltage
Supply Current
4.5
5
V
CC
I
I
I
I
VCC
CC
Normal Mode
Shutdown
V
V
= 5V
= 0V
2.8
20
4
30
mA
μA
CC
SDB
V
Supply Current
DR
VDR
Normal Mode
Shutdown
V
V
= 5V (Note 6)
= 0V
5
1
mA
μA
DR
SDB
V
Supply Current
BOOST
Normal Mode
Shutdown
BOOST
SDB
V
V
= 5V, V = 0V (Note 6)
1
1
mA
μA
BOOST
SDB
SW
= 0V
SDB Source Current
SDB1, SDB2, SDB3 Source Content
–1.5
–0.5
μA
μA
●
●
●
●
V
SDB Power Up Threshold
SDB1 Pin CH1 ON Threshold
SDB2 Pin CH2 ON Threshold
SDB3 Pin CH3 ON Threshold
Ramping Positive
0.4
1.14
1.71
2.3
V
V
V
V
SDB
1.2
1.8
2.4
1.26
1.89
2.5
Channel On Threshold Hysteresis
SENSE Pins Source Current
–10
–13
98.5
2.2
1.8
2.4
0.9
50
ꢀ
μA
ꢀ
Ω
+
–
I
V
, V = 1.2V, Current at Each Pin
SENSE
–20
SENSE
SENSE
DF
Maximum Duty Factor
PLLFLTR Floats, In Dropout
97
MAX
TG R
TG R
BG R
BG R
TG Driver Pull-Up On-Resistance
TG Driver Pull-Down On-Resistance
BG Driver Pull-Up On-Resistance
BG Driver Pull-Down On-Resistance
TG High, I
= 100mA (Note 7)
= 100mA (Note 7)
= 100mA (Note 7)
= 100mA (Note 7)
UP
OUT
OUT
TG Low, I
Ω
DOWN
UP
Ω
BG High, I
OUT
OUT
BG Low, I
Ω
DOWN
TG/BG t
Top Gate OFF to Bottom Gate ON Delay
Synchronous Switch-On Delay Time
All Controllers
ns
1D
BG/TG t
Bottom Gate OFF to Top Gate ON Delay
Top Switch-On Delay Time
All Controllers
50
ns
ns
2D
t
Minimum On-Time
Tested with a Square Wave (Note 8)
130
ON(MIN)
Tracking
I
TRACK Pin Pull-Up Current
V
SDB
= 5V, V = 0V
TRACK
–1
μA
TRACK
V
V
Voltage During Tracking
V
V
= 0.2V, V = 1.2V (Note 4)
180
380
200
400
220
420
mV
mV
FBTRACK
FB
TRACK
TRACK
ITH
= 0.4V, V = 1.2V (Note 4)
ITH
3773fb
3
LTC3773
ELECTRICAL CHARACTERISTICS (Note 3) The ● denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. VCC = VDR = VBOOST = VSDB = 5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Good Output Indication
V
PGOOD Voltage Output Low
PGOOD Output Leakage
PGOOD Trip Thresholds
FB
FB
I
= 2mA
= 5V
0.1
0.3
1
V
PGL
PGOOD
I
V
μA
PGOOD
PGOOD
V
with Respect to 0.6V Reference
FB
V
V
V
V
Ramping Negative
Ramping Positive
PGOOD Goes Low After V
Delay
–7
7
–10
10
–13
13
ꢀ
ꢀ
PGTHNEG
PGTHPOS
PGDLY
V
PGDLY
PGOOD Delay
100
150
μs
Oscillator and Phase-Locked Loop
f
f
f
f
f
Nominal Frequency
V
V
V
Open
= 0V
= 5V
360
190
510
400
220
560
160
700
440
250
630
200
kHz
kHz
kHz
kHz
kHz
NOM
PLLFLTR
PLLFLTR
PLLFLTR
Low Frequency
LOW
High Frequency
HIGH
PLLIN Minimum Input Frequency
PLLIN Maximum Input Frequency
PLLLOW
PLLHIGH
540
PLLIN/FC, PHASEMD, PLLFLTR
Logic Input
V
V
V
Low Level Input Voltage
Floating Voltage
1.0
1.6
3.0
V
V
V
LO
FLOAT
HI
High Level Input Voltage
V
PLLIN Synchronization Input Threshold
1
V
PLLIN
I
Phase Detector Output Current
Sinking Capability
Sourcing Capability
V
PLLIN
PLLIN
= 1.5V
OSC
OSC
PLLFLTR
PLLFLTR
f
f
< f
> f
25
–25
μA
μA
P
Controller 2 - Controller 1 Phase
Controller 3 - Controller 1 Phase
PHASEMD Floats or V
= 0V
120
240
Deg
Deg
RELPHS
PHASEMD
Controller 2 - Controller 1 Phase
Controller 3 - Controller 1 Phase
V
= 5V
90
270
Deg
Deg
PHASEMD
CLKOUT
Controller 1 TG to CLKOUT Phase
PHASEMD Floats
PHASEMD
PHASEMD
0
Deg
Deg
Deg
V
V
= 0V
= 5V
60
180
Note 3: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4: The IC is tested in a feedback loop that adjusts V to achieve a
FB
specified error amplifier output voltage (V ).
Note 5: Guaranteed by design, not subject to test.
Note 6: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 2: The LTC3773 is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
ITH
with statistical process controls. T is calculated from the ambient
J
temperature T and power dissipation P according to the following
A
D
Note 7: R
limit is guaranteed by design and/or correlation to static
DS(ON)
formula.
test.
LTC3773EG: T = T + (P x 95°C/W)
J
A
D
Note 8: The minimum on-time condition corresponds to an inductor
peak-to-peak ripple current of ≥40ꢀ of I (see minimum on-time
LTC3773EUHF: T = T + (P x 34°C/W)
J
A
D
MAX
considerations in the Applications Information section).
3773fb
4
LTC3773
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current,
Shutdown CH2 and CH3
Efficiency vs Load Current,
Power-Up CH2 and CH3
100
90
10000
1000
100
10
100
90
10000
1000
80
80
70
60
50
40
30
20
70
60
50
40
30
20
100
10
1
CONTINUOUS
MODE
CONTINUOUS
MODE
DISCONTINUOUS
MODE
DISCONTINUOUS
MODE
Burst Mode
OPERATION
Burst Mode
OPERATION
1
EFFICIENCY
POWER LOSS
EFFICIENCY
POWER LOSS
10
0
10
0
0.1
100
0.1
0.001
0.01
0.1
1
10
0.001
0.01
CHANNEL 1 LOAD CURRENT (A)
= 12V, V = 5V, V = 2.5V
0.1
1
10
100
CHANNEL 1 LOAD CURRENT (A)
V
V
f
V
f
= 12V, V = 5V, V
CC
= 220kHz
= 2.5V
OUT1
IN
OUT2
CC
OUT1
IN
= 1.8V (NO LOAD), V
= 1.2V (NO LOAD)
3773 G01
OUT3
SW
3773 G02
= 220kHz
SW
Efficiency vs VIN
Shutdown CH2 and CH3
Load Regulation
100
95
90
85
80
75
4.0
3.2
2.4
1.6
0.8
0.0
5
0
0.2
V
= 5V, V
= 2.5V, I
= 5A
OUT1
CC
OUT1
V
= 12V, V = 5V, V
= 2.5V
OUT
IN
CC
SHUTDOWN CH2 AND CH3
0.0
–5
–0.2
–0.4
–0.6
–0.8
–1.0
PLLFLTR = 5V
f
= 560kHz
SW
–10
–15
–20
–25
PLLFLTR FLOATS
= 400kHz
f
SW
PLLFLTR = 0V
= 220kHz
f
SW
CONTINUOUS MODE
DISCONTINUOUS MODE
Burst Mode OPERATION
EFFICIENCY
POWER LOSS
0
5
10
15
(V)
20
25
0
5
10
15
20
V
LOAD CURRENT (A)
IN
3773 G03
3773 G04
Line Regulation
Current Limit vs VIN
25
20
15
10
5
2.5
2.0
1.0
V
= 5V, V
= 2.5V, I
= 5A
OUT
CC
OUT
0.8
R
R
= 3mΩ
SENSE
1.5
0.6
1.0
0.4
0.5
0.2
= 5mΩ
SENSE
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–0.2
–0.4
–0.6
–0.8
–1.0
V
= 5V, V
5
= 2.5V, f = 220kHz
OUT SW
CC
0
0
10
15
(V)
20
25
0
5
10
V
15
20
25
V
(V)
IN
IN
3773 G06
3773 G05
3773fb
5
LTC3773
TYPICAL PERFORMANCE CHARACTERISTICS
IVCC and IVDR vs Load Current
IVDR and IVCC vs Switching Frequency
100
120
100
80
60
40
20
0
2.6
2.5
2.4
2.3
2.2
2.1
2.0
V
= 10V, V = V = 5V,
CC DR
IN
I
VDR
FORCED CONTINUOUS MODE
FORCED CONTINUOUS
V
V
V
= 2.5V WITH 5A LOAD
= 1.8V WITH 5A LOAD
= 1.2V WITH 5A LOAD
OUT1
OUT2
OUT3
I
VCC
DISCONTINUOUS
MODE
10
Burst Mode
OPERATION
PLLFLTR = 0V
PLLFLTR = 5V
PLLFLTR = FLOATS
1
0.001
150
250
350
450
550
650
750
0.01
CHANNEL 1 LOAD CURRENT (A)
= 12V, V = V = 5V, V = 2.5V
0.1
1
10
100
SWITCHING FREQUENCY (kHz)
3773 G07
V
V
IN
OUT2
CC
DR
OUT1
= 1.8V (NO LOAD), V
= 1.2V (NO LOAD)
OUT3
3773 G08
Forced Continuous Mode
0A to 10A Load Step
Discontinuous Mode 0A to 5A
Load Step at 5kHz Interval
1.8V V
OUT
50mV/DIV
1.8V V
OUT
AC COUPLED
50mV/DIV
AC COUPLED
I
L
5A/DIV
I
L
5A/DIV
V
SW
10V/DIV
I
LOAD
I
LOAD
5A/DIV
10A/DIV
50μs/DIV
50μs/DIV
V
= 12V, f = 220kHz
SW
3773 G09
V
= 12V, f = 220kHz
SW
3773 G10
IN
IN
Burst Mode Operation 0A to 5A
Load Step at 5kHz Interval
1.8V V
OUT
50mV/DIV
AC COUPLED
I
L
5A/DIV
V
SW
10V/DIV
I
LOAD
5A/DIV
50μs/DIV
V
= 12V, f = 220kHz
SW
3773 G11
IN
3773fb
6
LTC3773
TYPICAL PERFORMANCE CHARACTERISTICS
Error Amplifier gm
vs Temperature
VFB vs Temperature
606.0
604.5
1.00
0.75
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
603.0
601.5
600.0
598.5
597.0
0.50
0.25
0
–0.25
–0.50
595.5
594.0
–0.75
–1.00
–50 –25
0
25
50
75 100 125
–50 –25
25
50
75 100 125
0
TEMPERATURE (°C)
TEMPERATURE (°C)
3773 G12
3773 G13
Maximum Current Limit
Threshold vs Temperature
Maximum Current Limit
Threshold vs VITH
84
81
78
75
72
69
66
12
8
80
60
V
= 0.58V
FB
V
– = 5V
SENSE
SENSE
V
– = 2.5V
4
40
20
0
–4
–8
–12
0
V
– = 0.6V
SENSE
–20
–40
–50 –25
0
25
50
75 100 125
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
(V)
TEMPERATURE (°C)
V
ITH
3773 G14
3773 G15
Maximum Current Limit
Threshold vs SENSE Common
Mode Voltage
Maximum Current Limit
Threshold vs Duty Factor
90
87
84
81
78
75
72
69
66
63
60
80
70
60
V
V
= 5V
= 0.58V
CC
FB
50
40
30
20
10
0
0
0.5
V
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
0
10 20 30 40 50 60 70 80 90 100
COMMON MODE VOLTAGE (V)
DUTY FACTOR (%)
SENSE
3773 G16
3773 G17
3773fb
7
LTC3773
TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Current Limit
SENSE Pin Input Current vs
Threshold vs VFB
SENSE Common Mode Voltage
80
40
30
V
= 5V
= I
V
= 1V
CC
TRACK
+
–
I
= I
SENSE SENSE
SENSE
70
60
20
50
40
30
20
10
0
10
0
–10
–20
–30
0
100
200
300
(mV)
400
500
600
0
0.5
V
1
1.5
2
2.5 3 3.5 4 4.5 5 5.5
V
COMMON MODE VOLTAGE (V)
FB
SENSE
3773 G18
3773 G19
Switching Frequency
vs Temperature
Synchronization Switching
Frequency vs VPLLFLTR
650
600
550
500
450
400
350
300
250
200
150
800
700
600
500
400
300
200
100
V
= 5V
CC
V
= 5V
PLLFLTR
PLLFLTR FLOATING
V
= 0V
0
PLLFLTR
–50 –25
25
50
75 100 125
0
0.5
1
1.5
2
2.5
3
TEMPERATURE (°C)
V
(V)
PLLFLTR
3773 G20
3773 G21
Maximum Duty Factor
vs Temperature
TG Minimum Pulse Width
vs Temperature
180
160
140
120
100
100
96
92
88
84
80
V
= 100mV STEP
SENSE
V
= 0V
PLLFLTR
DROPOUT
PLLFLTR FLOATING
= 5V
V
PLLFLTR
V
= 0V, f = 220kHz
SW
PLLFLTR
V
FLOATING, f = 400kHz
SW
PLLFLTR
TG, BG OPEN
–50 –25
V
= 5V, f = 560kHz
SW
PLLFLTR
25
–50 –25
0
25
50
75 100 125
0
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
3773 G22
3773 G23
3773fb
8
LTC3773
TYPICAL PERFORMANCE CHARACTERISTICS
VCC Undervoltage Reset Voltage
vs Temperature
TRACK and SDB Pull-Up Current
vs Temperature
4.4
1.2
I
TRACK
4.3
0.9
0.6
4.2
POWER UP
4.1
4.0
I
SHUTDOWN
SDB2
3.9
3.8
3.7
0.3
0
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
3773 G24
3773 G25
PLLIN/FC, PHASEMD, PLLFLTR,
Threshold Voltage vs Temperature
PGOOD Delay vs Temperature
180
170
160
150
140
130
120
110
100
3.3
2.9
2.5
2.1
1.7
1.3
0.9
0.5
V
= 5V
CC
HIGH THRESHOLD
PGOOD ↑
FLOATING THRESHOLD
LOW THRESHOLD
PGOOD ↓
–50 –25
0
25
50
75 100 125
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
3773 G27
3773 G26
SDB2 Threshold Voltage
vs Temperature
2
1.5
1
V
= 5V
CC
CHANNEL 2 ENABLE
CHANNEL 2 DISABLE
SDB2 SHUTDOWN
0.5
0
–50 –25
0
25
50
75 100 125
TEMPERATURE (°C)
3773 G28
3773fb
9
LTC3773
PIN FUNCTIONS (G/UHF)
+
SENSE1 (Pin 1/Pin 34): The (+) Input to the Channel 1
I
(Pin 9/Pin 6): Channel 3 Error Amplifier Output and
TH3
Switching Regulator Compensation Point. See I
.
Differential Current Comparator. The I
pin voltage and
TH1
TH1
–
+
controlled offsets between the SENSE1 and SENSE1
V
(Pin 10/Pin 7): Channel 2 Error Amplifier Feedback
FB2
pins in conjunction with R
trip threshold.
set the channel 1 current
SENSE
Input. See V
.
FB1
V
(Pin 11/Pin 8): Channel 3 Error Amplifier Feedback
FB3
–
SENSE1 (Pin 2/Pin 35): The (–) Input to the Channel 1
Input. See V
.
FB1
Differential Current Comparator.
TRACK2 (Pin 12/Pin 9): Channel 2 Tracking Input. Tie the
TRACK2 pin to a resistive divider connected to the output
of channel 1 for either coincident or ratiometric output
tracking. See the Soft-Start/Tracking application. TRACK2
comes with a 1μA pull-up current. An external capacitor
can be added at this pin to provide soft-start. During
startup or output short-circuit condition, if the potential
at TRACK2 is less than 0.54V, current limit foldback is
disabled. When channel 2 is powered down, this pin will
be pulled low.
SDB/SDB1, SDB2, SDB3 (Pin 3/Pins 36, 37, 38): Shut-
down, Active Low. For G package, SDB1, SDB2 and SDB3
are shorted at the SDB pin. The power up thresholds for
channel 1, 2 and 3 are set at 1.2V, 1.8V and 2.4V respec-
tively. By pulling the SDB1, SDB2 and SDB3 pins below
0.4V, the IC is put into low current shutdown mode (I
VCCQ
<30μA). There is a 0.5μA pull-up current at each SDB pin.
An external capacitor can be added at this pin to provide
power up delay.
TRACK3 (Pin 13/Pin 10): Channel 3 Tracking Input. See
TRACK1 (Pin 4/Pin 1): Channel 1 Tracking Input. TRACK1
is used for tracking multiple LTC3773s. See the Startup
Tracking application. To disable this feature, float this pin
TRACK2.
–
SENSE2 (Pin 14/Pin 11): The (–) Input to the Channel 2
–
Differential Current Comparator. See SENSE1 .
or tie it to V . TRACK1 provides a 1μA pull-up current.
CC
+
An external capacitor can be added at this pin to provide
soft-start.Duringstartuporoutputshort-circuitcondition,
if the potential at TRACK1 is less than 0.54V, current limit
foldback is disabled. When channel 1 is powered down,
this pin will be pulled low.
SENSE2 (Pin 15/Pin 12): The (+) Input to the Channel 2
+
Differential Current Comparator. See SENSE1 .
–
SENSE3 (Pin 16/Pin 13): The (–) Input to the Channel 3
–
Differential Current Comparator. See SENSE1 .
+
SENSE3 (Pin 17/Pin 14): The (+) Input to the Channel 3
V
FB1
(Pin 5/Pin 2): Channel 1 Error Amplifier Feedback
+
Differential Current Comparator. See SENSE1 .
Input. This pin connects the error amplifier input to an
external resistive divider from V
V
(Pin18/Pin15):MainInputSupply.Allinternalcircuits
.
CC
OUT1
except the output drivers are powered from this pin. V
CC
I
(Pin 6/Pin 3): Channel 1 Error Amplifier Output and
TH1
should be connected to a low noise 5V power supply and
should be bypassed to SGND with at least a 1μF capacitor
in close proximity to the LTC3773.
Switching Regulator Compensation Point. The current
comparator’s threshold increases with this control volt-
age.
PLLFLTR (Pin 19/Pin 16): Phase-Locked Loop Lowpass
Filter. The phase-locked loop’s lowpass filter is tied to this
pin. Alternatively, when external frequency synchronizing
is not used, this pin can be forced low, left floating or tied
high to vary the frequency of the internal oscillator.
SGND (Pin 7/Pin 4): Signal Ground. This pin must be
routed separately under the IC to the PGND pin and then
to the main ground plane.
I
(Pin 8/Pin 5): Channel 2 Error Amplifier Output and
TH2
Switching Regulator Compensation Point. See I
.
TH1
3773fb
10
LTC3773
PIN FUNCTIONS (G/UHF)
BOOST3 (Pin 28/Pin 25): Channel 3 Top Gate Driver Sup-
PLLIN/FC (Pin 20/Pin 17): Synchronization Input to the
Phase Detector and Forced Continuous Control Input.
Whenfloating,itsitsaround1.6V,andthecontrollerenters
discontinuous mode operation at light load. Shorting this
pin low or high for more than 20μs enables Burst Mode
operation or forced continuous current mode operation,
respectively.Duringfrequencysynchronization,thephase
locked loop will force the controller to operate in continu-
ous mode and the rising top gate signal of controller 1 to
be synchronized with the rising edge of the PLLIN signal.
When synchronization is not required, it is advisable to
bypass the PLLIN/FC pin with a 1000pF capacitor to avoid
noise coupling.
ply. See BOOST1.
BOOST2 (Pin 29/Pin 26): Channel 2 Top Gate Driver Sup-
ply. See BOOST1.
TG2 (Pin 30/Pin 27): Channel 2 Top Gate Drive. See TG1.
SW2 (Pin 31/Pin 28): Channel 2 Switching Node.
See SW1.
SW1 (Pin 32/Pin 29): Channel 1 Switching Node. The (–)
terminal of the bootstrap capacitor connects here. This
pin swings from a Schottky diode (external) voltage drop
below ground to V (where V is the external MOSFET
IN
IN
supply rail).
CLKOUT (Pin 18 UHF Only): CLK Output. Output clock
signal available to synchronize other controller ICs for
additional MOSFET controller stages/phases.
TG1 (Pin 33/Pin 30): Channel 1 Top Gate Drive. The TG1
pin drives the top N-channel MOSFET with a voltage
swing equal to V superimposed on the switch node
BG3 (Pin 21/Pin 19): Channel 3 Bottom Gate Drive. See
BG1.
DR
voltage SW.
PGND (Pin 22/Pin 39): Driver’s Power Ground. This pin
BOOST1(Pin34/Pin31):Channel1TopGateDriverSupply.
The (+) terminal of the bootstrap capacitor connects here.
This pin swings from approximately V up to V + V
connects directly to the sources of the bottom N-channel
externalMOSFETsandthe(–)terminalsofC .Thebackside
IN
DR
IN
DR
exposed pad (QFN) must be soldered to PCB ground.
(where V is the external MOSFET supply rail).
IN
V
(Pin23/Pin20):DriverSupply.Providessupplytothe
DR
PGOOD (Pin 35/Pin 32): Open Drain Power Good Output.
This open-drain output is pulled low during shutdown or
when any of the three output voltages has been outside
the PGOOD tolerance window for more than 100μs.
drivers for the bottom gates. Also used for charging the
bootstrap capacitors. This pin needs to be very carefully
and closely decoupled to the IC’s PGND pin. If the V
DR
potential is lower than V potential by 1V, the drivers
CC
PHASEMD (Pin 36/Pin 33): Phase Select Input. This pin
controls the phase relationship between controller 1,
controller 2, controller 3 and CLKOUT. When PHASEMD
is floating, its value is around 1.6V, the three channels
switch 120° out of phase, and CLKOUT synchronizes to
the rising edge of TG1. When PHASEMD is grounded,
TG1 leads CLKOUT by 60°. When PHASEMD is shorted
will be disabled.
BG2 (Pin 24/Pin 21): Channel 2 Bottom Gate Drive. See
BG1.
BG1(Pin25/Pin22):Channel1BottomGateDrive. Drives
thegateofthebottomN-channelMOSFETbetweenground
and V .
DR
to V , TG1 leads TG2, TG3, and CLKOUT by 90°, 270°
SW3 (Pin 26/Pin 23): Channel 3 Switching Node. See
SW1.
CC
and 180°, respectively.
TG3 (Pin 27/Pin 24): Channel 3 Top Gate Drive. See
TG1.
3773fb
11
LTC3773
FUNCTIONAL DIAGRAM
PLLIN/FC
PLLFLTR
CLKOUT PHASEMD
PHASE DET
F
IN
R
LP
C
LP
PGOOD
+
–
CH3 PBAD
CH2 PBAD
CLK3
CLK2
–
+
100
s
OSCILLATOR
ENABLE
BURST
DELAY
V
V
IN
DR
CH1 PBAD
3V
1V
DUPLICATE FOR CH2 AND CH3
FORCE CONT
FORCE BOT
BOOST
TG
D
B
DROP
OUT
DET
C
B
CLK1
+
TOP
C
IN
BOT
Q
TOP ON
SW
S
R
SWITCH
LOGIC
+
–
+
–
Q
V
DR
SHDN
SLEEP
RS
LATCH
0.5V
0.54V
0.66V
OV
+
0.6225V
–
+
BG
V
FB
BOT
CC
–
V
V
CC
CC
PGND
V
–
+
–
I
I
–
+ +
–
1
2
+
–
EA
+
L
+
–
SENSE
3mV
+
–
SLOPE
COMP
36k
36k
R
SENSE
SENSE
5.3 x V
FB
0.645V
TRACK
0.6V
C
OUT
+
54k
54k
1.8V
+
2.4V
SLOPE
COMP
V
I
OUT
TH
R2
R1
CH1
0.6V
CH3
SHDN
CH2
V
V
CC
CC
+
SHDN
SHDN
3.94V
MASTER
SHDN
UV
–
RESET
V
CC
V
REF
V
DR
V
CC
INTERNAL
SUPPLY
C
+
+
–
+
C
–
–
SHDN
DRV
+
SDB2
SDB3
C
VCC
R
C
2.4V
1.8V
1.2V
3773 F01
SDB3
SDB2
SDB1
SGND
Figure 1. Functional Diagram
3773fb
12
LTC3773
(Refer to the Functional Diagram)
OPERATION
Main Control Loop
Thestart-upofV
iscontrolledbytheLTC3773’sTRACK
OUT
pin. An external capacitor at the TRACK pin provides the
The LTC3773 uses a constant frequency, current mode
step down architecture. During normal operation, each
top MOSFET is turned on each cycle when the oscillator
sets the RS latch, and turned off when the main current
soft-start function. During soft-start, the error amplifier
EA compares the feedback signal, V , to the TRACK pin’s
FB
potential(insteadofthe0.6Vreference),whichriseslinearly
from 0V to 0.6V. This allows the output voltage to rise
smoothlyfrom0Vtoitsfinalvaluewhilemaintainingcontrol
of the inductor current. When the potential at the TRACK
pin approaches the 0.6V reference voltage, the control
comparator, I , resets the RS latch. The peak inductor
1
current at which I resets the RS latch is controlled by
1
the voltage on the I pin, which is the output of the error
TH
amplifierEA.Theerroramplifierinputpin,V ,receivesthe
FB
loop servos V to the internal reference. The TRACK pin
FB
output voltage feedback signal from an external resistor
divider. This feedback signal is compared to the internal
0.6V reference voltage by the EA. When the load current
can also be used for power up/down tracking. A resistor
divider on V
connected to the TRACK2/TRACK3 pin
OUT1
allows the startup of V
/V
to track that of V
increases it causes a slight decrease in V relative to the
0.6V reference, which in turn causes the I voltage to
OUT2 OUT3 OUT1
FB
(refer to the Soft-Start/Tracking section for more detail).
TH
increase until the average inductor current matches the
new load current. While the top N-channel MOSFET is off,
thebottomN-channelMOSFETisturnedonuntileitherthe
next cycle begins or the inductor current starts to reverse,
Low Current Operation
The PLLIN/FC pin is a multifunction pin: 1) an external
clock input for PLL synchronization, and 2) a logic input
to select between three modes of operation.
as indicated by the current reversal comparator, I .
2
The top MOSFET drivers are biased from floating boot-
A) Continuous Current Operation: When the PLLIN/FC
pin voltage is above 3V or driven by an external oscil-
lator, the controller performs as a continuous, PWM
current mode synchronous switching regulator. The
top and bottom MOSFETs are alternately turned on to
maintain the output voltage independent of direction
of inductor current. This is the least efficient light load
operating mode, but has lowest output ripple. The
output can source or sink current in this mode. When
sinking current while in forced continuous operation,
the controller can cause current to flow back into the
input supply filter capacitor. Be sure to use an input
capacitor with enough capacitance to prevent the input
strap capacitor C , which is normally recharged during
B
each off cycle through an external Schottky diode. When
V
decreases to a voltage close to V , however, the
IN
OUT
loop may enter dropout and attempt to turn on the top
MOSFET continuously. The dropout detector counts the
number of oscillator cycles that the bottom MOSFET
remains off and periodically triggers a brief refresh pulse
to recharge C .
B
Shutdown, Soft-Start and Tracking Startup
The main control loop is enabled by allowing the SDBn pin
to go high. In the G package, SDB1, SDB2 and SDB3 are
shorted together at the SDB pin. The power-up thresholds
for channels 1, 2 and 3 are set at 1.2V, 1.8V and 2.4V
respectively. By forcing the SDB1, SDB2 and SDB3 pins
below0.4V, theICenterslowcurrentshutdownmode, and
the chip draws less than 30μA. Releasing SDBn allows an
internal 0.5μA current source to pull up the SDBn pin. If
voltage from boosting too high. See C and C
Se-
IN
OUT
lection in the Applications Information section. Certain
applications must not allow continuous operation at
startup with prebiased output or power down; this can
be easily avoided by shorting the PGOOD output to the
PLLIN/FC pin. The controller will be forced to operate
in Burst Mode until all three outputs are within 10ꢀ
of their nominal values.
a resistive divider connected to V drives the SDB pin,
IN
the controller will automatically start up when V is fully
IN
powered up.
B) Burst Mode Operation: When the PLLIN/FC pin volt-
age is below 1V and the regulated output voltage is
within 10ꢀ of its nominal value, the controller behaves
3773fb
13
LTC3773
(Refer to the Functional Diagram)
OPERATION
as a Burst Mode switching regulator. Burst Mode op-
eration clamps the minimum peak inductor current to
approximately 20ꢀ of the current limit programmed
When PLLIN/FC is not being driven by an external clock
source, the PLLFLTR can be floated, tied to V or SGND
CC
to select 400kHz, 560kHz or 220kHz switching frequency,
respectively.
by R
. As the load current goes down, the EA will
SENSE
reduce the voltage on the I pin. When the I voltage
TH
TH
Power Good
drops below 0.5V, the internal SLEEP signal goes high
and both external MOSFETs are turned off.
The PGOOD pin is connected to the drain of an internal
N-channel MOSFET. The MOSFET is turned on under
shutdown state or if any regulator output voltage has
been away from its nominal value by greater than 10ꢀ
for more than 100μs. To shut off this MOSFET, all three
regulatoroutputvoltagesmustbewithinthe 10ꢀwindow
for more than 100μs.
In Burst Mode operation, the load current is supplied
by the output capacitor. As the output voltage falls,
the I voltage rises. When the I voltage reaches
TH
TH
0.55V, the SLEEP signal goes low and the controller
resumes normal operation by turning on the external
top MOSFET at the next cycle of the internal oscillator.
During Burst Mode operation, the inductor current is
not allowed to reverse.
Short-Circuit Protection and Current Foldback
Uponstart-up, thesoft-startactionattheTRACKpinlimits
the inrush current from the input power source; yet the
controller provides the maximum rated output current to
charge up the output capacitor as quickly as possible. If
TRACK ramps above 0.54V but the output voltage is less
than 70ꢀ of its nominal value, foldback current limiting is
activated on the assumption that the output is in a severe
overcurrent and/or short-circuit condition.
C) Discontinuous Mode Operation: When the PLLIN/FC
pin is floating, Burst Mode operation is disabled but
the inductor current is not allowed to reverse. The 20ꢀ
minimuminductorcurrentclamppresentinBurstMode
operation is removed, providing constant frequency
discontinuousoperationoverthewidestpossibleoutput
currentrange. Thisconstantfrequencyoperationisnot
quiteasefficientasBurstModeoperation,butprovides
a lower noise, constant frequency spectrum.
Output Overvoltage Protection
Frequency Synchronization
As a further protection, the overvoltage comparator (OV)
guardsagainsttransientovershoots,aswellasothermore
serious conditions that may overvoltage the output. When
Theselectionofswitchingfrequencyisatradeoffbetween
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
the feedback voltage on the V pin has risen 3.75ꢀ above
FB
the reference voltage of 0.6V, the top gate is turned off
and the bottom gate is turned on until the overvoltage is
cleared.
The phase-locked loop allows the internal oscillator to be
synchronized to an external source using the PLLIN/FC
pin. The output of the phase detector at the PLLFLTR pin is
alsotheDCfrequencycontrolinputoftheoscillator, which
operates over a 160kHz to 700kHz range corresponding
to a voltage input from 0V to 2.5V. When locked, the PLL
aligns the turn on of the controller 1 top MOSFET to the
rising edge of the synchronizing signal.
Undervoltage Lockout
To prevent operation of the external MOSFETs below safe
V
supplylevels,anundervoltagelockoutisincorporated
CC
in the LTC3773. When V drops below 3.9V, the MOSFET
CC
driversandallinternalcircuitryareturnedoffexceptforthe
undervoltage block and SDB input circuitry. If V is lower
DR
than V by more than 1V, the drivers are disabled.
CC
3773fb
14
LTC3773
APPLICATIONS INFORMATION
frequency and increases with higher V or V
:
The basic application circuit is shown on the first page
of this data sheet. External component selection is
driven by the load requirement, and normally begins
with the selection of an inductance value based upon the
desired operating frequency, inductor current and output
voltageripplerequirements. Oncetheinductorsandoper-
ating frequency have been chosen, the current sensing
resistorscanbecalculated. Next, thepowerMOSFETsand
IN
OUT
ꢁ
OUT ꢄ
V
VOUT
(f)(L)
ꢀIL =
1–
ꢃ
ꢆ
V
ꢂ
ꢅ
IN
Accepting larger values of ΔI allows the use of low in-
L
ductances, but results in higher output voltage ripple and
greater core losses. A reasonable starting point for setting
ripple current is ΔI = 0.3 to 0.6 (I
). Remember, the
L
MAX
Schottky diodes are selected. Finally, C and C
are
IN
OUT
maximum ΔI occurs at the maximum input voltage. The
L
selected according to the required voltage ripple require-
ments. The circuit on the front page can be configured for
operation up to a MOSFET supply voltage of 36V (limited
inductor value also has an effect on low current operation.
The transition to low current operation begins when the
inductor current reaches zero while the bottom MOSFET
is on. Burst Mode operation begins when the average
inductor current required results in a peak current below
by the external MOSFETs, V capacitor voltage rating and
IN
possibly the minimum on-time).
20ꢀ of the current limit determined by R
. Lower
SENSE
Operating Frequency and Synchronization
inductor values (higher ΔI ) will cause this to occur at
L
higher load currents, which can cause a dip in efficiency
in the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
The choice of operating frequency, f , is a trade-off
OSC
betweenefficiencyandcomponentsize.Lowfrequencyop-
erationimprovesefficiencybyreducingMOSFETswitching
losses,bothgatechargelossandtransitionloss.However,
lower frequency operation requires more inductance for a
given amount of ripple current. The internal oscillator for
eachoftheLTC3773’scontrollersrunsatanominal400kHz
frequency when the PLLFLTR pin is left floating and the
PLLIN/FC pin input is not switching. Pulling PLLFLTR to
Inductor Core Selection
Once the inductance value is determined, the type of in-
ductor must be selected. Actual core loss is independent
of core size for a fixed inductor value, but it is very de-
pendent on inductance selected. As inductance increases,
corelossesgodown. Unfortunately, increasedinductance
V
CC
selects 560kHz operation; pulling PLLFLTR to SGND
selects 220kHz operation. Alternatively, the LTC3773 will
phase-lock to a clock signal applied to the PLLIN/FC pin
withafrequencybetween160kHzand700kHz(seePhase-
Locked Loop and Frequency Synchronization).
2
requires more turns of wire and therefore copper (I R)
losses will increase.
Ferritedesignshaveverylowcorelossandarepreferredat
high switching frequencies, so designers can concentrate
Inductor Value Calculation
2
on reducing I R loss and preventing saturation. Ferrite
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFETgate-chargelosses.Inadditiontothisbasictrade-
off, the effect of inductor value on ripple current and low
current operation must also be considered. The inductor
value has a direct effect on ripple current. The inductor
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Differentcorematerialsandshapeswillchangethesize/cur-
rent and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and do not radiate much energy, but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
3773fb
ripple current ΔI decreases with higher inductance or
L
15
LTC3773
APPLICATIONS INFORMATION
mainly depends on the price vs size requirements and any
radiatedfield/EMIrequirements.Newdesignsforhighcur-
rentsurfacemountinductorsareavailablefromnumerous
manufacturers, including Coiltronics, Vishay, TDK, Pulse,
Panasonic, Vitec, Coilcraft, Toko and Sumida.
a combination of several components but can be taken
fromthetypical“gatecharge”curveincludedonmostdata
sheets as shown in Figure 2. The curve is generated by
forcing a constant input current into the gate of a common
source, current source loaded stage and then plotting the
gatevoltageversustime.Theinitialslopeistheeffectofthe
gate-to-source and the gate-to-drain capacitance. The flat
portionofthecurveistheresultoftheMillermultiplication
effectofthedrain-to-gatecapacitanceasthedraindropsthe
voltage across the current source load. The upper sloping
line is due to the drain-to-gate accumulation capacitance
and the gate-to-source capacitance.
Power MOSFET and Schottky Diode Selection
At least two external power MOSFETs must be selected for
each of the three output sections: One N-channel MOSFET
for the top (main) switch and one or more N-channel
MOSFET(s) for the bottom (synchronous) switch. The
number, type and on-resistance of all MOSFETs selected
take into account the voltage step-down ratio as well as
the actual position (main or synchronous) in which the
MOSFET will be used. A much smaller and much lower
input capacitance MOSFET should be used for the top
MOSFET in applications that have an output voltage that
is less than 1/3 of the input voltage. In applications where
The Miller charge (the increase in coulombs on the hori-
zontal axis from A to B while the curve is flat) is specified
for a given V drain voltage, but can be adjusted for
DS
different V voltages by multiplying by the ratio of the
DS
application V to the curve specified V values. A way
DS
DS
to estimate the C
term is to take the change in gate
MILLER
charge from points A and B on a manufacturers data sheet
V >> V , the top MOSFETs’ on-resistance is normally
IN
OUT
and divide by the stated V voltage specified. C
DS
MILLER
less important for overall efficiency than its input capaci-
tance at operating frequencies above 300kHz. MOSFET
manufacturershavedesignedspecialpurposedevicesthat
provide reasonably low on-resistance with significantly
reduced input capacitance for the main switch application
in switching regulators.
is the most important selection criterion for determining
the transition loss term in the top MOSFET but is not di-
rectly specified on MOSFET data sheets. C
and C are
RSS
OS
specified sometimes but definitions of these parameters
are not included.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
The peak-to-peak MOSFET gate drive levels are set by
the driver supply voltage, V , requiring the use of logic-
DR
VOUT
level threshold MOSFETs in most applications. Pay close
Main Switch Duty Cycle =
attention to the BV
specification for the MOSFETs as
V
DSS
IN
well; many of the logic-level MOSFETs are limited to 30V
V – VOUT
IN
Synchronous SwitchDuty Cycle=
or less.
V
IN
Selection criteria for the power MOSFETs include the on-
The power dissipation for the main and synchronous
MOSFETs at maximum output current is given by:
resistance R
, input capacitance, input voltage and
DS(ON)
maximum output current. MOSFET input capacitance is
V
V
OUT (IMAX2)(1+ ꢀ)RDS(ON)
+
V
IN
PMAIN
=
IN
+
–
2 I
MAX (RDR)(CMILLER)•
V
IN
MILLER EFFECT
2
V
GS
ꢁ
ꢃ
ꢂ
ꢄ
ꢆ
ꢅ
A
B
1
1
+
–
V
+
DS
+
(f)
V
GS
V
ꢃ DR – VTH(IL) VTH(IL) ꢆ
–
Q
IN
= (Q – Q )/V
C
3773 F02
MILLER
B
A
DS
V – V
IN
PSYNC
=
OUT (IMAX2)(1+ ꢀ)RDS(ON)
Figure 2. MOSFET Miller Capacitance
V
IN
3773fb
16
LTC3773
APPLICATIONS INFORMATION
where δ is the temperature dependency of R
, R
ment. Increasing the output current drawn from the other
controller will actually decrease the input RMS ripple cur-
rent from its maximum value. The out-of-phase technique
typically reduces the input capacitor’s RMS ripple current
by a factor of 30ꢀ to 70ꢀ when compared to a single
phase power supply solution.
DS(ON) DR
is the effective top driver resistance (approximately 2Ω
at V = V ), and V is the drain potential and the
GS
MILLER
IN
change in drain potential in the particular application.
is the typical gate threshold voltage shown in the
V
TH(IL)
power MOSFET data sheet at the specified drain current.
isthecalculatedcapacitanceusingthegatecharge
C
MILLER
The type of input capacitor, value and ESR rating have ef-
ficiency effects that need to be considered in the selection
process.Thecapacitancevaluechosenshouldbesufficient
tostoreadequatechargetokeephighpeakbatterycurrents
down. The ESR of the capacitor is important for capacitor
power dissipation as well as overall battery efficiency. All
the power (RMS ripple current • ESR) not only heats up
the capacitor but wastes power from the battery.
curve from the MOSFET data sheet and the technique
described above.
2
BothMOSFETshaveI RlosseswhilethetopsideN-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V < 12V,
IN
the high current efficiency generally improves with larger
MOSFETs, while for V > 12V the transition losses rapidly
IN
increasetothepointthattheuseofahigherR
device
DS(ON)
Medium voltage (20V to 35V) ceramic, tantalum, OS-CON
and switcher-rated electrolytic capacitors can be used as
input capacitors, but each has drawbacks: ceramics have
high voltage coefficients of capacitance and may have
audible piezoelectric effects; tantalums need to be surge
rated; OS-CONs suffer from higher inductance, larger
case size and limited surface mount applicability; and
electrolytics’ higher ESR and dry out possibility require
severaltobeused.SanyoOS-CONSVP,SVPDseries;Sanyo
POSCAP TQC series or aluminum electrolytic capacitors
from Panasonic WA series or Cornell Dubilier SPV series,
in parallel with a couple of high performance ceramic ca-
pacitors, can be used as an effective means of achieving
low ESR and large bulk capacitance. Multiphase systems
allow the lowest amount of capacitance overall. As little
as one 22μF or two to three 10μF ceramic capacitors are
an ideal choice in 20W to 35W power supplies due to their
extremely low ESR. Even though the capacitance at 20V
is substantially below their rating at zero-bias, very low
ESR loss makes ceramics an ideal candidate for highest
efficiency battery operated systems.
withlowerC
actuallyprovideshigherefficiency.The
MILLER
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
a short-circuit when the synchronous switch is on close
to 100ꢀ of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R
vs temperature curve, but
DS(ON)
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The Schottky diodes in Figure 1 conduct during the dead
time between the conduction of the two large power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on, storing charge during the dead
time and requiring a reverse recovery period which could
cost as much as several percent in efficiency. A 2A to 8A
Schottky is generally a good compromise for both regions
of operation due to the relatively small average current.
Larger diodes result in additional transition loss due to
their larger junction capacitance.
Incontinuousmode, thesourcecurrentofthetopN-chan-
C and C
Selection
IN
OUT
nel MOSFET is a square wave of duty cycle V /V . To
OUT IN
The selection of C is simplified by the 3-phase architec-
IN
prevent large voltage transients, a low ESR input capaci-
tor sized for the maximum RMS current of one channel
must be used. The maximum RMS capacitor current is
given by:
ture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can
be shown that the worst-case capacitor RMS current oc-
curs when only one controller is operating. The controller
VOUT(V – VOUT
)
with the highest (V )(I ) product needs to be used to
determine the maximum RMS capacitor current require-
IN
OUT OUT
IRMS ꢀIOUT(MAX)
V
IN
3773fb
17
LTC3773
APPLICATIONS INFORMATION
This formula has a maximum value at V = 2V , where
The first condition relates to the ripple current into
the ESR of the output capacitance while the second
term guarantees that the output capacitance does not
significantly discharge during the operating frequency
period due to ripple current. The choice of using smaller
outputcapacitanceincreasestheripplevoltageduetothe
discharging term but can be compensated for by using
capacitors of very low ESR to maintain the ripple voltage
IN
OUT
I
= I /2. This simple worst-case condition is com-
RMS
OUT
monlyusedfordesignbecauseevensignificantdeviations
donotoffermuchrelief.Notethatcapacitormanufacturer’s
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the capaci-
tor, or to choose a capacitor rated at a higher temperature
than required. Several capacitors may also be paralleled
to meet size or height requirements in the design. Always
consult the manufacturer if there is any question.
at or below 50mV. The I pin OPTI-LOOP compensation
TH
components can be optimized to provide stable, high
performance transient response regardless of the output
capacitors selected.
The benefit of the LTC3773 multiphase clocking can be
calculated by using the equation above for the highest
power controller and then calculating the loss that would
have resulted if all three channels switched on at the same
time.ThetotalRMSpowerlostislowerwhentriplecontrol-
lers are operating due to the interleaving of current pulses
through the input capacitor’s ESR. This is why the input
capacitance requirement calculated above for the worst-
case controller is adequate for the triple controller design.
Remember that input protection fuse resistance, battery
resistance and PC board trace resistance losses are also
reduced due to the reduced peak currents in a multiphase
system.Theoverallbenefitofamultiphasedesignwillonly
be fully realized when the source impedance of the power
supply/battery is included in the efficiency testing. The
drains of the three top MOSFETs should be placed within
Manufacturers such as Sanyo, Panasonic and Cornell
Dubilier should be considered for high performance
through-hole capacitors. The OS-CON semiconductor
electrolyte capacitor available from Sanyo has a good
(ESR)(size) product. An additional ceramic capacitor in
parallelwithOS-CONcapacitorsisrecommendedtooffset
the effect of lead inductance.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the relevant ESR or transient
current handling requirements. Aluminum electrolytic
and dry tantalum capacitors are both available in surface
mount configurations. New special polymer surface
mount capacitors offer very low ESR also but have much
lower capacitive density per unit volume. In the case of
tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. Several excellent
outputcapacitorchoicesaretheSanyoPOSCAPTPD,TPE,
TPF, AVX TPS, TPSV, the Kemet T510 series of surface
mount tantalums, Kemet AO-CAPs or the Panasonic SP
series of surface mount special polymer capacitors avail-
able in case heights ranging from 2mm to 4mm. Other
capacitor types include Nichicon PL series and Sprague
595D series. Consult the manufacturers for other specific
recommendations.
1cmofeachotherandshareacommonC (s). Separating
IN
the drains and C may produce undesirable voltage and
IN
current resonances at V .
IN
The selection of C
is driven by the required effective
OUT
series resistance (ESR). Typically once the ESR require-
ment is satisfied the capacitance is adequate for filtering.
The output ripple (ΔV ) is determined by:
OUT
ꢂ
ꢅ
1
ꢀVOUT ꢁ ꢀIL ESR+
ꢄ
ꢇ
8 • f •C
ꢃ
OUT ꢆ
Where f = operating frequency, C
= output capacitance,
OUT
R
SENSE
Selection for Output Current
and ΔI = ripple current in the inductor. The output ripple is
L
highest at maximum input voltage since ΔI increases with
L
Oncethefrequencyandinductorhavebeenchosen,R
SENSE
input voltage. With ΔI = 0.3I
the output ripple will
L
OUT(MAX)
isdeterminedbasedontherequiredpeakinductorcurrent.
typically be less than 50mV at maximum V assuming:
IN
The current comparator has a typical maximum threshold
of 75mV/R
and an input common mode range of
CC
COUT Recommended ESR <2RSENSE
SENSE
SGND to (1.1) • V . The current comparator threshold
1
and COUT
>
sets the peak inductor current, yielding a maximum aver-
(8 • f •RSENSE
)
3773fb
18
LTC3773
APPLICATIONS INFORMATION
V
IN
age output current I
equal to the peak value less half
MAX
R
Z
2k
the peak-to-peak ripple current, ΔI .
+
L
C
IN
100Ω
Allowing a margin for variations in the IC and external
component values yields:
Q1
D
B
BOOST
TG
C
B
55mV
IMAX
QT
RSENSE
=
R
L
SENSE
V
SW
OUT
V
Z
6.8V
+
BG
C
QB
OUT
D1
The IC works well with values of R
from 0.002Ω to
SENSE
LTC3773
0.1Ω.
V
DR
+
+
0.1μF
0.1μF
10μF
10μF
Slope Compensation and Inductor Peak Current
PGND
10Ω
Slope compensation provides stability in constant fre-
quency architectures by preventing subharmonic oscilla-
tions at duty cycles greater than 50ꢀ. It is accomplished
internally by adding a compensating ramp to the inductor
current signal at duty cycles in excess of 40ꢀ. Normally,
at the maximum duty cycle, with slope compensation, the
maximum inductor peak current is reduced by more than
50ꢀ, reducing the maximum output current at high duty
cycleoperation.However,theLTC3773’sslopecompensa-
tion recovery is implemented to allow 70ꢀ rated inductor
peak current at the maximum duty cycle.
V
CC
SGND
Q1: ZETEX FZT603
V : ON SEMI MM5Z6V8ST1
3773 F03
Z
Figure 3. LTC3773 VCC and VDR Power Supplies
Topside MOSFET Driver Supply (C , D )
B
B
External bootstrap capacitors, C , connected to the
B
BOOST pins, supply the gate drive voltages for the topside
MOSFETs.CapacitorC inFigure3ischargedthoughdiode
B
D from V when the SW pin is low. When the topside
B
DR
MOSFETs turns on, the driver places the C voltage across
B
V
and V Power Supplies
DR
CC
the gate-source of the desired MOSFET. This enhances
Power for the top and bottom MOSFET drivers is derived
the MOSFET and turns on the topside switch. The switch
fromtheV pin;theinternalcontrollercircuitryisderived
node voltage, SW, rises to V and the BOOST pin follows.
DR
IN
from the V pin. Under typical operating conditions, the
With the topside MOSFET on, the boost voltage is above
CC
totalcurrentconsumptionatthesetwopinsshouldbewell
below100mA. Hence, V andV canbeconnectedtoan
the input supply (V
= V + V ). The value of the
BOOST
DR IN
boost capacitor C needs to be 30 to 100 times that of the
DR
CC
B
externalauxiliary5Vpowersupply. Ifanauxiliarysupplyis
not available, a simple zener diode and a darlington NPN
buffer can be used to power these two pins as shown in
Figure 3. To prevent switching noise from coupling to the
total gate charge capacitance of the topside MOSFET(s)
as specified on the manufacturer’s data sheet. The reverse
breakdown of D must be greater than V
.
B
IN(MAX)
Regulator Output Voltage
sensitive analog control circuitry, V should have a 1μF
CC
bypasscapacitor,atleast,closetothedevice.TheBiCMOS
The regulator output voltages are each set by an external
feedbackresistivedividercarefullyplacedacrosstheoutput
capacitor. The resultant feedback signal is compared with
the internal precision 0.6V voltage reference by the error
amplifier. The output voltage is given by the equation:
process that allows the LTC3773 to include large on-chip
MOSFET drivers also limits the maximum V and V
DR
CC
voltage to 7V. This limits the practical maximum auxiliary
supply to a loosely regulated 7V rail. If V drops below
CC
3.9V, LTC3773 goes into undervoltage lockout; if V
DR
R2
R1
ꢀ
ꢃ
ꢄ
drops below V by more than 1V, the driver outputs are
CC
VOUT = 0.6V 1+
ꢂ
ꢅ
ꢁ
disabled.
where R1 and R2 are defined in Figure 1.
3773fb
19
LTC3773
APPLICATIONS INFORMATION
SENSE /SENSE Pins
+
–
small external capacitor larger than 100pF at the SDB pin
reduces the slew rate at the node, permitting the internal
circuit to settle before actual conversion begins.
The common mode input range of the current compara-
tor sense pins is from 0V to (1.1)V . Continuous linear
CC
operation is guaranteed throughout this range allowing
LTC3773 can be easily configured to produce a sequential
power up/down supply. By adding an external capacitor
at the SDB pin; or by controlling the SDB input voltage,
channel 1 will be powered up first, followed by channel
2 and sequentially channel 3. The channel turn on time
delay is determined by the SDB capacitor value. Figure 4
shows the sequential power up/down configuration and
its waveform. The capacitor at the TRACK pins control
the individual channel power up slew rate.
output voltage setting from 0.6V to 7.7V, depending upon
the voltage applied to V . A differential NPN input stage
CC
is biased with internal resistors from an internal 2.4V
source as shown in Figure 1. This requires that current
either be sourced or sunk from the SENSE pins depending
on the regulator output voltage. If the output voltage is
below 2.4V, current will flow out of both SENSE pins to
the main output. The output can be easily preloaded by
the V
resistive divider to compensate for the current
OUT
LTC3773
comparator’s negative input bias current. The maximum
TRACK1
TRACK2
TRACK3
current flowing out of each pair of SENSE pins is:
RAMP
SOURCE
2.4V – VOUT
ISENSE+ +ISENSE– = 2•
60k
SDB1
SDB2
SDB3
C
SLEW
1MΩ
10k
C
SS
Since V is servoed to the 0.6V reference voltage, we
FB
POWER
DOWN
0V TO 2V
can choose R1 in Figure 1 to have a maximum value to
absorb this current.
ꢀ
ꢃ
0.6V
2.4V – V
R1(MAX) = 30k
for VOUT <2.4V
ꢂ
ꢅ
ꢁ
OUT ꢄ
SDB
1V/DIV
Regulating an output voltage of 1.8V, the maximum value
of R1 should be 30k. Note that for an output voltage above
2.4V, R1 has no maximum value necessary to absorb the
2.5V V
1.8V V
1.2V V
1V/DIV
1V/DIV
1V/DIV
OUT1
OUT2
OUT3
sense currents; however, R1 is still bounded by the V
feedback current.
FB
0.1s/DIV
3773 F04
Power Up from Shutdown
Figure 4. Sequential Power Up/Down
If the SDB1, SDB2 and SDB3 pins are forced below 0.4V,
the IC enters low current shutdown mode. Under this
condition, most of the internal circuit blocks, including
the reference, are disabled. The supply current drops to a
typical value of 20μA. Disconnecting the external applied
voltage source allows an internal 0.5μA current source to
pull up the SDBn pin. Once the voltage at any of the SDB
pins is above the shutdown threshold, the reference and
the internal biasing circuit wake up. When the voltage at
theSDBnpingoesaboveitspower-upthreshold, itsdriver
startstotoggle.Thepower-upthresholdsforchannels1,2
and 3 are set at 1.2V, 1.8V and 2.4V respectively. Adding a
Soft-Start/Tracking
When the voltage on the TRACK pin is less than the
internal 0.6V reference, the LTC3773 regulates the V
FB
voltage to the TRACK pin voltage instead of 0.6V. After
the soft-start/tracking cycle, the TRACK pin voltage must
be higher than 0.8V; otherwise, the tracking circuit intro-
duces offset in the error amplifier and the switcher output
will be regulated to a slightly lower potential. If tracking is
not required, a soft-start capacitor should be connected
to the TRACK pin to regulate the output startup slew rate.
3773fb
20
LTC3773
APPLICATIONS INFORMATION
An internal 1μA current source pull-up at the TRACK pin
programs the output to take about 600ms/μF to reach its
steady state value. The output voltage ramp down slew
reach their steady-state values at about the same time.
If any of the channel SDB pins are asserted, its TRACK
pin will be internally pulled low and all channels will be
disabled.
rate can be controlled by the external capacitor C
SLEW
and the TRACK DOWN switch as shown in Figure 5a
and 5b.
To implement coincident tracking, connect extra resistor
dividerstotheoutputofchannel1.Theseresistordividers
With a simple configuration, TRACK allows V
start-
are selected to be the same as the V dividers across
OUT
FB
up to track the master channel as shown qualitatively
in Figures 5a and 5b. The LTC3773 can be configured
for two different up/down tracking modes:coincident or
ratiometric.
the outputs of channels 2 and 3. TRACK2 and TRACK3
are connected to these extra resistor dividers as shown
in Figure 5b. In this tracking scheme, V
must be set
OUT1
higher than V
and V
. The coincident configura-
OUT2
OUT3
tion produces the same slew rate at the three outputs,
so that the lowest output voltage channel reaches its
steady state first.
ToimplementtheratiometrictrackingshowninFigure5a,
no extra divider is needed; simply connect the TRACK2
and TRACK3 pins to the TRACK1 pin. Do not connect
TRACK to the V pin. With a ratiometric configuration,
The TRACK pin 1μA internal pull-up current performs the
soft-start action, but in tracking mode it introduces an
error term in the resistive divider. To minimize this error,
build the resistive divider with smaller value resistors, or
FB
the LTC3773 produces three different output slew rates.
Because each channel’s slew rate is proportional to its
corresponding output voltage, the three output voltages
MASTER
OUT
V
OUT1
V
V
OUT1
V
OUT2
V
OUT2
R22
RM2
R12
R22
R12
V
V
FB1
LTC3773
FB2
V
V
FB1
FB2
FB3
MASTER
OUT
R11
RM1
R11
R21
R21
TRACK2
TRACK3
TRACK1
V
LTC3773
R22
R21
V
OUT3
V
OUT3
TRACK2
TRACK3
TRACK1
R12
R32
R32
V
FB3
V
R32
R31
RAMP
SOURCE
R31
3773 F04a
C
SLEW
R31
R11
1MΩ
TRACK
DOWN
C
10k
RAMP
SOURCE
SS
C
SLEW
3773 F05b
0V TO 2V
C
SS
1MΩ
TRACK
10k
DOWN
0V TO 2V
TRACK 1
1V/DIV
TRACK 1
0.5V/DIV
2.5V V
1.8V V
1.2V V
1V/DIV
1V/DIV
1V/DIV
OUT1
OUT2
OUT3
2.5V V
1.8V V
1.2V V
1V/DIV
1V/DIV
1V/DIV
OUT1
OUT2
OUT3
3773 F05b
0.1s/DIV
0.1s/DIV
3773 F05a
Figure 5a. Ratiometric Tracking. TRACK1 Functions
as a Soft-Start Pin; VOUT2 and VOUT3 Track VOUT1
with Ratiometric Start-Up Slew Rate
Figure 5b. Coincident Tracking. TRACK1 Functions
as a Soft-Start Pin; VOUT2 and VOUT3 Track VOUT1
with the Same Start-Up Slew Rate
3773fb
21
LTC3773
APPLICATIONS INFORMATION
stays at 75mV and the regulator current limit remains at
its rated value. This feature allows the LTC3773 to power
the core and I/O of low voltage FPGAs.
add an extra tracking resistive divider. When the tracking
resistivedividerinputisgrounded,thepull-upcurrentflow-
ing through the network could produce a small unwanted
offset at the TRACK pin, forcing the controller to create
an unwanted low voltage supply at the regulator output.
To compensate for this error, the LTC3773 introduces a
30mV offset in the tracking circuit, which disables the
driver until the potential at the TRACK pin is above 30mV.
The magnitude of this offset diminishes as the potential
at the TRACK pin approaches 100mV, allowing accurate
tracking after startup.
When power is first applied to an FPGA, the device can
draw current several times its normal operating current.
This power-on surge current is due to the programmable
nature of FPGAs. When the FPGA powers up, before ini-
tialization, the RAM cells are briefly in a random state. This
results in contention at the interconnect and significant
power dissipation. The duration of the power-on surge
current is typically quite brief but can cause problems
for power supply designs. LTC3773 views currents that
are outside the normal operation range as possible short-
circuits. Disabling the current foldback at startup allows
the regulator to provides a higher surge current to meet
the FPGA’s requirement. Nevertheless, when calculating
the current sense resistor value for FPGA power supply
applications, the computed output current value must be
higher than the power-on surge current to allow a proper
startup.
Fault Conditions: Current Limit and Current Foldback
The LTC3773 current comparator has a maximum sense
voltage of 75mV resulting in a maximum MOSFET cur-
rent of 75mV/R
. The maximum value of current
SENSE
limit generally occurs with the largest V at the highest
IN
ambient temperature, conditions that cause the highest
power dissipation in the top MOSFET.
The LTC3773 includes current foldback to help further
limit load current when the output is shorted to ground.
If the potential at the TRACK pin is above 0.54V and the
Fault Conditions: Overvoltage Protection
A comparator monitors the output for overvoltage
conditions. The comparator (OV) detects overvoltage
faults greater than 3.75ꢀ above the nominal output volt-
age. When this condition is sensed, the top MOSFET is
turned off and the bottom MOSFET is turned on until the
overvoltage condition is cleared. The bottom MOSFET
remains on continuously for as long as the OV condition
V
voltage falls below 70ꢀ of its nominal level, then the
FB
maximum sense voltage is progressively lowered from
75mV to 15mV. Under short-circuit conditions with very
low duty cycles, the LTC3773 will begin cycle skipping in
order to limit the short-circuit current. In this situation
the bottom MOSFET will be dissipating most of the power
but less than in normal operation. The short-circuit ripple
persists. If V
returns to a safe level, normal operation
current is determined by the minimum on-time, t
,
OUT
ON(MIN)
automatically resumes.
of the LTC3773 (less than 200ns), the input voltage and
inductor value:
Note that under extreme power-up conditions, e.g. with
high input voltage, a small inductor and a small soft-start
capacitor, once the OV comparator trips, the output volt-
age might continue to charge above the rated value until
the energy in the inductor is depleted. The peak of the
overshoot might be higher than the rated voltage of the
output capacitors.
V
L
ꢁ
IN ꢄ
ꢀIL(SC) = tON(MIN) ꢃ
ꢆ
ꢂ
ꢅ
The resulting short-circuit current is:
15mV
RSENSE
1
2
ISC
=
ꢀ ꢁIL(SC)
Phase-Locked Loop and Frequency Synchronization
Disable Current Foldback at Start-Up
The LTC3773 has a phase-locked loop (PLL) comprised of
aninternalvoltage-controlledoscillator(VCO)andaphase
detector. This allows the turn-on of the external N channel
3773fb
At start-up, if the potential at the TRACK pin is lower than
0.54V, the LTC3773 current comparator threshold voltage
22
LTC3773
APPLICATIONS INFORMATION
MOSFET of controller 1 to be locked to the rising edge of
an external clock signal applied to the PLLIN/FC pin. The
turn-on of controller 2’s/3’s external N-channel MOSFET
and CLKOUT signal are controlled by the PHASEMD
pin as showed in Table 1. Note that when PHASEMD is
forced high, controller 2 and controller 3 outputs can be
connected in parallel to produce a higher output power
voltage source.
800
700
600
500
400
300
200
100
V
= 5V
CC
Table 1. Phase Relationship between the PLLIN/FC Pin vs
Controller 1, 2, 3 Top Gate and CLKOUT Pin
0
0.5
1
1.5
2
2.5
3.0
PHASEMD
GND
CH1
CH2
CH3
CLKOUT
60 Deg
0 Deg
V
(V)
PLLFLTR
0 Deg
0 Deg
0 Deg
120 Deg
120 Deg
90 Deg
240 Deg
240 Deg
270 Deg
3773 F06b
Floating
Figure 6b. Relationship Between Oscillator Frequency
and Voltage at the PLLFLTR Pin When Synchronizing
to an External Clock
V
CC
180 Deg
The phase detector is an edge sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
A simplified Phase-Locked Loop Block Diagram is shown
in Figure 6a. The output of the phase detector is a pair of
complementary current sources that charge or discharge
the external filter network connected to the PLLFLTR pin.
The relationship between the voltage on the PLLFLTR pin
and operating frequency, when there is a clock signal ap-
plied to PLLIN/FC, is shown in Figure 6b and specified in
the Electrical Characteristics table. Note that the LTC3773
can only be synchronized to an external clock whose
frequency is within range of the LTC3773’s internal VCO,
which is nominally 160kHz to 700Hz. This is guaranteed,
over temperature and variations, to be between 200kHz
and 540kHz.
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, f , then current is sourced
OSC
continuously from the phase detector output, pulling up
the PLLFLTR pin. When the external clock frequency is
less than f , current is sunk continuously, pulling down
OSC
the PLLFLTR pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the PLLFLTR pin is
adjusted until the phase and frequency of the oscillators
are identical. At the stable operating point, the phase
detector has high impedance and the filter capacitor C
holds the voltage.
LP
The loop filter components, C and R , smooth out the
LP
LP
current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The filter
components C and R determine how fast the loop ac-
LP
LP
V
CC
quires lock. Typically R = 10k and C is 0.01μF to 0.1μF.
R
LP
LP
LP
The external clock (on the PLLIN/FC pin) input threshold
is typically 1V. Table 2 summarizes the different states in
which the PLLIN/FC and PLLFLTR pins can be used.
C
LP
PLLFLTR
PLLIN/
FC
DIGITAL
PHASE/
FREQUENCY
DETECTOR
EXTERNAL
OSCILLATOR
Table 2. PLLFLTR Pin Voltage vs Switching Frequency
OSCILLATOR
PLLFLTR
GND
PLLIN/FC
DC Voltage
DC Voltage
DC Voltage
Clock Signal
FREQUENCY
220kHz
Floating
400kHz
V
560kHz
CC
3773 F06a
RC Loop Filter
Phase-Locked
to External Clock
Figure 6a. Phase-Locked Loop Block Diagram
3773fb
23
LTC3773
APPLICATIONS INFORMATION
The LTC3773 can be configured to operate at any switch-
ing frequency within the synchronization range. Figure 7
showsasimplecircuittoachievethis.Theresistivedivider
at the PLLFLTR pin programs the LTC3773 switching
frequency according to the transfer curve of Figure 6b. By
connecting the PLLIN/FC pin to the BG1 or the CLKOUT
(UHF package only) node, the pre-set frequency selection
is disengaged and the PLLFLTR pin potential determines
the switching frequency.
ripple current at light loads. If the duty cycle drops below
the minimum on-time limit in this situation, a significant
amount of cycle skipping can occur with correspondingly
larger current and voltage ripple.
Ifanapplicationcanoperateclosetotheminimumon-time
limit, an inductor must be chosen that is low enough in
value to provide sufficient ripple amplitude to meet the
minimum on-time requirement. As a general rule, keep
the inductor ripple current for each channel equal to or
greater than 30ꢀ of I
at V
.
OUT(MAX)
IN(MAX)
PHASE
DETECTOR/
OSCILLATOR
Efficiency Considerations
V
CC
OSCILLATOR
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100ꢀ.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
V
CC
R
PLLFL2
DIGITAL
PHASE/
FREQUENCY
DETECTOR
PLLIN/FC
PLLFLTR
C
LP
BG1
R
PLLFL1
ꢀEfficiency = 100ꢀ – (L1 + L2 + L3 + ...)
CLKOUT
where L1, L2, etc. are the individual losses as a percent-
age of input power.
3773 F07
Figure 7. Fixed Frequency Adjustment
Checking Transient Response
Minimum On-Time Considerations
Minimum on-time, t , is the smallest time duration
that the IC is capable of turning on the top MOSFET. It is
determined by internal timing delays and the gate charge
of the top MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:
The regulator loop response can be checked by look-
ing at the load transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
ON(MIN)
load current. When a load step occurs, V
shifts by an
OUT
amount equal to ΔI
• ESR, where ESR is the effective
LOAD
series resistance of C . ΔI
also begins to charge or
OUT
LOAD
discharge C , generating the feedback error signal that
OUT
forces the regulator to adapt to the current change and
VOUT
return V
time, V
to its steady-state value. During this recovery
can be monitored for excessive overshoot or
tON(MIN)
<
OUT
OUT
V (f)
IN
ringing, which would indicate a stability problem. The
If the duty cycle falls below what can be accommodated
by the minimum on-time, the IC will begin to skip every
other cycle, resulting in half-frequency operation. The
output voltage will continue to be regulated, but the ripple
current and ripple voltage will increase.
availability of the I pin not only allows optimization of
TH
control loop behavior, but also provides a DC coupled and
AC filtered closed-loop response test point. The DC step,
rise time and settling at this test point truly reflects the
closed-loop response. Assuming a predominantly second
ordersystem, phasemarginand/ordampingfactorcanbe
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining
the rise time at the pin.
The minimum on-time for the IC is generally about
130ns. However, as the peak sense voltage decreases,
the minimum on-time gradually increases. This is of par-
ticular concern in forced continuous applications with low
3773fb
24
LTC3773
APPLICATIONS INFORMATION
tow-truck operators finding that a 24V jump start cranks
cold engines faster than 12V.
The I series R -C filter sets the dominant pole-zero
TH
C
C
loop compensation. The values can be modified slightly
to maximize transient response once the final PC layout
is done and the particular output capacitor type and value
have been determined. The output capacitors need to be
decided upon because the various types and values deter-
mine the loop feedback factor gain and phase. An output
current pulse of 20ꢀ to 80ꢀ of full load current having
ThenetworkshowninFigure8isthemoststraightforward
approach to protect a DC/DC converter from the ravages
of an automotive battery line. The series diode prevents
current from flowing during reverse battery, while the
transient suppressor clamps the input voltage during
load dump. Note that the transient suppressor should not
conduct during double-battery operation, but must still
clamptheinputvoltagebelowbreakdownoftheconverter.
Although the IC has a maximum input voltage of 36V on
the SW pins, most applications will be limited to 30V by
a rise time of <2μs will produce output voltage and I
TH
pin waveforms that will give a sense of the overall loop
stability without breaking the feedback loop. The initial
output voltage step, resulting from the step change in
output current, may not be within the bandwidth of the
feedback loop, so this signal cannot be used to determine
phase margin. This is why it is better to look at the I
pin signal which is in the feedback loop and is the filtered
and compensated control loop response. The gain of the
the MOSFET B
.
VDSS
V
CC
5V
V
TH
BAT
12V
+
TG
loop will be increased by increasing R and the bandwidth
LTC3773
SW
C
of the loop will be increased by decreasing C . If R is
C
C
increased by the same factor that C is decreased, the
BG
C
zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range
of the feedback loop. The output voltage settling behavior
is related to the stability of the closed-loop system and
will demonstrate the actual overall supply performance.
For a detailed explanation of optimizing the compensation
components, including a review of control loop theory,
refer to Application Note 76.
PGND
3773 F08
Figure 8. Automotive Application Protection
Design Example
As a design example for one channel, assume V = 12V
IN
(nominal), V = 22V(max), V
= 1.8V, I
= 15A, and
IN
OUT
MAX
f = 220kHz.
Automotive Considerations: Plugging into the
Cigarette Lighter
The inductance value is chosen first based on a 30ꢀ
ripple current assumption. The highest value of ripple
current occurs at the maximum input voltage. Short the
PLLFLTR pin to ground to program for 220kHz operation.
The minimum inductance for 30ꢀ ripple current is:
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserveorevenrechargebatterypacksduringoperation.
But before you connect, be advised: you are plugging into
thesupplyfromhell.Themainbatterylineinanautomobile
is the source of a number of nasty potential transients, in-
cluding load dump, reverse battery and double battery.
ꢁ
OUT ꢄ
V
VOUT
L =
1–
ꢃ
ꢆ
(f)(ꢀI )
V
ꢂ
ꢅ
L
IN
1.8V
(220k)(30%)(15A)
1.8V
22V
ꢁ
ꢂ
ꢄ
ꢅ
=
1ꢇ
=1.67μH
ꢃ
ꢆ
Load dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alterna-
tor can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse battery is
just what it says, while double battery is a consequence of
Using L = 1.5μH, a commonly available value results in
30ꢀ ripple current. The peak inductor current will be the
maximum DC value plus one half the ripple current, or
17.3A. Increasing the ripple current will also help ensure
3773fb
25
LTC3773
APPLICATIONS INFORMATION
that the minimum on-time of 130ns is not violated. The
A short-circuit to ground will result in a folded back
current of
minimum on-time occurs at maximum V :
IN
VOUT
IN(MAX)f 22V(220kHz)
1.8V
ꢂ
ꢄ
ꢅ
15mV 1 130ns(22V)
tON(MIN)
=
=
= 372ns
ISC
=
ꢁ
= 4.05A
ꢇ
V
0.003ꢀ 2ꢃ 1.5μH
ꢆ
The R
resistor value can be calculated by using the
SENSE
PC Board Layout Checklist
maximum current sense voltage specification with a con-
servative maximum sense current threshold of 55mV:
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 10. Check the following in the
PC layout:
55mV
R
SENSE ꢀ
ꢁ3.2mꢂ
17.3A
Use a commonly available 0.003Ω sense resistor.
1. Are the top N-channel MOSFETs located within 1cm of
Since the output voltage is below 2.4V the output resistive
dividerwillneedtobesizedtonotonlysettheoutputvoltage
but also to absorb the SENSE pin’s specified input current.
each other with a common drain connection at C ? Do
IN
not attempt to split the input decoupling for the three
channels as it can cause a large resonant loop.
ꢁ
ꢄ
0.6V
2.4V ꢀ V
2. Are the signal and power grounds kept separate? Keep
the SGND at one end of a printed circuit path thus
preventing MOSFET currents from traveling under
the IC. The SGND pin should be used to hook up all
control circuitry on one side of the IC. The combined
R1(MAX) = 30k
ꢃ
ꢆ
ꢂ
OUT ꢅ
0.6V
2.4V ꢀ1.8V
ꢁ
ꢂ
ꢄ
ꢅ
= 30k
= 30k
ꢃ
ꢆ
Choosing 1ꢀ resistors; R1 = 10k and R2 = 20k yields an
output voltage of 1.8V.
LTC3773 SGND pin and the ground return of C
must
VCC
return to the combined C
(–) terminals. The output
OUT
capacitor (–) terminals should be connected as close
as possible to the (–) terminals of the input capacitor
by placing the capacitors next to each other and away
from the charge pump circuitry. The path formed by
The power dissipation on the top side MOSFET can be
easilyestimated.ChoosingaRenesasHAT2168HMOSFET
resultsin:R
=13.5mΩ, C
=6nC/25V=240pF.
DS(ON)
MILLER
At maximum input voltage with T (estimated) = 50°C:
the top N-channel MOSFET, Schottky diode and the C
IN
capacitor should have short leads and PC trace lengths.
The power ground returns to the sources of the bottom
N-channel MOSFETs, anodes of the Schottky diodes
1.8V
22V
ꢁ
ꢂ
ꢃ
PMAIN
=
(15)2 1+(0.005)(50°Cꢀ 25°C)
[
]
ꢁ
ꢅ
15A
2
ꢈ
ꢊ
ꢋ
ꢍ
(13.5mꢄ) + (22V)2
(2ꢄ)(240pF)
IN
and (–) plates of C , which should have as short lead
ꢆ ꢂ
ꢉ
ꢌ
lengths as possible.
ꢇ
ꢃ
ꢅ
1
1
ꢑ
ꢎ
3. TheV decouplingcapacitorshouldbeplacedimmedi-
CC
+
(220kHz) = 0.612W
ꢆ
ꢐ
ꢓ
ately adjacent to the IC between the V pin and SGND.
5ꢀ1.8 1.8
ꢏ
ꢒ
CC
ꢇ
A1μFceramiccapacitoroftheX7Rtypeissmallenough
to fit very close to the IC to minimize the ill effects of the
largecurrentpulsesdrawntodrivethebottomMOSFETs.
Anadditional4.7μFto10μFofceramic,tantalumorother
very low ESR capacitance is recommended in order to
keep the internal IC supply quiet.
Using a Renesas HAT2165H as a bottom MOSFET, the
worst-casepowerdissipationbythesynchronousMOSFET
under normal operating conditions at elevated ambient
temperature and an estimated 50°C junction temperature
rise is:
22V ꢀ1.8V
(15)2(1.125)(5.3mꢁ)=1.23W
4. Do the LTC3773 V resistive dividers connect to the (+)
FB
PSYNC
=
22V
terminals of C ? The resistive divider must be con-
OUT
3773fb
26
LTC3773
APPLICATIONS INFORMATION
nected between the (+) terminal of C
and SGND and
Figure 10 illustrates all branch currents in a three-phase
switching regulator. It becomes very clear after study-
ing the current waveforms why it is critical to keep the
high switching current paths to a small physical size.
High electric and magnetic fields will radiate from these
“loops” just as radio stations transmit signals. The output
capacitor ground should return to the negative terminal
of the input capacitor and not share a common ground
path with any switched current paths. The left half of the
circuit gives rise to the “noise” generated by a switching
regulator. The ground terminations of the synchronous
MOSFETs and Schottky diodes should return to the bot-
tom plate(s) of the input capacitor(s) with a short isolated
PC trace since very high switched currents are present.
A separate isolated path from the bottom plate(s) of the
inputandoutputcapacitor(s)shouldbeusedtotieintheIC
power ground pin (PGND). This technique keeps inherent
signals generated by high current pulses taking alternate
current paths that have finite impedances during the total
period of the switching regulator. External OPTI-LOOP
compensation allows overcompensation for PC layouts
which are not optimized but this is not the recommended
design procedure.
OUT
a small decoupling capacitor should be placed across
this divider; as close as possible to the LTC3773 SGND
pin and away from any high current or high frequency
switching nodes.
–
+
5. Are the SENSE and SENSE printed circuit traces for
each channel routed together with minimum PC trace
+
spacing? The filter capacitors between SENSE and
–
SENSE foreachchannelshouldbeascloseaspossible
–
+
to the pins of the IC. Connect the SENSE and SENSE
pins to the pads of the sense resistor as illustrated in
Figure 9.
6. Keep the switching nodes, SW, BOOST and TG away
+
–
from sensitive small-signal nodes (SENSE , SENSE ,
V
I ). Ideally the SW, BOOST and TG printed circuit
FB, TH
traces should be routed away and separated from the IC
and the “quiet” side of the IC. Separate the high dV/dt
printed circuit traces from sensitive small-signal nodes
with ground traces or ground planes.
7. Use a low impedance source such as a logic gate to
drive the PLLIN pin and keep the lead as short as
possible.
8. Minimize trace impedances of TG, BG and SW nets.
TG and SW must be routed in parallel with minimum
distance.
INDUCTOR
10Ω
+
SENSE
SENSE
RESISTOR
1000pF
LTC3773
SENSE
–
10Ω
OUTPUT
CAPACITOR
37773 F09
Figure 9. Kelvin Sensing RSENSE
3773fb
27
LTC3773
APPLICATIONS INFORMATION
SW1
D1
L1
V
OUT1
OUT2
OUT3
R
SENSE1
+
C
R
OUT1
L1
L2
L3
SW2
L2
V
V
IN
R
R
SENSE2
+
IN
+
C
IN
C
R
OUT2
D2
BOLD LINES INDICATE
HIGH SWITCHING
CURRENTS.
KEEP LINES TO A
MINIMUM LENGTH.
SW3
D3
L3
V
R
SENSE3
+
C
R
OUT3
3773 F10
Figure 10. Branch Current Waveforms
3773fb
28
LTC3773
APPLICATIONS INFORMATION
10Ω
10Ω
POWER DOWN V
POWER DOWN V
OUT1
OUT2
1nF
10k
32
V
5V
PGOOD
4.5V TO 6V
39
38
37
36
35
34
33
V
IN
4.5V TO 22V
V
OUT1
10μF
25V
x6
0.01μF
CMDSH-3
0.1μF
C
IN
+
1
2
31
56μF
TRACK1
BOOST1
TG1
47.5k
1500pF
25V
x5
30
29
28
27
26
25
24
23
22
21
20
V
L1
1μH
FB1
TH1
3mΩ
15k
100pF
3
V
HAT2168H
OUT1
I
SW1
2.5V/15A
C
+
OUT1
4
330μF
4V
SGND
SW2
B340B
LTC3773
47μF
0.1μF
CMDSH-3
x2
5
1500pF 330pF
6.8k
HAT2165H
I
I
TG2
TH2
TH3
V
IN
6
BOOST2
BOOST3
TG3
L2
0.6μH
7
15k
V
FB2
V
FB3
3mΩ
HAT2168H
HAT2165H
V
0.1μF
CMDSH-3
OUT2
8
1.8V/30A
20k
10k
B340B
9
TRACK2
TRACK3
SW3
10
11
12
V
IN
BG1
20k
C
OUT2
+
330μF
2.5V
x4
–
SENSE2
SENSE2
BG2
V
47μF
x2
OUT2
HAT2168H
+
10k
V
DR
L3
0.6μH
3mΩ
13
14
15
16
17
18
19
B340B
1nF
1nF
CLKOUT
CLKIN
HAT2165H
10Ω
10Ω
10k
0.1μF CONTINUOUS
MODE FOR
L1: PULSE PG0006.102
L2, L3: PULSE PG0006.601
10Ω
10Ω
TRACKING
C
OUT1
C
OUT2
: SANYO POSCAP 4TPD330M
: SANYO POSCAP 2R5TPE330M9
+
2Ω
+
10μF
1μF
10μF
3773 F11
Figure 11. 3-Phase, Dual Output with Coincident Output Tracking Function
3773fb
29
LTC3773
PACKAGE DESCRIPTION
G Package
36-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
12.50 – 13.10*
(.492 – .516)
1.25 ±0.12
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
7.8 – 8.2
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 ±0.03
0.65 BSC
5
7
8
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
6
9 10 11 12 13 14 15 16 17 18
2.0
(.079)
MAX
5.00 – 5.60**
(.197 – .221)
0° – 8°
0.65
(.0256)
BSC
0.09 – 0.25
(.0035 – .010)
0.55 – 0.95
(.022 – .037)
0.05
0.22 – 0.38
(.009 – .015)
TYP
(.002)
MIN
NOTE:
G36 SSOP 0204
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
(INCHES)
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
3773fb
30
LTC3773
PACKAGE DESCRIPTION
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701)
0.70 ± 0.05
5.50 ± 0.05
(2 SIDES)
4.10 ± 0.05
(2 SIDES)
3.15 ± 0.05
(2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
5.15 ± 0.05 (2 SIDES)
6.10 ± 0.05 (2 SIDES)
7.50 ± 0.05 (2 SIDES)
RECOMMENDED SOLDER PAD LAYOUT
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
3.15 ± 0.10
(2 SIDES)
0.75 ± 0.05
5.00 ± 0.10
(2 SIDES)
37 38
0.00 – 0.05
0.40 ±0.10
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
5.15 ± 0.10
(2 SIDES)
7.00 ± 0.10
(2 SIDES)
0.40 ± 0.10
0.200 REF 0.25 ± 0.05
R = 0.115
TYP
(UH) QFN 0205
0.50 BSC
0.200 REF
BOTTOM VIEW—EXPOSED PAD
0.75 ± 0.05
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3. ALL DIMENSIONS ARE IN MILLIMETERS
3773fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. How-
ever, no responsibility is assumed for its use. Linear Technology Corporation makes no representation
that the interconnection of its circuits as described herein will not infringe on existing patent rights.
31
LTC3773
TYPICAL APPLICATION
POWER DOWN V
POWER DOWN V
POWER DOWN V
OUT1
OUT2
OUT3
10Ω
10Ω
V
CC
4.5V TO 6V
68.1k
1000pF
PGOOD
V
IN
10k
+
4.5V TO 14V
47μF
4.7μF
16V
39
38
37
36
35
34
33
32
16V
8
Si4816BDY
CMDSH-3
0.1μF
0.01μF
1
31
1
5
4
L1
2.2μH
TRACK1
BOOST1
7mΩ
6, 7
2, 3
2
3
4
30
29
28
V
OUT1
V
TG1
SW1
FB1
TH1
3.3V/5A
20k
150pF
+
+
1nF
C
OUT1
15k
10k
I
220μF
22μF
X5R
4V
SGND
SW2
8.2k
0.1μF
CMDSH-3
150pF
150pF
1nF
5
6
27
26
25
24
23
22
21
20
I
I
TG2
TH2
TH3
5.9k
LTC3773
1nF
V
BOOST2
BOOST3
TG3
IN
4.7μF
7
8 Si4816BDY
CMDSH-3
V
V
16V
FB2
10k
0.1μF
8
1
5
4
L2
1.5μH
FB3
7mΩ
0.01μF
9
6, 7
2, 3
V
TRACK2
TRACK3
SW3
OUT2
2.5V/5A
0.01μF
10
11
12
C
OUT2
BG1
220μF
22μF
X5R
–
4V
SENSE2
SENSE2
BG2
+
V
DR
20k
+
V
IN
4.7μF
13
14
15
16
17
18
19
8 Si4816BDY
4.7μF
16V
31.6k
1
5
4
L3
1.5μH
10Ω
0.1μF
V
OUT3
1.8V/5A
7mΩ
+
6, 7
2, 3
1000pF
1000pF
2.2μF
+
C
OUT3
220μF
L1:
22μF
X5R
4V
TDK RLF7030T-2R2M5R4
10Ω
10Ω
10Ω
10Ω
L2, L3:
TDK RLF7030T-1R5M5R4
C
C
C
,:
OUT1 OUT2 OUT3
SANYO POSCAP 4TPE220MF
Figure 12. High Efficiency, Small Footprint Triple Output Step-Down Converter
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
V : 2.5V to 5.5V, V : 0.6V to 5V, 100ꢀ Maximum Duty Cycle
LTC3407-2
Dual Synchronous, 800mA, 2.25MHz Step-Down Monolithic
DC/DC Regulator
IN
OUT
LTC3417A
LTC3703
LTC3708
Dual Synchronous Step-Down Monolithic 1.5A/1A
V : 2.25V to 5.5V, V : 0.8V to 5V, 100ꢀ Maximum Duty Cycle
IN
OUT
High Input Synchronous Step-Down Controller
V
IN
≤ 100V
TM
SENSE
No R
, Dual, 2-Phase Synchronous Step-Down Controller Very Low Duty Factor Operation, Programmable Output Voltage
Voltage Up/Down Tracking
with Output Tracking
LTC3727
Dual Output 2-Phase Current Mode Synchronous DC/DC Step- V : 4V to 36V, V : 0.8V to 14V, 99ꢀ Maximum Duty Cycle,
IN
OUT
Down Switching Regulator Controller
Selectable Burst Mode Operation
LTC3728
LTC3729
Dual PolyPhase® Synchronous Step-Down Switching Regulator Dual Output, Current Mode
20A to 200A, 500kHz PolyPhase Synchronous Controller
3- to 12-Phase Step-Down Synchronous Controller
Expandable from 2-Phase, Uses All Surface Mount Components,
up to 36V
V
IN
LTC3731
Single Output, 60A to 240A Output Current, 0.6V ≤ V
4.5V ≤ V ≤ 32V
≤ 6V,
OUT
IN
LTC3778
LTC3802
Wide Operating Range, No R
Step-Down Controller
Single Channel, Separate V Programming
ON
SENSE
Dual PolyPhase Voltage Mode Synchronous Step-Down
Switching Regulator with Output Tracking
Very Low Duty Factor Operation, Programmable Output Voltage
Up/Down Tracking, V Up to 30V
IN
LTC3827
Low I , Dual, 2-Phase Synchronous Step-Down Controller
Low 80μA I , 0.8V ≤ V
≤ 10V, 4V ≤ V ≤ 36V
OUT IN
Q
Q
No R
is a trademark of Linear Technology Corporation. PolyPhase is a registered trademark of Linear Technology Corporation.
SENSE
3773fb
LT 0907 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
32
●
●
© LINEAR TECHNOLOGY CORPORATION 2006
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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