LTC3815EUFE#PBF [Linear]
LTC3815 - 6A Monolithic Synchronous DC/DC Step-Down Converter with Digital Power System Management; Package: QFN; Pins: 38; Temperature Range: -40°C to 85°C;
| 型号： | LTC3815EUFE#PBF |
| 厂家： | 
Linear |
| 描述： | LTC3815 - 6A Monolithic Synchronous DC/DC Step-Down Converter with Digital Power System Management; Package: QFN; Pins: 38; Temperature Range: -40°C to 85°C 开关 输出元件 |
| 文件： | 总42页 (文件大小：2919K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3815
6A Monolithic Synchronous DC/DC
Step-Down Converter with PMBus Interface
FEATURES
DESCRIPTION
n
2.25V to 5.5V Input Voltage Range
The LTC®3815 is a high efficiency, 6A monolithic synchro-
nous buck regulator using a phase lockable controlled
on-time, current mode architecture. The output voltage
n
1% Total Output Voltage Accuracy Over
Temperature at V = 3.3V or 5V
IN
n
n
Single Resistor-Programmable Output Voltage
PMBus Compliant Serial Interface:
is programmable from 0.4V to 72% of V with a single
IN
external resistor or an external voltage reference through
the reference input (REF) pin. The output voltage can be
margined up or down up to 25% with 0.1% resolution
via a PMBus-compliant serial interface. The serial inter-
face can also be used to read back fault status and both
time-averaged (~4ms) and peak input/output current,
input/output voltage and temperature. System configu-
ration and monitoring is supported by the LTpowerPlay®
development system.
n
Programmable Output Voltage Margining:
Up to 25% V
Read back of Average and Peak Temperature,
Current, and Voltage (25Hz Refresh Rate)
Fault Status
Range with 0.1% Resolution
OUT
n
n
n
n
n
n
n
n
Phase-Lockable Fixed Frequency Up to 3MHz
Less Than 1ms Power-Up Time
Integrated 13-Bit ADC
Optional External Reference Input
The architecture provides extremely fast transient
response and allows operation at the very low on-times
required to regulate low output voltages at high switching
frequencies. The operating frequency is programmable
from 400kHz to 3MHz with an external resistor or for
noise sensitive applications, it can be synchronized to an
external clock over the same range. The operating supply
voltage range is from 2.25V to 5.5V making it suitable
for operation from 2.5V, 3.3V or 5V rails or Lithium-Ion
batteries.
Pin Selectable Fast-Margining of the Output Voltage
Power Good Flag with Pin Programmable Thresholds
and Filter Delay
n
n
n
n
Differential Remote Output Voltage Sensing
Master Shutdown Mode: <1μA Supply Current
Clock Out for 2-Phase Operation (12A Output Current)
Available in a Thermally-Enhanced 38-Lead
4mm × 6mm QFN Package
APPLICATIONS
n
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents including 5481178, 5705919, 5929620, 6144194, 6177787, 6580258, 5408150,
7420359. Licensed under U.S. Patent 7000125 and other related patents worldwide.
Intelligent Energy Efficient Power Conversion
n
ASIC/FPGA/Processor Power
n
Distributed Power Systems
Point of Load Power Conversion
n
TYPICAL APPLICATION
Efficiency and Power Loss
vs Load Current
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Rev B
1
Document Feedback
For more information www.analog.com
LTC3815
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 7)
V , P ....................................................... –0.3V to 6V
CC_SENSE SS_SENSE SLEW T TH
ꢅꢆꢇ ꢈꢉꢊꢋ
IN VIN
V
, V
, C
, R , I , MODE/SYNC,
REF, TRACK/SS, PGFD, PGLIM, ASEL, DA , MARGIN,
OUT
ꢁꢕ ꢁꢥ ꢁꢄ ꢁꢃ ꢁꢂ ꢁꢁ ꢁꢡ
RUN_STBY, FB.............................. –0.3V to (V + 0.3V)
IN
R
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RUN_MSTR, PGOOD, ALERT, SCL,
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SDA Voltage............................................. –0.3V to 6V
WP............................................................ –0.3V to 2.5V
Operating Junction Temperature Range
(Notes 2, 3)............................................ –40°C to 125°C
Storage Temperature Range .................. –65°C to 125°C
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ꢠ ꢀꢡꢃꢢꢓꢣ θ ꢠ ꢁꢕꢢꢓꢤꢋ
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ORDER INFORMATION
LEAD FREE FINISH
LTC3815EUFE#PBF
LTC3815IUFE#PBF
TAPE AND REEL
PART MARKING*
3815
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3815EUFE#TRPBF
LTC3815IUFE#TRPBF
38-Lead (4mm × 6mm) Plastic QFN
38-Lead (4mm × 6mm) Plastic QFN
–40°C to 125°C
–40°C to 125°C
3815
Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Rev B
2
For more information www.analog.com
LTC3815
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, VIN = 3.3V unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
2.25
0.4
TYP
MAX
5.5
UNITS
l
l
V
V
Input Supply Range
V
V
IN
Output Voltage Programming Range
72% of V
OUT
IN
I
Q
V Supply Current
IN
Normal Mode
Standby
V
V
V
> 1V (Note 4)
5
120
1
8
200
mA
µA
µA
RUN_MSTR
RUN_STBY
RUN_MSTR
= 0V, V
> 1V
SCL IN
RUN_MSIR
Shutdown
= 0V, V
= V
≥ V
SDA
V
UVLO
V
Undervoltage Reset
V
V
Rising
Falling
2.05
2.15
0.2
2.25
V
V
IN
IN
IN
Hysterisis
l
I
Reference Current
(Note 10)
99.2
99.5
100
100
100.8
100.5
µA
µA
REF
l
l
ΔI
Reference Current Line Regulation
Regulation Accuracy
V
V
= 2.5V to 5.5V (Note 10)
0.05
0.2
0.5
%/V
%
REF,LINE
IN
ΔV
= 1.5V (Notes 5, 10)
–0.5
OUT,OFFSET
REF
ΔV
= (V
– V
) – V
SS_SEN REF
OUT,OFFSET
CC_SEN
ΔV
OUT,MARGIN
Maximum Margining Range
Set Point Accuracy
–25
–0.5
25
0.5
%
%
l
MFR_VOUT_COMMAND = –25% to
25%, V = 1.5V (Note 5)
REF
Resolution
LSD Step Size
9
0.1
Bits
%
NL_V
DAC Nonlinearity
1
LSB
dB
OUT
A
EA
Error Amplifier Open Loop Gain
I
= 1V (Note 5)
TH
80
20
f
BW
Error Amp Gain Bandwidth Product
(Note 6)
MHz
kΩ
R
IN
Differential Amplier Input Resistance
Internal Soft-Start Time/V
Measured at V
Pin
160
1
CC_SEN
t
I
I
External C = Float
ms/V
µA
SS
REF
SS
C
SLEW
Pull-Up Current
V = 0V
CSLEW
–10
CSLEW
LIM
l
SW Valley Current Limit
Sourcing (Note 8)
Sinking
5.5
6.5
–6
7.5
A
A
I
Regulator On Source Current
V
= 0V
RUN_STBY
–2.5
µA
RUN_STBY
V
Regulator On Threshold (Master Shutdown)
Regulator On Hysterisis
Rising Edge
Falling Edge
Q
0.9
0.7
1
1.1
1.2
V
V
V
RUN_MSTR
0.1
Regulator Power-Down Threshold
I < 10μA
0.65
V
Regulator On Threshold (Standby Mode)
ASEL Programming Current
PGFD Programming Current
SS Current
1
10
10
5
V
µA
µA
µA
RUN_STBY
ASEL
I
I
I
PGFD
V
= 0V
SS
4
6
SS
V
V
MARGIN High Voltage
MARGIN Low Voltage
1.2
V
V
IH,MARGIN
IL,MARGIN
0.4
I
WP
WP Pin Pull-Up Current
WP = 0V
10
µA
SR
MARGIN
Reference Slew Rate During Margin Change
C
C
C
= 1nF
0.1
23
10
%/ms
%/ms
%/µs
SLEW
SLEW
SLEW
= OPEN
= SV
IN
t
Initialization Time
Delay from Power Applied Until
Ramp Up
1
2
ms
INIT
V
OUT
Oscillator and Power Switch
l
f
Oscillator Frequency
R = 25.5k
0.85
0.85
1.0
1.0
1.15
1.15
MHz
MHz
OSC
T
R = SV
T
IN
V
SYNC
SYNC Level High
SYNC Level Low
1.2
V
V
0.3
Rev B
3
For more information www.analog.com
LTC3815
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, VIN = 3.3V unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
1
MAX
UNITS
V
V
MODE
Discontinuous Mode Threshold
Minimum On-Time
t
t
75
ns
ON(MIN)
OFF(MIN)
Minimum Off-Time
100
35
ns
R
R
Top Power PMOS On Resistance
Bottom Power NMOS On Resistance
Relative Phase of CLKOUT
mΩ
mΩ
Deg
TOP
20
BOTTOM
MODE/SYNC = 0V
180
θCLKOUT
PGOOD
V
V
Default PGOOD Threshold
Program PGOOD Threshold
V
= V , V >1V
IN OUT
8
10
12
%
PGOOD,DEFAULT
PGLIM
V
V
/V = 0.19, V ≥ 1V
OUT
6
13
10
30
9
17
%
%
PGOOD,PROGRAM
PGLIM REF
/V = 0.38
PGLIM REF
I
PGOOD Leakage Current
PGOOD Output Low Voltage
PGOOD Filter Delay
5
µA
V
LEAK
V
I
= 3mA
0.1
0.3
OL
OUT
t
PGFD = 0V
150
1.0
17
190
1.6
24
250
2.2
32.5
µs
ms
ms
PGFD
PGFD = 0.65V
PGFD = V
IN
Output Voltage Readback
N
Resolution
LSB Step Size
13
0.5
Bits
mV
V
V
Full Scale Output Voltage
Total Unadjusted Error
(Note 9)
16.4
V
F/S
l
0.75
0.5
%
%
OUT_TUE
t
Conversion Time
40
ms
CONVERT
Input Voltage Readback
N
Resolution
LSB Step Size
13
4
Bits
mV
V
V
Full Scale Input Voltage
Total Unadjusted Error
Conversion Time
(Note 9)
131
V
%
F/S
l
1.5
IN_TUE
CONVERT
t
40
ms
Output Current Readback
N
Resolution
LSB Step Size
13
10
Bits
mA
V
Full Scale Output Current
Total Unadjusted Error
Conversion Time
82
A
%
F/S
I
t
3
OUT_TUE
CONVERT
40
ms
Input Current Readback
N
Resolution
LSB Step Size
13
10
Bits
mA
V
Full Scale Input Current
Total Unadjusted Error
Conversion Time
82
A
%
F/S
I
t
3
IN_TUE
CONVERT
40
ms
Rev B
4
For more information www.analog.com
LTC3815
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range, VIN = 3.3V unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Temperature Readback
N
Resolution
LSB Step Size
9
1
Bits
°C
V
Full Scale Temperature
Total Unadjusted Error
Conversion Time
256
3
°C
°C
F/S
T
TUE
t
40
ms
CONVERT
PMBus Interface Parameters
V
V
SDA, SCL
SDA, SCL
Input High Voltage
2.1
–5
V
V
IH,
IL,
Input Low Voltage
0.8
5
I
IH,
SDA, SCL
Input Leakage Current
Output Low Voltage (SDA)
Output Low Voltage (ALERT)
Serial Bus Operating Frequency
0V ≤ V ≤ 5.5V
µA
V
PIN
V
V
I
I
= 3mA
0.4
0.4
400
OL, SDA
SDA
ALERT
= 1mA
V
OL, ALERT
SCL
f
t
10
kHz
µs
Bus Free Time Between Stop and Start
Condition
1.3
BUF
t
t
t
t
t
t
t
t
t
Hold Time After (Repeated) Start Condition
Repeated Start Condition Setup Time
Stop Condition Setup Time
Data Hold Time
0.6
0.6
0.6
300
0
µs
µs
µs
ns
ns
ns
µs
µs
ms
HD_SDA
SU_SDA
SU_STO
900
HD_DAT(OUT)
HD_DAT(IN)
SU_DAT
Input Data Hold Time
Data Set-Up Time
100
1.3
0.6
Clock Low Period
10000
LOW
Clock High Period
HIGH
Stuck PMBus Timer
Measured from Last PMBus Start
Event
30
TIMEOUT_SMB
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 4 : The dynamic input supply current is higher due to power
MOSFET gate charging (Q × f ). See applications Information for more
information.
G
OSC
Note 5: The LTC3815 is tested in a feedback loop that servos V to a
FB
Note 2: The LTC3815 is tested under pulsed load conditions such that T ≈ T .
The LTC3815E is guaranteed to meet specifications from 0°C to 85°C
referenced voltage with the I pin forced to a voltage between 0.6V
and 1V.
J
A
TH
junction temperature. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
Note 6: Guaranteed by design, not subject to test.
Note 7: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum junction temperature
may impair device reliability or permanently damage the device.
Note 8: The LTC3815 uses valley current mode control so the current
limits specified correspond to the valley of the inductor current waveform.
Maximum load current is higher and equals the valley current limit I
plus one half of the inductor ripple current.
Note 9: The maximum input and output voltage is 5.5V.
correlation with statistical process controls. The LTC3815I is guaranteed
over the –40°C to 125°C operating junction temperature range. Note that
the maximum ambient temperature consistent with these specifications
is determined by specific operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors.
Note 3: The junction temperature (T , in °C) is calculated from the ambient
J
LIM
temperature (T , in °C) and power dissipation (PD, in Watts) according to
A
the formula:
T = T + (PD • θJA
)
J
A
Note 10: Total output accuracy is the sum of the tolerances of I
,
REF
R , ΔV , and ΔI
REF(EXTERNAL) OUT,OFFSET
• ΔV .
REF,LINE IN
where θJA (in °C/W) is the package thermal impedance.
Rev B
5
For more information www.analog.com
LTC3815
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step
(Forced Continuous Mode)
Efficiency vs Load Current
Efficiency vs Input Voltage
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ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢂꢃ ꢄꢅꢂ
Load Step
(Discontinuous Mode)
Output Margining
Load Regulation
ꢀꢁꢂꢀ
ꢀꢁꢂꢀ
ꢀ
ꢀ
ꢀ ꢁꢂꢁꢃ
ꢀꢁ
ꢀꢁRꢂꢃꢄ
ꢅꢆꢇꢈꢃꢆ
ꢀ
ꢁꢂꢃ
ꢄꢅꢆꢀꢇꢈꢉꢀ
ꢀ
ꢁꢂꢃ
ꢄꢅꢅꢆꢀꢇꢈꢉꢀ
ꢀ
ꢁꢂꢃꢄ
ꢅꢃꢆꢄꢀꢇ
ꢀꢁꢂꢃꢄ
ꢅꢆꢇꢈꢉꢆ
ꢀꢁꢂꢃꢁ
ꢀꢁꢂꢃꢁ
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢂꢃ ꢄꢅꢃ
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀ
ꢄ ꢅꢀ
ꢄ ꢊꢈ ꢃꢁ ꢋꢈ
ꢁꢂꢃ
ꢀꢁRꢂꢃꢄ RꢅꢂꢃꢆꢇꢅRꢆ ꢈRꢅꢉꢊꢋꢁꢌꢅꢌ
ꢇꢋ ꢍꢎꢏ ꢁꢄꢌ ꢐꢍꢎꢏ
ꢆ
ꢇꢁꢈꢉ
ꢉꢌꢍ ꢍꢁꢉꢎ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢑ
ꢆꢊꢅꢒ
ꢓ ꢍꢎꢔꢕ
ꢏRꢁꢐꢃ ꢑꢈꢒꢎ ꢌꢆRꢌꢂꢆꢃ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢅꢆ
Forced Continuous Mode
Operation
Line Regulation
Discontinuous Mode Operation
ꢀꢁꢂꢀ
ꢀꢁꢂꢀ
ꢀ
ꢀ
ꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢄꢅꢆꢀꢇꢈꢉꢀ
ꢄꢅꢆꢀꢇꢈꢉꢀ
ꢀ
ꢁ
ꢀ
ꢁ
ꢂꢃꢄꢅꢀꢆ
ꢂꢃꢄꢅꢀꢆ
ꢀꢁꢂꢃꢁ
ꢀꢁꢂꢃꢁ
ꢀ
ꢀ ꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃ ꢄꢅꢁ
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀꢀꢁ ꢁꢂꢃꢄ
ꢀRꢁꢂꢃ ꢄꢅꢆꢇ ꢈꢉRꢈꢊꢉꢃ
ꢀ
ꢄ ꢅꢆꢇꢀ
ꢀ
ꢄ ꢅꢆꢇꢀ
ꢄ ꢅꢌꢌꢍꢊ
ꢄ ꢌꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢈ
ꢄ ꢅꢌꢌꢍꢊ
ꢄ ꢐꢆꢐꢀ
ꢈ
ꢉꢁꢊꢋ
ꢉꢁꢊꢋ
ꢀ
ꢀ
ꢎꢁꢋꢏ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢎꢁꢋꢏ
ꢑRꢁꢒꢃ ꢓꢊꢔꢏ ꢕꢈRꢕꢂꢈꢃ
ꢐRꢁꢑꢃ ꢒꢊꢓꢏ ꢔꢈRꢔꢂꢈꢃ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢃ ꢄꢅꢆ
Rev B
6
For more information www.analog.com
LTC3815
TYPICAL PERFORMANCE CHARACTERISTICS
Valley Current Limit
vs Input Voltage
Current Sense Threshold
vs ITH Voltage
Valley Current Limit vs
Temperature
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢀ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂ ꢃꢄꢅꢁꢆꢇꢈ ꢉꢃꢊ
ꢀꢁꢂꢃ ꢄꢂꢅ
ꢀꢁꢂꢃ ꢄꢂꢅ
ꢀꢁꢂꢃ ꢄꢂꢂ
Oscillator Frequency
vs Temperature
Oscillator Frequency vs Input
Voltage
Quiescent Current vs Input
Voltage
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢃ ꢄꢂꢀ
ꢀꢁꢂꢃ ꢄꢂꢅ
ꢀꢁꢂꢃ ꢄꢂꢃ
Shutdown Current vs Input
Voltage
Standby Current vs Input Voltage
Oscillator Frequency vs RT
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁ
ꢀꢁ ꢀꢁ
R (kΩ)
ꢀ
ꢀꢁ
ꢀꢁꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢃ ꢄꢂꢅ
ꢀꢁꢂꢃ ꢄꢂꢁ
ꢀꢁꢂꢃ ꢄꢂꢅ
Rev B
7
For more information www.analog.com
LTC3815
TYPICAL PERFORMANCE CHARACTERISTICS
VOUT Measurement Error vs VOUT
VOUT Command INL
VOUT Command DNL
ꢀꢁꢂꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀ ꢁꢂ
ꢀ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢁ
ꢀꢁꢂꢃꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁRꢂꢃꢄꢅꢆꢂꢇꢄꢀꢀꢈꢉꢊ ꢃꢈꢋꢅꢌ ꢍꢎꢏ
ꢀꢁRꢂꢃꢄꢅꢆꢂꢇꢄꢀꢀꢈꢉꢊ ꢃꢈꢋꢅꢌ ꢍꢎꢏ
ꢀꢁꢂꢃꢁꢂ ꢄꢀꢅꢂꢆꢇꢈ ꢉꢄꢊ
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢂꢃ ꢄꢅꢂ
ꢀꢁꢂꢃ ꢄꢂꢅ
IIN, IOUT Measurement Error vs
Temperature, VIN and Frequency
IOUT Measurement Error vs IOUT
IIN Measurement Error vs IIN
ꢀꢁꢂꢀ
ꢀꢁꢀꢂ
ꢀ
ꢀꢁꢂꢀ
ꢀꢁꢀꢂ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃ ꢄꢅ ꢆꢁꢇꢃ
ꢀꢀꢁ ꢁꢂꢃꢄ
ꢀRꢁꢂꢃ ꢄꢅꢆꢇ ꢈꢉRꢈꢊꢉꢃ
ꢀꢁꢂꢃ ꢄꢅ ꢆꢁꢇꢃ
ꢀꢀꢁ ꢁꢂꢃꢄ
ꢀRꢁꢂꢃ ꢄꢅꢆꢇ ꢈꢉRꢈꢊꢉꢃ
ꢀ
ꢀ ꢁ ꢂꢃ ꢄꢅ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂꢃꢄꢅ ꢆꢇꢈꢉ
ꢀ ꢁꢂꢁꢃꢄ ꢅꢆꢇꢈ
ꢀ ꢁꢂꢃ ꢄꢅꢆꢇ
ꢀ ꢁꢂꢁꢃꢄ ꢅꢆꢇꢈ
ꢀ ꢁꢂꢃ ꢄꢅꢆꢇ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂꢁꢃ
ꢀꢁꢂꢃꢁ
ꢀꢁꢂꢁꢃ
ꢀꢁꢂꢃꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ
ꢀꢁꢂꢃꢁꢂ ꢄꢁRRꢅꢆꢂ ꢇꢈꢉ
ꢀꢁꢂꢃꢄ ꢅꢃRRꢆꢁꢄ ꢇꢈꢉ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃ ꢄꢅꢅ
ꢀꢁꢂꢃ ꢄꢅꢀ
ꢀꢁꢂꢃ ꢄꢅꢆ
VIN Measurement Error vs VIN
IREF vs Temperature
IREF vs Input Voltage
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢀ
ꢀꢁꢂꢃ
ꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢁ
ꢀꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋꢅꢌ
ꢀꢁꢂꢃ ꢄꢅꢃ
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢂꢃ ꢄꢅꢆ
Rev B
8
For more information www.analog.com
LTC3815
TYPICAL PERFORMANCE CHARACTERISTICS
Normal Start-Up
Start-Up Into Pre-Biased Output
VOUT Short and Recovery
Rꢀꢁ
ꢂꢃꢄꢅꢆꢃ
Rꢀꢁ
ꢂꢃꢄꢅꢆꢃ
ꢀ
ꢁꢂꢃ
ꢄꢅꢆꢀꢇꢈꢉꢀ
ꢀ
ꢀ
ꢁꢂꢃ
ꢄꢅꢆꢀꢇꢈꢉꢀ
ꢁꢂꢃ
ꢄꢅꢆꢀꢇꢈꢉꢀ
ꢀꢁꢂꢂꢃ
ꢄꢅꢆꢃꢇꢅ
ꢀꢁꢂꢂꢃ
ꢄꢅꢆꢃꢇꢅ
ꢀ
ꢁ
ꢂꢃꢄꢅꢀꢆ
ꢀ
ꢀ
ꢁ
ꢂꢃꢄꢅꢀꢆ
ꢁ
ꢂꢃꢄꢅꢀꢆ
ꢀꢁꢂꢃ ꢄꢀꢅ
ꢀꢁꢂꢃ ꢄꢅꢁ
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
ꢀ
ꢄ ꢅꢀ
ꢀ
ꢄ ꢅꢀ
ꢁꢂꢃ
ꢁꢂꢃ
ꢆꢁꢇꢈ ꢄ ꢉ
ꢆꢁꢇꢈ ꢄ ꢉ
ꢊRꢁꢋꢃ ꢌꢍꢎꢈ ꢏꢐRꢏꢂꢐꢃ
ꢊRꢁꢋꢃ ꢌꢍꢎꢈ ꢏꢐRꢏꢂꢐꢃ
Switch On-Resistance
vs Input Voltage
Switch On-Resistance
vs Temperature
Switch Leakage
vs Temperature, Main Switch
ꢀꢁ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂꢃꢄRꢅꢂꢅꢆꢀ ꢀꢇꢈꢉꢃꢄ
ꢀꢁꢂꢃ ꢄꢅꢂꢆꢇꢈ
ꢀꢁꢂꢃꢄRꢅꢂꢅꢆꢀ ꢀꢇꢈꢉꢃꢄ
ꢀꢁꢂꢃ ꢄꢅꢂꢆꢇꢈ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋvꢌ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃ ꢄꢀꢀ
ꢀꢁꢂꢃ ꢄꢀꢂ
ꢀꢁꢂꢃ ꢄꢀꢅ
Switch Leakage vs Temperature,
Synchronous Switch
Dynamic Supply Current
vs Input Voltage
Minimum VIN vs Load, VOUT and
Frequency
ꢀꢁ
ꢀꢀ
ꢀ
ꢀꢁ
ꢀꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢄꢅ ꢁꢆꢇꢈ
ꢀꢁꢂꢃꢄꢅ ꢃꢆꢇꢈ
ꢀꢁꢂꢃꢄꢅ ꢁꢆꢇꢈ
ꢀꢁꢂꢃꢄꢅ ꢆꢇꢈꢉ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂ
ꢀ
ꢀꢁ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁꢂꢃꢁRꢄꢀꢅRꢁ ꢆꢇꢈꢉ
ꢀꢁꢂꢃꢄ ꢅꢆꢇꢄꢈꢉꢊ ꢋvꢌ
ꢀꢁꢂꢃ ꢄꢅRRꢆꢇꢈ ꢉꢂꢊ
ꢀꢁꢂꢃ ꢄꢀꢅ
ꢀꢁꢂꢃ ꢄꢀꢃ
ꢀꢁꢂꢃ ꢄꢀꢅ
Rev B
9
For more information www.analog.com
LTC3815
PIN FUNCTIONS
R (Pin 1): Oscillator Frequency. This pin provides two
SW (Pins 10, 11, 13, 14, 18, 19, 21, 22, 23): Switching
Node. This pin connects to the drains of the internal main
and synchronous power MOSFET switches.
T
modes of setting the constant switching frequency.
Connect a resistor from R pin to ground to program the
T
switching frequency from 400kHz to 3MHz. Tying this
NC (Pins 12, 20): No Connection. Can be connected to
ground or left open. This pin does not connect to any
internal circuitry.
pin to V enables the internal 1MHz oscillator frequency.
IN
ASEL (Pin 2): Serial Bus Address Configuration Input.
Connect a 1% resistor from this pin to ground in order
to select the 3 LSBs of the serial bus interface address.
(see Table 7).
PV (Pins 15-17): Power Input Supply. PV connects to
IN
IN
the source of the internal P-channel power MOSFET. This
pin is independent of V and may be connected to the
IN
MARGIN (Pin 3): Fast Margining Select. In the default
mode when this pin is floating, the reference voltage
margin offset is changed with MFR_VOUT_COMMAND
through the serial interface. If this pin is pulled high, the
reference voltage margin offset is immediately ramped to
the value pre-stored in the MFR_VOUT_MARGIN_HIGH
register. If this pin is pulled low, the reference voltage mar-
gin offset is immediately ramped to the value pre-stored
in MFR_VOUT_MARGIN_LOW register.
same voltage or to a lower voltage supply.
PGOOD (Pin 29): Power Good. This open-drain output
is pulled down to SGND on start-up and while the out-
put voltage is outside the power good window set by
the PGLIM pin. If the output voltage increases and stays
inside the power good window for more than the delay
programmed at the PGFD pin, the PGOOD pin is released.
If the output voltage leaves the power good window for
more than 16 switching cycles the PGOOD pin is pulled
down.
WP (Pin 4): Write Protect Pin. Pulling this pin high dis-
ables writes to MFR_VOUT_COMMAND, MFR_VOUT_
MARGIN_HIGH, and MFR_VOUT_MARGIN_LOW. When
this pin is grounded, there are no write restrictions.
VIN (Pin 24): Signal Input Supply. Decouple this pin to
SGND with a capacitor. This pin powers the internal con-
trol circuitry. This pin is independent of PV and may
IN
ALERT (Pin 5): Open Drain Digital Output. Connect the
system SMBALERT interrupt signal to this pin. A pull-up
resistor is required in the application.
be connected to the same voltage or to a higher supply
voltage.
PGFD (Pin 25): PGOOD Deglitch Filter Delay Select. The
voltage at this pin sets the delay that the output must be
in regulation before the PGOOD flag is asserted. The delay
CLKOUT (Pin 6): Clock Out Signal for 2-Phase Operation.
The phase of this clock is 180° with respect to the internal
clock. Signal swing is from V to GND.
can be programmed to one of seven discrete values where
IN
N
t
= 200μs • 2 (N = 0 to 5, 7).
DELAY
SDA (Pin 7): Serial Bus Data Input and Output. A pull-up
resistor is required in the application.
RUN_MSTR (Pin 26): Master Run. The power up thresh-
old is set at 1V. When forced below 0.4V, all circuitry is
shut off and the IC is put into a low current shutdown
SCL (Pin 8): Serial Bus Clock Input. A pull-up resistor is
required in the application.
mode (I < 1μA).
Q
MODE/SYNC (Pin 9): Mode Selection and External Clock
Input. If this pin is tied to VIN, discontinuous mode is
enabled at light loads. If this pin is connected to ground,
forced continuous mode is selected. Driving the MODE/
SYNC pin with an external clock signal will synchronize
the switching frequency to the applied frequency. There
is an internal 20k resistor to ground on this pin.
RUN_STBY (Pin 27): Standby Mode Off. The regulator
power up threshold is set at 1V. When forced below 0.4V,
only the voltage regulator is shut off while the ADC and
PMBus interface are still active. When shut off, the ADC
refresh rate is reduced to 1Hz and the IC quiescent current
Rev B
10
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LTC3815
PIN FUNCTIONS
is reduced to 120μA. This pin sources 2.5μA. Do not pull
up with a low impedance (<10kΩ).
Use an RC network between the I pin and the V pin
TH FB
to compensate the feedback loop for optimum transient
response.
C
(Pin 28): Slew Rate Control. Add a capacitor to
SLEW
program the V
transition slew rate during margining.
FB (Pin 35): Error Amplifier Input. FB will be servoed to
the REF pin voltage plus or minus any margining offset
set through the serial interface.
OUT
The slew rate is equal to 0.1% per ms per nF slew rate
capacitance. With a 1nF capacitor, the slew rate is 0.1%/
ms. Two default slew rates are also available when this
REF (Pin 36): Reference Input and Programming Pin. The
voltage at this pin is the default reference that the output
is regulated to. The PMBus interface allows margining
around this default voltage by up to 25%. This pin can
be driven by an external voltage or can be programmed
with a resistor to ground. An internal accurate low drift
100μA current source times the external resistor sets the
reference voltage.
pin is open or shorted to V .
IN
TRACK/SS (Pin 30): Tracking/Soft-Start Input. For soft-
start, a capacitor to ground at this pin sets the ramp rate
of the output voltage (approximately 5V/sec/μF). For
coincident tracking, connect this pin to a resistive divider
between the voltage to be tracked and ground.
VSS_SENSE (Pin 31): VOUT Negative Terminal Voltage
Sense. The internal unity gain differential gain amplifier
PGLIM (Pin 37): PGOOD Threshold Programming Pin.
The voltage difference ΔV between this pin and SGND sets
connects to the V
negative terminal through this pin.
IN
OUT
Tying this pin to the V pin forces the IC to operate as a
the V
overvoltage threshold to V +0.4 • ΔV and the
OUT REF
undervoltage threshold to V –0.4 • ΔV. Tying this pin to
slave in a two-phase configuration.
V sets the threshold to itsRdEeFfault value of 10%.
IN
VCC_SENSE (Pin 32): VOUT Positive Terminal Voltage Sense.
The internal unity gain differential gain amplifier connects
SGND (Pin 38): Signal Ground. Reference setting resistor,
slew rate control capacitor, and frequency setting resistor
connections should return to SGND. For optimum load
regulation, the SGND pin should be kelvin-connected to
the PCB location between the negative terminals of the
output capacitors and should not be connected through
the PGND plane.
to the V
positive terminal through this pin.
OUT
DA
(Pin 33): Differential Amplifier Output.
OUT
ITH (Pin 34): Error Amplifier Output and Switching
Regulator Compensation Point. The current compara-
tor’s trip threshold is linearly proportional to this voltage.
PGND (Exposed Pad Pin 39): Power Ground. Must be
soldered to PCB for electrical connection and rated ther-
mal performance.
Rev B
11
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LTC3815
BLOCK DIAGRAM
PGFD
PGOOD
PV
IN
PV
100µA
IN
10µA
+
+
REF
REF
REF+∆V/2.5
REF–∆V/2.5
–
+
PPG
PGOOD
FILTER
+
+
C
IN
R
REF
+
PGLIM
+
0.4
+
∆V
–
25ꢀ
+
V
–
IN
R
UV/OV
NPG
V
IN
–
DAC
TO EA
FAULT
+
SDA
SCL
C
IN
PMBus
INTERFACE
RAM/
STATUS
Q
T
COUNTER
ALERT
WP
L
ON/OFF
+
LOGIC
V
C
OUT
OVP
+
REF+∆V/2.5
–
SW
FORCED
OUT
ASEL
Q
B
A/D
CONTINUOUS
PGND
MARGIN
TG ON
ICMP
IREV
10µA
C
MUX
SLEW
+
–
CURRENT
SENSE
0.4V
CLKOUT
I
, I
IN OUT
R
T
OSC
V
ON
OST
S
R
I
Q
TON
PLL
SYNC
MODE/SYNC
RUN_STBY
V
tON
=
ON (0.64pF)
ITON
V
IN
V
IN
TEMP
TEMPERATURE
SENSE
2.5µA
+
–
PWM ON/OFF
1.0V
5µA
+
–
RUN_MSTR
CHIP ON/OFF
REF
+
+
–
6A
TRACK/SS
1.0V
80k
80k
EA
–6A
C
SS
80k
1k
+
DA
OUT
V
CC_SENSE
DAMP
–
OFF
80k
V
SS_SENSE
SGND
FB
R
I
DA
OUT
TH
3815 BD
C1
C
C1
C
C
C2
C3
R
R
C2
C3
Rev B
12
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LTC3815
OPERATION
Table 1. LTC3815 Supported PMBus Commands
PMBUS
COMMAND
CODE
PMBUS-DEFINED SMBUS
DATA
COMMAND NAME
TRANSACTION TYPE
SCALING BYTES DESCRIPTION
0x01
0x20
0x79
OPERATION
R/W Byte
1
On/Off Command and Set Output to MFR_VOUT_
MARGIN_HIGH or MFR_VOUT_MARGIN_LOW value
VOUT_MODE
Read Byte
R/W Word
1 or 2 Read Data Format for MFR_VOUT_COMMAND
Hard-wired to VID format (0x3E), not writable
STATUS_WORD
2
Read Fault Status: Communication fault, PGOOD, V UV,
IN
V
OV, overtemperature, V fault, V
fault
OUT
IN
OUT
Individual faults are reset by writing a '1' to the bit
position of the fault to be reset
0x88
0x89
0x8B
0x8C
0x8D
0x98
0xD7
READ_VIN
READ_IIN
R Word
R Word
4mV/Bit
10mA/Bit
0.5mV/Bit
10mA/Bit
1°C/Bit
2
2
2
2
2
Read V
IN
Read I
IN
READ_VOUT
R Word
Read V
OUT
OUT
READ_IOUT
R Word
Read I
READ_TEMPERATURE_1
PMBUS_REVISION
MFR_IOUT_PEAK
R Word
Read Die Temperature (°C)
Read Byte
R/W Word
1 or 2 Read PMBus Revision = 0x22 for Rev 1.2
10mA/Bit
0.5mV/Bit
4mV/Bit
1°C/Bit
2
2
2
2
2
Read highest output current observed since last restart
Write will restart peak monitor routine
0xDD
0xDE
0xDF
0xE1
MFR_VOUT_PEAK
MFR_VIN_PEAK
R/W Word
R/W Word
R/W Word
R/W Word
Read highest output voltage observed since last restart
Write will restart peak monitor routine
Read highest input voltage observed since last restart
Write will restart peak monitor routine
MFR_TEMPERATURE1_
PEAK
Read highest temperature observed since last restart
Write will restart peak monitor routine
MFR_IIN_PEAK
10mA/Bit
Read highest input current observed since last restart
Write will restart peak monitor routine
0xE3
0xE5
0xE7
MFR_CLEAR_PEAKS
MFR_VOUT_MARGIN_HIGH
MFR_SPECIAL_ID
W Byte
R/W Word
R Word
0, 1 or 2 Clear all peak values, write data is ignored
0.1%/Bit
2
2
Same format as MFR_VOUT_COMMAND
Read 16-bit value (0x8000) that GUI will recognize as
LTC3815
0xE8
MFR_VOUT_COMMAND
R/W Word
0.1%/Bit
0.1%/Bit
2
2
V
Margining Command 25% range at 0.1%/bit in
OUT
2's compliment. Defaults to 0% at power-up
0xED
0xFA
MFR_VOUT_MARGIN_LOW
MFR_RAIL_ADDRESS
R/W Word
R/W Byte
Same format as MFR_VOUT_COMMAND
1 or 2 Set Common PMBus Address (B6-B0), Clear B7 to
enable. Set B7 to disable. Valid addresses are 0x00 to
0x7 F.
0xFD
MFR_RESET
W Byte
0, 1 or 2 Reset PMBus Interface and ADC to Power-On State
Write data is ignored
Rev B
13
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LTC3815
OPERATION
Main Control Loop
value is changed with the MFR_VOUT_COMMAND com-
mand through the PMBus interface. When a change in
the reference is detected, the reference is ramped (0.1%/
step) from its current value to the new value at a rate
The LTC3815 is a 6A current mode monolithic step-down
regulator with PMBus Interface. The accurate 100µA cur-
rent source on the REF pin allows the user to use just one
external resistor to program the output voltage. In nor-
mal operation, the internal top power MOSFET is turned
on for a fixed interval determined by a one-shot timer,
OST. When the top power MOSFET turns off, the bottom
power MOSFET turns on until the current comparator,
ICMP, trips, restarting the one-shot timer and initiating
the next cycle. Inductor current is determined by sensing
the voltage drop across the bottom power MOSFET’s VDS.
set by the capacitor value connected to the C
pin,
SLEW
thus providing programmable slew rate of the V
tran-
OUT
sition. To eliminate the latency of the PMBus transaction
when faster changes are required, the LTC3815 can be
pre-loaded with two additional offsets with the MFR_
VOUT_MARGIN_HIGH and MFR_VOUT_MARGIN_LOW
commands. The reference offset can then be switched
between any of these three register values with the 3-state
MARGIN pin. When using the MARGIN pin, the latency of
The voltage on the I pin sets the comparator threshold
TH
the V
transition is limited only by the chosen C
OUT
capacitor and the loop bandwidth of the power suSpLpElWy.
Changes to these registers are prevented by pulling the
write protect (WP) pin high.
corresponding to the inductor valley current. The error
amplifier, EA, adjusts this I voltage by comparing the
TH
feedback signal, V , from the output voltage with that of
FB
voltage on the REF pin. If the load current increases, it
causes a drop in the feedback voltage relative to the inter-
Telemetry Readback
nal reference. The I voltage then rises until the average
TH
The LTC3815 has an integrated 13-bit ADC that moni-
tors and performs conversions on the input and output
voltage, input and output current, and die temperature.
The values are refreshed at a 25Hz rate and are readable
through the PMBus interface.
inductor current matches that of the load current.
At low load current, the inductor current can drop to zero
and become negative. This is detected by current reversal
comparator, IREV, which then shuts off the bottom power
MOSFET, resulting in discontinuous operation. Both power
MOSFETs will remain off with the output capacitor sup-
plying the load current until the I voltage rises above
the zero current level (~0.6V) toTiHnitiate another cycle.
Discontinuous mode operation is disabled by tying the
A peak monitor is also available for each of these teleme-
try measurements to provide that highest value measured
since the start of the monitor. The monitor is reset by the
MFR_CLEAR_PEAKS command, writing to the individual
peak register, or de-asserting RUN_MSTR.
MODE pin to V , which forces continuous synchronous
IN
operation regardless of output load.
Output Voltage Tracking and Soft-Start
The operating frequency is determined by the value of the
The LTC3815 allows the user to program its output volt-
age ramp rate by means of the TRACK/SS pin. An inter-
nal 5µA pulls up the TRACK/SS pin to VIN. Putting an
external capacitor on TRACK/SS enables soft starting the
output to prevent current surge on the input supply. If
no capacitor is connected or TRACK/SS pin is connected
R resistor, which programs the current for the internal
T
oscillator. The internal phase-lock loop servos the switch-
ing regulator on-time to track the internal oscillator to
force constant switching frequency. If an external clock
signal is detected on the MODE/SYNC pin, the phase-lock
loop will servo the on-time to track the external clock
signal instead.
to V , the ramp rate defaults to 1.1 volts/ms. For out-
IN
put tracking applications, TRACK/SS can be externally
driven by another voltage source. For TRACK/SS less than
V
Margining
OUT
the output voltage reference (set by the I resistor and
REF
The LTC3815 has an internal 9-bit DAC that provides up
to 25% adjustment at 0.1%/bit resolution around the
reference voltage set at the REF pin. The digital offset
margin register), the TRACK/SS voltage will override the
reference input to the error amplifier, thus regulating the
Rev B
14
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LTC3815
OPERATION
feedback voltage to that of TRACK/SS pin. During this
start-up time, the LTC3815 will operate in discontinuous
mode. When TRACK/SS is above the reference voltage,
tracking is disabled and the feedback voltage will regulate
to the reference voltage. Either concurrent or ratiomet-
ric tracking can be implemented by connecting the track
voltage to either the IREF pin or the TRACK/SS pin as
described in the applications section.
Pulling RUN_STBY pin low or clearing the ON bit in the
OPERATION register puts the LTC3815 in a standby mode
where the regulator is off but the ADC and PMBus are still
active. In standby mode the LTC3815 will still respond to
the PMBus host but will only refresh the telemetry data
at 1Hz rate instead of 25Hz. In standby mode the supply
current is 120μA. Exiting standby mode with the rising
edge of the ON bit resets all faults and the ALERT pin. All
data written to the internal registers, such as the margin
registers, is not affected by this shutdown mode, so when
Output Power Good
RUN_STBY is re-asserted, the V
will power back up
OUT
When the LTC3815’s output voltage is within the its power
good window of the regulation point, the output voltage
is good and the PGOOD pin is pulled high with an exter-
nal resistor. Otherwise, an internal open-drain pull-down
device (40Ω) will pull the PGOOD pin low. This window
is programmed by the PGLIM pin by connecting it to a
resistive divider to the REF pin. This allows the the PGOOD
window to be programmed as a percentage of the output
to the last value written prior to shutdown (as long as no
change to the margin registers or MARGIN pin was made
during shutdown).
For the switcher to run and provide output regulation all
three must be asserted, i.e. RUN_MSTR and RUN_STBY
pins high and OPERATION ON bit set. At power on or
master shutdown, the ON bit is automatically set in the
OPERATION register. Pulling RUN_MSTR low overrides
the standby controls and puts the LTC3815 in master
shutdown.
voltage reference. If PGLIM is tied to V , the PGOOD
window defaults to 10%.
IN
The PGOOD Filter Delay pin provides a user program-
mable delay from output voltage good to the rising edge
of PGOOD. A wide range of delays from 200μs to 25ms
can be user programmed by a configuration resistor con-
nected to the PGFD pin. To prevent unwanted PGOOD
Table 2. Shutdown Modes
INPUT CONDITIONS
ON/OFF STATES
RUN_MSTR RUN_STBY ON BIT
V
OUT
PMBus
ADC
I
Q
High
X
0
OFF
ON
1Hz Refresh 120μA
(see Note)
glitches during transients or dynamic V
changes, the
OUT
LTC3815’s PGOOD falling edge includes a blanking delay
of approximately 16 switching cycles.
Low
High
X
X
1
OFF
ON
OFF
ON
OFF
<1μA
5mA
High
25Hz
Refresh
Continuous operation is forced during OV and UV condi-
tion except during start-up when the TRACK/SS pin is
ramping up to the internal reference voltage.
High
Low
X
OFF
ON
1Hz Refresh 120μA
(see Note)
Note: Only V , V
and temperature telemetry are refreshed.
IN OUT
Master Shutdown and Standby Modes
Short Circuit Protection
There are three different ways to shut down the LTC3815:
RUN_MSTR pin, RUN_STBY pin, and the ON bit of the
OPERATION command.
The LTC3815 has a precision cycle-by-cycle current limit
to prevent inductor saturation in a short circuit condition.
The valley of the inductor current is guaranteed to not
exceed 6A 10%. The maximum cycle-by-cycle inductor
Pulling the RUN_MSTR pin low forces the LTC3815 into a
master shutdown state, turning off both power MOSFETs,
the internal control circuitry, the ADC converter, and the
PMBus interface. Also, all data written to the internal reg-
isters, such as the margin register, will be reset to the
power-on state. Supply current in this mode is typically
less than 1μA.
current is therefore limited to 6A + 10% + ΔI , where ΔI
L
L
depends on the inductor valley and operating frequency
but is typically ~2A. Internal control circuitry also guar-
antees smooth recovery with no output voltage overshoot
once the short is removed.
Rev B
15
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LTC3815
OPERATION
25MHz Error Amplifier and Remote Sense Differential
Amplifier
2-Phase Operation
For output loads that demand more than 6A of current,
two LTC3815’s can be paralleled to run out-of-phase to
provide up to 12A output current. To configure a 2-phase
system, one LTC3815 will act as a master and the other
a slave (see the schematic in the Typical Applications
section). Connecting the VSS_SENSE pin to VIN puts the
LTC3815 in slave mode by tri-stating its error amplifier
The LTC3815 utilizes a 25MHz error amplifier and dif-
ferential amplifier for fast and accurate output voltage
regulation. The operational amplifier style error amplifier
allows precision tuning of the system poles and zeros
for optimal transient response. The remote sense dif-
ferential amplifier allows output voltage sensing at the
point-of-load and thus provides very accurate regulation
of the output voltage and telemetry readback regardless of
load current. The sensed output voltage is available at the
and remote sense amplifier. The I pins of both IC’s are
TH
connected together so that both are regulating the induc-
tor current based on the master’s I voltage. The mas-
TH
DA
pin (referenced to SGND). This pin is typically con-
ter’s CLKOUT pin is a clock waveform that is 180° out-of-
phase to its internal clock. This CLKOUT can be connected
to the MODE/SYNC pin of the slave to force the slave’s
PLL to lock onto this clock input and run out-of-phase
with the master. The RUN_STBY pins are also connected
together as a handshaking signal between the two so that
both will shutoff together in case of a fault in only one of
the phases, such as overtemperature condition.
OUT
nected to the FB pin which is the error amplifier “-“ input.
Using Separate V /PV Supplies
IN
IN
The LTC3815 has two supply pins: V that supplies the
IN
IC control circuitry and PV that supplies the driver and
IN
power switches. VIN requires a minimum of 2.25V to
guarantee proper operation, while PVIN may be able to
supply power to the load at lower voltages if the load
demands do not exceed the weaker capability of the power
switches at the lower voltage. To maximize the lower oper-
ating range of the supply voltage, two separate supplies
See the Applications Information section for further
details regarding 2-phase operation.
Discontinuous/Forced Continuous Operation
can be used – a V supply that is > 2.25V and rated at
IN
The LTC3815 can operate in one of two modes selectable with
the MODE/SYNC pin:discontinuous mode or forced continu-
10mA or higher and a PV supply, rated for the load, that
IN
can be run all the way into dropout. Each supply pin has
an individual undervoltage-lockout comparator to shut
off the supply when its respective voltage is too low to
guarantee proper operation.
ous mode. Connecting the MODE/SYNC pin to V selects dis-
IN
continuous mode. Discontinuous mode is selected when high
efficiency at very light loads is desired. In this mode, when
the inductor current reverses, the bottom MOSFET turns off
to minimize the efficiency loss due to reverse current flow.
This reduces the conduction loss and slightly improves the
efficiency. As the load reduces, the driver switching frequency
drops in proportion to the load, which further improves effi-
ciency by minimizing gate charge losses.
Thermal Warning and Thermal Shutdown
The LTC3815 has two levels of thermal thresholds and
two levels of responses. When the internal die tem-
perature exceeds 150°C, the overtemperature bit in the
STATUS_WORD is set and the ALERT pin pulls low to alert
the PMBus master. If the temperature continues to rise
and exceeds 170°C, the LTC3815 shuts down all circuitry,
including output regulation, and will no longer respond to
the PMBus host. Both temperature monitors have about
20°C of hysteresis before the overtemperature condition
is cleared. The temperature warning bit in the STATUS_
WORD is latched and remains set until the host clears it.
Forcing the MODE/SYNC pin low enables forced continu-
ous mode operation. In forced continuous mode, the
bottom MOSFET is always on when the top MOSFET is
off, allowing the inductor current to reverse at low cur-
rents. This mode is less efficient due to conduction and
switching losses, but has the advantage of better tran-
sient response at low currents, constant frequency opera
-
tion, and the ability to maintain regulation when sinking
current.
Rev B
16
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LTC3815
OPERATION
During soft-start, the LTC3815 forces the controller to
operate in discontinuous mode until the soft-start volt-
age reaches the internal reference to guarantee smooth
startup into a precharged output capacitor. During mar-
gining transitions and overvoltage conditions, however,
the LTC3815 always operates in forced continuous mode
to allow the switcher to sink current.
PMBus address can be dynamically assigned by using
the MFR_RAIL_ADDRESS command. It is recommended
that rail addressing should be limited to command write
operations.
All four means of PMBus addressing require the user to
employ disciplined planning to avoid addressing conflicts.
Fault Status
SERIAL INTERFACE
The STATUS_WORD and ALERT pin provide fault status
information of the LTC3815 to the host.
The LTC3815 serial interface is a PMBus compliant slave
device and can operate at any frequency between 10kHz
and 400kHz. The address is configurable using an external
resistor. In addition the LTC3815 always responds to the
global broadcast address of 0x5A or 0x5B (7 bit). The
serial interface supports the following protocols defined
in the PMBus specifications: 1) send command, 2) write
byte, 3) write word, 4) group, 5) read byte and 6) read
word. The PMBus write operations are not acted upon
until a complete valid message is received by the LTC3815
including the STOP bit.
Bus Timeout Failure
The LTC3815 implements a timeout feature to avoid hang-
ing the serial interface. The data packet timer begins at the
first START event before the device address write byte.
Data packet information must be completed within 25ms
or the LTC3815 will tri-state the bus and ignore the given
data packet. Data packet information includes the device
address byte write, command byte, repeat start event (if a
read operation), device address byte read (if a read opera-
tion), and all data bytes.
Communication Failure
The user is encouraged to use as high a clock rate as
possible to maintain efficient data packet transfer between
all devices sharing the serial bus interface. The LTC3815
supports the full PMBus frequency range from 10kHz to
400kHz.
Attempts to access unsupported commands or writing
invalid data to supported commands will result in a CML
fault. The CML bit is set in the STATUS_WORD command
and the ALERT pin is pulled low.
Device Addressing
2
Similarity Between PMBus, SMBus and I C 2-Wire
The LTC3815 offers four different types of addressing over
the PMBus interface, specifically: 1) global, 2) device, 3)
rail addressing and 4) alert response address (ARA).
Interface
The PMBus 2-wire interface is an incremental extension
of the SMBus. SMBus is built upon I C with some minor
2
Global addressing provides a means of the PMBus master
to address all LTC3815 devices on the bus. The LTC3815
global address is fixed 0x5A or 0x5B (7 bit) or 0xB4 or
0xB6 (8 bit) and cannot be disabled.
differences in timing, DC parameters and protocol. The
PMBus/SMBus protocols are more robust than simple
I2C byte commands because PMBus/SMBus provide
time-outs to prevent bus hangs and optional packet error
checking (PEC) to ensure data integrity. In general, a mas-
Device addressing provides the standard means of the
PMBus master communicating with a single instance
of an LTC3815. The value of the device address is set
by the ASEL configuration pin. Rail addressing pro-
vides a means of the PMBus master addressing a set of
channels connected to the same output rail, simultane-
ously. This is similar to global addressing, however, the
2
ter device that can be configured for I C communication
can be used for PMBus communication with little or no
change to hardware or firmware. Repeat start (restart)
2
is not supported by all I C controllers but is required for
2
SMBus/PMBus reads. If a general purpose I C controller
is used, check that repeat start is supported.
Rev B
17
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LTC3815
OPERATION
For a description of the minor extensions and exceptions
PMBus makes to SMBus, refer to PMBus Specification
Part 1 Revision 1.1: Paragraph 5: Transport.
The LTC3815 is a slave device. The master can communi-
cate with the LTC3815 using the following formats:
n
Master transmitter, slave receiver
For a description of the differences between SMBus
and I2C, refer to System Management Bus (SMBus)
Specification Version 2.0: Appendix B—Differences
n
Master receiver, slave transmitter
The following PMBus protocols are supported:
2
Between SMBus and I C.
n
Write Byte, Write Word, Send Byte
n
Read Byte, Read Word
PMBus Serial Interface
n
Alert Response Address
The LTC3815 communicates with a host (master) using
the standard PMBus serial bus interface. The Timing
Diagram, Figure 1, shows the timing relationship of the
signals on the bus. The two bus lines, SDA and SCL,
must be high when the bus is not in use. External pull-up
resistors or current sources are required on these lines.
Figure 3 through Figure 6 illustrate the aforementioned
PMBus protocols. All transactions support GCP (group
command protocol).
Figure 2 is a key to the protocol diagrams in this section.
ꢀꢁꢂ
ꢅ
ꢒ
ꢅ
ꢀꢊꢇꢁꢂꢈꢉ
ꢅ
ꢅ
ꢀꢍ
ꢅ
ꢆꢁꢇꢀꢁꢂꢉ
ꢒ
ꢅ
ꢓ
ꢅ
ꢅ
ꢅ
Bꢊꢎ
ꢓ
ꢄꢋꢌ
ꢀꢃꢄ
ꢅ
ꢅ
ꢅ
ꢀꢊꢇꢀꢈꢋꢉ
ꢆꢁꢇꢀꢈꢂꢉ
ꢀꢊꢇꢀꢈꢂꢉ
ꢅ
ꢅ
ꢆꢐꢔꢆ
ꢆꢁꢇꢁꢂꢈꢉ
ꢕꢖꢗꢘ ꢎꢙꢗ
ꢀꢈꢂRꢈ
ꢃꢋꢏꢁꢐꢈꢐꢋꢏ
Rꢑꢍꢑꢂꢈꢑꢁ ꢀꢈꢂRꢈ
ꢃꢋꢏꢁꢐꢈꢐꢋꢏ
ꢀꢈꢋꢍ
ꢀꢈꢂRꢈ
ꢃꢋꢏꢁꢐꢈꢐꢋꢏ ꢃꢋꢏꢁꢐꢈꢐꢋꢏ
Figure 1. Timing Diagram
ꢍ
ꢒ
ꢍ
ꢍ
ꢂ
ꢛ
ꢌ
ꢍ
ꢂ
ꢛ
ꢍ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢈꢉ
ꢅꢂꢆꢂ Bꢇꢆꢄ
ꢊ
ꢀ
ꢀꢆꢂRꢆ ꢓꢔꢕꢅꢖꢆꢖꢔꢕ
ꢀꢉ
Rꢄꢊꢄꢂꢆꢄꢅ ꢀꢆꢂRꢆ ꢓꢔꢕꢅꢖꢆꢖꢔꢕ
Rꢗ Rꢄꢂꢅ ꢘBꢖꢆ ꢃꢂꢁꢙꢄ ꢔꢏ ꢍꢚ
ꢈꢉ ꢈRꢖꢆꢄ ꢘBꢖꢆ ꢃꢂꢁꢙꢄ ꢔꢏ ꢐꢚ
ꢛ
ꢀꢜꢔꢈꢕ ꢙꢕꢅꢄR ꢂ ꢏꢖꢄꢁꢅ ꢖꢕꢅꢖꢓꢂꢆꢄꢀ ꢆꢜꢂꢆ ꢆꢜꢂꢆ
ꢏꢖꢄꢁꢅ ꢖꢀ RꢄꢝꢙꢖRꢄꢅ ꢆꢔ ꢜꢂꢃꢄ ꢆꢜꢄ ꢃꢂꢁꢙꢄ ꢔꢏ ꢛ
ꢂ
ꢊ
ꢂꢓꢞꢕꢔꢈꢁꢄꢅꢟꢄ ꢘꢆꢜꢖꢀ Bꢖꢆ ꢊꢔꢀꢖꢆꢖꢔꢕ ꢠꢂꢇ Bꢄ ꢐ
ꢏꢔR ꢂꢕ ꢂꢓꢞ ꢔR ꢍ ꢏꢔR ꢂ ꢕꢂꢓꢞꢚ
ꢀꢆꢔꢊ ꢓꢔꢕꢅꢖꢆꢖꢔꢕ
ꢊꢄꢓ ꢊꢂꢓꢞꢄꢆ ꢄRRꢔR ꢓꢔꢅꢄ
ꢠꢂꢀꢆꢄR ꢆꢔ ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢃꢄ ꢆꢔ ꢠꢂꢀꢆꢄR
ꢡꢡꢡ
ꢓꢔꢕꢆꢖꢕꢙꢂꢆꢖꢔꢕ ꢔꢏ ꢊRꢔꢆꢔꢓꢔꢁ
ꢋꢌꢍꢎ ꢏꢐꢑ
Figure 2. PMBus Packet Protocol Diagram Element Key
Rev B
18
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LTC3815
OPERATION
A value shown below a field in the following figures is a
mandatory value for that field.
n
Combined format. During a change of direction within
a transfer, the master repeats both a start condition and
the slave address but with the R/W bit reversed. In this
case, the master receiver terminates the transfer by
generating a NACK on the last byte of the transfer and
a STOP condition.
The data formats implemented by PMBus are:
n
Master transmitter transmits to slave receiver. The
transfer direction in this case is not changed.
n
Master reads slave immediately after the first byte. At
Examples of these formats are shown in Figure 3 through
Figure 7.
the moment of the first acknowledgment (provided by
the slave receiver) the master transmitter becomes a
master receiver and the slave receiver becomes a slave
transmitter.
ꢑ
ꢕ
ꢑ
ꢑ
ꢐ
ꢑ
ꢐ
ꢑ
ꢑ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢌꢍ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢅꢂꢊꢂ Bꢋꢊꢄ
ꢂ
ꢎ
ꢏꢐꢑꢒ ꢓꢔꢏ
Figure 3. Write Byte Protocol
ꢑ
ꢖ
ꢑ
ꢑ
ꢐ
ꢑ
ꢐ
ꢑ
ꢐ
ꢑ
ꢑ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢌꢍ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢅꢂꢊꢂ Bꢋꢊꢄ ꢁꢇꢌ
ꢂ
ꢅꢂꢊꢂ Bꢋꢊꢄ ꢗꢘꢙꢗ
ꢂ
ꢎ
ꢏꢐꢑꢒ ꢓꢔꢕ
Figure 4. Write Word Protocol
ꢋ
ꢏ
ꢋ
ꢋ
ꢊ
ꢋ
ꢋ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢆꢇ
ꢂ
ꢐꢑꢒꢒꢂꢓꢅ ꢐꢑꢅꢄ
ꢂ
ꢈ
ꢉꢊꢋꢌ ꢍꢎꢌ
Figure 5. Send Byte Protocol
ꢏ
ꢔ
ꢏ
ꢏ
ꢎ
ꢏ
ꢏ
ꢔ
ꢏ
ꢏ
ꢎ
ꢏ
ꢎ
ꢏ
ꢂ
ꢏ
ꢏ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢚ
ꢂ
ꢅꢂꢕꢂ Bꢖꢕꢄ ꢁꢇꢊ
ꢂ
ꢅꢂꢕꢂ Bꢖꢕꢄ ꢗꢘꢙꢗ
ꢌ
ꢍꢎꢏꢐ ꢑꢒꢓ
Figure 6. Read Word Protocol
ꢏ
ꢓ
ꢏ
ꢏ
ꢎ
ꢏ
ꢏ
ꢎ
ꢏ
ꢏ
ꢎ
ꢏ
ꢂ
ꢏ
ꢏ
ꢀ
ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ ꢊꢋ
ꢂ
ꢆꢇꢈꢈꢂꢉꢅ ꢆꢇꢅꢄ
ꢂ
ꢀꢋ ꢀꢁꢂꢃꢄ ꢂꢅꢅRꢄꢀꢀ Rꢖ
ꢂ
ꢅꢂꢔꢂ Bꢕꢔꢄ
ꢌ
ꢍꢎꢏꢐ ꢑꢒꢓ
Figure 7. Read Byte Protocol
Rev B
19
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LTC3815
APPLICATIONS INFORMATION
The basic LTC3815 application circuit is shown in Figure 8.
Tying the RT pin to V sets the default internal operating
IN
frequency to 1MHz 15%.
Operating Frequency
The LTC3815’s internal oscillator can be synchronized to
an external frequency by applying a square wave clock
signal to the MODE/SYNC pin. During synchronization,
the top switch turn-on is locked to the rising edge of the
external frequency source. The synchronization frequency
range is 300kHz to 3MHz. During synchronization, dis-
continuous operation is disabled.
Selection of the operating frequency is a trade-off between
efficiency and component size. High frequency operation
allows the use of smaller inductor and capacitor values.
Operation at lower frequencies improves efficiency by
reducing internal gate charge losses but requires larger
inductance values and/or capacitance to maintain low
output ripple voltage. The operating frequency of the
LTC3815 is determined by an external resistor that is con-
nected between the RT pin and ground. The value of the
resistor sets the ramp current that is used to charge and
discharge an internal timing capacitor within the oscillator
and can be calculated by using the following equation:
The internal PLL has a synchronization range of 30%
around its programmed frequency. Therefore, during
external clock synchronization be sure that the external
clock frequency is within this 30% range of the R pro-
T
grammed frequency.
When using the RT pin to program the oscillator frequency,
a square wave clock that is running 180° out-of-phase
with the internal oscillator is available at the CLKOUT pin
for connection to a second LTC3815 for 2-phase opera-
tion (see the 2-Phase section).
11
1.15 • 10
R =
Ω
T
1.11
f
OSC
Frequencies as high as 3MHz are possible, as long as the
minimum on-time requirement is met (see next section).
ꢀ
ꢁꢂ
ꢃꢄꢃꢅꢀ ꢆꢇ ꢅꢄꢅꢀ
ꢓ
ꢁꢂ
ꢃꢃꢢꢛ
ꢣꢤ
ꢍꢀ
ꢁꢂ
ꢀ
ꢁꢂ
ꢑꢓꢒꢝ ꢑꢏꢌꢝ ALERT
ꢕꢇꢏꢖꢗꢑꢘꢂꢓ
RꢈꢂꢙꢕꢑꢆR
RꢈꢂꢙꢑꢆBꢘ
ꢍꢕBꢈꢑ
ꢕꢌRꢎꢁꢂ
ꢐꢍ
ꢍꢎꢇꢇꢏ
ꢒ
ꢒꢆꢓꢔꢊꢉꢅ
ꢔꢡꢡꢞꢜ
ꢀ
ꢇꢈꢆ
ꢓ
ꢑꢑ
ꢉꢅꢞꢛ
ꢑꢐ
ꢉꢄꢊꢀ
ꢋꢌ
ꢓꢒꢚꢇꢈꢆ
ꢀ
ꢀ
ꢓꢓꢙꢑꢖꢂꢑꢖ
ꢓ
ꢑꢑꢗꢆRꢌꢓꢚ
ꢇꢈꢆ
ꢓ
ꢉꢞꢛ
ꢑꢒꢖꢐ
ꢉꢡꢡꢢꢛ
ꢑꢑꢙꢑꢖꢂꢑꢖ
R
ꢣꢃ
ꢓꢉ
ꢓꢑꢒꢖꢐ
R
ꢉꢟ
ꢆ
ꢏꢌ
ꢉꢉꢄꢊꢟꢝ ꢉꢠ
ꢇꢈꢆ
Rꢆ
ꢀ
ꢛB
ꢍꢎꢒꢁꢕ
Rꢖꢛ
ꢁ
ꢆꢜ
R
ꢓꢃ
ꢓ
ꢌꢑꢖꢒ
ꢍꢎꢛꢏ
R
R
ꢉꢤꢄꢔꢟ
ꢡꢄꢅꢠ
Rꢖꢛꢃ
Rꢖꢛꢉ
ꢓꢃ
ꢉꢡꢟ
ꢔꢄꢥꢟ
ꢉꢞꢛ
ꢡꢄꢅꢠ
R
R
ꢍꢎꢛꢏ
ꢌꢑꢖꢒ
ꢓ
ꢓꢉ
ꢤꢥꢦꢛ
ꢔꢊꢉꢅ ꢛꢡꢊ
Figure 8. 1.8V, 6A Step-Down Regulator
Rev B
20
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LTC3815
APPLICATIONS INFORMATION
Minimum Off-Time and Minimum On-Time
Considerations
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low fre-
quency with small ripple current. However, achieving this
requires a large inductor. There is a trade-off between
component size, efficiency and operating frequency.
The minimum off-time, t
, is the smallest amount
OFF(MIN)
of time that the LTC3815 is capable of turning on the bot-
tom power MOSFET, tripping the current comparator and
turning the power MOSFET back off. This time is generally
about 100ns. The minimum off-time limit imposes a maxi-
A reasonable starting point is to choose a ripple current
that is about 30-40% of IOUT(MAX). This is especially
important at low VOUT operation where VOUT is 1.8V
or below. Care must be given to choose an inductance
value that will generate a big enough current ripple so
that the chip’s valley current comparator has enough sig-
nal-to-noise ratio to force constant switching frequency.
Meanwhile, also note that the largest ripple current occurs
mum duty cycle of t /(t + t
). If the maximum
OFF(MIN)
ON ON
duty cycle is reached, due to a dropping input voltage for
example, then the output will drop out of regulation. The
minimum input voltage to avoid dropout is:
t
+ t
ON
OFF(MIN)
ON
V
= V
•
IN(MIN)
OUT
t
at the highest V . To guarantee that ripple current does
IN
Conversely, the minimum on-time is the smallest dura-
tion of time in which the top power MOSFET can be in
its “on” state. This time is typically 75ns. In continuous
mode operation, the minimum on-time limit imposes a
minimum duty cycle of:
not exceed a specified maximum, the inductance should
be chosen according to:
⎛
⎞
⎟
⎟
⎠
V
V
OUT
OUT
⎜
L =
• 1−
⎜
⎝
f • ΔI
V
IN(MAX)
L(MAX)
DC
= f • t
MIN
ON(MIN)
Once the value for L is known, the type of inductor must
be selected. Actual core loss is independent of core size
for a fixed inductor value, but is very dependent on the
inductance selected. As the inductance or frequency
increases, core losses decrease. Unfortunately, increased
inductance requires more turns of wire and therefore cop-
per losses will increase.
where t
is the minimum on-time. As the equation
ON(MIN)
shows, reducing the operating frequency will alleviate the
minimum duty cycle constraint.
In the cases where the minimum duty cycle is surpassed,
the output voltage will still remain in regulation, but the
switching frequency will decrease from its programmed
value. This is an acceptable result in many applications, so
this constraint may not be of critical importance in most
cases. High switching frequencies may be used in the
design without any fear of severe consequences. As the
sections on inductor and capacitor selection show, high
switching frequencies allow the use of smaller board com-
ponents, thus reducing the size of the application circuit.
Ferrite designs have very low core losses and are pre-
ferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard”, which means that
LTC3815 inductance collapses abruptly when the peak
design current is exceeded. This results in an abrupt
increase in inductor ripple current and consequent output
voltage ripple. Do not allow the core to saturate!
Inductor Selection
Different core materials and shapes will change the size/
current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy materi-
als are small and don’t radiate much energy, but generally
cost more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
Given the desired input and output voltages, the induc-
tor value and operating frequency determine the ripple
current:
⎛
⎞
⎟
⎠
V
V
OUT
OUT
ΔI =
• 1−
⎜
L
f • L
V
IN
⎝
Rev B
21
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LTC3815
APPLICATIONS INFORMATION
mainly depends on the price versus size requirements
and any radiated field/EMI requirements. New designs for
surface mount inductors are available from Toko, Vishay,
NEC/Tokin, Cooper, TDK, Würth Elektronik and Coilcraft.
Refer to Table 3 for more details.
The selection of C
is determined by the effective series
OUT
resistance (ESR) that is required to minimize voltage rip-
ple and load step transients as well as the amount of bulk
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
the load transient response. The output ripple, ΔV , is
determined by:
OUT
Table 3. Representative Surface Mount Inductors
INDUCTANCE
(μH)
DCR
(mΩ)
MAX
CURRENT (A)
DIMENSIONS
(mm)
HEIGHT
(mm)
⎛
⎜
⎝
⎞
⎟
⎠
1
ΔV
< ΔI
+ESR
Coilcraft XAL6030 Series
L
OUT
8 • f • C
OUT
0.18
0.33
0.56
1.59
2.30
3.01
39
30
29
6.56 × 3.36
6.56 × 3.36
6.56 × 3.36
3.1
3.1
3.1
The output ripple is highest at maximum input voltage
since ΔIL increases with input voltage. Multiple capacitors
placed in parallel may be needed to meet the ESR and
RMS current handling requirements. Dry tantalum, spe-
cial polymer, aluminum electrolytic, and ceramic capaci-
tors are all available in surface mount packages. Special
polymer capacitors are very low ESR but have lower
capacitance density than other types. Tantalum capacitors
have the highest capacitance density but it is important
to only use types that have been surge tested for use in
switching power supplies. Aluminum electrolytic capaci-
tors have significantly higher ESR, but can be used in
cost-sensitive applications provided that consideration
is given to ripple current ratings and long-term reliability.
Ceramic capacitors have excellent low ESR characteristics
and small footprints. Their relatively low value of bulk
capacitance may require multiples in parallel.
Würth 744316 Series
0.18
0.33
0.47
0.68
1.25
25
20
5.5 × 5.2
5.5 × 5.2
5.5 × 5.2
5.5 × 5.2
4
4
4
4
1.75
2.75
4.00
16
13.5
C and C
Selection
IN
OUT
The input capacitance, CIN, is needed to filter the trapezoi-
dal wave current at the drain of the top power MOSFET.
To prevent large voltage transients from occurring, a low
ESR input capacitor sized for the maximum RMS current
should be used. The maximum RMS current is given by:
V
V
IN
OUT
I
≅ I
− 1
RMS
OUT(MAX)
V
V
OUT
IN
This formula has a maximum at V = 2V , where
Using Ceramic Input and Output Capacitors
IN
OUT
I
≅I /2.
OUT
Higher value, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
RMS
This simple worst-case condition is commonly used for
design because even significant deviations do not offer
much relief. Note that ripple current ratings from capaci-
tor manufacturers are often based on only 2000 hours of
life which makes it advisable to further derate the capaci-
tor, or choose a capacitor rated at a higher temperature
than required.
V
input. At best, this ringing can couple to the output
IN
Several capacitors may also be paralleled to meet size or
height requirements in the design. For low input voltage
applications, sufficient bulk input capacitance is needed
to minimize transient effects during output load changes.
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at V large enough to damage the
IN
part.
Rev B
22
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LTC3815
APPLICATIONS INFORMATION
When choosing the input and output ceramic capacitors,
choose the X5R and X7R dielectric formulations. These
dielectrics have the best temperature and voltage char-
acteristics of all the ceramics for a given value and size.
The OPTI-LOOP compensation allows the transient
response to be optimized for a wide range of output
capacitors. The availability of the I pin not only allows
TH
optimization of the control loop behavior but also pro-
vides a DC-coupled and AC-filtered closed-loop response
test point. The DC step, rise time and settling at this test
point truly reflects the closed-loop response. Assuming a
predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin.
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge stor-
age requirement. During a load step, the output capaci-
tor must instantaneously supply the current to support
the load until the feedback loop raises the switch current
enough to support the load. The time required for the
feedback loop to respond is dependent on the compensa-
tion and the output capacitor size. Typically, 3 to 4 cycles
are required to respond to a load step, but only in the first
cycle does the output drop linearly. The output droop,
The I external components (R , C , C ) shown in
TH
C1 C1 C2
the Figure 8 circuit provides an adequate starting point
for most applications. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because their various types and values determine the loop
feedback factor gain and phase. An output current pulse
of 20% to 100% of full load current having a rise time of
1µs to 10µs will produce output voltage and ITH pin wave-
forms that will give a sense of the overall loop stability
without breaking the feedback loop.
V
, is usually about 2 to 3 times the linear drop of
DROOP
the first cycle. Thus, a good place to start with the output
capacitor value is approximately:
ΔI
OUT
C
≈ 2.5
OUT
f • V
O
DROOP
More capacitance may be required depending on the duty
cycle and load step requirements.
In most applications, the input capacitor is merely required
to supply high frequency bypassing, since the impedance
to the supply is very low. A 22µF ceramic capacitor is usu-
ally enough for these conditions. Place this input capaci-
In some applications, a more severe transient can be
caused by switching in loads with large (>10µF) input
capacitors. The discharged input capacitors are effec-
tively put in parallel with C , causing a rapid drop in
OUT
tor as close to the PV pins as possible.
IN
V
. No regulator can deliver enough current to prevent
OUT
this problem, if the switch connecting the load has low
resistance and is driven quickly. The solution is to limit
the turn-on speed of the load switch driver. A Hot Swap
controller is designed specifically for this purpose and
usually incorporates current limiting, short-circuit protec-
tion and soft-starting.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in load current.
When a load step occurs, V
immediately shifts by an
OUT
amount equal to ΔI
• ESR, where ESR is the effective
LOAD
Calculating Compensation Values
series resistance of C . ΔI
also begins to charge or
OUT
LOAD
discharge C
generating a feedback error signal used by
OUT
If the “trial and error” approach described in the previous
section doesn’t result in adequate transient performance,
the procedure described in this section can be used to
calculate more precise compensation component values
to achieve a desired bandwidth and phase margin. This
the regulator to return V
to its LTC3815 steady-state
OUT
value. During this recovery time, V
can be monitored
for overshoot or ringing that wouOldUTindicate a stability
problem.
Rev B
23
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LTC3815
APPLICATIONS INFORMATION
procedure is also helpful if the output capacitor type is
very different than the one specified in the application
circuits or if a Type 3 compensation network is required.
A Type 3 compensation network includes the additional
power supply model shown in Figure 9. The error
amplifier EA can be modeled as an ideal op amp (for
crossover frequencies < 200kHz) and the inductor as
a voltage controlled current source. The gain/phase
plot should look similar to Figure 10.
components R and C shown in Figure 9.
C3
C3
1) Choose the crossover frequency. For best perfor-
mance, the crossover frequency should be as high
as possible but not greater than about 20% of the
switching frequency.
3) Calculate the component values. Once the gain and
phase are known, note the gain (GAIN, in dB) and
phase (PHASE, in degrees) at the crossover fre-
quency. The compensation components can then be
calculated to make the loop gain (VCCSEN to VOUT
)
2) Plot Gain and Phase of the modulator and output filter.
The modulator and output filter is the portion of the
equal to 0dB and the phase margin equal to 60° at
this frequency. Use the equations below to calculate
the component values. Normally the Type 2 network
will provide the required phase margin. If not, use the
Type 3 equations.
loop from the error amp output (I ) to the regulator
TH
output (V ). To do this, insert a 10Ω to 50Ω resis-
OUT
tor between the output capacitor and the V
pin
CCSEN
(this is R7 on the DC2065 demo board). Then use a
network analyzer to inject an AC signal across this
resistor and plot the Gain and Phase. If a network
analyzer is not available, a close approximation can
obtained with a PSPICE simulator using the LTC3815
4) Add the calculated components to the LTC3815 circuit
and check the load step response. If not adequate, the
components values may need to be tweaked further
or recalculated with a lower crossover frequency until
the desired response is obtained.
ꢌ
ꢌꢂ
ꢌ
ꢌꢀ
ꢔ
ꢌ
ꢌꢙ
R
ꢔ
R
ꢌꢀ
ꢌꢙ
R
ꢌꢂ
ꢋ
ꢈ
ꢇ
ꢌꢌꢍꢉꢎ
ꢋꢌꢍꢄ
ꢏ
ꢐꢑ
ꢒ
= 12 • V
ꢏꢐꢑ
ꢓ
ꢉꢊ
ꢖ
ꢖ
ꢋ
Rꢉꢄ
R
ꢉꢍR
ꢗꢘꢖ
ꢗꢔꢓꢖ
ꢏꢈꢌꢐꢁ
ꢔꢐꢕꢖꢉ ꢀ ꢗꢎꢘꢕ
R
ꢘꢗꢊꢚ
ꢇ
ꢀRꢁꢂꢃꢁꢄꢅꢆ ꢇꢈꢉꢊ
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢒꢓꢔꢕ ꢀꢔꢖ
Figure 9. PSPICE Model of a LTC3815 Current Mode Regulator
Figure 10. Transfer Function of Buck Modulator
Rev B
24
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LTC3815
APPLICATIONS INFORMATION
R
C1
= A convenient resistor value ~1kΩ.
ꢇꢈ
f = chosen crossover frequency
ꢉꢊ
(GAIN/20)
G = 10
lute gain)
(this converts GAIN in dB to G in abso-
ꢀꢁꢂꢃꢄꢅꢆ
Rꢋꢌ
ꢑꢒꢀꢉꢓ
Type 2 Loop:
ꢃꢄꢅꢆ ꢌꢅꢅꢐ
R
ꢍ Rꢅ ꢎ Rꢏ
Rꢋꢌ
⎛
⎜
⎝
⎞
⎟
⎠
BOOST
k = tan
+ 45°
2
1
Figure 11a. PGOOD Window Set to 10% Default
C
=
C1
2π • f • G • K • R
C1
ꢇꢈ
ꢉꢊ
2
C
R
= C K − 1
Rꢋꢌ
C2
C1
(
)
ꢀꢁꢂꢃꢄꢅꢆ
Rꢅ
Rꢎ
K
ꢏꢐꢀꢉꢑ
=
C2
2π • f • C
C2
ꢃꢄꢅꢆ ꢌꢅꢅꢍ
V
(R )
C1
REF
R =
B
V
− V
REF
Figure 11b. PGOOD Window Set By R1/R2
Figure 11. PGOOD Window
OUT
Type 3 Loop:
⎛
⎞
BOOST
Programming PGOOD Threshold and Filter Delay
k = tan
+ 45°
⎜
⎝
⎟
⎠
4
The upper and lower Power Good threshold default to
1
10% when the PGLIM pin is tied to V (see Figure 11a).
IN
C
C
=
C1
C2
2π • f • G • RC1
= C K − 1
However, if a narrower or wider window is desired, these
windows can be programmed to any desired value in the
range of 5% to 40%.
(
)
C1
K
R
R
=
=
C2
C3
The PGOOD upper/lower threshold is programmed by
replacing the single resistor on the REF pin with a resis-
tor divider as follows (see Figure 11b):
2π • f • C
C2
R
C1
K − 1
Reference Voltage = 100µA • (R1+R2)
PGOOD Window = 40% • R2/(R1+R2)
1
C3 =
2πf K • R
C3
The PGOOD window is always centered on the DAC
adjusted reference voltage, thus the center will move to
the new reference voltage when margined up or down.
V
(R )
C1
REF
R =
B
V
− V
REF
OUT
The falling PGOOD (power good to power bad) is filtered
and delayed by 16 clock cycles, thus giving the loop 16
switching cycles to recover from the power bad condition
before pulling the PGOOD pin low.
Output Voltage Programming
The output voltage is set by an external resistor according
to the following equation:
V
= 100µA • R
,
OUT
REF
The rising PGOOD (power bad to power good) filter delay
is user programmable by a configuration resistor at the
where R
SGND.
is the total resistance between REF pin and
REF
PGFD pin and is programmable to one of 7 possible delays
Rev B
25
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LTC3815
APPLICATIONS INFORMATION
from 200μs to 25.6ms as shown in Table 4. Minimum
delay of 200μs can be set by grounding the PGLIM pin
and maximum delay of 25.6ms can be set by tying PGLIM
Margining/C
Selection/Margin Pin
SLEW
Writing to the MFR_VOUT_COMMAND register via the
PMBus allows the adjustment of the V reference up to
OUT
to SV .
IN
25% around the voltage at the REF pin. This voltage can
be adjusted in 0.1% increments by writing the appropriate
9-bit two’s complement value to the register. The MFR_
VOUT_MARGIN_HIGH and MFR_VOUT_MARGIN_LOW
register can also be used to adjust the VOUT reference
value by selecting the desired register with the MARGIN
pin or the OPERATION command as specified in Table 6.
The PGFD pin is sampled only at power on and at initial-
ization after the rising edge of RUN_MSTR, RUN_STBY
or the OPERATION register ON bit. Changes to PGFD will
not take effect until one of these events occur.
Table 4. PGFD Resistor Selection
PGFD RESISTOR
0Ω
PGOOD DELAY
200μs
Table 6. VOUT Margining with the MARGIN Pin and OPERATION
Command
28kΩ
400μs
OPERATION
46.4kΩ
800μs
BITS [5:4]
64.9kΩ
1.6ms
MARGIN
PIN
<0.4V
>1.2V
Hi-Z
BIT 5 BIT 4
V
OUT
REFERENCE
84.5kΩ
3.2ms
X
X
X
X
= [1 + MFR_VOUT_MARGIN_LOW(%) ] • V
REF
113kΩ
6.4ms
= [1 + MFR_VOUT_MARGIN_HIGH(%) ] • V
Open or short to V
25.6ms
REF
IN
0
0
= [1 + MFR_VOUT_COMMAND(%) ] • V
REF
Address Selection (ASEL pin)
Hi-Z
0
1
= [1 + MFR_VOUT_MARGIN_LOW(%) ] • V
= [1 + MFR_VOUT_MARGIN_HIGH(%) ] • V
REF
Hi-Z
1
0
REF
The LTC3815 slave address is selected by the ASEL pin.
The upper four bits of the address are hardwired inter-
nally to 0100 and the lower three bits are programmed
by a resistor connected between the ASEL and SGND
(see Table 5). This allows up to 7 different LTC3815’s
on a single board. The LTC3815 will also respond to the
Global Address 0x5A and the 7-bit address stored in the
MFR_RAIL_ADDRESS register.
Hi-Z
1*
1*
= [1 + MFR_VOUT_COMMAND(%) ] • V
REF
* Setting both bits 4 and 5 high at the same time is illegal and will be
ignored.
Pre-loading the registers and using the MARGIN pin pro-
vides fast margining by eliminating the latency inherent to
serial bus communication. Once the registers are loaded
the output voltage change is limited only by the loop band-
width and the slew rate capacitor (C
).
SLEW
The ASEL pin is sampled only at power on and at initial-
ization after the rising edge of RUN_MSTR, RUN_STBY
or OPERATION register ON bit. Changes to ASEL will not
take affect until one of these events occur.
The C
pin provides slew rate limiting during reference
SLEW
voltage changes. When the reference is changed by either
the MARGIN pin, OPERATION command, or writing new
values to the register, the LTC3815 counts up or down
from the current value in the register to the new value
Table 5. ASEL Resistor Selection
ASEL RESISTOR
0Ω
SLAVE ADDRESS
0100000
at 0.1% per step. The step duration is set by the C
capacitor. The slew rate during the transition is thus:
SLEW
28kΩ
0100001
0.1
46.4kΩ
0100010
SR =
% / ms
64.9kΩ
0100011
C
(nF)+ 0.0043
SLEW
84.5kΩ
0100100
If the CSLEW pin is left open, SR defaults to 23%/ms.
The slew rate limit can be disabled if desired by tying the
102kΩ
0100101
Open or short to V
0100111
IN
C
pin to V . When disabled, the reference is imme-
SLEW
IN
diately stepped from old value to new value in <100ns.
Rev B
26
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LTC3815
APPLICATIONS INFORMATION
Soft-Start
Ratiometric Tracking
After the LTC3815 is turned on or power applied and fin-
ishes its ~500µs initialization sequence, the chip enters
a soft start-up state. The type of soft startup behavior is
set by the TRACK/SS pin:
To implement ratiometric tracking (Figure 13a and
Figure 13b) the controlling voltage, VMASTER is connected
to the REF pin. This source must be able to sink the 100µA
IREF current. Using the REF pin allows VOUT to be adjusted
with the margining commands and MARGIN pin. For
1. Tying TRACK/SS to V selects the internal soft-start
IN
V
> V
connect V
to the REF pin thru a
MASTER
SLAVE
MASTER
circuit. This circuit ramps the output voltage to the
resistive divider. The relationship of V
to V
is:
MASTER
SLAVE
final value within 1ms.
⎛
⎞
⎟
⎠
R1
V
= V
• 1+
⎜
SLAVE
−R1• 100µA
2. If a longer soft-start period is desired, it can be set exter-
nally with a capacitor on the TRACK/SS pin as shown
in Figure 10. The TRACK/SS pin reduces the value of
the internal reference at FB until TRACK/SS charges
above the REF pin voltage. The external soft-start dura-
tion can be calculated by using the following formula:
MASTER
⎝
R2
Note that the 100µA I
current requires V
> R1
REF
MASTER
• 100µA before V
starts rising above 0V. Choose a
SLAVE
low value for R1 to minimize this offset.
For V < V connect V directly to REF
MASTER
MASTER
pin. The ratio of V
SLAVE
MASTER
V
• C
REF
SS
t
=
to V
is now:
SLAVE
SS
5µA
V
R1
MASTER
=
3. The TRACK/SS pin can be used to track the output
voltage of another supply.
V
R1+R2
SLAVE
Coincident Tracking
Regardless of either internal or external soft-start state,
the MODE pin is ignored and soft-start will always be in
discontinuous mode until SS voltage reaches the pro-
To implement coincident tracking with V
≥ V
SLAVE
(Figure 13c) connect VMASTER to theMTARSTAECRK/SS pin
directly or with a resistive divider:
grammed V
reference voltage for the first time.
OUT
V
R1
MASTER
TRACKING
=
V
R1+R2
SLAVE
Using the TRACK/SS or the REF pin, two types of tracking/
sequencing can be used for the LTC3815 (see Figure 12).
V
will follow V
(or a ratio of it as set by R1/
OUT
MASTER
> V at which time V
For ratiometric tracking, V
will always track a ratio of
R2) until V
is regulated
OUT
OUT
MASTER
REF
the input tracking voltage. In coincident tracking, V
to V
.
OUT
REF
will track a ratio of the input tracking voltage until V
≥
OUT
DDR Mode
V
, then V
is regulated to V . Also, with ratiometric
trRaEcFking, the V
can be adjusted with the margin com-
OUT REF
OUT
The LTC3815 can both sink and source current if the
MODE/SYNC pin is set to forced continuous mode. Current
sinking is limited to –6A+ΔIL/2. An external reference volt-
age connected to the REF pin can be used to set the output
voltage. The output voltage can be margined by 25% in
the same way as a resistor programmed reference.
mands and MARGIN pin relative to the tracking voltage.
With coincident tracking, V
can only be adjusted rela-
REF
OUT
tive to V when V
≥ V
.
REF
MASTER
For coincident tracking, be aware that the PGOOD window
is always centered around the DAC adjusted REF pin volt-
age, not the TRACK/SS pin voltage.
Rev B
27
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LTC3815
APPLICATIONS INFORMATION
ꢄ
ꢄ
ꢅꢆꢀꢇ
ꢅꢆꢀꢈ
ꢀꢁꢂꢃ
(12a) Coincident Tracking
ꢄ
ꢄ
ꢅꢆꢀꢇ
ꢅꢆꢀꢈ
ꢍꢎꢇꢏ ꢐꢇꢑ
ꢀꢁꢂꢃ
(12b) Ratiometric Tracking
Figure 12. Two Different Modes of Output Voltage Tracking
Rꢂ
ꢊ
ꢉ
Rꢎꢄ
ꢏꢌ
Rꢍꢄ
ꢎꢋ
ꢋꢌꢍꢇꢎR
ꢊꢋꢌꢇꢍR
ꢐꢑꢇ
ꢄB
ꢏꢐꢇ
Rꢂ
Rꢓ
ꢆꢇꢈꢀꢁꢂꢃ
ꢆꢇꢈꢀꢁꢂꢃ
Rꢉ
ꢄB
ꢍꢍꢒꢇRꢌꢈꢓ
ꢌꢌꢑꢇRꢋꢈꢒ
ꢀꢁꢂꢃ ꢄꢂꢂꢅ
ꢀꢁꢂꢃ ꢄꢂꢂꢅ
Figure 13a. Slave IC Circuit for Ratiometric
Tracking and VMASTER ≤ VSLAVE
Figure 13b. Slave IC Circuit for Ratiometric
Tracking and VMASTER ≥ VSLAVE
Rꢎꢄ
ꢏꢌ
ꢐꢑꢇ
ꢄB
ꢆꢇꢈꢀꢁꢂꢃ
Rꢂ
ꢊ
ꢍꢍꢒꢇRꢌꢈꢓ
ꢋꢌꢍꢇꢎR
Rꢉ
ꢀꢁꢂꢃ ꢄꢂꢂꢅ
Figure 13c. Slave IC Circuit for Coincident
Tracking and VMASTER ≥ VSLAVE
Figure 13. Slave IC Circuits
Rev B
28
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LTC3815
APPLICATIONS INFORMATION
Efficiency Considerations
The RDS(ON) for both the top and bottom MOSFETs
can be obtained from the Typical Performance
The efficiency of a switching regulator is equal to the out-
put power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
2
Characteristics curves. To obtain I R losses, simply
add R to R and multiply the result by the square of
SW
L
the average output current.
Other losses including C and C
ESR dissipative
OUT
IN
losses and inductor core losses generally account for
Efficiency = 100% – (L1 + L2 + L3 + ...)
less than 2% of the total loss.
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Thermal Considerations
Although all dissipative elements in the circuit produce
In most applications, the LTC3815 does not dissipate
much heat due to its high efficiency.
losses, two main sources usually account for most of
2
the losses: V quiescent current and I R losses. The V
IN
IN
However, in applications where the LTC3815 is running
at high ambient temperature with low supply voltage and
high duty cycles, such as in dropout, the heat dissipated
may exceed the maximum junction temperature of the
part. If the junction temperature reaches approximately
160°C, both power switches will be turned off and the SW
node will become high impedance.
quiescent current loss dominates the efficiency loss at
2
very low load currents whereas the I R loss dominates
the efficiency loss at medium to high load currents. In a
typical efficiency plot, the efficiency curve at very low load
currents can be misleading since the actual power lost is
usually of no consequence.
1. The VIN quiescent current is due to two compo-
nents: the DC bias current as given in the Electrical
Characteristics and the internal main switch and syn-
chronous switch gate charge currents. The gate charge
current results from switching the gate capacitance of
the internal power MOSFET switches. Each time the
gate is switched from low to high to low again, a packet
To prevent the LTC3815 from exceeding the maximum
junction temperature, some thermal analysis is required.
The temperature rise is given by:
T
RISE
= (P )(θJA)
D
where P is the power dissipated by the regulator and
D
θJA is the thermal resistance from the junction of the die
of charge dQ moves from V to ground. The resulting
IN
to the ambient temperature. The junction temperature,
dQ/dt is the current out of V due to gate charge, and
IN
T , is given by:
J
it is typically larger than the DC bias current. Both the
T = T + T
RISE
DC bias and gate charge losses are proportional to V ;
J
A
IN
thus, their effects will be more pronounced at higher
where T is the ambient temperature.
A
supply voltages.
As an example, consider the case when the LTC3815 is in
dropout at an input voltage of 3.3V with a load current of
6A at an ambient temperature of 70°C. From the Typical
Performance Characteristics graph of Switch Resistance,
the RDS(ON) resistance of the P-channel switch is 0.035Ω.
Therefore, power dissipated by the part is:
2
2. I R losses are calculated from the resistances of the
internal switches, R , and external inductor, R . In
SW
L
continuous mode the average output current flow-
ing through inductor L is chopped between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET RDS(ON) and the duty cycle
(DC) as follows:
2
P = (I ) • R
= 1.26W
D
OUT
DS(ON)
For the QFN package, the θJA is 38°C/W.
R
SW
= (R )(DC) + (R )(1 – DC)
DS(ON)TOP DS(ON)BOT
Rev B
29
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LTC3815
APPLICATIONS INFORMATION
Therefore, the junction temperature of the regulator oper-
ating at 70°C ambient temperature is approximately:
IIN value. Because of slight differences in tracking
between phases due to IC and inductor tolerances, a
more accurate reading will be obtained by connect-
T = 1.26W • 38°C/W + 70°C = 118°C
J
ing to both phases so that total I
and I can be
OUT
IN
We can safely assume that the actual junction temperature
will not exceed the absolute maximum junction tempera-
ture of 125°C. The actual die temperature can be verified
with the READ_TEMPERATURE_1 command after the
power supply is built and operating.
computed by summing each phase’s contribution.
2) Slave PGOOD/ALERT status and margining: When the
master and slave are monitoring the same output,
it is sufficient to monitor the master’s PGOOD and
ALERT pins only. The PGOOD/ALERT pins from both
master and slave can also be wire OR’ed if desired.
However, if the output voltage is margined with the
PMBus interface, the PGOOD/ALERT status of the
slave will only be valid if the slave knows what the new
margined reference is, i.e. the margin change needs
to be sent to both the master and the slave. This can
be done easily by using the MFR_RAIL_ADDRESS to
assign the same rail address to both the master and
slave so that the margin change can be done with a
single write. Be aware that PMBus reads from a com-
mon address need to be done separately to avoid bus
contentions.
Note that for very low input voltage, the junction tempera-
ture will be higher due to increased switch resistance,
R
. It is not recommended to use full load current
DS(ON)
for high ambient temperature and low input voltage.
To maximize the thermal performance of the LTC3815 the
exposed pad should be soldered to a ground plane. See
the PCB Layout Board Checklist.
2-Phase Operation
Using two LTC3815’s as a 2-phase regulator to supply
12A loads was discussed on Page 16. A few more details
need to be brought to the user’s attention to ensure cor-
rect operation:
3) Using the Master’s CLKOUT: The CLKOUT pin pro-
vides an 180° out-of-phase clock that can be con-
nected to the slaves MODE/SYNC pin as a simple
way to run the phases out-of-phase with each other.
However, be aware that the master’s CLKOUT pin only
provides this out-of-phase clock when the master is
using its internal oscillator programmed from the RT
pin. If the master is externally clocked, the slave’s
anti-phase clock will need to be obtained from another
source.
1) PMBus connection and READ_IIN/IOUT: Although the
2-phase regulator will operate fine with the PMBus
interface connected to the master only, the READ_
IOUT and READ_IIN measured values will only be
available for the phase(s) that are connected. Since
each phase’s LTC3815 supplies half the load in a
2-phase converter, the value read (if from the master
only) needs to be doubled to obtain the total I
or
OUT
Rev B
30
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LTC3815
APPLICATIONS INFORMATION
Design Example
A value of 18k, 0.5% will be selected for R
.
REF
As a design example, consider using the LTC3815 in an
application with the following specifications:
Finally, define the soft start-up time choosing the proper
value for the capacitor and the resistor connected to
TRACK/SS. If we set minimum t = 5ms, the following
SS
VIN = 2.25V to 5.5V, VOUT = 1.8V, IOUT(MAX) = 6A, IOUT(MIN)
= 200mA, f = 2MHz.
equation can be solved:
5µA • 5ms
Efficiency is important at both high and low load current,
so discontinuous operation will be utilized.
C
=
= 13.9nF
SS
1.8V
The standard value of 15nF guarantees the minimum soft-
start up time of 5ms.
First, calculate the timing resistor:
11
1.15 • 10 Hz
R =
= 11.7k
Figure 10 shows the schematic for this design example.
T
1.11
6
2 • 10
PC Board Layout Checklist
Next, calculate the inductor value for about 30% ripple
current at maximum V :
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3815:
IN
⎛
⎜
⎝
⎞ ⎛
⎞
⎟
⎠
1.8V
1.8V
5.5V
L =
• 1–
= 0.303µH
⎟ ⎜
1. A ground plane is recommended. If a ground plane
layer is not used, the signal and power grounds should
be segregated with all small-signal components return-
ing to the SGND pin at one point which is then con-
nected to the PGND pin close to the LTC3815.
⎠ ⎝
2MHz • 2A
Using a standard value of 0.3µH inductor results in a
maximum ripple current of:
⎛
⎞
⎛
⎞
⎟
⎠
1.8V
1.8V
5.5V
ΔI =
• 1–
= 2.02A
⎜
⎜
⎟
L
2. Connect the (+) terminal of the input capacitor(s), C ,
⎝
2MHz • 0.3µH
IN
⎝
⎠
as close as possible to the PV pin, and the (–) ter-
IN
C
will be selected based on the ESR that is required
minal as close as possible to the exposed pad, PGND.
This capacitor provides the AC current into the internal
power MOSFETs.
OUT
to satisfy the output voltage ripple requirement and the
bulk capacitance needed for loop stability. For this design,
a 150µF (or 47µF plus 100µF) ceramic capacitor is used
with a X5R or X7R dielectric.
3. Keep the switching node, SW, away from all sensitive
small-signal nodes.
Assuming worst-case conditions of VIN = 2VOUT, CIN
should be selected for a maximum current rating of:
4. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise of
power components. Connect the copper areas to PGND
(exposed pad) for best performance
⎛
⎜
⎝
⎞
1.8V
3.6V
3.6V
1.8V
I
= 6A •
•
– 1 = 3A
⎟
RMS
RMS
⎠
5. Connect the remote sense pins, V
and V
SS_
OUT
CC_SENSE
Decoupling PVIN with four 22µF capacitors is adequate
for most applications.
, directly to the point where maximum V
accu-
rSaEcNySEis desired. The two traces should be routed as
close together as possible.
The value of R can now be determined by solving the
REF
following equation.
1.8V
R
=
= 18k
REF
100µA
Rev B
31
For more information www.analog.com
LTC3815
APPLICATIONS INFORMATION
CONNECTING THE USB TO THE I C/SMBus/PMBus
CONTROLLER TO THE LTC3815 IN SYSTEM
The ADI USB to I2C/SMBus/PMBus controller can be
interfaced to the LTC3815 on the user’s board for pro-
gramming, telemetry and system debug. The controller,
when used in conjunction with LTpowerPlay, provides a
powerful way to debug an entire power system.
2
system power is not present, the LTC3815 can be pow-
ered directly from the DC1613's 3.3V supply. Since the
current sourcing ability of this 3.3V supply is limited, the
LTC3815 should be lightly loaded (<10mA) and operating
in discontinuous mode (MODE/SYNC tied to 3.3V).
2
In addition any device sharing the I C bus connections
with the LTC3815 should not have body diodes between
the SDA/SCL pins and their respective V node because
DD
illustrates the application schematic for powering,
programming and communication with one or more
this will interfere with bus communication in the absence
of system power.
2
LTC3815s via the ADI I C/SMBus/PMBus controller
regardless of whether or not system power is present. If
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Figure 14. ADI Controller Connection
Rev B
32
For more information www.analog.com
LTC3815
APPLICATIONS INFORMATION
LTpowerPlay: AN INTERACTIVE GUI FOR DIGITAL
POWER
diagnostic tool during board bring-up to program or
tweak the power system or to diagnose power issues
when bring up rails. LTpowerPlay utilizes Analog Devices’
USB-to-I2C/SMBus/PMBus controller to communica-
tion with one of the many potential targets including the
DC1590B-A/DC1590B-B demo board, the DC1709A sock-
eted programming board, or a customer target system.
The software also provides an automatic update feature
to keep the revisions current with the latest set of device
drivers and documentation. A great deal of context sen-
sitive help is available with LTpowerPlay along with sev-
eral tutorial demos. Complete information is available at
http://www.linear.com/ltpowerplay.
LTpowerPlay is a powerful Windows-based development
environment that supports Analog Devices power sys-
tem management ICs and other digital power IC’s like
the LTC3815. The software supports a variety of differ-
ent tasks. LTpowerPlay can be used to evaluate Analog
Devices ICs by connecting to a demo board or the user
application. LTpowerPlay can also be used in an offline
mode (with no hardware present) in order to build mul-
tiple IC configuration files that can be saved and reloaded
at a later time. LTpowerPlay provides unprecedented
diagnostic and debug features. It becomes a valuable
Figure 15. LTpowerPlay
Rev B
33
For more information www.analog.com
LTC3815
PMBus COMMAND DETAILS
MFR_RESET
slower 1Hz rate to minimize supply current. Either RUN_
STBY pin or ON bit can be cleared/deasserted to put the
LTC3815 into this standby mode. The ON bit is automati-
cally reset to ON after a master shutdown (RUN_MSTR =
0V), power cycle, or MFR_RESET command.
This command provides a means by which the user can
perform a reset of the LTC3815. All latched faults (ALERT
and status register) and register (telemetry, margin, etc)
contents will be reset to a power-on condition by this
command. VOUT will remain in regulation but may change
due to the reset of the margin registers. ASEL and PGFD
config resistors are re-measured.
The MARGIN_LOW/HIGH bits command the V
refer-
OUT
ence to the offset value stored in either the MFR_VOUT_
MARGIN_HIGH or MFR_VOUT_MARGIN_LOW, resp. at
the slew rate set by the C
capacitor. These bits are
SLEW
This write-only command accepts zero, one, or two data
bytes but ignores them.
identical in function to margin high/low from the MARGIN
pin. However, the MARGIN pin has precedence over the
MARGIN_LOW/HIGH bits when there is a conflict. Cycling
the RUN_STBY pin has no affect on the margin bits and
thus when re-asserting RUN_STBY, VOUT will return to
the state it was in prior to the shutdown.
MFR_RAIL_ADDRESS
The MFR_RAIL_ADDRESS command allows all devices
to share a common address, such as all devices attached
to a single power supply rail. The desired 7-bit address
value is written to the 7 bits of the data byte.
Margin high (ignore faults) and margin low (ignore faults)
operations are not supported by the LTC3815.
The MSB (bit B7) must be set low to enable communica-
tion using the MFR_RAIL_ADDRESS address. Setting this
bit disables this address.
This command has one data byte. It will accept one or two
but ignore the second byte.
Table 7. Supported OPERATION Command Register Values
ACTION
Turn off immediately
Turn on
VALUE
0x00
0x80
0x98
0xA8
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Margin Low
Margin High
Figure 16. MFR_RAIL_ADDRESS Data Byte
VOUT_MODE
The user should only perform command writes to this
address. If a read is performed from this address and
the rail devices do not respond with EXACTLY the same
value, the LTC3815 will detect bus contention and set a
CML communications fault.
VOUT_MODE command specifies the formatting for read-
ing output voltage. The data byte always reads 0x3E for
VID data format and cannot be changed. Attempts to write
to VOUT_MODE will set a CML fault.
This command accepts one or two data bytes but the
second is ignored.
This read-only command has one data byte.
MFR_VOUT_COMMAND
OPERATION
The MFR_VOUT_COMMAND consists of a value (%) used
to offset the output reference voltage at the REF pin. The
The OPERATION command is used to turn the unit on/off
and for margining the output voltage.
C
capacitor sets the slew rate limit of the output volt-
SLEW
age if this command is modified while the output is active
The ON bit has the same function as the RUN_STBY pin,
i.e. clearing it turns off the output voltage with PMBus
interface still active and telemetry data refreshed at a
and in a steady-state condition.
Rev B
34
For more information www.analog.com
LTC3815
PMBus COMMAND DETAILS
This command has two data bytes and is formatted as a
9-bit 2’s complement number with 0.1%/bit scaling.
PMBus_REVISION
The PMBUS_REVISION command indicates the revi-
sion of the PMBus to which the device is compliant. The
LTC3815 is PMBus Version 1.2 compliant in both Part I
and Part II.
The range of MFR_VOUT_COMMAND value is limited to
25%.
Do not attempt to write values outside of this range or
unpredictable behavior may result. Writes to this register
are inhibited when the WP pin is high.
This read-only command has one data byte.
MFR_SPECIAL_ID
MFR_ VOUT_MARGIN_LOW
The 16-bit word representing the part name and revision.
The MSB equals 0x80 and denotes the part is an LTC3815.
The LSB is adjustable by the manufacturer.
The MFR_VOUT_MARGIN_LOW command loads
the LTC3815 with the value to which the output is
changed, in percent, when the OPERATION command is
set to margin low or the fast margining pin, MARGIN,
is pulled below 0.4V. Slew rate limiting is same as
MFR_VOUT_COMMAND.
This read-only command has 2 data bytes.
MFR_CLEAR_PEAKS
The MFR_CLEAR_PEAKS command clears the MFR_*_
PEAK data values and restarts the peak monitor routine.
This command has two data bytes and is formatted as a
9-bit 2’s complement number with 0.1%/bit scaling.
This write-only command requires no data bytes, but will
accept (and ignore) up to two.
The range of MFR_VOUT_MARGIN_LOW value is limited
to 25%. There is no restriction on the value relative to
VOUT_COMMAND and MFR_VOUT_MARGIN_HIGH, i.e.
the value is not required to be lower.
STATUS_WORD
The STATUS_WORD command returns two bytes of infor-
mation with a summary of the unit’s fault condition.
Do not attempt to write values outside of this range or
unpredictable behavior may result. Writes to this register
are inhibited when the WP pin is high.
See Table 8 for a list of the status bits that are supported
and the conditions in which each bit is set. Certain bits
when set in the STATUS_WORD also cause the ALERT
pin to be asserted.
MFR_VOUT_MARGIN_HIGH
The MFR_VOUT_MARGIN_HIGH command loads
the LTC3815 with the value to which the output is
changed, in percent, when the OPERATION command is
set to margin high or the fast margining pin, MARGIN,
is pulled above 1.1V. Slew rate limiting is same as
MFR_VOUT_COMMAND.
Writing a "1" to a particular bit in the status word will
attempt to reset that fault in the status word and the
ALERT pin. If the fault is still present the status word bit
and ALERT will remain asserted. If the ALERT has previ-
ously been cleared by an ARA message, the ALERT will
be re-asserted. If the fault is no longer present, the ALERT
pin will be de-asserted and the fault bit in the status word
will be cleared.
This command has two data bytes and is formatted as a
9-bit 2’s complement number with 0.1%/bit scaling.
The range of MFR_VOUT_MARGIN_HIGH value is lim-
ited to 25%. There is no restriction on the value relative
to MFR_VOUT_COMMAND and MFR_VOUT_MARGIN_
LOW, i.e. the value is not required to be higher.
All bits in the status word are also cleared by toggling the
RUN_MSTR pin or the ON bit in OPERATION. The bit will
immediately be set again if the fault remains.
This command has two data bytes.
Do not attempt to write values outside of this range or
unpredictable behavior may result. Writes to this register
are inhibited when the WP pin is high.
Rev B
35
For more information www.analog.com
LTC3815
PMBus COMMAND DETAILS
Table 8. Status Word Bit Descriptions and Conditions
CLEARABLE BY
BIT
DESCRIPTION
None of the Above
Communication Failure
Temperature Fault
CONDITION
If b[15] set due to V undervoltage
SET ALERT?
WRITING ‘1’ TO BIT?
0 (LSB)
Yes
Yes
Yes
No
Yes
Yes
OUT
1
(See Note 1)
2
Temp > 150°C
3
V
Undervoltage Fault
Not Implemented
Not Implemented
> PGOOD High Threshold
IN
4
Output Overcurrent Fault
5
Output Overvoltage Fault
V
OUT
Yes
No
Yes
No
6
OFF
Busy
No Power to the Output (Note 2)
Not Implemented
7
8
Unknown
Not Implemented
9
10
Other
Not Implemented
Fans
Not Implemented
11
PGOOD
Inverted state of PGOOD pin
Not Implemented
No
Yes
Yes
No
Yes
Yes
12
Manufacturer Specific
Input Voltage/ Current/Power Fault
Output Current/Power Fault
Output Voltage Fault
13
Not Implemented
14
Not Implemented
15 (MSB)
V
OUT
outside PGOOD window
(Note 3)
Note 1: Communication failure is one of following faults: host sends too
overtemperature warning. When the power is off due to RUN_MSTR
few bits, host reads too few bits, host writes too few bytes, host reads too
many bytes, improper R/W bit set, unsupported command code, attempt
to write to a read-only command. See PMBus Specification v1.2, Part II,
Sections 10.8 and 10.9 for more information.
low or due to a more serious fault conditions such as V low or
IN
overtemperature fault, the PMBus interface is turned off instead of
asserting the OFF bit.
Note 3: This bit is disabled when drivers are off for any reason, soft-start
Note 2: Power may be off due to any one of the following conditions:
not complete, or the V
time.
has not reached the PGOOD window for the first
OUT
RUN_STBY low, OPERATION ON cleared, PV undervoltage or
IN
All of the following telemetry registers are initialized to
0x8000 when cycling power, cycling RUN_MSTR pin or
sending a MFR_RESET command. The register will remain
at this value until its first conversion is complete—typi-
cally within 50ms of the initialization event.
The output voltage is sensed at the VCC_SEN and VSS_
SEN pins.
This read-only command has two data bytes and is for-
matted as a 16-bit 2’s complement value scaled 0.5mV/
bit.
READ_VIN
READ_IIN
The READ_VIN command returns the measured input
voltage, in volts, at the V pin.
The READ_IIN command returns the input current in
Amperes. The input current is derived from READ_IOUT
current and the measured duty cycle with an offset term
added to account for quiescent current and driver current.
For accurate values at light load currents the part must be
in continuous conduction mode.
IN
This read-only command has two data bytes and is for-
matted as a 16-bit 2’s complement value scaled 4mV/bit.
READ_VOUT
The READ_VOUT command returns the measured out-
put voltage, in volts as specified by the VOUT_MODE
command.
This register is reset to 0x8000 is standby mode when
the drivers are off.
Rev B
36
For more information www.analog.com
LTC3815
PMBus COMMAND DETAILS
This read-only command has two data bytes and is for-
matted as a 16-bit 2’s complement value scaled 10mA/bit.
This command has two data bytes and is formatted as a
16-bit 2’s complement value scaled 4mV/bit.
READ_IOUT
MFR_TEMPERATURE_1_PEAK
The READ_IOUT command returns the average output
current in amperes. The LTC3815 senses and measures
the currents through its top and bottom power switches
The MFR_TEMPERATURE_1_PEAK command reports the
highest temperature, in degrees Celsius, reported by the
READ_TEMPERATURE_1 measurement.
to derive I
current. For accurate values at light load
OUT
To clear the peak value and restart the peak monitor,
use the MFR_CLEAR_PEAKS command or write to the
MFR_TEMPERATURE_1_PEAK. When writing to MFR_
TEMPERATURE_1__PEAK zero, one or two data bytes
are accepted but the data is ignored.
currents the part must be in continuous conduction mode.
This register is reset to 0x8000 is standby mode when
the drivers are off.
This read-only command has two data bytes and is for-
matted as a 16-bit 2’s complement value scaled 10mA/bit.
This command has two data bytes and is formatted as a
16-bit 2’s complement value scaled 1°C/bit.
READ_TEMPERATURE_1
MFR_IOUT_PEAK
The READ_TEMPERATURE_1 command returns the inter-
nal die temperature, in degrees Celsius, of the LTC3815.
The MFR_IOUT_PEAK command reports the high-
est current, in amperes, reported by the READ_IOUT
measurement.
This read-only command has two data bytes and is for-
matted as a 16-bit 2’s complement value scaled 1°C/bit.
To clear the peak value and restart the peak monitor, use
the MFR_CLEAR_PEAKS command or write to the MFR_
IOUT_PEAK. When writing to MFR_IOUT_PEAK, zero, one
or two data bytes are accepted but the data is ignored.
MFR_VOUT_PEAK
The MFR_VOUT_PEAK command reports the highest volt-
age, in volts, reported by the READ_VOUT measurement.
This command has two data bytes and is formatted as a
16-bit 2’s complement value scaled 10mA/bit.
To clear the peak value and restart the peak monitor, use
the MFR_CLEAR_PEAKS command or write to the MFR_
VOUT_PEAK. When writing to MFR_VOUT_PEAK, zero,
one or two data bytes are accepted but the data is ignored.
MFR_IIN_PEAK
The MFR_IIN_PEAK command reports the highest cur-
rent, in amperes, reported by the READ_IIN measurement.
This command has two data bytes and is formatted as a
16-bit 2’s complement value scaled 0.5mV/bit.
To clear the peak value and restart the peak monitor, use
the MFR_CLEAR_PEAKS command or write to the MFR_
IIN_PEAK. When writing to MFR_IIN_PEAK, zero, one or
two data bytes are accepted but the data is ignored.
MFR_VIN_PEAK
The MFR_VIN_PEAK command reports the highest volt-
age, in volts, reported by the READ_VIN measurement.
This command has two data bytes and is formatted as a
16-bit 2’s complement value scaled 10mA/bit.
To clear the peak value and restart the peak monitor, use
the MFR_CLEAR_PEAKS command or write to the MFR_
VIN_PEAK. When writing to MFR_VIN_PEAK zero, one
or two data bytes are accepted but the data is ignored.
Rev B
37
For more information www.analog.com
LTC3815
TYPICAL APPLICATIONS
1.2V/6A 1MHz Buck Regulator with Minimum External Components
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1.2V/6A 2MHz Buck Regulator
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ꢘꢘꢢꢘꢞꢂꢘꢞ
ꢓ
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ꢏꢖꢖꢤꢜ
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R
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Rꢞꢜ
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ꢖꢄꢅꢚ
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ꢙꢦꢛꢜ
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Rev B
38
For more information www.analog.com
LTC3815
TYPICAL APPLICATIONS
12V Input, 1.0V/6A Output Buck Regulator
C1
2.2µF
0.1µF
10Ω
D1
V
IN
4V TO 15V
C
IN
24
23
22
21
20
19
22µF
CLKIN CLKOUT SGND INTV BOOST SV
C1: AVX 0805ZD225MAT2A
×2
CC
IN
0.1µF
1
2
3
4
5
18
17
16
15
14
13
C
C
: TDK C4532X5RIC226M
IN
RT
PV
IN
IN
: TDK C3216X5ROJ476M
OUT
D1: CENTRAL SEMI CMDSH-3
16.2k
PHMODE
MODE
FB
PV
L1: VISHAY IHLP-2525CZERR68-M01
SW
SW
SW
L1 0.68µH
LTC3605
3.3V
22.6k
TRACK/SS
C
OUT
12k
6
47µF
ITH
SW
SW
4.99k
×2
330pF
10pF
0.1µF
RUN PGOOD
V
PGND SW
10 11
ON
7
8
9
12
SV
IN
100k
PGND
SGND
100k 10k
10k
10k
PGOOD DELAY: 190ms
PGOOD THRESHOLD 10%
FREQUENCY: 1MHz
SOFT-START DELAY: 1ms
MARGIN SLEW RATE: 23%/ms
DCM MODE
PV
V
IN
IN
PGOOD
PMBus
PGOOD
SCL
MODE/SYNC
RUN_MSTR
RUN_STBY
CLKOUT
LTC3815
SDA
ALERT
PGFD
PMBus ADDRESS: 0x20
MARGIN
ASEL
0.33µH
V
OUT
1.0V
6A
TRACK/SS
SW
V
V
CC_SENSE
SS_SENSE
C
OUT
C
100µF
×2
SLEW
1k
R
T
DA
OUT
10k
0.5%
PGLIM
REF
V
FB
I
TH
SGND PGND WP
10k
1nF
47pF
C
C
: TAIYO YUDEN LMK316BJ226ML-T
IN
: MURATA GRM32ER60J107ME20
OUT
L: COILCRAFT XAL6030-331MEB
3815 TA04
Rev B
39
For more information www.analog.com
LTC3815
PACKAGE DESCRIPTION
UFE Package
38-Lead Plastic QFN (4mm × 6mm)
(Reference LTC DWG # 05-08-1750 Rev B)
0.70 ±0.05
4.50 ±0.05
3.10 ±0.05
2.40 REF
2.65 ±0.05
4.65 ±0.05
PACKAGE OUTLINE
0.20 ±0.05
0.40 BSC
4.40 REF
5.10 ±0.05
6.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH
R = 0.30 OR
0.35 × 45°
CHAMFER
R = 0.10
0.75 ±0.05
2.40 REF
TYP
4.00 ±0.10
37 38
0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
4.65 ±0.10
4.40 REF
6.00 ±0.10
2.65 ±0.10
(UFE38) QFN 0708 REV B
0.200 REF
R = 0.115
TYP
0.20 ±0.05
0.40 BSC
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
Rev B
40
For more information www.analog.com
LTC3815
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
03/16 Changed V
from 1% to 1.5%
4
1
IN_TUE
B
06/18 Changed title to include “PMBus Interface”
Rev B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
41
LTC3815
TYPICAL APPLICATION
1.2V/12A 2-Phase Buck Regulator
MASTER
SLAVE
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ꢌꢄꢃꢀꢍ ꢌꢃꢎ
ꢁꢂ
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PART
NUMBER
DESCRIPTION
COMMENTS
4.5V ≤ V ≤ 17V, 0.5V ≤ V
2
LTM4676A Dual 13A or Single 26A Step-Down DC/DC µModule Regulator
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LTM4675
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with Digital Power System Management
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OUT
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Dual Output Multiphase Step-Down Controller with Sub MilliOhm DCR 4.5V ≤ V ≤ 38V, 0.5V ≤ V
( 0.5%) ≤ 5.5V, 70ms Start-Up, I C/PMBus
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LTC3887-1 with Digital Power System Management, 70ms Start-Up
4.5V ≤ V ≤ 24V, 0.5V ≤ V
( 0.5%) ≤ 5.5V, 70ms Start-Up, I C/
IN
OUT0,1
PMBus Interface, –1 Version Uses DrMOS and Power Blocks
LTC3882/ Dual Output Multiphase Step-Down DC/DC Voltage Mode
LTC3882-1 Controller with Digital Power System Management
3V ≤ V ≤ 38V, 0.5V ≤ V
≤ 5.25V, 0.5% V
Accuracy
IN
OUT1,2
OUT
2
I C/PMBus Interface, Uses DrMOS or Power Blocks
LTC3886
60V Dual Output Step-Down Controller
with Digital Power System Management
4.5V ≤ V ≤ 60V, 0.5V ≤ V
( 0.5%) ≤ 13.8V, 70ms Start-Up,
IN
OUT0,1
2
I C/PMBus Interface, Input Current Sense
LTC3883/ Single Phase Step-Down DC/DC Controller
LTC3883-1 with Digital Power System Management
V
Up to 24V, 0.5V ≤ V
≤ 5.5V, Input Current Sense Amplifier,
IN
OUT
2
I C/PMBus Interface with EEPROM and 16-Bit ADC, 0.5% V
Accuracy
OUT
LTC3870/ 60V Dual Output Multiphase Step-Down Slave Controller for
LTC3870-1 Current Mode Control Applications with Digital Power System
Management
V
Up to 60V, 0.5V ≤ V
≤ 14V, Very High Output Current Applications
IN
OUT
with Accurate Current Share Between Phases Supporting LTC3880/
LTC3880-1, LTC3883/LTC3883-1, LTC3886, LTC3887/LTC3887-1
LTC3874
Multiphase Step-Down Synchronous Slave Controller
with Sub MilliOhm DCR Sensing
4.5V ≤ V ≤ 38V, V
Up to 5.5V, Very High Output Current,
OUT
IN
Accurate Current Sharing, Current Mode Applications
LTC3880/ Dual Output Multiphase Step-Down DC/DC Controller
LTC3880-1 with Digital Power System Management
4.5V ≤ V ≤ 24V, 0.5V ≤ V
( 0.5%) ≤ 5.4V, 145ms Start-Up,
IN
OUT0
2
I C/PMBus Interface with EEPROM and 16-Bit ADC
Rev B
D16955-0-6/18(B)
www.analog.com
© ANALOG DEVICES, INC. 2015-2018
42
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